Semiconductor memory

Abstract

This disclosure provides a semiconductor memory including multiple memory blocks, each memory block including multiple sensing amplifiers, each memory block including a body bias generation module, and each sensing amplifier including a body bias module. The body bias generation module is coupled to the multiple body bias modules and is used to send a first control signal to a target body bias module among the multiple body bias modules. The target body bias module is coupled to the body terminal of a P-type transistor in a target sensing amplifier and is used to adjust the body terminal voltage of the P-type transistor in the target sensing amplifier under the action of the first control signal to compensate for the threshold voltage mismatch of the N-type transistor in the target sensing amplifier. This reduces the mismatch between devices in one or more sensing amplifiers in the semiconductor memory, enabling each sensing amplifier to effectively amplify the voltage difference between corresponding bit lines and complementary bit lines, thereby improving the accuracy of data reading.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a semiconductor memory. Background Technology

[0002] A semiconductor memory comprises multiple banks, each containing multiple sense amplifiers (SAs). These sense amplifiers amplify the voltage difference between the bit line (BL) and the complementary bit line (BLB) to read the data stored in the memory cell.

[0003] Due to mismatches among the components in the inductive amplifier, the inductive amplifier cannot effectively amplify the voltage difference between the bit line and the complementary bit line, resulting in erroneous read / write results during data reading. Summary of the Invention

[0004] This disclosure provides a semiconductor memory that can compensate for mismatches between devices in any inductive amplifier within the semiconductor memory, thereby improving the accuracy of data reading.

[0005] The semiconductor memory disclosed herein includes multiple memory blocks, and each memory block includes multiple sensing amplifiers;

[0006] Each of the aforementioned storage blocks includes a volume bias generation module, and each of the aforementioned sensing amplifiers includes a volume bias module;

[0007] The volume bias generation module is coupled to multiple volume bias modules and is used to send a first control signal to the target volume bias module among the multiple volume bias modules;

[0008] The target body bias module couples to the body terminal of the P-type transistor in the target inductive amplifier, and is used to adjust the body terminal voltage of the P-type transistor under the action of the first control signal.

[0009] In some embodiments, the volume bias generating module includes:

[0010] The selection unit, which is coupled to a plurality of the volume bias modules, is used to select a target volume bias module from the plurality of the volume bias modules, such that the first end of the comparison unit is coupled to the readout bit line of the target sensing amplifier, and the second end of the comparison unit is coupled to the complementary readout bit line of the target sensing amplifier.

[0011] The comparison unit has a control terminal coupled with a first enable signal, used to compare the readout bit line voltage and the complementary readout bit line voltage of the target sensing amplifier, and send a first control signal to the target body bias module according to the comparison result.

[0012] In some embodiments, the comparison unit is configured to output a first level signal when the readout bit line voltage of the target sensing amplifier is greater than the complementary readout bit line voltage, and to output a second level signal when the readout bit line voltage of the target sensing amplifier is less than the complementary readout bit line voltage, wherein the first level signal is less than the second level signal.

[0013] In some embodiments, the comparison unit includes:

[0014] An operational amplifier, whose control terminal serves as the control terminal of the comparison unit and is coupled with a first enable signal, whose non-inverting input terminal serves as the first terminal of the comparison unit and is coupled with the readout bit line of the target sensing amplifier, whose inverting input terminal serves as the second terminal of the comparison unit and is coupled with the complementary readout bit line of the target sensing amplifier, and whose output terminal is coupled with the selection unit, so that the selection unit sends a first control signal to the target body bias module according to the comparison result.

[0015] In some embodiments, each of the inductive amplifiers includes:

[0016] The first P-type transistor has its source coupled to the first power supply terminal;

[0017] The second P-type transistor has its source coupled to the source of the first P-type transistor, its gate coupled to the drain of the first P-type transistor, and its drain coupled to the gate of the first P-type transistor.

[0018] The first N-type transistor has its drain coupled to the drain of the first P-type transistor, its source coupled to the third power supply terminal, and its gate coupled to the bit line.

[0019] The second N-type transistor has its drain coupled to the drain of the second P-type transistor, its source coupled to the source of the first N-type transistor, and its gate coupled to a complementary bit line.

[0020] Each of the said inductive amplifiers includes a volume bias module comprising:

[0021] A latching module, whose control terminal is coupled to a second enable signal and whose first terminal is coupled to the body bias generating module, is used to convert the first control signal into a second control signal, wherein the level of the first control signal is different from the level of the second control signal;

[0022] A body terminal potential biasing module, wherein a first terminal is coupled to a second terminal of the latching module, a second terminal is coupled to a third terminal of the latching module, and a third terminal is coupled to the body terminal of the first P-type transistor and / or the body terminal of the second P-type transistor, is used to adjust the body terminal voltage of the first P-type transistor and / or the body terminal voltage of the second P-type transistor under the action of the first control signal and the second control signal, thereby compensating for the difference in threshold voltage between the second N-type transistor and the first N-type transistor.

[0023] In some embodiments, the body terminal potential biasing module includes:

[0024] The first body terminal potential biasing module has a first terminal as the first terminal of the body terminal potential biasing module, a second terminal as the second terminal of the body terminal potential biasing module, and a third terminal as the third terminal of the body terminal potential biasing module, which is coupled to the body terminal of the first P-type transistor and used to adjust the body terminal voltage of the first P-type transistor.

[0025] In some embodiments, the body terminal potential biasing module includes:

[0026] The second body terminal potential bias module has a first terminal coupled to the first terminal of the first body terminal potential bias module, a second terminal coupled to the second terminal of the first body terminal potential bias module, and a third terminal serving as the third terminal of the body terminal potential bias module, coupled to the body terminal voltage of the second P-type transistor, for adjusting the body terminal voltage of the second P-type transistor.

[0027] In some embodiments, the first body terminal potential biasing module includes:

[0028] The first transistor has its gate serving as the second terminal of the first body terminal potential bias module, its source coupled to the first power supply terminal, and its drain serving as the third terminal of the first body terminal potential bias module, coupled to the body terminal of the first P-type transistor.

[0029] The second transistor has its gate serving as the first terminal of the first body terminal potential bias module, its source coupled to the second power supply terminal, and its drain coupled to the drain of the first transistor.

[0030] In some embodiments, the second body terminal potential biasing module includes:

[0031] The third transistor has its gate serving as the second terminal of the second body terminal potential bias module, coupled to the gate of the first transistor; its source is coupled to the second power supply terminal; and its drain serves as the third terminal of the second body terminal potential bias module, coupled to the body terminal of the second P-type transistor.

[0032] The fourth transistor has its gate serving as the first terminal of the second body terminal potential bias module, coupled to the gate of the second transistor, its source coupled to the first power supply terminal, and its drain coupled to the drain of the third transistor.

[0033] In some embodiments, the first transistor, the second transistor, the third transistor, and the fourth transistor are P-type transistors.

[0034] In some embodiments, the control terminal of the latch module includes a first control terminal and a second control terminal, and the second enable signal includes a first sub-enable signal and a second sub-enable signal;

[0035] The latch module includes:

[0036] The transmission gate has its control terminal serving as the first control terminal of the latch module, coupled with the first sub-enable signal; its first terminal serving as the first terminal of the latch module, coupled with the first control signal; and its second terminal serving as the second terminal of the latch module, used to transmit the first control signal.

[0037] The latch has its control terminal serving as the second control terminal of the latch module, coupled with the second sub-enable signal, its first terminal coupled with the second terminal of the transmission gate, and its second terminal serving as the third terminal of the latch module, used to convert the first control signal into the second control signal.

[0038] In some embodiments, the latch includes:

[0039] The first inverter, whose control terminal serves as the control terminal of the latch, is coupled with the second sub-enable signal, whose input terminal serves as the first terminal of the latch, and whose output terminal serves as the second terminal of the latch.

[0040] The second inverter has its control terminal serving as the control terminal of the latch, coupled with the second sub-enable signal, its output terminal coupled with the input terminal of the first inverter, and its input terminal coupled with the output terminal of the first inverter.

[0041] In some embodiments, each of the inductive amplifiers further includes:

[0042] A first control unit has a control terminal coupled to a third enable signal, a first terminal coupled to a bit line, and a second terminal coupled to the drain of a first N-type transistor, used to control the coupling between the bit line and the first N-type transistor;

[0043] The second control unit has a control terminal coupled to the third enable signal, a first terminal coupled to a complementary bit line, and a second terminal coupled to the drain of the second N-type transistor, used to control the coupling between the complementary bit line and the second N-type transistor.

[0044] In some embodiments, the first control unit includes:

[0045] The first control transistor has its gate serving as the control terminal of the first control unit and coupled with a third enable signal, its source serving as the first terminal of the first control unit and coupled with a bit line, and its drain serving as the second terminal of the first control unit and coupled with the drain of the first N-type transistor.

[0046] The second control unit includes:

[0047] The second control transistor has its gate serving as the control terminal of the second control unit and coupled with a third enable signal, its source serving as the first terminal of the second control unit and coupled with the complementary bit line, and its drain serving as the second terminal of the second control unit and coupled with the drain of the second N-type transistor.

[0048] In some embodiments, each of the inductive amplifiers further includes:

[0049] The third control unit has a control terminal coupled to a fourth enable signal, a first terminal coupled to the first power supply terminal, and a second terminal coupled to the source of the first P-type transistor.

[0050] The fourth control unit has a control terminal coupled to a fifth enable signal, a first terminal coupled to a third power supply terminal, and a second terminal coupled to the source of the first N-type transistor.

[0051] In some embodiments, the third control unit includes:

[0052] The third control transistor has its gate serving as the control terminal of the third control unit, its source serving as the first terminal of the third control unit and coupled to the first power supply terminal, and its drain serving as the second terminal of the third control unit and coupled to the source of the first P-type transistor.

[0053] The fourth control unit includes:

[0054] The fourth control transistor has its gate serving as the control terminal of the fourth control unit, its source serving as the first terminal of the fourth control unit and coupled to the third power supply terminal, and its drain serving as the second terminal of the fourth control unit and coupled to the source of the first N-type crystal.

[0055] In some embodiments, each of the inductive amplifiers further includes:

[0056] The seventh control unit has a control terminal coupled to a seventh enable signal, a first terminal coupled to a fourth power supply terminal, and a second terminal coupled to a bit line and a complementary bit line, used to control the bit line and the complementary bit line to be precharged to the reference voltage;

[0057] The fifth control unit has a control terminal coupled to a sixth enable signal, a first terminal coupled to a bit line, and a second terminal coupled to the drain of a second P-type transistor, used to control the coupling between the bit line and the readout bit line of the sensing amplifier.

[0058] The sixth control unit has a control terminal coupled to a sixth enable signal, a first terminal coupled to a complementary bit line, and a second terminal coupled to the drain of the first P-type transistor, used to control the coupling between the complementary bit line and the complementary readout bit line of the sensing amplifier.

[0059] In some embodiments, the seventh control unit includes:

[0060] The seventh control transistor has its gate as the control terminal of the seventh control unit, its source as the first terminal of the seventh control unit and is coupled to the fourth power supply terminal, and its drain as the second terminal of the seventh control unit and is coupled to the bit line and the complementary bit line.

[0061] The fifth control unit includes:

[0062] The fifth control transistor has its source serving as the first terminal of the fifth control unit and coupled to a bit line, and its drain serving as the second terminal of the fifth control unit and coupled to the complementary bit line of the sensing amplifier.

[0063] The sixth control unit includes:

[0064] The sixth control transistor has its source serving as the first terminal of the sixth control unit and coupled to the complementary bit line, and its drain serving as the second terminal of the sixth control unit and coupled to the complementary readout bit line of the sensing amplifier.

[0065] The semiconductor memory disclosed herein includes multiple memory blocks, each memory block including multiple sensing amplifiers, each memory block including a body bias generation module, and each sensing amplifier including a body bias module. The body bias generation module is coupled to the multiple body bias modules and is used to send a first control signal to a target body bias module among the multiple body bias modules. The target body bias module is coupled to the body terminal of a P-type transistor in a target sensing amplifier and is used to adjust the body terminal voltage of the P-type transistor in the target sensing amplifier under the action of the first control signal to compensate for the threshold voltage mismatch of the N-type transistor in the target sensing amplifier. This reduces the mismatch between devices in one or more sensing amplifiers in the semiconductor memory, enabling each sensing amplifier to effectively amplify the voltage difference between corresponding bit lines and complementary bit lines, thereby improving the accuracy of data reading. Attached Figure Description

[0066] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0067] Figure 1 A circuit diagram of a semiconductor memory provided according to an embodiment of this disclosure;

[0068] Figure 2 A circuit diagram of an inductive amplifier provided in an embodiment of this disclosure;

[0069] Figure 3 A circuit diagram of a volume bias module provided in an embodiment of this disclosure;

[0070] Figure 4 This is an operation flowchart of a semiconductor memory provided in an embodiment of the present disclosure;

[0071] Figure 5 This is a schematic diagram of the control timing of a semiconductor memory provided in one embodiment of the present disclosure.

[0072] The accompanying drawings have illustrated specific embodiments of this disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0073] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0074] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the foregoing claims.

[0075] Figure 1 This is a circuit diagram of a semiconductor memory provided according to an embodiment of the present disclosure. Figure 1As shown, the semiconductor memory provided in this disclosure includes multiple memory banks, each memory bank includes multiple word line control blocks, each word line control block includes multiple sense amplifier memory array groups, and each sense amplifier memory array group includes multiple sense amplifiers 102. Therefore, the semiconductor memory includes multiple sense amplifiers 102. For example, if the semiconductor memory includes 16 memory banks, one memory bank includes 72 sub-word line control blocks (SWCs), one word line control block includes 8 sense amplifier memory array groups (SA1MATs), and one sense amplifier memory array group includes 6 sense amplifiers, then the semiconductor memory includes 3456 sense amplifiers.

[0076] Each memory block includes a body bias generation module 101 (VBGEN), and each induction amplifier 102 includes a body bias module 1021 (VBSA). The body bias generation module 101 is coupled to the body bias module 1021 in each induction amplifier and can select a target body bias module from multiple body bias modules 1021. A first control signal Vo0 is sent to the target body bias module. The first control signal Vo0 is used to instruct the target body bias module to adjust the body terminal voltage of the P-type transistor in the corresponding target induction amplifier.

[0077] The target body bias module couples to the body terminal of the P-type transistor in the target induction amplifier. Under the action of the first control signal Vo0, it adjusts the body terminal voltage of the P-type transistor in the target induction amplifier to adjust the threshold voltage of the P-type transistor, reduce the mismatch of the threshold voltage of the N-type transistor in the target induction amplifier, thereby reducing the mismatch between the devices in the target induction amplifier, so that the target induction amplifier can effectively amplify the voltage difference between the target bit line and the target complementary bit line.

[0078] It should be noted that the target body bias module can be any body bias module 1021 corresponding to any inductive amplifier in the semiconductor memory, and there can be one or more body bias modules 1021. Therefore, the body bias generating module 101 can send a first control signal Vo0 to any body bias module 1021, so that the body bias module 1021 receiving the first control signal Vo0 adjusts the body terminal voltage of the P-type transistor in the corresponding inductive amplifier 102, thereby reducing the mismatch between the devices in each inductive amplifier 102, so that each inductive amplifier 102 can effectively amplify the voltage difference between the corresponding bit line BL and the complementary bit line BLB.

[0079] In some embodiments, the body bias generation module 101 includes a selection unit 1012 and a comparison unit 1011. The selection unit 1012 is coupled to a plurality of body bias modules 1021 in the semiconductor memory and is used to select a target body bias module from the plurality of body bias modules 1021. The first end of the comparison unit 1011 is coupled to the readout bit line SABL in the target sense amplifier corresponding to the target body bias module, and the second end of the comparison unit 1011 is coupled to the complementary readout bit line SABLB of the target sense amplifier. The comparison unit 1011 can then compare the readout bit line voltage of the target sense amplifier with the complementary readout bit line voltage of the target sense amplifier, and generate a first control signal Vo0 based on the comparison result of the readout bit line voltage and the complementary readout bit line voltage. The first control signal Vo0 is then sent to the selection unit 1012, so that the selection unit 1012 sends the first control signal Vo0 to the target body bias module. This allows the target body bias module to adjust the body terminal voltage of the P-type transistor in the target sense amplifier under the action of the first control signal Vo0, reducing the mismatch between devices in the target sense amplifier. The selection unit 1012 is, for example, a switch array. The switch array controls the comparison unit 1011 coupled with the target body bias module. By setting the selection unit 1012, the comparison unit 1012 can be multiplexed.

[0080] It should be noted that since the target sensing amplifier can be any sensing amplifier in the semiconductor memory, the comparison unit can compare the read bit line voltage of any sensing amplifier with the complementary read bit line voltage, thereby reducing the circuit area by multiplexing the comparison unit 1012.

[0081] For example, the comparator unit 1011 generates a first-level signal when the readout bit line voltage of the target sensing amplifier is greater than the complementary readout bit line voltage, and generates a second-level signal when the readout bit line voltage of the target sensing amplifier is less than the complementary readout bit line voltage, wherein the first-level signal is less than the second-level signal. The comparator unit 1011 sends either the first-level signal or the second-level signal to the selection unit 1012, which then sends either the first-level signal or the second-level signal to the target body bias module. When the comparator unit 1011 outputs the first-level signal, the target body bias module can decrease the body terminal voltage of the first P-type transistor P1 and / or increase the body terminal voltage of the second P-type transistor P2 in the target sensing amplifier. When the comparator unit 1011 outputs the second-level signal, the target body bias module can increase the body terminal voltage of the first P-type transistor P1 and / or decrease the body terminal voltage of the second P-type transistor P2 in the target sensing amplifier.

[0082] In some embodiments, the comparison unit 1011 may include an operational amplifier. The control terminal of the operational amplifier serves as the control terminal of the comparison unit 1011 and is coupled to a first enable signal EN1. The non-inverting input terminal of the operational amplifier serves as the first terminal of the comparison unit 1011 and is coupled to the readout bit line SABL of the target inductive amplifier. The inverting input terminal of the operational amplifier serves as the second terminal of the comparison unit 1011 and is coupled to the complementary readout bit line SABLB of the target inductive amplifier. The output terminal of the operational amplifier is coupled to a selection unit 1012. The operational amplifier compares the readout bit line voltage of the inductive amplifier with the complementary readout bit line voltage of the inductive amplifier, generates a first control signal Vo0 based on the comparison result, and sends the first control signal Vo0 to the selection unit 1012. It should be noted that... Figure 1 VBEN in the code is the first control signal Vo0.

[0083] Figure 2 This is a circuit diagram of an inductive amplifier provided according to an embodiment of the present disclosure. Figure 2 As shown, each inductive amplifier includes a cross-coupling module 1022. The cross-coupling module 1022 includes a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1, and a second N-type transistor N2. The source of the first P-type transistor P1 is coupled to a first power supply terminal VPP. The source of the second P-type transistor P2 is coupled to the source of the first P-type transistor P1. The gate of the second P-type transistor P2 is coupled to the drain of the first P-type transistor P1. The drain of the first N-type transistor N1 is coupled to the drain of the first P-type transistor P1. The source of the first N-type transistor N1 is coupled to a third power supply terminal VSS. The gate of the first N-type transistor N1 is coupled to a bit line BL. The drain of the second N-type transistor N2 is coupled to the drain of the second P-type transistor P2. The source of the second N-type transistor N2 is coupled to the source of the first N-type transistor N1. The gate of the second N-type transistor N2 is coupled to a complementary bit line BLB.

[0084] Figure 3 This is a circuit diagram of a volume bias module provided in one embodiment of the present disclosure. Figure 2 and 3As shown, each inductive amplifier's body bias module 1021 includes a latch module 1023 and body terminal potential bias modules 130 / 140. The control terminal of the latch module 1023 serves as the control terminal of the body bias module 1021, coupled with second enable signals EN2 / EN3 (wherein, the second enable signals EN2 / EN3 include a first sub-enable signal EN2 and a second sub-enable signal EN3). The first terminal of the latch module 1023 serves as the input terminal of the body bias module 1021, coupled with the body bias generation module 101. The latch module 1023 is used to convert a first control signal Vo0 into a second control signal Vo2, where the level of the first control signal Vo0 is different from the level of the second control signal Vo2. The levels of the first control signal Vo0 and the second control signal Vo2 are opposite; for example, the first control signal Vo0 is low and the second control signal Vo2 is high, or vice versa.

[0085] The first terminal of the body terminal potential bias module 130 / 140 is coupled to the second terminal of the latch module 1023, the second terminal of the body terminal potential bias module 130 / 140 is coupled to the third terminal of the latch module 1023, and the third terminal of the body terminal potential bias module is coupled to the body terminal of the first P-type transistor P1 and / or the body terminal of the second P-type transistor P2. This is used to adjust the body terminal voltage of the first P-type transistor P1 and / or the body terminal voltage of the second P-type transistor P2 under the action of the first control signal Vo0 and the second control signal Vo2, so as to compensate for the difference in threshold voltage between the second N-type transistor N2 and the first N-type transistor N1.

[0086] Therefore, when the target body bias module receives the first control signal Vo0, it can adjust the body terminal voltage of the first P-type transistor P1 and / or the body terminal voltage of the second P-type transistor P2 in the target inductive amplifier under the action of the first control signal Vo0, so as to compensate for the difference in threshold voltage between the second N-type transistor N2 and the first N-type transistor N1 in the target inductive amplifier.

[0087] In some embodiments, the body terminal potential biasing module 130 / 140 includes a first body terminal potential biasing module 130, a first terminal of the first body terminal potential biasing module 130 serving as the first terminal of the body terminal potential biasing module 130 / 140, a second terminal of the first body terminal potential biasing module 130 serving as the second terminal of the body terminal biasing module 130 / 140, and a third terminal of the first body terminal potential biasing module 130 serving as the third terminal of the body terminal biasing module 130 / 140, which is coupled to the body terminal of the first P-type transistor P1 for adjusting the body terminal voltage of the first P-type transistor P1.

[0088] In one implementation, the first body terminal potential bias module 130 includes a first transistor T1 and a second transistor T2. The gate of the first transistor T1 serves as the second terminal of the first body terminal potential bias module 130, the source of the first transistor T1 is coupled to the first power supply terminal VPP, and the drain of the first transistor T1 serves as the third terminal of the first body terminal potential bias module 130, coupled to the body terminal of the first P-type transistor P1. The gate of the second transistor T2 serves as the first terminal of the first body terminal potential bias module 130, the source of the second transistor T2 is coupled to the second power supply terminal VDD, and the drain of the second transistor T2 is coupled to the drain of the first transistor T1.

[0089] When the body bias generation module 101 sends the first control signal Vo0, the latch module 1023 converts the first control signal Vo0 into the second control signal Vo2. The second transistor T2 is turned on or off under the action of the first control signal Vo0, and the first transistor T1 is turned on or off under the action of the second control signal Vo2.

[0090] For example, if the first control signal Vo0 is low and the second control signal Vo2 is high, and both the first transistor T1 and the second transistor T2 are P-type transistors, then the second transistor T2 will be turned on under the action of the first control signal Vo0, and the first transistor T1 will be turned off under the action of the second control signal Vo2. Therefore, the second power supply terminal VDD, which is coupled to the source of the second transistor T2, provides voltage to the body terminal of the first P-type transistor P1, thereby reducing the body terminal voltage of the first P-type transistor P1.

[0091] For example, if the first control signal Vo0 is a high-level signal and the second control signal Vo2 is a low-level signal, then the second transistor T2 will be turned off under the action of the first control signal Vo0, and the first transistor T1 will be turned on under the action of the second control signal Vo2. Then, the first power supply terminal VPP coupled to the source of the first transistor T1 will provide voltage to the body terminal of the first P-type transistor P1, thereby increasing the body terminal voltage of the first P-type transistor P1.

[0092] In some other embodiments, the body terminal potential biasing module 130 / 140 may include a first body terminal potential biasing module 130 and a second body terminal potential biasing module 140. The first end of the second body terminal potential biasing module 140 is coupled to the first end of the first body terminal potential biasing module 130, and the second end of the second body terminal potential biasing module 140 is coupled to the second end of the first body terminal potential biasing module 130. The third end of the second body terminal potential biasing module 140 serves as the third end of the body terminal potential biasing module 130 / 140 and is coupled to the body terminal voltage of the second P-type transistor P2. Thus, the body terminal voltage of the first P-type transistor P1 can be adjusted using the first body terminal potential biasing module 130, while the body terminal voltage of the second P-type transistor P2 can be adjusted using the second body terminal potential biasing module 140.

[0093] In one implementation, the first body-terminal potential biasing module 130 includes a first transistor T1 and a second transistor T2, and the second body-terminal potential biasing module 140 includes a third transistor T3 and a fourth transistor T4. The gate of the first transistor T1 serves as the second terminal of the first body-terminal potential biasing module 130, the source of the first transistor T1 is coupled to the first power supply terminal VPP, and the drain of the first transistor T1 serves as the third terminal of the first body-terminal potential biasing module 130, coupled to the body terminal of the first P-type transistor P1. The gate of the second transistor T2 serves as the first terminal of the first body-terminal potential biasing module 130, the source of the second transistor T2 is coupled to the second power supply terminal VDD, and the drain of the second transistor T2 is coupled to the drain of the first transistor T1. The gate of the third transistor T3 serves as the second terminal of the second body-terminal potential biasing module 140, coupled to the gate of the first transistor T1, the source of the third transistor T3 is coupled to the second power supply terminal VDD, and the drain of the third transistor T3 serves as the third terminal of the second body-terminal potential biasing module 140, coupled to the body terminal of the second P-type transistor P2. The gate of the fourth transistor T4 serves as the first terminal of the second body terminal potential bias module 140 and is coupled to the gate of the second transistor T2. The source of the fourth transistor T4 is coupled to the first power supply terminal VPP, and the drain of the fourth transistor T4 is coupled to the drain of the third transistor T3.

[0094] When the body bias generation module 101 sends the first control signal Vo0, and the latch module 1023 converts the first control signal Vo0 into the second control signal Vo2, the second transistor T2 and the fourth transistor T4 are turned on or off under the action of the first control signal Vo0, and the first transistor T1 and the third transistor T3 are turned on or off under the action of the second control signal Vo2.

[0095] For example, if the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are P-type transistors, and the first control signal Vo0 is a high-level signal and the second control signal Vo2 is a low-level signal, then the first transistor T1 and the third transistor T3 will be turned on under the action of the second control signal Vo2, and the second transistor T2 and the fourth transistor T4 will be turned off under the action of the first control signal Vo0. The first power supply terminal VPP coupled to the first transistor T1 provides voltage to the body terminal of the first P-type transistor P1, increasing the body terminal voltage of the first P-type transistor P1. The second power supply terminal VDD coupled to the third transistor T3 provides voltage to the body terminal of the second P-type transistor P2, decreasing the body terminal voltage of the second P-type transistor P2.

[0096] For example, if the first control signal Vo0 is a low-level signal and the second control signal Vo2 is a high-level signal, then the first transistor T1 and the third transistor T3 will be turned off under the action of the second control signal Vo2, while the second transistor T2 and the fourth transistor T4 will be turned on under the action of the first control signal Vo0. The second power supply terminal VDD coupled to the second transistor T2 provides voltage to the body terminal of the first P-type transistor P1, reducing the body terminal voltage of the first P-type transistor P1. The first power supply terminal VPP coupled to the fourth transistor T4 provides voltage to the body terminal of the second P-type transistor P2, increasing the body terminal voltage of the second P-type transistor P2.

[0097] In some embodiments, the control terminal of the latch module 1023 includes a first control terminal and a second control terminal. The latch module 1023 includes a transmission gate 120 and a latch 110. The control terminal of the transmission gate 120 serves as the first control terminal of the latch module 1023 and is coupled with a first sub-enable signal EN2. The first end of the transmission gate 120 serves as the first end of the latch module 1023 and is coupled with a body bias generation module 101. The second end of the transmission gate 120 serves as the second end of the latch module 1023 and is used to transmit a first control signal Vo0. The input signal and output signal of the transmission gate 120 are both the first control signal Vo0. Therefore, the transmission gate 120 can apply the first control signal Vo0 output by the comparison unit 1011 to the second transistor T2 and the fourth transistor T4. The control terminal of latch 110 serves as the second control terminal of latch module 1023. The first terminal of latch 110 is coupled to the second terminal of transmission gate 120. The second terminal of latch 110 serves as the third terminal of latch module 1023, used to convert the first control signal Vo0 into the second control signal Vo2.

[0098] The latch 110 may include a first inverter and a second inverter. The control terminal of the first inverter serves as the control terminal of the latch 110 and is coupled with a second sub-enable signal EN3. The input terminal of the first inverter serves as the first terminal of the latch 110, and the output terminal of the first inverter serves as the second terminal of the latch 110. The control terminal of the second inverter serves as the control terminal of the latch 110 and is coupled with the second sub-enable signal EN3. The input terminal of the second inverter is coupled with the output terminal of the first inverter. This allows the first control signal Vo0 to be converted into a second control signal Vo2, and the first control signal Vo0 and the second control signal Vo2 to be interlocked. Even after the transmission gate 120 is turned off, the mismatch compensation between the first N-type transistor N1 and the second N-type transistor N2 can still be maintained.

[0099] When the threshold voltage of the first N-type transistor N1 is larger than that of the second N-type transistor N2, the drain voltage of the first N-type transistor N1 is larger, resulting in a smaller turn-on degree. In this case, the body voltage of the first P-type transistor P1 can be reduced to lower its threshold voltage, increase its operating current, and thus increase the charge compensation it provides. Because the charge compensation of the first P-type transistor P1 increases, the charge accumulated at the gate of the first N-type transistor N1 increases, thereby increasing the turn-on degree of the first N-type transistor N1 and reducing the mismatch between the first N-type transistor N1 and the second N-type transistor N2.

[0100] In some embodiments, when it is necessary to adjust the body terminal voltage of the P-type transistors in all sensing amplifiers 102, the target body bias module is all body bias modules 1021 in the semiconductor memory, and the body bias generation module 101 can send a first control signal Vo0 to each body bias module 1021 in sequence.

[0101] like Figure 4As shown, in step S101, the first enable signal EN1 is turned on. It should be noted that since mismatch adjustment is only performed upon each power-on, the first enable signal EN1 and the second enable signals EN2 / EN3 are turned on at the end of the first pre-charge, and the first sub-enable signal EN2 is turned off before the second pre-charge begins. The second sub-enable signal EN3 remains constantly on in subsequent processes. In step S102, the selection unit 1012 selects the Nth body bias module from the plurality of body bias modules, and simultaneously turns on the second enable signals EN2 / EN3. The selection unit 1012 selects the Nth body bias module, such that the comparison unit 1011 couples the readout bit line SABL of the Nth sense amplifier corresponding to the Nth body bias module with the complementary readout bit line SABLB of the Nth sense amplifier. In step S103, the comparison unit 1011 compares whether the readout bit line voltage of the Nth sense amplifier is greater than the complementary readout bit line voltage of the Nth sense amplifier. If yes, proceed to step S104; otherwise, proceed to step S105. In step S104, the comparator unit 1011 outputs a first-level signal to provide a second voltage to the first P-type transistor P1 in the Nth inductive amplifier and a first voltage to the second P-type transistor in the Nth inductive amplifier, where the first voltage is greater than the second voltage. In step S105, the comparator unit outputs a second-level signal to provide a first voltage to the first P-type transistor P1 in the Nth inductive amplifier and a second voltage to the second P-type transistor P2 in the Nth inductive amplifier. Subsequently, proceed to step S106 to adjust the body terminal voltages of the first P-type transistor P1 and the second P-type transistor P2. In step S107, the first sub-enable signal EN2 is turned off, while the second sub-enable signal EN3 remains on. In step S108, it is determined whether all inductive amplifiers 102 have completed mismatch adjustment. If yes, proceed to step S109; otherwise, proceed to step S110. In step S109, the first enable signal EN1 is turned off. After all sensing amplifiers 102 have completed mismatch adjustment, the first enable signal EN1 is turned off. In step S110, the control selection unit 1012 selects the (N+1)th body bias module from the plurality of body bias modules and turns on the second sub-enable signal EN2, continuing to execute steps S103-S107 until all sensing amplifiers 102 have completed mismatch adjustment. It should be noted that after turning off the first enable signal EN1, the control logic is still maintained, ensuring that the body terminal voltage of the first P-type transistor and the body terminal voltage of the second P-type transistor remain at the adjusted body terminal voltage.

[0102] For example, a semiconductor memory includes 3456 inductive amplifiers 102, labeled 0, 1, 2...3455, and thus includes 3456 individual bias modules 1021. Figure 5A control timing diagram provided for embodiments of this disclosure, such as Figure 5 As shown, firstly, the first enable signal EN1 is turned on, and the selection unit 1012 selects the 0th body bias module 1021 while simultaneously turning on the second enable signals EN2 / EN3, causing the comparison unit 1011 to couple the readout bit line SABL and the complementary readout bit line SABLB of the 0th sensing amplifier corresponding to the 0th body bias module. Then, the comparison unit 1011 compares the readout bit line voltage of the 0th sensing amplifier with the complementary readout bit line voltage to generate a first control signal Vo0, and uses the first control signal Vo0 to adjust the body terminal voltage of the P-type transistor in the 0th sensing amplifier. Subsequently, the first sub-enable signal EN3 is turned off, and the first sub-enable signal EN2 is turned on. Next, the control selection unit 1012 selects the first body bias module and simultaneously enables the second sub-enable signal EN3, causing the comparison unit 1011 to couple the bit line BL and complementary bit line BLB of the first induction amplifier corresponding to the first body bias module, and adjust the body terminal voltage of the P-type transistor in the first induction amplifier using the first control signal Vo0. This process continues until the comparison unit 1011 couples the bit line BL and complementary bit line BLB of the 3455 induction amplifier, and adjusts the body terminal voltage of the P-type transistor in the 3455 induction amplifier using the first control signal Vo0, thereby completing the mismatch adjustment between the devices in the 3456 induction amplifiers.

[0103] It should be noted that the body bias generation module and the body bias module can be used to adjust the body terminal voltage of the P-type transistor in the inductive amplifier during the reset phase, refresh phase and memory block activation phase after power-on, so as not to affect the operating speed of the inductive amplifier.

[0104] In some embodiments, each inductive amplifier 102 includes a first control unit 1031 and a second control unit 1032. The control terminal of the first control unit 1031 is coupled to a third enable signal OC, a first terminal of the first control unit 1031 is coupled to a bit line BL, and a second terminal of the first control unit 1031 is coupled to the drain of a first N-type transistor N1, for controlling the coupling between the bit line BL and the first N-type transistor N1. The control terminal of the second control unit 1032 is coupled to the third enable signal OC, a first terminal of the second control unit 1032 is coupled to a complementary bit line BLB, and a second terminal of the second control unit 1032 is coupled to the drain of a second N-type transistor N2, for controlling the coupling between the complementary bit line BLB and the second N-type transistor N2.

[0105] The first control unit 1031 may include a first control transistor N3, and the second control unit 1032 may include a second control transistor N4. The gate of the first control transistor N3 serves as the control terminal of the first control unit 1031, the source of the first control transistor N3 serves as the first terminal of the first control unit 1031 and is coupled to a bit line BL, and the drain of the first control transistor N3 serves as the second terminal of the first control unit 1031 and is coupled to the drain of a first N-type transistor N1. The second control unit 1032 may include a second control transistor N4, the gate of the second control transistor N4 serves as the control terminal of the second control unit 1032, the source of the second control transistor N4 serves as the first terminal of the second control unit 1032 and is coupled to a complementary bit line BLB, and the drain of the second control transistor N4 serves as the second terminal of the second control unit 1032 and is coupled to the drain of a second N-type transistor N2. The first control transistor N3 and the second control transistor N4 are, for example, N-type transistors.

[0106] In some embodiments, each inductive amplifier 102 includes a third control unit 1051 and a fourth control unit. The control terminal of the third control unit 1051 is coupled to a fourth enable signal SAP, a first terminal of the third control unit 1051 is coupled to a first power supply terminal VPP, and a second terminal of the third control unit 1051 is coupled to the source of a first P-type transistor P1, for controlling the first power supply terminal VPP to provide a first voltage. The control terminal of the fourth control unit is coupled to a fifth enable signal SAN, a first terminal of the fourth control unit is coupled to a third power supply terminal VSS, and a second terminal of the fourth control unit is coupled to the source of a first N-type transistor N1, for controlling the third power supply terminal VSS to provide a third voltage, for example, less than the first and second voltages.

[0107] The third control unit 1051 includes a third control transistor P0, and the fourth control unit includes a fourth control transistor N0. The gate of the third control transistor P0 serves as the control terminal of the third control unit 1051, the source of the third control transistor P0 serves as the first terminal of the third control unit 1051 and is coupled to the first power supply terminal VPP, and the drain of the third control transistor P0 serves as the second terminal of the third control unit 1051 and is coupled to the source of the first P-type transistor P1. The third control transistor P0 is turned on by a fourth enable signal SAP, causing the first power supply terminal VPP to provide a first voltage. The fourth control unit 1041 includes a fourth control transistor N0, the gate of the fourth control transistor N0 serves as the control terminal of the fourth control unit 1041, the source of the fourth control transistor N0 serves as the first terminal of the fourth control unit 1041 and is coupled to the third power supply terminal VSS, and the drain of the fourth control transistor N0 serves as the second terminal of the fourth control unit 1041 and is coupled to the source of the first N-type transistor N1. The fourth control transistor N0 is turned on by a fifth enable signal SAN, causing the third power supply terminal VSS to provide a third voltage. The third control transistor P0 is, for example, a P-type transistor, and the fourth control transistor N0 is, for example, an N-type transistor.

[0108] In some embodiments, each sensing amplifier includes a seventh control unit 1071, a fifth control unit 1061, and a sixth control unit 1062. The control terminal of the seventh control unit 1071 is coupled to a seventh enable signal PRE. A first terminal of the seventh control unit 1071 is coupled to a fourth power supply terminal VBLP, and a second terminal of the seventh control unit 1071 is coupled to a bit line BL and a complementary bit line BLB, for controlling the fourth power supply terminal VBLP to provide a reference voltage to precharge the bit line BL and the complementary bit line BLB to the reference voltage. The control terminal of the fifth control unit 1061 is coupled to a sixth enable signal ISO. A first terminal of the fifth control unit 1061 is coupled to the bit line BL, and a second terminal of the fifth control unit 1061 is coupled to the sense bit line SABL of the sensing amplifier, for controlling the coupling between the bit line BL and the sense bit line SABL of the sensing amplifier to precharge the sense bit line SABL of the sensing amplifier to the reference voltage. The control terminal of the sixth control unit 1062 is coupled with the sixth enable signal ISO, and the second terminal of the sixth control unit 110 is coupled with the complementary readout bit line SABLB of the sensing amplifier. This is used to control the coupling between the complementary bit line BLB and the complementary readout bit line SABLB of the sensing amplifier to precharge the readout bit line SABLB of the sensing amplifier to the reference voltage.

[0109] The seventh control unit 1071 may include a seventh control transistor N7. The gate of the seventh control transistor N7 serves as the control terminal of the seventh control unit 1071. The source of the seventh control transistor N7 serves as the first terminal of the seventh control unit 1071 and is coupled to the fourth power supply terminal VBLP. The drain of the seventh control transistor N7 serves as the second terminal of the seventh control unit 1071 and is coupled to bit line BL and complementary bit line BLB. The fifth control unit 1061 may include a fifth control transistor N5. The source of the fifth control transistor N5 serves as the first terminal of the fifth control unit 1061 and is coupled to bit line BL. The drain of the fifth control unit 1061 serves as the second terminal of the fifth control unit 1061 and is coupled to the drain of the second P-type transistor P2. The sixth control unit 1062 may include a sixth control transistor N6. The source of the sixth control transistor N6 serves as the first terminal of the sixth control unit 1062 and is coupled to complementary bit line BLB. The drain of the sixth control unit 1062 serves as the second terminal of the sixth control unit 1062 and is coupled to the drain of the first P-type transistor P1.

[0110] During the pre-charging phase, the seventh enable signal PRE, the sixth enable signal ISO, and the third enable signal OC are turned on. The first control transistor N3 and the second control transistor N4 are turned on under the action of the third enable signal OC, so that the fourth power supply terminal VBLP provides a reference voltage to pre-charge the bit line BL and the complementary bit line BLB to the reference voltage. The fifth control transistor N5 and the sixth control transistor N6 are turned on under the action of the sixth enable signal ISO, so that the sense bit line SABL of the sense amplifier 102 is coupled to the bit line BL, and the complementary sense bit line SABLB of the sense amplifier 102 is coupled to the complementary bit line BLB. The first control transistor N3 and the second control transistor N4 are turned on under the action of the third enable signal OC, so that the bit line BL is coupled to the complementary sense bit line SABLB of the sense amplifier 102, and the complementary bit line BLB is coupled to the sense bit line SABL of the sense amplifier 102, thereby charging the sense bit line SABL and the complementary sense bit line SABLB of the sense amplifier to the reference voltage.

[0111] Then, the seventh enable signal PRE and the sixth enable signal ISO are turned off, and the fourth enable signal SAP and the fifth enable signal SAN are turned on. Then the third control transistor P0 and the fourth control transistor N0 are turned on, so that the first power supply terminal VPP provides the first voltage and the second power supply terminal VDD provides the second voltage. Since the third enable signal OC is turned on, the gate of the first N-type transistor N1 is coupled to the drain and the gate of the second N-type transistor N2 are coupled to the drain. The first charge can be accumulated on the gate of the first N-type transistor N1 and the second charge can be accumulated on the gate of the second N-type transistor N2, thus completing the mismatch compensation of the first N-type transistor N1 and the second N-type transistor N2.

[0112] Subsequently, the fourth enable signal SAP, the fifth enable signal SAN, and the third enable signal OC can be turned off, and the word line WL can be turned on, allowing charge sharing between the read bit line SABL and the complementary read bit line SABLB of the sensing amplifier 102. Then, the sixth enable signal ISO is turned on, thereby reading out the data from the bit line BL and the complementary bit line BLB.

[0113] Finally, the fourth enable signal SAP and the fifth enable signal SAN are activated, thereby utilizing the inductive amplifier 102 to amplify the data on bit line BL and complementary bit line BLB. It should be noted that... Figure 1 VBEN in the code is the first control signal Vo0.

[0114] The semiconductor memory disclosed herein sends a first control signal to a target body bias module among multiple body bias modules through a body bias generation module. Under the action of the first control signal, the target body bias module adjusts the body terminal voltage of the P-type transistor in the target inductive amplifier to compensate for the mismatch of the threshold voltage of the N-type transistor in the target inductive amplifier. This reduces the mismatch between devices in one or more inductive amplifiers in the semiconductor memory, enabling each inductive amplifier to effectively amplify the voltage difference between the corresponding bit line and the complementary bit line, thereby improving the accuracy of data reading.

[0115] It should be understood that this disclosure is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. This disclosure relates to, but is not limited to, a semiconductor memory.

Claims

1. A semiconductor memory, characterized in that, It includes multiple storage blocks, and each storage block includes multiple induction amplifiers; Each of the aforementioned storage blocks includes a volume bias generation module, and each of the aforementioned sensing amplifiers includes a volume bias module; The volume bias generation module is coupled to multiple volume bias modules and is used to send a first control signal to the target volume bias module among the multiple volume bias modules; The target body bias module is coupled to the body terminal of the P-type transistor in the target inductive amplifier, and is used to adjust the body terminal voltage of the P-type transistor under the action of the first control signal. The volume bias generation module includes: The selection unit, which is coupled to a plurality of the volume bias modules, is used to select a target volume bias module from the plurality of the volume bias modules, such that the first end of the comparison unit is coupled to the readout bit line of the target sensing amplifier, and the second end of the comparison unit is coupled to the complementary readout bit line of the target sensing amplifier. The comparison unit has a control terminal coupled with a first enable signal, used to compare the readout bit line voltage of the target sensing amplifier with the complementary readout bit line voltage, generate a first control signal based on the comparison result, and send the first control signal to the selection unit.

2. The semiconductor memory according to claim 1, characterized in that, The comparison unit is configured to output a first level signal when the readout bit line voltage of the target sensing amplifier is greater than the complementary readout bit line voltage, and to output a second level signal when the readout bit line voltage of the target sensing amplifier is less than the complementary readout bit line voltage, wherein the first level signal is less than the second level signal.

3. The semiconductor memory according to claim 2, characterized in that, The comparison unit includes: An operational amplifier, whose control terminal serves as the control terminal of the comparison unit and is coupled with a first enable signal, whose non-inverting input terminal serves as the first terminal of the comparison unit and is coupled with the readout bit line of the target sensing amplifier, whose inverting input terminal serves as the second terminal of the comparison unit and is coupled with the complementary readout bit line of the target sensing amplifier, and whose output terminal is coupled with the selection unit, is used to generate a first control signal based on the comparison result and send the first control signal to the selection unit.

4. The semiconductor memory according to any one of claims 1-3, characterized in that, Each of the aforementioned inductive amplifiers includes: The first P-type transistor has its source coupled to the first power supply terminal; The second P-type transistor has its source coupled to the source of the first P-type transistor, its gate coupled to the drain of the first P-type transistor, and its drain coupled to the gate of the first P-type transistor. The first N-type transistor has its drain coupled to the drain of the first P-type transistor, its source coupled to the third power supply terminal, and its gate coupled to the bit line. The second N-type transistor has its drain coupled to the drain of the second P-type transistor, its source coupled to the source of the first N-type transistor, and its gate coupled to a complementary bit line. Each of the said inductive amplifiers includes a volume bias module comprising: A latching module, whose control terminal is coupled to a second enable signal and whose first terminal is coupled to the body bias generating module, is used to convert the first control signal into a second control signal, wherein the level of the first control signal is different from the level of the second control signal; A body terminal potential biasing module, wherein a first terminal is coupled to a second terminal of the latching module, a second terminal is coupled to a third terminal of the latching module, and a third terminal is coupled to the body terminal of the first P-type transistor and / or the body terminal of the second P-type transistor, is used to adjust the body terminal voltage of the first P-type transistor and / or the body terminal voltage of the second P-type transistor under the action of the first control signal and the second control signal, thereby compensating for the difference in threshold voltage between the second N-type transistor and the first N-type transistor.

5. The semiconductor memory according to claim 4, characterized in that, The body terminal potential biasing module includes: The first body terminal potential biasing module has a first terminal as the first terminal of the body terminal potential biasing module, a second terminal as the second terminal of the body terminal potential biasing module, and a third terminal as the third terminal of the body terminal potential biasing module, which is coupled to the body terminal of the first P-type transistor and used to adjust the body terminal voltage of the first P-type transistor.

6. The semiconductor memory according to claim 5, characterized in that, The body terminal potential biasing module includes: The second body terminal potential bias module has a first terminal coupled to the first terminal of the first body terminal potential bias module, a second terminal coupled to the second terminal of the first body terminal potential bias module, and a third terminal serving as the third terminal of the body terminal potential bias module, coupled to the body terminal voltage of the second P-type transistor, for adjusting the body terminal voltage of the second P-type transistor.

7. The semiconductor memory according to claim 6, characterized in that, The first body terminal potential bias module includes: The first transistor has its gate serving as the second terminal of the first body terminal potential bias module, its source coupled to the first power supply terminal, and its drain serving as the third terminal of the first body terminal potential bias module, coupled to the body terminal of the first P-type transistor. The second transistor has its gate serving as the first terminal of the first body terminal potential bias module, its source coupled to the second power supply terminal, and its drain coupled to the drain of the first transistor.

8. The semiconductor memory according to claim 7, characterized in that, The second body terminal potential bias module includes: The third transistor has its gate serving as the second terminal of the second body terminal potential bias module, coupled to the gate of the first transistor; its source is coupled to the second power supply terminal; and its drain serves as the third terminal of the second body terminal potential bias module, coupled to the body terminal of the second P-type transistor. The fourth transistor has its gate serving as the first terminal of the second body terminal potential bias module, coupled to the gate of the second transistor, its source coupled to the first power supply terminal, and its drain coupled to the drain of the third transistor.

9. The semiconductor memory according to claim 8, characterized in that, The first transistor, the second transistor, the third transistor, and the fourth transistor are P-type transistors.

10. The semiconductor memory according to claim 4, characterized in that, The control terminal of the latch module includes a first control terminal and a second control terminal, and the second enable signal includes a first sub-enable signal and a second sub-enable signal; The latch module includes: The transmission gate has its control terminal serving as the first control terminal of the latch module, coupled with the first sub-enable signal; its first terminal serving as the first terminal of the latch module, coupled with the first control signal; and its second terminal serving as the second terminal of the latch module, used to transmit the first control signal. The latch has its control terminal serving as the second control terminal of the latch module, coupled with the second sub-enable signal, its first terminal coupled with the second terminal of the transmission gate, and its second terminal serving as the third terminal of the latch module, used to convert the first control signal into the second control signal.

11. The semiconductor memory according to claim 10, characterized in that, The latch includes: The first inverter, whose control terminal serves as the control terminal of the latch, is coupled with the second sub-enable signal, whose input terminal serves as the first terminal of the latch, and whose output terminal serves as the second terminal of the latch. The second inverter has its control terminal serving as the control terminal of the latch, coupled with the second sub-enable signal, its output terminal coupled with the input terminal of the first inverter, and its input terminal coupled with the output terminal of the first inverter.

12. The semiconductor memory according to claim 4, characterized in that, Each of the aforementioned inductive amplifiers also includes: A first control unit has a control terminal coupled to a third enable signal, a first terminal coupled to a bit line, and a second terminal coupled to the drain of a first N-type transistor, used to control the coupling between the bit line and the first N-type transistor; The second control unit has a control terminal coupled to the third enable signal, a first terminal coupled to a complementary bit line, and a second terminal coupled to the drain of the second N-type transistor, used to control the coupling between the complementary bit line and the second N-type transistor.

13. The semiconductor memory according to claim 12, characterized in that, The first control unit includes: The first control transistor has its gate serving as the control terminal of the first control unit and coupled with a third enable signal, its source serving as the first terminal of the first control unit and coupled with a bit line, and its drain serving as the second terminal of the first control unit and coupled with the drain of the first N-type transistor. The second control unit includes: The second control transistor has its gate serving as the control terminal of the second control unit and coupled with a third enable signal, its source serving as the first terminal of the second control unit and coupled with the complementary bit line, and its drain serving as the second terminal of the second control unit and coupled with the drain of the second N-type transistor.

14. The semiconductor memory according to claim 4, characterized in that, Each of the aforementioned inductive amplifiers also includes: The third control unit has a control terminal coupled to a fourth enable signal, a first terminal coupled to the first power supply terminal, and a second terminal coupled to the source of the first P-type transistor. The fourth control unit has a control terminal coupled to a fifth enable signal, a first terminal coupled to a third power supply terminal, and a second terminal coupled to the source of the first N-type transistor.

15. The semiconductor memory according to claim 14, characterized in that, The third control unit includes: The third control transistor has its gate serving as the control terminal of the third control unit, its source serving as the first terminal of the third control unit and coupled to the first power supply terminal, and its drain serving as the second terminal of the third control unit and coupled to the source of the first P-type transistor. The fourth control unit includes: The fourth control transistor has its gate serving as the control terminal of the fourth control unit, its source serving as the first terminal of the fourth control unit and coupled to the third power supply terminal, and its drain serving as the second terminal of the fourth control unit and coupled to the source of the first N-type crystal.

16. The semiconductor memory according to claim 4, characterized in that, Each of the aforementioned inductive amplifiers also includes: The seventh control unit has a control terminal coupled to a seventh enable signal, a first terminal coupled to a fourth power supply terminal, and a second terminal coupled to a bit line and a complementary bit line, used to control the bit line and the complementary bit line to be precharged to the reference voltage; The fifth control unit has a control terminal coupled to a sixth enable signal, a first terminal coupled to a bit line, and a second terminal coupled to the drain of a second P-type transistor, used to control the coupling between the bit line and the readout bit line of the sensing amplifier. The sixth control unit has a control terminal coupled to the sixth enable signal, a first terminal coupled to a complementary bit line, and a second terminal coupled to the drain of the first P-type transistor, used to control the coupling between the complementary bit line and the complementary readout bit line of the sensing amplifier.

17. The semiconductor memory according to claim 16, characterized in that, The seventh control unit includes: The seventh control transistor has its gate as the control terminal of the seventh control unit, its source as the first terminal of the seventh control unit and is coupled to the fourth power supply terminal, and its drain as the second terminal of the seventh control unit and is coupled to the bit line and the complementary bit line. The fifth control unit includes: The fifth control transistor has its source serving as the first terminal of the fifth control unit and coupled to a bit line, and its drain serving as the second terminal of the fifth control unit and coupled to the complementary bit line of the sensing amplifier. The sixth control unit includes: The sixth control transistor has its source serving as the first terminal of the sixth control unit and coupled to the complementary bit line, and its drain serving as the second terminal of the sixth control unit and coupled to the complementary readout bit line of the sensing amplifier.

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