Chip packaging method, wafer-level chip packaging component, and chip packaging component

Abstract

The present application discloses a chip packaging method, a wafer-level chip packaging component, and a chip packaging component, comprising: obtaining a wafer including multiple chips, wherein a plurality of pads are provided on one surface of the chips; providing a dicing path between adjacent chips; forming a patterned seed layer on the wafer; the patterned seed layer includes multiple first seed layers covering the multiple pads, and a second seed layer connecting the multiple first seed layers; the second seed layer includes a trunk portion located within the dicing path and multiple branch portions intersecting the trunk portion, wherein both ends of the branch portions extend to the pads of adjacent chips; forming a first redistribution layer corresponding to the pads on the first seed layer; and cutting the wafer based on the dicing path to obtain multiple packaged chips. The present application can remove the residual seed layer by cutting the wafer, without reserving an etching margin on the first redistribution layer, thereby obtaining a small linewidth redistribution layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chip packaging method, a wafer-level chip packaging component, and a chip packaging component. Background Art

[0002] Wafer-level packaging has the characteristics of small size and high efficiency, and is gradually becoming a trend in packaging development.

[0003] In the prior art, wafer-level chips are generally packaged as a whole and then sliced into individual chips. However, the prior art cannot produce packaged chips with good performance. Summary of the Invention

[0004] In order to solve the above problems or other problems, this application provides the following technical solutions.

[0005] The first technical solution adopted in the present application is to provide a chip packaging method, including: obtaining a wafer including multiple chips, and multiple pads are arranged on one side surface of each chip; wherein a cutting road is arranged between adjacent chips; forming a patterned seed layer on the wafer; wherein the patterned seed layer includes multiple first seed layers covering multiple pads, and a second seed layer connecting the multiple first seed layers; wherein the second seed layer includes a main part located in the cutting road and multiple branch parts intersecting with the main part, and both ends of each branch part extend to the pads of adjacent chips respectively; forming a first redistribution layer on the patterned seed layer; wherein the first redistribution layer corresponds to the pads; cutting the wafer based on the cutting road to obtain multiple packaged chips.

[0006] Among them, the step of forming a patterned seed layer on the wafer includes: forming a seed layer on the wafer; wherein the seed layer covers multiple chips and cutting paths; forming a photoresist layer on the seed layer, and forming multiple windows on the photoresist layer; wherein the windows correspond to the positions of each pad, the middle of the cutting path, and the position between the two nearest pads of adjacent chips; removing the seed layer exposed by the windows; and removing the photoresist layer to obtain a patterned seed layer.

[0007] After forming the first rewiring layer on the patterned seed layer, the method includes forming at least one new rewiring layer on the first rewiring layer; a dielectric layer is provided between adjacent rewiring layers, and adjacent rewiring layers are interconnected through vias provided on the dielectric layer.

[0008] The step of forming at least one new rewiring layer on the first rewiring layer includes: forming a first dielectric layer; wherein the first dielectric layer covers the first rewiring layer, the patterned seed layer and a side surface of the wafer; forming a plurality of first vias on the first dielectric layer to expose a portion of the first rewiring layer; forming a second rewiring layer; wherein the second rewiring layer covers the first rewiring layer and a portion of the first dielectric layer exposed at the first vias.

[0009] Among them, after the step of forming the second redistribution layer, it includes: forming a second dielectric layer; wherein the second dielectric layer covers the second redistribution layer and the first dielectric layer; forming multiple second vias on the second dielectric layer to expose part of the second redistribution layer; forming a third redistribution layer; wherein the third redistribution layer covers the second redistribution layer and part of the second dielectric layer exposed at the second vias.

[0010] Among them, the step of cutting the wafer based on the cutting line to obtain multiple packaged chips includes: cutting the wafer based on the middle of the cutting line to disconnect the main part of the second seed layer from the multiple branch parts to obtain multiple packaged chips.

[0011] In order to solve the above technical problems, the second technical solution adopted in this application is to provide a wafer-level chip packaging component, including: a wafer including multiple chips; wherein, multiple pads are arranged on one side surface of each chip; wherein, a cutting road is arranged between adjacent chips; a patterned seed layer, including multiple first seed layers covering multiple pads, and a second seed layer connecting the multiple first seed layers; wherein, the second seed layer includes a main part located in the cutting road and multiple branch parts intersecting with the main part, and the two ends of each branch part extend to the pads of the adjacent chip respectively; a first redistribution layer, arranged on the multiple first seed layers; wherein the first redistribution layer corresponds to the pads.

[0012] Among them, multiple chips are distributed in an array, and cutting lanes are set between each row or column of chips; among them, the trunk part of the second seed layer is located in the middle of the cutting lane, and the trunk part is in a checkerboard grid shape; the multiple branch parts of the second seed layer are in strip shape.

[0013] In order to solve the above technical problems, the third technical solution adopted in this application is to provide a chip packaging component, including: a wafer, a plurality of solder pads are arranged on one side surface of the wafer; a patterned seed layer, the patterned seed layer includes a plurality of first seed layers covering the plurality of solder pads and a plurality of branch parts of the second seed layer; wherein, one end of the branch part is connected to the first seed layer, and the other end extends to the edge of the wafer closest to the first seed layer; a first redistribution layer, arranged on the plurality of first seed layers; wherein the first redistribution layer corresponds to the solder pad.

[0014] The chip packaging assembly further includes: a first dielectric layer, covering the first redistribution layer, the patterned seed layer and one side surface of the chip; a plurality of first vias exposing a portion of the first redistribution layer are provided on the first dielectric layer; and a second redistribution layer, the second redistribution layer covering the first redistribution layer and a portion of the first dielectric layer exposed at the first vias.

[0015] The beneficial effects of the present application are as follows: Different from the prior art, the present application provides a chip packaging method, a wafer-level chip packaging component, and a chip packaging component. By forming a patterned seed layer on a wafer, a first redistribution layer can be formed at positions corresponding to multiple pads through a single electroplating process. Furthermore, since the trunk portion of the second seed layer is located within the dicing lane and the multiple branches of the second seed layer intersect with the trunk portion, the connection between the trunk portion and the multiple branches can be effectively disconnected by cutting the wafer based on the dicing lane. At the same time, since the ends of the multiple branches extend to the pads of adjacent chips, there is no direct connection between the multiple pads inside the chip. After the branches are disconnected from the trunk portion, the multiple pads inside the chip are also disconnected, which will not cause a short circuit in the packaged chip. Furthermore, since the residual seed layer can be removed by cutting the wafer after the first redistribution layer is formed, damage to the side of the first redistribution layer caused by wet etching can be avoided. Therefore, there is no need to reserve a side etching margin on the first redistribution layer, which can effectively reduce the line width of the first redistribution layer, thereby obtaining a first redistribution layer with a line width less than a set width. Through the above method, the present application can prepare a first redistribution layer with a smaller line width and higher yield, thereby effectively improving the packaging performance and yield of the packaged chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the example description. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 This is a flow chart of the first embodiment of the chip packaging method of the present application;

[0018] Figure 2 This is a schematic flow chart of a second embodiment of the chip packaging method of the present application;

[0019] Figure 3 is a schematic structural diagram of an embodiment of a wafer obtained in S21;

[0020] Figure 4 yes Figure 3 Schematic diagram of the enlarged structure of area A in the middle;

[0021] Figure 5 is a schematic structural diagram of an embodiment of a wafer obtained in S25;

[0022] Figure 6 yes Figure 5 Schematic diagram of the enlarged structure of area A in the middle;

[0023] Figure 7 yes Figure 6 Schematic diagram of the cross-section structure along line BB;

[0024] Figure 8 is a schematic cross-sectional structural diagram of an embodiment of the wafer obtained in S26;

[0025] Figure 9 Yes Figure 6 Schematic diagram of the wafer after cutting;

[0026] Figure 10 1 is a schematic cross-sectional view of a first embodiment of a chip packaging assembly of the present application;

[0027] Figure 11 It is a schematic cross-sectional structure diagram of the second embodiment of the chip packaging assembly of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0029] The terms used in the examples of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms "a," "the," and "the" used in the examples of this application and the appended claims are also intended to include plural forms. Unless otherwise clearly indicated above, "a plurality" generally includes at least two, but does not exclude the inclusion of at least one.

[0030] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0031] It should be understood that the terms "comprises," "comprising," or any other variations used herein are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0032] In one embodiment, wafer-level chips are generally packaged as a whole and then sliced into individual chips. However, existing technologies are unable to produce packaged chips with good performance.

[0033] Based on the above situation, the present application provides a chip packaging method, a wafer-level chip packaging component and a chip packaging component, which can solve the problem that packaged chips with good performance cannot be prepared in the above-mentioned embodiments.

[0034] The present application is described in detail below with reference to the accompanying drawings and implementation methods.

[0035] See also Figure 1 , Figure 1 FIG. 1 is a flow chart of a first embodiment of a chip packaging method of the present application. In this embodiment, the chip packaging method includes:

[0036] S11: A wafer including a plurality of chips is obtained, wherein a plurality of pads are provided on one surface of each chip; wherein dicing lanes are provided between adjacent chips.

[0037] In this embodiment, the wafer is a silicon wafer. The silicon wafer includes a plurality of chips, and adjacent chips are separated by cutting lines.

[0038] It can be understood that a wafer is an integration of multiple chips, and a single chip can be obtained by cutting the wafer along the cutting line.

[0039] One side surface of each chip is covered with a passivation layer, and a window exposing a plurality of pads is provided on the passivation layer, and the plurality of pads are not connected to each other.

[0040] S12: forming a patterned seed layer on the wafer; wherein the patterned seed layer includes a plurality of first seed layers covering a plurality of pads, and a second seed layer connecting the plurality of first seed layers; wherein the second seed layer includes a trunk portion located within the cutting path and a plurality of branch portions intersecting with the trunk portion, and both ends of each branch portion extend to the pads of adjacent chips respectively.

[0041] In this embodiment, the plurality of first seed layers cover the plurality of pads, and the orthographic projection area of the first seed layers is larger than the orthographic projection area of the pads.

[0042] In this embodiment, since the main part of the second seed layer is located in the cutting path, the multiple branch parts of the second seed layer intersect with the main part, and the two ends of the branch parts extend to the pads of the adjacent chips respectively, so no direct connection is formed between the multiple pads inside the chip.

[0043] In some implementations, both ends of each branch portion extend to two nearest pads of an adjacent chip, respectively, to reduce the connection path of the branch portion.

[0044] It can be understood that the multiple first seed layers are mainly connected through the second seed layers arranged in the cutting lanes and between adjacent chips, and no direct conductive path is formed between the multiple seed layers corresponding to the multiple pads inside the same chip.

[0045] In this embodiment, a seed layer is first formed on the entire surface of the wafer by sputtering, and then the seed layer is patterned by photolithography and etching to form a patterned seed layer with an entire surface being conductive.

[0046] Before forming the seed layer, an adhesion layer is formed on the surface of the wafer by sputtering, and then the seed layer is deposited on the surface of the adhesion layer.

[0047] Among them, the material types of the adhesion layer include titanium (Ti) and titanium tungsten (TiW), and the material types of the seed layer include copper (Cu), gold (Au), nickel (Ni), aluminum (Al), tin (Sn) and tin silver (SnAg), etc., and the material type of the seed layer is the same as the material type of the first redistribution layer formed by subsequent electroplating.

[0048] The thickness of the adhesion layer is 0.1-0.4 μm, and the thickness of the seed layer is 0.2-0.6 μm.

[0049] S13: forming a first redistribution layer on the patterned seed layer; wherein the first redistribution layer corresponds to the pad.

[0050] In this embodiment, the first redistribution layer is formed at a preset position of the conductive patterned seed layer by electroplating.

[0051] In this embodiment, the width of the first redistribution layer is smaller than the set width.

[0052] Here, the width is set to 5 μm.

[0053] S14: Cutting the wafer based on the cutting lines to obtain a plurality of packaged chips.

[0054] In this embodiment, the wafer is cut based on the cutting streets, so that the residual seed layer can be removed to avoid short circuits of multiple pads inside the packaged chip.

[0055] It can be understood that this embodiment forms a patterned seed layer before electroplating the first redistribution layer, and the entire surface of the patterned seed layer is conductively connected through a second seed layer disposed within the dicing lanes and between adjacent chips. After the first redistribution layer is formed, the wafer is diced to remove the main trunk portion of the second seed layer within the dicing lanes, thereby disconnecting the multiple branch portions from the main trunk portion. Since there is no direct connection between the multiple pads within the chip, disconnecting the branch portions from the main trunk portion also disconnects the multiple pads within the chip, preventing a short circuit in the packaged chip.

[0056] In other embodiments, the main process of the wafer-level rewiring process is as follows: first, a seed layer is sputtered and electroplated on the surface of the silicon wafer, and then a photoresist opening pattern is formed on the seed layer by a photolithography method, and then a rewiring layer is deposited in the photoresist opening by an electroplating method, and finally, the residual seed layer is removed by wet etching.

[0057] Since wet etching is isotropic, when removing the seed layer, the redistribution layer (RDL) will inevitably be etched from the side. The seed layer thickness is usually 0.2 to 0.6 μm. To ensure that there is no metal residue in the seed layer, the etching amount must be more than 1.5 times that of the metal layer, that is, the etching amount is 0.3 to 0.9 μm. This will result in 0.3 to 0.9 μm being etched off one side of the RDL, and the width of both sides will be reduced by a total of 0.6 to 1.8 μm. If the width of the RDL is less than 5 μm, this etching amount will cause the RDL to detach. Therefore, the RDL width in other implementations must exceed 5 μm.

[0058] Unlike other embodiments, this embodiment removes the residual seed layer that can cause short circuits by cutting the wafer after forming the first redistribution layer, eliminating the need for wet etching. This avoids damage to the sides of the first redistribution layer caused by wet etching, and eliminates the need to reserve side etching margins on the first redistribution layer. This effectively reduces the line width of the first redistribution layer, resulting in a first redistribution layer with a line width of less than 5μm. Through the above-described method, the present application can prepare a first redistribution layer with a smaller line width and higher yield, thereby effectively improving the packaging performance and yield of the packaged chip.

[0059] See also Figure 2 , Figure 2 FIG. 1 is a flow chart of a second embodiment of the chip packaging method of the present application. In this embodiment, the chip packaging method includes:

[0060] S21: A wafer including a plurality of chips is obtained, wherein a plurality of pads are provided on one surface of each chip; wherein dicing lanes are provided between adjacent chips.

[0061] In this embodiment, the plurality of chips are distributed in an array, and the dicing lanes are provided between each row or column of chips.

[0062] Specifically, see Figure 3 and Figure 4 , Figure 3 is a schematic structural diagram of an embodiment of a wafer obtained in S21, Figure 4 yes Figure 3 Schematic diagram of the enlarged structure of area A in the middle.

[0063] In this embodiment, the wafer 100 includes a plurality of chips 10 distributed in an array, a cutting path 20 is provided between each row or column of chips 10, a plurality of pads 11 are provided on one surface of each chip 10, and a passivation layer (not shown) is provided between the plurality of pads 11.

[0064] In this embodiment, there is no limit on the number of chips 10 included in the wafer 100, and there is no limit on the number of pads 11 provided on each chip 10. In some embodiments, each chip 10 may be provided with four pads 11. In other embodiments, each chip 10 may be provided with six, eight, or another number of pads 11.

[0065] S22: forming a seed layer on the wafer; wherein the seed layer covers the plurality of chips and the dicing streets.

[0066] In this embodiment, a physical vapor deposition (PVD) method is used to sequentially deposit an adhesion layer and a seed layer on the wafer surface.

[0067] S23: forming a photoresist layer on the seed layer, and forming a plurality of openings on the photoresist layer; wherein the openings correspond to positions of each pad, the middle of the dicing lane, and the area between the two nearest pads of adjacent chips.

[0068] In this embodiment, a photoresist is coated on the seed layer to form a photoresist layer, and a plurality of openings are formed on the photoresist layer by exposure and development.

[0069] S24: removing the seed layer exposed by the window.

[0070] In this embodiment, the seed layer and the adhesion layer exposed by the opening are removed by etching.

[0071] The etching may be dry etching or wet etching, which is not limited in this application.

[0072] S25: removing the photoresist layer to obtain a patterned seed layer; wherein the patterned seed layer includes a plurality of first seed layers covering a plurality of pads, and a second seed layer connecting the plurality of first seed layers; wherein the second seed layer includes a main portion located within the cutting path and a plurality of branch portions intersecting with the main portion, and both ends of each branch portion extend to the pads of an adjacent chip respectively.

[0073] In this embodiment, the photoresist layer is removed to obtain a patterned seed layer and an adhesion layer.

[0074] In some implementations, both ends of each branch portion extend to two nearest pads of an adjacent chip, respectively, to reduce the connection path of the branch portion.

[0075] Specifically, see Figure 5 、 Figure 6 and Figure 7 , Figure 5 is a schematic structural diagram of an embodiment of a wafer obtained in S25, Figure 6 yes Figure 5 Schematic diagram of the enlarged structure of area A in the middle. Figure 7 yes Figure 6 Schematic diagram of the cross-sectional structure along line BB.

[0076] In this embodiment, a patterned seed layer 30 and a patterned adhesion layer 40 are formed on the wafer 100. The patterned seed layer 30 is used to cover and connect multiple pads 11. The patterned seed layer 30 includes multiple first seed layers 31 covering the multiple pads 11, and a second seed layer 32 connecting the multiple first seed layers 31. The second seed layer 32 includes a main portion 321 located within the dicing street 20 and multiple branch portions 322 intersecting with the main portion 321. The two ends of each branch portion 322 extend to the two nearest pads 11 of the adjacent chip 10.

[0077] Furthermore, in this embodiment, the main portion 321 of the second seed layer 32 is located in the middle of the dicing street 20. It is understood that in order to avoid damaging the chip 10 during dicing, dicing is usually performed from the middle of the dicing street 20 to leave margins on both sides. Positioning the main portion 321 in the middle of the dicing street 20 ensures that the main portion 321 is removed during subsequent dicing.

[0078] In this embodiment, the plurality of chips 10 are distributed in an array, and the dicing lanes 20 arranged between each row or column of the chips 10 are in a checkerboard grid shape, so the main portion 321 of the second seed layer 32 is also in a checkerboard grid shape.

[0079] In this embodiment, the plurality of branch portions 322 of the second seed layer 32 are in a strip shape.

[0080] In this embodiment, the branch portion 322 is perpendicular to the intersecting trunk portion 321 .

[0081] In other embodiments, the branch portion 322 and the intersecting trunk portion 321 may also be at other angles, which is not limited in this application.

[0082] S26: forming a first redistribution layer on the patterned seed layer; wherein the first redistribution layer corresponds to the pad.

[0083] In this embodiment, photoresist is coated on the patterned seed layer and the exposed wafer surface to form a photoresist layer, and a plurality of first openings are formed on the photoresist layer by exposure and development, etc. The plurality of first openings correspond to the plurality of bonding pads.

[0084] Furthermore, the wafer is electroplated to deposit a first redistribution layer in the plurality of opening windows.

[0085] The material of the first redistribution layer may be one of Cu, Au, Ni, Al, Sn, and SnAg, which is not limited in this application.

[0086] In this embodiment, the width of the first redistribution layer is smaller than the set width.

[0087] Here, the width is set to 5 μm.

[0088] Furthermore, after the electroplating is completed, the photoresist is removed by a wet stripping process.

[0089] Specifically, see Figure 8 , Figure 8 : is a schematic diagram of the cross-sectional structure of an embodiment of the wafer obtained in S26. In this embodiment, the wafer 100 includes a plurality of chips 10 distributed in an array, and a plurality of pads 11 are provided on one side surface of each chip 10. A patterned seed layer 30 and a patterned adhesion layer 40 are formed on the wafer 100. The patterned seed layer 30 is used to cover and conduct the plurality of pads 11. Among them, a first redistribution layer 50 is provided on the patterned seed layer 30, and the first redistribution layer 50 corresponds to the pads 11.

[0090] S27: forming at least one new redistribution layer on the first redistribution layer; wherein a dielectric layer is provided between adjacent redistribution layers, and adjacent redistribution layers are interconnected through vias provided in the dielectric layer.

[0091] In this embodiment, the step of forming at least one new redistribution layer on the first redistribution layer includes: forming a first dielectric layer; wherein the first dielectric layer covers the first redistribution layer, the patterned seed layer, and a side surface of the wafer; forming a plurality of first vias on the first dielectric layer to expose a portion of the first redistribution layer; forming a second redistribution layer; wherein the second redistribution layer covers the first redistribution layer and a portion of the first dielectric layer exposed at the first vias.

[0092] Specifically, photoresist is applied to the first redistribution layer, the patterned seed layer, and one side of the wafer to form a first dielectric layer. Multiple first vias are then formed in the first dielectric layer through exposure and development. Photoresist is then applied to the first dielectric layer, and multiple second openings are formed in the photoresist, with the orthographic projections of the first vias located within the orthographic projections of the second openings. The wafer is then electroplated to deposit metal within the second openings and the first vias to form a second redistribution layer, and the photoresist applied to the first dielectric layer is removed.

[0093] Furthermore, after forming the second redistribution layer, it also includes: forming a second dielectric layer; wherein the second dielectric layer covers the second redistribution layer and the first dielectric layer; forming a plurality of second vias on the second dielectric layer to expose a portion of the second redistribution layer; forming a third redistribution layer; wherein the third redistribution layer covers the second redistribution layer and a portion of the second dielectric layer exposed at the second vias.

[0094] It can be seen from the above steps that in this embodiment, there is no need to sputter the adhesion layer and the seed layer again. A new redistribution layer can be prepared by repeating the steps of coating, photolithography, development, electroplating, and desizing on the first redistribution layer.

[0095] In other embodiments, before forming each new redistribution layer, an adhesion layer and a seed layer are sputtered across the entire surface of the wafer, so that full-surface conductivity is achieved through the adhesion layer and the seed layer when the new redistribution layer is electroplated. This is because after each redistribution layer is formed, the residual seed layer is removed by wet etching to prevent chip short circuits. This means that only the seed layer corresponding to the redistribution layer remains, and full-surface conductivity is not achieved between the remaining seed layers. After the dielectric layer is formed, if the adhesion layer and the seed layer are not re-sputtered on the surface of the dielectric layer, without a metal film that is fully conductive, electroplating of the multiple openings on the dielectric layer is impossible.

[0096] Unlike other embodiments, this embodiment forms a patterned seed layer on the wafer surface before forming the first redistribution layer, and the patterned seed layer itself is in a checkerboard grid pattern, which can achieve full-surface conduction. Before cutting, even if a dielectric layer is formed on the first redistribution layer, the patterned seed layer, and one side of the wafer, it will not affect the full-surface conduction effect of the patterned seed layer, so there is no need to re-sputter a metal film on the dielectric layer. In this way, the present application can achieve the preparation of multiple redistribution layers by sputtering a seed layer once, thereby saving the preparation cost of multiple sputtering.

[0097] S28: Cutting the wafer based on the middle of the cutting line to disconnect the trunk portion of the second seed layer from the multiple branch portions, thereby obtaining multiple packaged chips.

[0098] In this embodiment, the wafer is cut based on the middle of the cutting street, which can avoid damaging the edge of the chip while ensuring the removal of the residual seed layer.

[0099] Specifically, see Figure 9 , Figure 9 Yes Figure 6 Schematic diagram of the wafer after cutting. In this embodiment, after cutting, the trunk portion of the second seed layer used to achieve the full-surface conduction function is removed, and the trunk portion is disconnected from the branch portions of the second seed layer retained on multiple chips. Since there is no direct connection between the multiple pads inside the chip, after the branch portions are disconnected from the trunk portion, the multiple pads inside the chip are also disconnected, which will not cause a short circuit in the packaged chip.

[0100] Correspondingly, the present application provides a chip packaging assembly.

[0101] See also Figure 10 , Figure 10 Schematic diagram of the cross-sectional structure of the first embodiment of the chip package assembly of the present application. In this embodiment, the chip package assembly 200 includes a wafer 100, a bonding pad 11 disposed on one side of the wafer 100, a patterned seed layer 30 covering the bonding pad, and a first redistribution layer 50 disposed on the patterned seed layer 30.

[0102] A patterned adhesion layer 40 is disposed between the patterned seed layer 30 and the pad 11 .

[0103] In this embodiment, the patterned seed layer 30 includes a plurality of first seed layers (not shown) covering the plurality of pads 11 and a plurality of branch portions (not shown) of the second seed layer.

[0104] One end of the branch portion is connected to the first seed layer, and the other end extends to the edge of the wafer closest to the first seed layer.

[0105] The first redistribution layer 50 corresponds to the pad 11 .

[0106] In some embodiments, the width of the first redistribution layer 50 is smaller than a set width, wherein the set width is 5 μm.

[0107] It can be understood that in this embodiment, after the first redistribution layer 50 is formed, the residual seed layer 30 that may cause a short circuit can be removed by cutting the wafer without the need for wet etching, thereby avoiding damage to the side of the first redistribution layer 50 caused by wet etching. Therefore, the prepared first redistribution layer 50 does not need to reserve a side etching margin, thereby obtaining a first redistribution layer 50 with a line width of less than 5μm.

[0108] See also Figure 11 , Figure 11 FIG2 is a schematic cross-sectional view of a second embodiment of a chip package assembly of the present application. In this embodiment, the chip package assembly 300 includes a wafer 100, a bonding pad 11 disposed on one side of the wafer 100, a patterned seed layer 30 covering the bonding pad, a first redistribution layer 50 disposed on the patterned seed layer 30, and a second redistribution layer 70 disposed on the first redistribution layer 50.

[0109] Among them, a first dielectric layer 60 is arranged between the first redistribution layer 50 and the second redistribution layer 70, and a plurality of first vias 61 exposing part of the first redistribution layer 50 are arranged on the first dielectric layer 60. The second redistribution layer 70 covers the first redistribution layer 50 and part of the first dielectric layer 60 exposed at the first vias 61, so as to achieve electrical connection with the first redistribution layer 50 through the first vias 61.

[0110] It can be understood that the chip packaging component 300 in this embodiment only includes a patterned seed layer 30 arranged below the first redistribution layer 50, and no seed layer is sputtered between the first redistribution layer 50 and the second redistribution layer 70, thereby reducing the preparation cost of the seed layer.

[0111] It can be understood that the present application forms a patterned seed layer on the wafer, and can form a first redistribution layer at positions corresponding to multiple pads by a single electroplating. Furthermore, since the trunk portion of the second seed layer is located within the cutting path, and the multiple branch portions of the second seed layer intersect with the trunk portion, the wafer is cut based on the cutting path, which can effectively disconnect the trunk portion from the multiple branch portions. At the same time, since the two ends of the multiple branch portions extend to the two nearest pad chips of the adjacent chip, no direct connection is formed between the multiple pads inside the chip. After disconnecting the branch portion from the trunk portion, the multiple pads inside the chip are also disconnected, which will not cause a short circuit in the packaged chip. Furthermore, since the residual seed layer can be removed by cutting the wafer after the first redistribution layer is formed, damage to the side of the first redistribution layer caused by wet etching can be avoided. Therefore, there is no need to reserve a side etching margin on the first redistribution layer, which can effectively reduce the line width of the first redistribution layer, thereby obtaining a first redistribution layer with a line width less than a set width. Through the above method, the present application can prepare a first redistribution layer with a smaller line width and higher yield, thereby effectively improving the packaging performance and yield of the packaged chip.

[0112] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A chip packaging method, characterized in that: include: A wafer including a plurality of chips is obtained, wherein a plurality of pads are provided on one surface of each chip; wherein dicing lanes are provided between adjacent chips; the plurality of chips are arranged in an array, and the dicing lanes are provided between each row or column of the chips; Forming a patterned seed layer on the wafer specifically includes: forming a seed layer on the wafer; wherein the seed layer covers the plurality of chips and the cutting path; forming a photoresist layer on the seed layer, and forming a plurality of openings on the photoresist layer; wherein the openings correspond to the positions of each of the pads, the middle of the cutting path, and the position between the two nearest pads of the adjacent chips; removing the seed layer exposed by the openings; removing the photoresist layer to obtain the patterned seed layer; wherein the patterned seed layer includes a plurality of first seed layers covering the plurality of pads, and a second seed layer connecting the plurality of first seed layers; wherein the second seed layer includes a main trunk portion located in the cutting path and a plurality of branch portions intersecting with the main trunk portion, and both ends of each branch portion extend to the pads of the adjacent chips respectively; the main trunk portion of the second seed layer is located in the middle of the cutting path, and the main trunk portion is in the shape of a checkerboard grid; the plurality of branch portions of the second seed layer are in the shape of strips; the branch portions are perpendicular to the intersecting main trunk portions; forming a first redistribution layer on the patterned seed layer; wherein the first redistribution layer corresponds to the pad; After the step of forming a first redistribution layer on the patterned seed layer, the method further comprises: forming at least one new rewiring layer on the first rewiring layer; wherein a dielectric layer is provided between adjacent rewiring layers, and adjacent rewiring layers are interconnected through vias provided on the dielectric layer; the new rewiring layer covers the first rewiring layer and a portion of the dielectric layer exposed at the vias; The wafer is cut based on the cutting path to obtain a plurality of packaged chips, including: cutting the wafer based on the middle of the cutting path to disconnect the trunk portion of the second seed layer from the plurality of branch portions to obtain a plurality of packaged chips.

2. The chip packaging method according to claim 1, wherein: The step of forming at least one new redistribution layer on the first redistribution layer comprises: forming a first dielectric layer; wherein the first dielectric layer covers the first redistribution layer, the patterned seed layer, and a side surface of the wafer; forming a plurality of first via holes on the first dielectric layer to expose a portion of the first redistribution layer; A second redistribution layer is formed; wherein the second redistribution layer covers the first redistribution layer and a portion of the first dielectric layer exposed at the first via hole.

3. The chip packaging method according to claim 2, wherein: After the step of forming the second redistribution layer, the method further comprises: forming a second dielectric layer; wherein the second dielectric layer covers the second redistribution layer and the first dielectric layer; forming a plurality of second via holes on the second dielectric layer to expose a portion of the second redistribution layer; A third redistribution layer is formed; wherein the third redistribution layer covers the second redistribution layer and a portion of the second dielectric layer exposed at the second via hole.

4. A wafer-level chip packaging assembly, characterized in that: include: A wafer comprising a plurality of chips; wherein a plurality of pads are provided on one surface of each chip; wherein dicing lanes are provided between adjacent chips; wherein the plurality of chips are arranged in an array, and the dicing lanes are provided between each row or column of the chips; A patterned seed layer, comprising a plurality of first seed layers covering a plurality of the pads, and a second seed layer connecting the plurality of the first seed layers; wherein the second seed layer comprises a trunk portion located within the cutting path and a plurality of branch portions intersecting the trunk portion, and both ends of each branch portion respectively extend to the pads of the adjacent chips; wherein the patterned seed layer is formed by removing the seed layer exposed at the opening, and the opening corresponds to the position between each pad, the middle of the cutting path, and the nearest two pads of the adjacent chips; wherein the trunk portion of the second seed layer is located in the middle of the cutting path, and the trunk portion is in the shape of a checkerboard grid; and the plurality of branch portions of the second seed layer are in the shape of strips; A first redistribution layer is provided on the plurality of first seed layers; wherein the first redistribution layer corresponds to the pads; a dielectric layer covering the first redistribution layer, the patterned seed layer, and a surface of one side of the chip; wherein the dielectric layer is provided with a plurality of vias exposing a portion of the first redistribution layer; A new redistribution layer is formed, where the new redistribution layer covers the first redistribution layer and a portion of the dielectric layer exposed at the via hole.

5. A chip packaging assembly, characterized in that: include: A wafer, wherein a plurality of pads are provided on one side surface of the wafer; a patterned seed layer, the patterned seed layer comprising a plurality of first seed layers covering the plurality of pads and a plurality of branch portions of a second seed layer; wherein one end of the branch portion is connected to the first seed layer and the other end extends to the wafer edge closest to the first seed layer; wherein the patterned seed layer is formed by removing the seed layer exposed at an opening, the opening corresponding to the position between each pad and the nearest two pads of the adjacent chip; the plurality of branch portions of the second seed layer are strip-shaped; A first redistribution layer is provided on the plurality of first seed layers; wherein the first redistribution layer corresponds to the pads; a first dielectric layer covering the first redistribution layer, the patterned seed layer, and a surface of one side of the chip; wherein the first dielectric layer is provided with a plurality of first vias exposing a portion of the first redistribution layer; A second redistribution layer covers the first redistribution layer and a portion of the first dielectric layer exposed at the first via hole.

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