Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, the method comprising: providing a substrate, the substrate having a stack structure formed thereon, the stack structure comprising one or more channel stacks stacked in sequence from bottom to top, each channel stack comprising a placeholder layer and a channel layer on the placeholder layer, the substrate further having a dummy gate structure formed thereon, the dummy gate structure spanning across the stack structure and covering part of the top and part of the sidewall of the stack structure; forming a recess through the stack structure on both sides of the dummy gate structure; removing a part of the length of the placeholder layer exposed by the sidewall of the recess along the extension direction of the channel layer to form an inner trench; forming an inner spacer material layer on the sidewall of the dummy gate structure and on the sidewall of the recess, the inner spacer material layer also filling in the inner trench; and performing a modification treatment on the inner spacer material layer outside the inner trench for converting the inner spacer material layer into a sacrificial layer, the sacrificial layer having an etching selectivity ratio with the inner spacer material layer and the channel layer. The embodiments of the present application are beneficial to the performance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] As semiconductor process technology advances, semiconductor process nodes continue to shrink, following Moore's Law. To adapt to the shrinking process nodes, the channel length of MOSFETs is also continuously shortening. However, as the channel length shortens, the distance between the source and drain also decreases, resulting in a decrease in the gate's control over the channel.

[0003] Therefore, in order to better adapt to the requirement of proportionally shrinking device size, semiconductor processes have gradually begun to transition from planar MOSFET transistors to three-dimensional transistors with higher efficiency, such as FinFETs. In FinFETs, the gate can be controlled from at least two sides of the ultrathin body (fin), providing much stronger gate-channel control capability than planar MOSFET devices.

[0004] However, the performance of semiconductor structures formed by existing technologies needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to improving the performance of semiconductor devices.

[0006] To address the aforementioned problems, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a stacked structure is formed on the substrate, the stacked structure including one or more channel stacks stacked sequentially from bottom to top, the channel stack including a placeholder layer and a channel layer located on the placeholder layer, a dummy gate structure is further formed on the substrate, the dummy gate structure spanning the stacked structure and covering a portion of the top and a portion of the sidewalls of the stacked structure; forming grooves penetrating the stacked structure on both sides of the dummy gate structure; and extending along the channel layer... The occupant layer, extending a portion of its length and exposed on the sidewall of the groove, is removed to form an inner trench. An inner sidewall material layer is formed on the sidewall of the pseudo-gate structure and the sidewall of the groove, and this inner sidewall material layer also fills the inner trench. The inner sidewall material layer outside the inner trench is modified to transform it into a sacrificial layer, wherein the sacrificial layer, the inner sidewall material layer, and the trench layer all have an etching selectivity ratio. The sacrificial layer is then removed, leaving the remaining inner sidewall material layer within the inner trench as the inner sidewall.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the semiconductor structure formation method provided by this invention, the inner sidewall material layer outside the inner trench is modified to transform the inner sidewall material layer into a sacrificial layer. The sacrificial layer, the inner sidewall material layer, and the channel layer all have an etching selectivity ratio. This reduces the probability of damage to the remaining inner sidewall material layer and the channel layer located in the inner trench when the sacrificial layer is subsequently removed, thereby helping to ensure the integrity of the inner sidewall and the channel layer. In addition, it improves the morphological quality and width uniformity of the formed inner sidewall, and correspondingly improves the performance of the semiconductor device. Attached Figure Description

[0009] Figures 1 to 8 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0010] Figures 9 to 17 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0011] As the background technology shows, the performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using a semiconductor structure formation method as an example. Figures 1 to 8 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] refer to Figure 1 A substrate (not shown) is provided on which a stacked structure 610 is formed. The stacked structure 610 includes one or more channel stacks 605 stacked sequentially from bottom to top. The channel stacks 605 include a placeholder layer 603 and a channel layer 604 located on the placeholder layer 603. A pseudo-gate structure 608 is also formed on the substrate. The pseudo-gate structure 608 spans the stacked structure 610 and covers a portion of the top and a portion of the sidewalls of the stacked structure 610.

[0013] refer to Figure 2 Grooves 666 are formed on both sides of the pseudo-gate structure 608, penetrating the stacked structure 610.

[0014] refer to Figure 3 After the groove 666 is formed, a portion of the occupant layer 604 exposed on the sidewall of the groove 666 is removed along the extension direction of the channel layer 604 to form an inner groove 688.

[0015] refer to Figure 4 An inner sidewall material layer 633 is formed on the sidewall of the pseudo-gate structure 608 and the sidewall of the groove 666, and the inner sidewall material layer 633 is also filled in the inner groove 688.

[0016] refer to Figure 5 Remove the inner wall material layer 633 outside the inner trench 688 to expose the end of the trench layer 604 along its extension direction, and retain the remaining inner wall material layer 633 filled in the inner trench 688 as the inner wall 635.

[0017] refer to Figure 6 After the inner sidewall 635 is formed, a source / drain doped layer 699 is formed in the groove 666, and the source / drain doped layer 699 is in contact with the end of the channel layer 604 along its extension direction.

[0018] refer to Figure 7 After the source / drain doped layer 699 is formed, an interlayer dielectric layer 698 is formed on the substrate on the side of the pseudo-gate structure 608, and the interlayer dielectric layer 698 covers the source / drain doped layer 699.

[0019] refer to Figure 8 The pseudo-gate structure 608 is removed to form a gate opening (not shown); the occupier layer 603 is removed through the gate opening to form a through-slot (not shown), the through-slot being surrounded by adjacent channel layers 604, or by adjacent channel layers 604 and a substrate; a gate structure 655 is formed in the gate opening and the through-slot, the gate structure 655 surrounding the channel layer 604.

[0020] In the step of removing the inner sidewall material layer 633 outside the inner trench 688 to expose the end of the channel layer 604 along the extension direction, since the etching selectivity between the material of the channel layer 604 and the material of the inner sidewall material layer 633 is relatively small, the channel layer 604 is easily etched by mistake during the removal of part of the inner sidewall material layer 633, which reduces the integrity of the channel layer 604 and, correspondingly, reduces the performance of the semiconductor device.

[0021] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a stacked structure is formed on the substrate, the stacked structure including one or more channel stacks stacked sequentially from bottom to top, the channel stack including a placeholder layer and a channel layer located on the placeholder layer, a dummy gate structure is also formed on the substrate, the dummy gate structure spanning the stacked structure and covering a portion of the top and a portion of the sidewalls of the stacked structure; forming grooves penetrating the stacked structure on both sides of the dummy gate structure; and extending along the channel layer... In the direction of the groove, a portion of the exposed length of the occupant layer is removed to form an inner trench; an inner sidewall material layer is formed on the sidewall of the pseudo-gate structure and the sidewall of the groove, and the inner sidewall material layer also fills the inner trench; the inner sidewall material layer outside the inner trench is modified to transform the inner sidewall material layer into a sacrificial layer, and the sacrificial layer, the inner sidewall material layer, and the trench layer all have an etching selectivity ratio; the sacrificial layer is removed, and the remaining inner sidewall material layer located in the inner trench is retained as the inner sidewall.

[0022] In the semiconductor structure formation method provided by this invention, the inner sidewall material layer outside the inner trench is modified to transform the inner sidewall material layer into a sacrificial layer. The sacrificial layer, the inner sidewall material layer, and the channel layer all have an etching selectivity ratio. This reduces the probability of damage to the remaining inner sidewall material layer and the channel layer located in the inner trench when the sacrificial layer is subsequently removed, thereby helping to ensure the integrity of the inner sidewall and the channel layer. In addition, it improves the morphological quality and width uniformity of the formed inner sidewall, and correspondingly improves the performance of the semiconductor device.

[0023] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Figures 9 to 17 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0024] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

[0025] refer to Figure 9 A substrate (not shown) is provided on which a stacked structure 810 is formed. The stacked structure 810 includes one or more channel stacks 810 stacked sequentially from bottom to top. The channel stack 810 includes a placeholder layer 803 and a channel layer 804 located on the placeholder layer 803. A pseudo-gate structure 808 is also formed on the substrate. The pseudo-gate structure 808 spans the stacked structure 810 and covers part of the top and part of the sidewalls of the stacked structure 810.

[0026] In this embodiment, a gate-all-around (GAA) transistor is used as an example of the semiconductor structure. In other embodiments, the semiconductor structure may also be other types of transistors such as forksheet transistors.

[0027] In this embodiment, in the step of providing the substrate, the substrate includes a substrate (not shown) and a fin 801 located on the substrate, and the stacked structure 810 is located on top of the fin 801.

[0028] The substrate serves as a process platform for the formation of semiconductor structures. In this embodiment, the substrate is a silicon substrate, meaning the substrate material is single-crystal silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium dihydrogen nitride. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0029] The fin 801 serves to provide support for the stacked structure 810. In this embodiment, the fin 801 and the substrate are an integral structure, and the material of the fin 801 is the same as that of the substrate, which is silicon. In other embodiments, the material of the protrusion may be different from that of the substrate. The material of the protrusion may be other suitable materials, such as one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0030] The channel stack 805 provides a process basis for the subsequent formation of the channel layer 804 and the gate structure enclosing the channel layer 804. In this embodiment, the number of channel stacks 805 is 3; in other embodiments, the number of channel stacks 805 may be other numbers.

[0031] The channel layer 804 is used to provide a conductive channel for the transistor. The placeholder layer 803 is used to support the channel layer 804, thereby providing a process basis for the subsequent implementation of the spaced floating arrangement of the channel layer 804. The placeholder layer 803 is also used to occupy space for the subsequent formation of the gate structure that encloses the channel layer 804.

[0032] In this embodiment, an NMOS transistor is formed, with the channel layer 804 made of Si and the placeholder layer 803 made of SiGe. During the subsequent removal of the placeholder layer 803, the etching selectivity for SiGe and Si is relatively high. By setting the material of the placeholder layer 803 to SiGe and the material of the channel layer 804 to Si, the impact of the placeholder layer 803 removal process on the channel layer 804 can be effectively reduced, thereby improving the quality of the channel layer 804 and ultimately contributing to improved device performance.

[0033] The dummy gate structure 808 is used to pre-reserve space for the subsequent formation of the gate structure. Specifically, the dummy gate structure 808 is a polysilicon gate structure or an amorphous silicon gate structure.

[0034] The dummy gate structure 808 can be a stacked structure or a single-layer structure. In this embodiment, the dummy gate structure 808 is a stacked structure, including a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) located on the dummy gate oxide layer. The material of the dummy gate oxide layer can be silicon oxide or silicon oxynitride, and the material of the dummy gate layer can be polycrystalline silicon or amorphous silicon.

[0035] Specifically, the steps for forming the pseudo-gate structure 808 include: forming a pseudo-gate structure material layer (not shown) on the fin 801; forming a patterned gate mask layer 821 on the pseudo-gate structure material layer; using the gate mask layer 821 as a mask, etching the pseudo-gate structure material layer to expose part of the top wall of the stacked structure 810, with the remaining pseudo-gate structure material layer serving as the pseudo-gate structure 808.

[0036] The gate mask layer 821 is used as a mask in the process of forming the pseudo gate structure 808.

[0037] In this embodiment, the gate mask layer 821 has a stacked structure, comprising a silicon nitride layer (not shown) and a silicon oxide layer (not shown) located on the silicon nitride layer. In other embodiments, the gate mask layer may also be a single-layer structure.

[0038] In this embodiment, during the step of providing the substrate, the sidewalls of the pseudo-gate structure 808 are formed with gate sidewalls 809.

[0039] The gate sidewall 809 serves as an etching mask for subsequent etching processes that form grooves, and also protects the dummy gate structure 808. In this embodiment, the material of the gate sidewall 809 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate, silicon carbonitride, boron nitride, and boron carbonitride. As an example, the material of the gate sidewall 809 is silicon nitride.

[0040] In this embodiment, the gate sidewall 809 also covers the top of the exposed stacked structure 810 and the top of the dummy gate structure 808.

[0041] refer to Figure 10 Grooves 811 are formed on both sides of the pseudo-gate structure 808, penetrating the stacked structure 810.

[0042] The groove 811 is used to provide space for the subsequent formation of source and drain doped layers.

[0043] Specifically, in this embodiment, an anisotropic etching process (e.g., anisotropic dry etching process) is used to etch the stacked structure 810 on both sides of the pseudo gate structure 808, which is beneficial to improve the cross-sectional morphology quality of the groove 811, thereby facilitating precise control of the sidewall morphology of the groove 811.

[0044] It should be noted that before etching the stacked structures 810 on both sides of the dummy gate structure 808, the process also includes etching away the top of the dummy gate structure 808 and the gate sidewalls 809 on the stacked structures.

[0045] Correspondingly, using the gate sidewall 809 on the sidewall of the pseudo gate structure 808 as a mask, the stacked structure 810 on both sides of the pseudo gate structure 808 is etched to form a groove 811.

[0046] refer to Figure 11 Along the extending direction of the channel layer 804, a portion of the occupant layer 803 exposed on the sidewall of the groove 811 is removed to form an inner groove 812.

[0047] The inner groove 812 provides space for the subsequent formation of the inner sidewall.

[0048] In this embodiment, a vapor etching process is used to etch a portion of the exposed width of the occupant layer 803 along the extension direction of the channel layer 804. Vapor etching is an isotropic etching process that can etch the occupant layer 803 along the extension direction of the channel layer 804. Furthermore, vapor etching easily achieves a large etching selectivity, which helps reduce the difficulty of etching the occupant layer 803 and reduces the probability of damage to other film structures (e.g., the channel layer 804).

[0049] In this embodiment, the material of the occupant layer 803 is SiGe, and the material of the channel layer 804 is Si. The occupant layer 803 on the sidewall of the groove 811 is etched by HCl vapor. The etching rate of HCl vapor on SiGe material is much greater than that on Si material, which can effectively reduce the probability of damage to the channel layer 804.

[0050] refer to Figure 12 An inner sidewall material layer 830 is formed on the sidewall of the pseudo-gate structure 808 and the sidewall of the groove 811, and the inner sidewall material layer 830 is also filled in the inner groove 812.

[0051] The inner wall material layer 830 is used for the subsequent formation of the inner wall.

[0052] Specifically, an inner sidewall material layer 830 is formed on the sidewall of the pseudo-gate structure 808 and the sidewall of the groove 811 by atomic layer deposition (ALD). The atomic layer deposition process has good step coverage, resulting in a high-quality inner sidewall material layer 830 with high thickness uniformity.

[0053] It should be noted that since a gate sidewall 809 is formed on the sidewall of the dummy gate structure 808, the inner sidewall material layer 830 on the sidewall of the dummy gate structure 808 covers the gate sidewall 809.

[0054] In this embodiment, in the step of forming the inner wall material layer 830, the material of the inner wall material layer 830 is one or more of silicon nitride and low-k dielectric materials. Here, a low-k dielectric material refers to a material with a dielectric constant k less than 3.9. The low-k dielectric material includes: silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the inner wall material layer is silicon nitride.

[0055] refer to Figure 13 The inner wall material layer 830 outside the inner trench 812 is modified to transform the inner wall material layer 830 into a sacrificial layer 875. The sacrificial layer 875, the inner wall material layer 830, and the trench layer 804 all have an etching selectivity ratio.

[0056] In this embodiment, the inner sidewall material layer 830 outside the inner trench 812 is modified to transform it into a sacrificial layer 875. The sacrificial layer 875, the inner sidewall material layer 830, and the trench layer 804 all have an etching selectivity ratio. This reduces the probability of damage to the remaining inner sidewall material layer 830 and the trench layer 804 located in the inner trench 812 when the sacrificial layer 875 is subsequently removed. This helps to ensure the integrity of the inner sidewall and the trench layer 804. In addition, it improves the morphological quality and width uniformity of the formed inner sidewall, thereby improving the performance of the semiconductor device.

[0057] The sacrificial layer 875 is to be removed subsequently, thereby retaining the remaining inner wall material layer 830 located in the inner trench 812 as the inner wall.

[0058] In this embodiment, the sacrificial layer 875, the inner wall material layer 830, and the channel layer 804 all have an etching selectivity ratio, which is beneficial for selectively removing the sacrificial layer 875 in the future. This reduces the probability of damage to the remaining inner wall material layer 830 and the channel layer 804 located in the inner trench 812, thereby helping to ensure the integrity of the inner wall and the channel layer 804.

[0059] In this embodiment, before modifying the inner wall material layer 830 outside the inner groove 812, the method further includes obtaining a preset thickness A of the inner wall material layer 830 located on the sidewall of the pseudo-grid structure 808.

[0060] In this embodiment, the preset thickness A is the thickness of the inner wall material layer 830 on the side wall of the pseudo-grid structure 808.

[0061] The preset thickness A of the inner wall material layer 830 located on the sidewall of the pseudo-gate structure 808 is obtained, which is beneficial to select the parameters for subsequent modification processing based on the preset thickness A of the inner wall material layer 830, and then perform targeted modification processing on the inner wall material layer 830 with the preset thickness.

[0062] In this embodiment, the method for obtaining the preset thickness A of the inner wall material layer 830 located on the sidewall of the pseudo-gate structure 808 is the optical feature dimension (OCD) measurement method, which is beneficial for obtaining the preset thickness of the inner wall material layer 830 with high accuracy.

[0063] In this embodiment, the step of modifying the inner wall material layer 830 outside the inner groove 812 includes: modifying the inner wall material layer 830 of a preset thickness outside the inner groove 812.

[0064] The inner wall material layer 830 of a predetermined thickness outside the inner groove 812 is modified so that only the remaining inner wall material layer 830 located inside the inner groove 812 is retained subsequently.

[0065] In this embodiment, the preset thickness A of the inner wall material layer 830 on the sidewall of the pseudo-grid structure 808 is equal to the preset thickness of the outer sidewall of the inner groove 812, so that the inner wall material layer 830 of the preset thickness outside the inner groove 812 can be modified according to the preset thickness of the inner wall material layer 830 on the sidewall of the pseudo-grid structure 808.

[0066] It should be noted that since the thickness of the modified inner wall material layer 830 can be adjusted by adjusting the parameters of the modification process, and there is an etching selectivity between the sacrificial layer 875 (i.e. the modified inner wall material layer 830) and the unmodified inner wall material layer 830, the amount of removal can be controlled more precisely when the sacrificial layer 875 is removed subsequently.

[0067] In this embodiment, during the modification treatment of the inner sidewall material layer 830 outside the inner trench, the sacrificial layer 875 satisfies the following condition: the etching selectivity ratio of the sacrificial layer 875 to the inner sidewall material layer 830 is greater than 6:1. The etching selectivity ratio of the sacrificial layer 875 to the inner sidewall material layer 830 should not be too small. If the etching selectivity ratio is too small, the inner sidewall material layer 830 is prone to accidental etching during the subsequent removal of the sacrificial layer 875, reducing the integrity of the subsequently formed inner sidewall.

[0068] In this embodiment, the sacrificial layer 875 further satisfies the following condition: the etching selectivity ratio of the sacrificial layer 875 to the channel layer 804 is greater than 50:1. The etching selectivity ratio of the sacrificial layer 875 to the channel layer 804 should not be too small. If the etching selectivity ratio of the sacrificial layer 875 to the channel layer 804 is too small, the channel layer 804 is prone to accidental etching during the subsequent removal of the sacrificial layer 875, reducing the integrity of the channel layer 804.

[0069] In this embodiment, the modification process is a plasma treatment process. The plasma treatment process is highly directional and can specifically modify the inner wall material layer 830 outside the trench. In other embodiments, the modification process can also be an ion implantation process.

[0070] In this embodiment, the process parameters of the plasma treatment process include bias power. The bias power should not be too low or too high. If the bias power is too low, the modification effect on the inner sidewall material layer 830 outside the inner trench 812 will be poor, which will hinder the increase of the etching selectivity ratio of the sacrificial layer 875 and the inner sidewall material layer 830, and thus hinder the subsequent selective removal of the sacrificial layer 875. If the bias power is too high, the fin 801 located under the inner sidewall material layer 830 will be easily damaged. Therefore, in this embodiment, the bias power is 100 Wb to 200 Wb.

[0071] In this embodiment, the process parameters of the plasma treatment process include plasma bombardment energy. The plasma bombardment energy should not be too low or too high. If the plasma bombardment energy is too low, the modification effect on the inner sidewall material layer 830 outside the inner trench 812 will be poor, which will be detrimental to increasing the etching selectivity ratio of the sacrificial layer 875 and the inner sidewall material layer 830, and thus detrimental to the subsequent selective removal of the sacrificial layer 875. If the plasma bombardment energy is too high, the fin 801 located under the inner sidewall material layer 830 will be easily damaged. Therefore, in this embodiment, the plasma bombardment energy is 450 eV to 850 eV.

[0072] In this embodiment, the process parameters of the plasma treatment process include the process time. As the process time increases, the thickness of the sacrificial layer 875 increases accordingly. However, the process time should not be too long. When the bias power and plasma bombardment energy are constant, when the process time increases to a certain extent, the thickness of the inner wall material layer 830 affected by the modification treatment reaches saturation. Therefore, if the process time is too long, it is easy to increase unnecessary waste of process time and process cost. Therefore, in this embodiment, the process time is greater than 0 seconds and less than 600 seconds.

[0073] In this embodiment, the process parameters of the plasma treatment process include a reaction gas, which is helium. Helium is beneficial to enhance the effect of modifying the inner wall material layer 830 outside the inner trench 812, thereby selectively removing the sacrificial layer 875 in the subsequent process. In other embodiments, the reaction gas also includes hydrogen or a mixture of hydrogen and helium.

[0074] It should be noted that in this embodiment, since the thickness of the inner wall material layer 830 affected by the modification treatment reaches saturation when the process time increases to a certain extent under the condition that the bias power and plasma bombardment energy are constant, it is beneficial to improve the etching load effect between different patterns.

[0075] refer to Figure 14 Remove the sacrificial layer 875 and retain the remaining inner wall material layer 830 located in the inner groove 812 as the inner wall 817.

[0076] The sacrificial layer 875 is removed to expose the remaining inner wall material layer 830 as an inner wall 817 and to expose the end of the channel layer 804, thereby preparing for the subsequent formation of source and drain doped layers.

[0077] In this embodiment, the inner wall 817 is used to support the channel layer 804, which facilitates the subsequent replacement of the pseudo gate structure 808 with the gate structure. In addition, the inner wall 817 is used to achieve isolation between the subsequently formed source / drain doped layer and the gate structure, thereby increasing the distance between the gate structure and the source / drain doped layer, which helps to reduce the parasitic capacitance between the gate structure and the source / drain doped layer.

[0078] In this embodiment, in the step of removing the sacrificial layer 875 and retaining the remaining inner sidewall material layer 830 located in the inner trench 812 as the inner sidewall, the sidewall of the inner sidewall is flush with the end of the channel layer 804, which is beneficial to fully expose the end of the channel layer 804 and improve the flatness of the sidewall of the remaining space of the groove 811. This, in turn, increases the probability of the subsequently formed source / drain doped layer contacting the channel layer 804 and improves the quality of the source / drain doped layer.

[0079] In this embodiment, the process for removing the sacrificial layer 875 is a wet etching process. Wet etching is simple, has a high etching rate, and high selectivity, thus facilitating the selective removal of the sacrificial layer 875 and reducing damage to the channel layer 804 and the remaining inner sidewall material layer 830 within the inner trench 812. In other embodiments, the process for removing the sacrificial layer also includes isotropic dry etching.

[0080] In this embodiment, when the process for removing the sacrificial layer 875 is a wet etching process, the etching solution is a hydrofluoric acid solution. The hydrofluoric acid solution can remove the sacrificial layer 875 formed by the above modification treatment. Moreover, the hydrofluoric acid solution has a relatively large etching selectivity for the sacrificial layer 875 and the inner sidewall material layer 830, which is beneficial for selectively removing the sacrificial layer 875.

[0081] The hydrofluoric acid solution exhibits low selectivity in etching the channel layer 804, which helps reduce the probability of damage to the channel layer 804. This, in turn, improves the interface foundation for the subsequent formation of the source / drain doped layer through epitaxial processes, thereby enhancing the quality of the source / drain doped layer.

[0082] In this embodiment, the process for removing the sacrificial layer 875 is a wet etching process. The process time of the wet etching process should not be too short or too long. If the process time is too short, the effect of completely removing the sacrificial layer 875 is likely to be poor, increasing the probability that the sacrificial layer 875 remains on the sidewall of the inner sidewall, and correspondingly increasing the probability that the end of the channel layer 804 is covered, thus adversely affecting the subsequent formation of the source and drain doped layers. If the process time is too long, the inner sidewall 817 is likely to be accidentally etched, thereby reducing the flatness of the sidewall of the inner sidewall 817. Therefore, in this embodiment, the process time of the wet etching process is 1 minute to 6 minutes.

[0083] refer to Figure 15 After removing the sacrificial layer 875 and retaining the remaining inner sidewall material layer 830 located in the inner trench 812 as the inner sidewall 817, the method further includes: forming a source / drain doped layer 818 in the groove 811, wherein the source / drain doped layer 818 is in contact with the end of the channel layer 804 in the extending direction.

[0084] The source / drain doped layer 818 is used as the source or drain of the field-effect transistor. When the field-effect transistor is working, the source / drain doped layer 818 is used to provide the source of charge carriers.

[0085] It should be noted that, since hydrofluoric acid solution is used to remove the sacrificial layer 875 in this embodiment, and the hydrofluoric acid solution has low selectivity for etching the channel layer 804, it is beneficial to reduce the probability of damage to the channel layer 804, which in turn is beneficial to improve the interface basis for forming the source / drain doped layer 818 by epitaxial process, and correspondingly improves the quality of the source / drain doped layer 818.

[0086] In this embodiment, the source / drain doped layer 818 includes an ion-doped stress layer, which provides stress to the channel region to improve carrier mobility. Specifically, when forming an NMOS transistor, the source / drain doped layer 818 includes an N-type ion-doped stress layer, and the material of the stress layer is Si or SiC; when forming a PMOS transistor, the source / drain doped layer 818 includes a P-type ion-doped stress layer, and the material of the stress layer is Si or SiGe.

[0087] In this embodiment, an epitaxial process is used to form a stress layer, and ions are self-doped in situ during the formation of the stress layer. The stress layer doped with ions is used as the source / drain doping layer 818.

[0088] In other embodiments, the stress layer may be ion implanted after it has been formed.

[0089] refer to Figure 16In this embodiment, after forming the source / drain doped layer 818 and before forming the gate opening, the method further includes: forming an interlayer dielectric layer 888 on the substrate on the side of the pseudo-gate structure 808, wherein the interlayer dielectric layer 888 covers the source / drain doped layer 818.

[0090] The interlayer dielectric layer 888 is used to isolate adjacent devices and also to support the channel layer 804 during the removal of the dummy gate structure 808 and the removal of the placeholder layer 803, so as to realize the overhang space setting of the channel layer 804.

[0091] Specifically, the interlayer dielectric layer 888 covers the sidewall of the gate sidewall 809 and the source / drain doped layer 818.

[0092] In this embodiment, the material of the interlayer dielectric layer 888 is silicon oxide. The material of the interlayer dielectric layer 888 can also be other insulating materials.

[0093] refer to Figure 17 The pseudo-gate structure 808 is removed to form a gate opening (not shown); the occupier layer 803 is removed through the gate opening to form a through trench (not shown), the through trench being surrounded by adjacent channel layers 804, or by adjacent channel layers 804 and a substrate; a gate structure 819 is formed in the gate opening and the through trench, the gate structure 819 surrounding the channel layer 804.

[0094] Specifically, after forming the interlayer dielectric layer 888, a gate opening is formed.

[0095] The gate opening provides space for forming the gate structure 819. The gate opening exposes the stacked structure 810 to facilitate subsequent removal of the placeholder layer 803 in the channel stack 805 through the gate opening.

[0096] In this embodiment, the gate opening spans the stacked structure 810.

[0097] The through-slot and the gate opening together provide space for forming the gate structure 819. The through-slot is connected to the gate opening.

[0098] In this embodiment, a vapor etching process is used to remove the occupant layer 803. Specifically, the channel layer 804 is made of Si, and the occupant layer 803 is made of SiGe. Therefore, removing the occupant layer 803 exposed by the gate opening using HCl vapor is beneficial because HCl vapor has a high etching selectivity between SiGe and Si, which helps to improve the removal efficiency of the occupant layer 803 and reduce the probability of damage to the channel layer 804.

[0099] During device operation, the gate structure 818 is used to control the opening and closing of the conductive channel. In this embodiment, the gate structure is a metal gate structure, which includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) located on the gate dielectric layer.

[0100] The gate electrode layer is used as an external electrode for electrical connection between the gate structure and external circuitry.

[0101] The material of the gate electrode layer includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN), and titanium aluminum carbide (TiAlC).

[0102] In this embodiment, the gate electrode layer includes one or both of a work function layer and an electrode layer.

[0103] In this embodiment, the work function layer is used to adjust the threshold voltage of the transistor. For example, when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of titanium aluminide and titanium aluminum carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of titanium nitride, tantalum nitride, and titanium silicon nitride.

[0104] The electrode layer is used for electrical connection with an external circuit. The electrode layer is made of a conductive material, including one or more of tungsten and aluminum. In this embodiment, the electrode layer is made of tungsten.

[0105] The gate dielectric layer is used to achieve electrical isolation between the gate electrode layer and the conductive channel.

[0106] In this embodiment, the material of the gate dielectric layer includes one or more of the following: hafnium oxide (HfO2), zirconium oxide (ZrO2), silicon hafnium oxide (HfSiO), silicon oxynitride hafnium (HfSiON), tantalum hafnium oxide (HfTaO), titanium hafnium oxide (HfTiO), zirconium hafnium oxide (HfZrO), aluminum oxide (Al2O3), silicon oxide (SiO2), and lanthanum oxide (La2O3).

[0107] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from zirconium oxide (ZrO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), or aluminum oxide (Al2O3). In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer may only include a gate oxide layer.

[0108] In this embodiment, a metal gate structure 819 is used as an example for illustration. In other embodiments, based on actual process requirements, the gate structure can also be other types of gate structures, such as polycrystalline silicon gate structures or amorphous silicon gate structures.

[0109] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which a stacked structure is formed, the stacked structure including one or more channel stacks stacked sequentially from bottom to top, the channel stack including a placeholder layer and a channel layer located on the placeholder layer, and a pseudo-gate structure is also formed on the substrate, the pseudo-gate structure spanning the stacked structure and covering a portion of the top and a portion of the sidewalls of the stacked structure; Grooves penetrating the stacked structure are formed on both sides of the pseudo-gate structure; Along the extension direction of the channel layer, a portion of the occupant layer exposed on the sidewall of the groove is removed to form an inner groove; An inner sidewall material layer is formed on the sidewall of the pseudo-gate structure and the sidewall of the groove, and the inner sidewall material layer is also filled in the inner groove; The inner sidewall material layer outside the inner trench is modified to transform the inner sidewall material layer into a sacrificial layer, wherein the sacrificial layer, the inner sidewall material layer, and the trench layer all have an etching selectivity ratio. Remove the sacrificial layer and retain the remaining inner wall material layer located in the inner trench as the inner wall.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, After removing the sacrificial layer and retaining the remaining inner wall material layer located within the inner trench as the inner wall, the system further includes: A source / drain doped layer is formed in the groove, and the source / drain doped layer is in contact with the end of the channel layer along the extension direction; Remove the pseudo-gate structure to form a gate opening; The occupant layer is removed through the gate opening to form a through-slot, which is surrounded by adjacent channel layers, or by adjacent channel layers and a substrate; A gate structure is formed within the gate opening and the through-slot, the gate structure surrounding the channel layer.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of modifying the inner wall material layer outside the inner trench, the sacrificial layer satisfies the following condition: the etching selectivity ratio of the sacrificial layer to the inner wall material layer is greater than 6:

1. The etching selectivity ratio of the sacrificial layer to the channel layer is greater than 50:

1.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before modifying the inner wall material layer outside the inner trench, the method further includes: obtaining a preset thickness of the inner wall material layer located on the sidewall of the pseudo-grid structure; The step of modifying the inner wall material layer outside the inner trench includes: modifying the inner wall material layer of a predetermined thickness outside the inner trench.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The modification process includes plasma treatment or ion implantation.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The process parameters of the plasma treatment process include: bias power of 100wb to 200wb; The plasma bombardment energy is 450 eV to 850 eV, and the process time is greater than 0 seconds and less than 600 seconds.

7. The method for forming a semiconductor structure as described in claim 5, characterized in that, The process parameters of the plasma treatment process include: the reaction gas includes one or more of helium and hydrogen.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for removing the sacrificial layer includes: wet etching or isotropic dry etching.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for removing the sacrificial layer is a wet etching process, and the etching solution for the wet etching process includes a hydrofluoric acid solution.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for removing the sacrificial layer is a wet etching process, and the process time of the wet etching process is 1 minute to 6 minutes.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of removing the sacrificial layer and retaining the remaining inner wall material layer located in the inner trench as the inner wall, the sidewall of the inner wall is flush with the end of the trench layer.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for forming the inner wall material layer includes atomic layer deposition.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the inner wall material layer, the material of the inner wall material layer includes one or more of silicon nitride and low-k dielectric materials.

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