A wide band gap semiconductor trench MOSFET device structure and a manufacturing method thereof

Abstract

The application particularly relates to a wide-bandgap semiconductor trench MOSFET device structure, which at least comprises a substrate, an epitaxial layer epitaxially grown on the substrate, gate electrodes made in the epitaxial layer, and source P+ regions made between the gate electrodes; the epitaxial layer comprises epitaxial layer one and epitaxial layer two made in the substrate in sequence, a P+ buried layer is made between the epitaxial layer one and the epitaxial layer two, a P+ mask layer is made right below the gate electrodes and is located in the epitaxial layer two, an N+ current channel is made in the P+ buried layer, the P+ mask layer is electrically connected with the P+ buried layer through a P+ grounding column; the source P+ regions comprise first source P+ regions and second source P+ regions, the first source P+ regions and the second source P+ regions are electrically connected with the P+ buried layer, one of the first source P+ regions and the second source P+ regions and / or the P+ grounding column extends to the epitaxial layer one through the P+ buried layer. The structure can not only improve the gate oxide reliability of the device, but also improve the compromise relationship between the specific on-resistance and the gate oxide electric field strength at the time of breakdown of the device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a wide bandgap semiconductor trench MOSFET device structure and a manufacturing method thereof. Background Art

[0002] Wide bandgap semiconductor trench MOSFET devices still have the following problems in actual process manufacturing and application: (1) The high electric field in the material drift region leads to a high electric field on the gate dielectric layer. This problem is exacerbated at the trench corner, causing the gate dielectric layer to quickly breakdown under high drain voltage, and poor tolerance to electrostatic effects in harsh environments and high-voltage spikes in circuits; (2) Traditional devices have a poor trade-off between specific on-resistance and gate oxide electric field strength at breakdown. Summary of the Invention

[0003] Based on the above description, the present invention provides a wide bandgap semiconductor trench MOSFET device structure, which can not only improve the gate oxide reliability of the device, but also improve the trade-off relationship between the device's specific on-resistance and the gate oxide electric field strength during breakdown.

[0004] The present invention solves the above-mentioned technical problems with the following technical solutions: The present invention provides a wide bandgap semiconductor trench MOSFET device structure, comprising at least a substrate, an epitaxial layer epitaxially grown on the substrate, a gate electrode formed in the epitaxial layer, and a source P+ region formed between the gate electrodes; the epitaxial layer comprises an epitaxial layer 1 and an epitaxial layer 2 stacked in sequence on the substrate, a P+ buried layer formed between the epitaxial layer 1 and the epitaxial layer 2, a P+ shielding layer formed directly below the gate electrode and located in the epitaxial layer 2, an N+ current channel formed in the P+ buried layer and located directly below the P+ shielding layer, and the P+ shielding layer being electrically connected to the P+ buried layer via a P+ grounding column;

[0005] The source P+ region includes a first source P+ region and a second source P+ region, both of which are electrically connected to the P+ buried layer, and one of the first source P+ region and the second source P+ region and / or the P+ grounding column extends through the P+ buried layer to the epitaxial layer one.

[0006] As a preferred embodiment, a P-well region, a source N+ region and a source electrode are sequentially formed on the epitaxial layer, the gate electrode passes through the source N+ region, the P-well region and part of the epitaxial layer 2, a source trench is formed between the gate electrodes, the source trench is filled with source polysilicon, the source P+ region is located on both sides of the source trench, and the source polysilicon and the source P+ region are electrically connected to the source electrode through the source ohmic contact region at the top of the source trench.

[0007] As a preferred embodiment, the source trench is a multi-level trench structure.

[0008] As a preferred embodiment, a drain electrode is formed on a surface of the substrate opposite to the epitaxial layer.

[0009] As a preferred embodiment, the first source P+ region and the second source P+ region are in the shape of a strip or a block.

[0010] As a preferred embodiment, the P+ grounding column and the source P+ region extending into the first epitaxial layer are arranged in an interlaced or parallel manner.

[0011] As a preferred embodiment, the substrate is an N+ type substrate, and the epitaxial layer is an N- epitaxial layer.

[0012] The present invention also provides a method for preparing the above-mentioned wide bandgap semiconductor trench MOSFET device structure, comprising the following steps:

[0013] An epitaxial layer 1, a P+ buried layer, an epitaxial layer 2, a P-well region, and a source N+ region are sequentially formed on a wide bandgap semiconductor material substrate;

[0014] Dry etching forms gate trenches and source trenches, followed by P-type ion implantation in the source trenches to form a first source P+ region and a second source P+ region, a P+ masking layer is formed at the bottom of the gate trenches by P-type ion implantation, an N+ current channel is formed in the P+ buried layer at the bottom of the gate trenches by N-type ion implantation, and a P+ grounding column is formed at the bottom of the gate trenches by P-type ion implantation;

[0015] Gate dielectric growth, gate polysilicon growth and etching, interlayer dielectric deposition and etching, gate electrode deposition and etching, source polysilicon growth and source ohmic contact area production, source electrode and drain electrode production.

[0016] As a preferred embodiment, the source trench is etched in two steps: first, etching the first-level trench, and then etching the second-level trench.

[0017] The present application forms a deep shielding structure by constructing a source trench, a source P+ region, a P+ buried layer, a P+ shielding layer, and a P+ grounding column, which can reduce the gate oxide electric field strength and improve the gate oxide reliability of the device; by forming an ohmic contact at the source, the source N+ region, the source polysilicon, the source P+ region, the P+ buried layer, the P+ grounding column, and the P+ shielding layer are short-circuited together; a conductive area is formed by constructing an N+ current channel; one of the first source P+ region and the second source P+ region and / or the P+ grounding column extends through the P+ buried layer to the epitaxial layer 1, so that the electric field strength at the bottom of the gate is no longer sensitive to the concentration and thickness of the N+ current channel, and the conduction characteristics of the device can be improved by increasing the concentration of the N+ current channel, and the trade-off relationship between the specific on-resistance and the gate oxide electric field strength of the device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic structural diagram of a wide bandgap semiconductor trench MOSFET device structure provided by an embodiment of the present invention;

[0019] Figure 2 A schematic structural diagram of another wide bandgap semiconductor trench MOSFET device structure provided by an embodiment of the present invention;

[0020] Figure 3 A schematic structural diagram of another wide bandgap semiconductor trench MOSFET device structure provided by an embodiment of the present invention;

[0021] Figure 4 for Figure 1 Schematic diagram of the path through which the current flows from the N+ current channel at the middle section A;

[0022] Figure 5 for Figure 1 Schematic diagram of the electric field concentrated at the bottom of the source deep P+ region at section B;

[0023] Figure 6 The position relationship of the source deep P+ region relative to the N+ current channel and the P+ ground column;

[0024] Figure 7 is a flow chart for manufacturing the device structure shown in Example 1;

[0025] In the accompanying drawings, the components represented by the reference numerals are as follows:

[0026] 1 substrate, 2 epitaxial layer, 3 source P+ region, 4 gate electrode, 5 P+ buried layer, 6 P+ masking layer, 7 N+ current channel, 8 P+ grounding column, 9 P well region, 10 source N+ region, 11 source electrode, 12 gate trench, 13 source ohmic contact region, 14 drain electrode;

[0027] 21 epitaxial layer 1, 22 epitaxial layer 2, 31 first source P+ region, 32 second source P+ region. DETAILED DESCRIPTION

[0028] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0030] It should be noted that in the description of this application, the drawings and descriptions of the embodiments are illustrative rather than restrictive, and the same drawings throughout the embodiments of the specification identify the same structure. In addition, for the sake of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. In addition, "on..." refers to positioning an element on or below another element, but does not essentially mean positioning on the upper side of another element according to the direction of gravity. The terms "upper", "lower", "top", "bottom", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting this application.

[0031] It should also be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intervening element. In the following embodiments, "connection" should be understood as "electrical connection", "communication connection", etc., if the connected circuits, modules, units, etc. can transmit electrical signals or data to each other.

[0032] like Figures 1 to 3As shown, a wide bandgap semiconductor trench MOSFET device structure includes at least a substrate 1, an epitaxial layer 2 epitaxially grown on the substrate 1, a gate electrode 4 formed in the epitaxial layer 2, and a source P+ region 3 formed between the gate electrodes 4; wherein, the epitaxial layer 2 includes an epitaxial layer 1 21 and an epitaxial layer 2 22 stacked in sequence on the substrate 1, a P+ buried layer 5 is formed between the epitaxial layer 1 21 and the epitaxial layer 2 22, a P+ shielding layer 6 is formed directly below the gate electrode 4 and the P+ shielding layer 6 is located in the epitaxial layer 2 22, an N+ current channel 7 is formed in the P+ buried layer 5 and the N+ current channel 7 is located directly below the P+ shielding layer 6, and the P+ shielding layer 6 is electrically connected to the P+ buried layer 5 through a P+ grounding column 8.

[0033] The source P+ region 3 includes a first source P+ region 31 and a second source P+ region 32. The first source P+ region 31 and the second source P+ region 32 are both electrically connected to the P+ buried layer 5. One of the first source P+ region 31 and the second source P+ region 32 and / or the P+ grounding column 8 passes through the P+ buried layer 5 and extends into the epitaxial layer 21.

[0034] The present application forms a deep shielding structure by the source P+ region 3, the P+ buried layer 5, the P+ shielding layer 6, and the P+ grounding column 8, which can reduce the gate oxide electric field strength and improve the gate oxide reliability of the device; by extending one of the first source P+ region 31 and the second source P+ region 32 and / or the P+ grounding column 8 through the P+ buried layer 5 into the epitaxial layer 21, the electric field strength at the bottom of the gate is no longer sensitive to the concentration and thickness of the N+ current channel, and the electric field is more concentrated at the bottom of the source P+ region or the P+ grounding column extending into the epitaxial layer 21, and the conduction characteristics of the device can be improved by increasing the concentration of the N+ current channel; the compromise relationship between the specific on-resistance and the gate oxide electric field strength of the device can be further improved by controlling the area ratio of the two cells: the source P+ region extending into the epitaxial layer 21 and the source P+ region not extending into the epitaxial layer 21.

[0035] Furthermore, a P-well region 9, a source N+ region 10 and a source electrode 11 are sequentially formed on the epitaxial layer 2. The gate electrode 4 penetrates the source N+ region 10, the P-well region 9 and part of the epitaxial layer 22. A source trench 12 is formed between the gate electrodes 4. The source trench 12 is filled with source polysilicon. The source P+ region 3 is located on both sides of the source trench 12. The source polysilicon and the source P+ region 3 are electrically connected to the source electrode 11 through the source ohmic contact region 13 at the top of the source trench 11.

[0036] It can be understood that the gate electrode 4 includes a gate trench and gate polysilicon filled in the gate trench, a gate dielectric layer is arranged around the gate trench, and an interlayer dielectric layer is deposited between the gate polysilicon and the source electrode.

[0037] Furthermore, in the present application, the source trench 12 is a multi-level trench structure. Setting the source trench 12 as a multi-level trench structure can provide a deeper ion implantation depth, ensuring that the source P+ region can be more easily implanted through the P+ buried layer 5 into the epitaxial layer 21.

[0038] A drain electrode 14 is formed on the surface of the substrate 1 opposite to the epitaxial layer 2 .

[0039] Furthermore, the first source P+ region 21 and the second source P+ region 32 are in the shape of strips or blocks, and the P+ grounding posts 8 are arranged in an interlaced or parallel manner with the source P+ regions extending into the first epitaxial layer 21 .

[0040] In the present application, the substrate 1 is an N+ type substrate, and the epitaxial layer 2 is an N- epitaxial layer.

[0041] The present invention also provides a method for preparing the above-mentioned wide bandgap semiconductor trench MOSFET device structure, comprising the following steps:

[0042] An epitaxial layer 1 21, a P+ buried layer 5, an epitaxial layer 2 22, a P-well region 9, and a source N+ region 10 are sequentially formed on a wide bandgap semiconductor material substrate 1;

[0043] Dry etching forms gate trenches and source trenches 12, followed by P-type ion implantation to form a first source P+ region 31 and a second source P+ region 32 in the source trench 12, a P+ masking layer 6 is formed at the bottom of the gate trench by P-type ion implantation, an N+ current channel 7 is formed in the P+ buried layer 5 at the bottom of the gate trench by N-type ion implantation, and a P+ grounding column 8 is formed at the bottom of the gate trench by P-type ion implantation;

[0044] Gate dielectric growth, gate polysilicon growth and etching, interlayer dielectric deposition and etching, gate electrode deposition and etching, source polysilicon growth and source ohmic contact area production, source electrode and drain electrode production.

[0045] Furthermore, the etching of the source trench 12 is divided into two steps: firstly etching the first-level trench and then etching the second-level trench.

[0046] In order to make the technical solution of this application clearer, several specific embodiments are further described below in detail:

[0047] Example 1

[0048] like Figure 1 As shown, a wide bandgap semiconductor trench MOSFET device structure at least includes a substrate 1, an epitaxial layer 2 epitaxially grown on the substrate 1, a gate electrode 4 made in the epitaxial layer 2, and a source P+ region 3 made between the gate electrodes 4.

[0049] Among them, the epitaxial layer 2 includes an epitaxial layer 1 21 and an epitaxial layer 2 22 stacked in sequence on the substrate 1, a P+ buried layer 5 is made between the epitaxial layer 1 21 and the epitaxial layer 2 22, a P+ shielding layer 6 is made directly below the gate electrode 4 and the P+ shielding layer 6 is located in the epitaxial layer 2 22, an N+ current channel 7 is made in the P+ buried layer 5, and the P+ shielding layer 6 is electrically connected to the P+ buried layer 5 through a P+ grounding column 8.

[0050] The source P+ region 3 includes a first source P+ region 31 and a second source P+ region 32. The bottom of the first source P+ region 31 is electrically connected to the P+ buried layer 5, and the second source P+ region 32 extends through the P+ buried layer 5 to the epitaxial layer 21 and is electrically connected to the P+ buried layer 5 (i.e., the source deep P+ region described below).

[0051] Furthermore, a P-well region 9, a source N+ region 10 and a source electrode 11 are sequentially formed on the epitaxial layer 22. The gate electrode 4 penetrates the source N+ region 10, the P-well region 9 and part of the epitaxial layer 22. A source trench 12 is formed between the gate electrodes 4. The source trench 12 is filled with source polysilicon. The source P+ region 3 is located on both sides of the source trench 12. The source polysilicon and the source P+ region 3 are electrically connected to the source electrode 11 through the source ohmic contact region 13 at the top of the source trench 11.

[0052] Furthermore, the source trench 12 is a multi-level trench structure.

[0053] This solution forms a deep shielding structure by constructing multi-level source trenches, source P+ region, source deep P+ region, P+ buried layer, P+ shielding layer, and P+ grounding column, which can reduce the gate oxide electric field strength and improve the gate oxide reliability of the device; by forming an ohmic contact at the source, the source N+ region, source polysilicon, source deep P+ region, source P+ region, P+ buried layer, P+ grounding column, and P+ shielding layer are short-circuited together; by constructing an N+ current channel, a conductive area is formed, in which the source deep P+ region and the source P+ region are arranged proportionally in space.

[0054] in Figure 4 This is a schematic diagram of the path through which the current in section A flows from the N+ current channel. Figure 5 Schematic diagram of the electric field concentration in the deep source P+ region at section B. The presence of the deep source P+ region makes the electric field strength at the bottom of the gate less sensitive to the concentration and thickness of the N+ current channel. The electric field is more concentrated at the bottom of the deep source P+ region, which can improve the device's conduction characteristics by increasing the concentration of N+ current channels. At the same time, by controlling the area ratio of the deep source P+ region and the source P+ region, the trade-off between the device's specific on-resistance and gate oxide electric field strength can be further improved.

[0055] The preparation process of the wide bandgap semiconductor trench MOSFET device structure is as follows (take Sister A and B as examples for explanation), for details, see Figure 7:

[0056] (1) (Section A and Section B) N-epitaxial layer is grown on a wide bandgap semiconductor material (SiC / GaN / Ga2O3 / C / AlN, etc.) substrate;

[0057] (2) (Sections A and B) Growth of a P+ buried layer on the N- epitaxial layer;

[0058] (3) (Sections A and B) Continue to grow the N- epitaxial layer on the P+ buried layer;

[0059] (4) (Sections A and B) forming a P-well region by ion implantation, secondary epitaxy, and growth of a P-type oxide;

[0060] (5) (Section A and Section B) Forming a source N+ region by ion implantation;

[0061] (6) (Section A and Section B) Dry etching to form the first-level source trench;

[0062] (7) (Section A and Section B) Dry etching to form gate trenches and source second-level trenches;

[0063] (8) (Section A) The source P+ region is formed by P-type ion implantation;

[0064] (9) (Section B) A source deep P+ region is formed by P-type ion implantation;

[0065] (10) (Section A) Forming a P+ masking layer by P-type ion implantation;

[0066] (11) (Section A) N+ current channel is formed by N-type ion implantation;

[0067] (12) (Section B) P+ grounding pillars are formed by P-type ion implantation;

[0068] (13) (Section A) Gate dielectric growth, gate polysilicon growth and etching, interlayer dielectric deposition and etching, gate electrode deposition and etching, drain electrode deposition;

[0069] (14) (Section B) Gate dielectric growth, gate polysilicon growth and etching, interlayer dielectric deposition and etching, gate electrode deposition and etching, drain electrode deposition.

[0070] Example 2

[0071] like Figure 2 As shown, a wide bandgap semiconductor trench MOSFET device structure at least includes a substrate 1, an epitaxial layer 2 epitaxially grown on the substrate 1, a gate electrode 4 made in the epitaxial layer 2, and a source P+ region 3 made between the gate electrodes 4.

[0072] Among them, the epitaxial layer 2 includes an epitaxial layer 1 21 and an epitaxial layer 2 22 stacked in sequence on the substrate 1, a P+ buried layer 5 is made between the epitaxial layer 1 21 and the epitaxial layer 2 22, a P+ shielding layer 6 is made directly below the gate electrode 4 and the P+ shielding layer 6 is located in the epitaxial layer 2 22, an N+ current channel 7 is made in the P+ buried layer 5, and the P+ shielding layer 6 is electrically connected to the P+ buried layer 5 through a P+ grounding column 8.

[0073] The bottom of the source P+ region 3 is electrically connected to the P+ buried layer 5, and the P+ grounding column 8 extends through the P+ buried layer 5 to the epitaxial layer 21 and is electrically connected to the P+ buried layer 5 (ie, the source deep P+ region described below).

[0074] Furthermore, a P-well region 9, a source N+ region 10 and a source electrode 11 are sequentially formed on the epitaxial layer 22. The gate electrode 4 penetrates the source N+ region 10, the P-well region 9 and part of the epitaxial layer 22. A source trench 12 is formed between the gate electrodes 4. The source trench 12 is filled with source polysilicon. The source P+ region 3 is located on both sides of the source trench 12. The source polysilicon and the source P+ region 3 are electrically connected to the source electrode 11 through the source ohmic contact region 13 at the top of the source trench 11.

[0075] This solution utilizes the deep P+ grounding column to gather the electric field during breakdown, achieving the same function as the source deep P+ region in Example 1, and improving the trade-off between the device's specific on-resistance and gate oxide electric field strength.

[0076] Example 3

[0077] like Figure 3 As shown, a wide bandgap semiconductor trench MOSFET device structure at least includes a substrate 1, an epitaxial layer 2 epitaxially grown on the substrate 1, a gate electrode 4 made in the epitaxial layer 2, and a source P+ region 3 made between the gate electrodes 4.

[0078] Among them, the epitaxial layer 2 includes an epitaxial layer 1 21 and an epitaxial layer 2 22 stacked in sequence on the substrate 1, a P+ buried layer 5 is made between the epitaxial layer 1 21 and the epitaxial layer 2 22, a P+ shielding layer 6 is made directly below the gate electrode 4 and the P+ shielding layer 6 is located in the epitaxial layer 2 22, an N+ current channel 7 is made in the P+ buried layer 5, and the P+ shielding layer 6 is electrically connected to the P+ buried layer 5 through a P+ grounding column 8.

[0079] The source P+ region 3 includes a first source P+ region 31 and a second source P+ region 32. The bottom of the first source P+ region 31 is electrically connected to the P+ buried layer 5. The second source P+ region 32 and the P+ grounding column 8 extend through the P+ buried layer 5 into the epitaxial layer 21 and are electrically connected to the P+ buried layer 5.

[0080] Furthermore, a P-well region 9, a source N+ region 10 and a source electrode 11 are sequentially formed on the epitaxial layer 22. The gate electrode 4 penetrates the source N+ region 10, the P-well region 9 and part of the epitaxial layer 22. A source trench 12 is formed between the gate electrodes 4. The source trench 12 is filled with source polysilicon. The source P+ region 3 is located on both sides of the source trench 12. The source polysilicon and the source P+ region 3 are electrically connected to the source electrode 11 through the source ohmic contact region 13 at the top of the source trench 11.

[0081] In this scheme, the deep P+ grounding column and the source deep P+ region exist at the same time, which can concentrate the breakdown electric field and improve the compromise relationship between the device's specific on-resistance and gate oxide electric field strength; the positions of the source deep P+ region and the P+ grounding column are arranged in three-dimensional space, which can realize the simultaneous concentration of the breakdown electric field at different positions, and improve the compromise relationship between the device's specific on-resistance and gate oxide electric field strength. Among them, the position of the source deep P+ region relative to the N+ current channel and the P+ grounding column in three-dimensional space can have the following situations: (1) The source deep P+ region is completely parallel to the position of the P+ grounding column; (2) The source deep P+ region is staggered with the P+ grounding column and the N+ current channel; (3) The source deep P+ region is parallel to the position of the N+ current channel, see for details. Figure 6 .

[0082] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A wide bandgap semiconductor trench MOSFET device structure, characterized in that: The device comprises at least a substrate (1), an epitaxial layer (2) epitaxially grown on the substrate (1), a gate electrode (4) formed in the epitaxial layer (2), and a source P+ region (3) formed between the gate electrodes (4); The epitaxial layer (2) comprises an epitaxial layer 1 (21) and an epitaxial layer 2 (22) which are sequentially stacked on a substrate (1); a P+ buried layer (5) is formed between the epitaxial layer 1 (21) and the epitaxial layer 2 (22); a P+ shielding layer (6) is formed directly below the gate electrode (4) and the P+ shielding layer (6) is located in the epitaxial layer 2 (22); an N+ current channel (7) is formed in the P+ buried layer (5) and the N+ current channel (7) is located directly below the P+ shielding layer (6); the P+ shielding layer (6) is electrically connected to the P+ buried layer (5) via a P+ grounding column (8); The source P+ region (3) includes a first source P+ region (31) and a second source P+ region (32), the first source P+ region (31) and the second source P+ region (32) are both electrically connected to the P+ buried layer (5), the first source P+ region (31) does not pass through the P+ buried layer, and the second source P+ region (32) and the P+ grounding column (8) pass through the P+ buried layer (5) and extend into the epitaxial layer 1 (21); A P-well region (9), a source N+ region (10) and a source electrode (11) are sequentially formed on the epitaxial layer (2); the gate electrode (4) penetrates the source N+ region (10), the P-well region (9) and a portion of the second epitaxial layer (22); a source trench (12) is formed between the gate electrodes (4); the source trench (12) is filled with source polysilicon; the source P+ region (3) is located on both sides of the source trench (12); the source polysilicon and the source P+ region (3) are electrically connected to the source electrode (11) via a source ohmic contact region (13) at the top of the source trench (12); The gate electrode (4) comprises a gate trench and gate polysilicon filled in the gate trench, a gate dielectric layer is arranged around the gate trench, and an interlayer dielectric layer is deposited between the gate polysilicon and the source electrode.

2. The wide bandgap semiconductor trench MOSFET device structure according to claim 1, characterized in that: The source trench (12) is a multi-level trench structure.

3. The wide bandgap semiconductor trench MOSFET device structure according to any one of claims 1 to 2, characterized in that: A drain electrode (14) is formed on a side of the substrate (1) opposite to the epitaxial layer (2).

4. The wide bandgap semiconductor trench MOSFET device structure according to any one of claims 1 to 2, characterized in that: The first source P+ region (31) and the second source P+ region (32) are in the shape of a long strip or a square.

5. The wide bandgap semiconductor trench MOSFET device structure according to any one of claims 1 to 2, characterized in that: The P+ grounding column (8) is arranged in an interlaced or parallel manner with the source P+ region extending into the epitaxial layer 1 (21).

6. The wide bandgap semiconductor trench MOSFET device structure according to any one of claims 1 to 2, characterized in that: The substrate (1) is an N+ type substrate, and the epitaxial layer (2) is an N- epitaxial layer.

7. The method for preparing a wide bandgap semiconductor trench MOSFET device structure according to any one of claims 1 to 6, characterized in that: The following steps are involved: An epitaxial layer 1 (21), a P+ buried layer (5), an epitaxial layer 2 (22), a P well region (9), and a source N+ region (10) are sequentially fabricated on a wide bandgap semiconductor material substrate (1); Dry etching forms a gate trench and a source trench (12), then forms a first source P+ region (31) and a second source P+ region (32) in the source trench (12) by P-type ion implantation, forms a P+ masking layer (6) at the bottom of the gate trench by P-type ion implantation, forms an N+ current channel (7) in the P+ buried layer (5) at the bottom of the gate trench by N-type ion implantation, and forms a P+ grounding column (8) at the bottom of the gate trench by P-type ion implantation; Gate dielectric growth, gate polysilicon growth and etching, interlayer dielectric deposition and etching, gate electrode deposition and etching, source polysilicon growth and source ohmic contact area production, source electrode and drain electrode production.

8. The method for preparing a wide bandgap semiconductor trench MOSFET device structure according to claim 7, wherein: The source trench (12) is etched in two steps, first etching the first-level trench and then etching the second-level trench.

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