A row drive circuit and applications thereof

Abstract

This invention provides a row driving circuit and its application. The row driving circuit is used to drive the row circuit in a pixel array. The row driving circuit includes: a level shifter that receives a row strobe enable signal and outputs a first control signal and a second control signal, wherein the first control signal and the row strobe enable signal are in phase, and the second control signal and the first control signal are out of phase; and a plurality of signal output modules electrically connected to the output terminal of the level shifter and the driving terminal of the row circuit. The input terminal of the signal output module receives the first control signal, the second control signal, and a device preset signal. When the first control signal is high, the output signal of the signal output module is out of phase with the device preset signal. When the first control signal is low, the output signal of the signal output module is a low-level signal.

Description

Technical Field

[0001] This invention relates to the field of image sensing technology, and in particular to a line drive circuit and its application. Background Technology

[0002] In electronic devices such as mobile phones, cameras, and computers, image sensors are used to capture images. Within an image sensor, pixel units are arranged in pixel rows and pixel columns. The row circuits and column circuits corresponding to the pixel rows and columns enable control of the pixels, performing operations such as data readout, resetting, and selective activation.

[0003] The timing structure of the driving circuit is quite complex. Therefore, the complex driving circuit makes it difficult to control the integrated circuit area and power consumption of the image sensor. Summary of the Invention

[0004] The purpose of this invention is to provide a row driving circuit and its application, which can reduce the integrated circuit area and reduce device power consumption.

[0005] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution:

[0006] This invention provides a row driving circuit, comprising:

[0007] A level shifter that receives a row strobe enable signal and outputs a first control signal and a second control signal, wherein the first control signal and the row strobe enable signal are in phase, and the second control signal and the first control signal are out of phase; and

[0008] Multiple signal output modules are electrically connected to the output terminal of the level shifter and the driving terminal of the horizontal circuit. The input terminal of each signal output module receives the first control signal, the second control signal, and the device preset signal. When the first control signal is high, the output signal of the signal output module is out of phase with the device preset signal. When the first control signal is low, the output signal of the signal output module is a low-level signal.

[0009] In one embodiment of the present invention, the row driving circuit includes a timing generation module, the output terminal of which is electrically connected to the level shifter and the signal output module, and outputs the row strobe enable signal and the device preset signal to the level shifter.

[0010] In one embodiment of the present invention, the level shifter includes a first level shift unit, the input terminal of the first level shift unit is electrically connected to the timing generation module, the power supply terminal and the ground terminal, and the first level shift unit outputs a high-level voltage and a ground voltage, wherein the high-level voltage is greater than the voltage of the power supply terminal.

[0011] In one embodiment of the present invention, the level shifter includes a second level shift unit, the input terminal of the second level shift unit is electrically connected to the first level shift unit, and the second level shift unit outputs the high-level voltage and the low-level voltage, wherein the low-level voltage is less than the voltage of the ground terminal.

[0012] In one embodiment of the present invention, the signal output module includes a controlled inverting unit, the controlled inverting unit includes a plurality of transistors, and the plurality of transistors are connected in series.

[0013] In one embodiment of the present invention, the signal output module includes a first transistor, the driving terminal of the first transistor is electrically connected to the timing generation module and receives the device preset signal, the first terminal of the first transistor is electrically connected to the output terminal of the second level shifting unit, and the first terminal of the first transistor is set to the high-level voltage.

[0014] In one embodiment of the present invention, the signal output module includes a second transistor and a third transistor connected in series. The driving terminals of the second transistor and the third transistor are electrically connected to the output terminal of the second level shifting unit. The second transistor and the third transistor are simultaneously turned on or simultaneously turned off, and the common terminal of the second transistor and the third transistor is the output terminal of the controlled inverting unit.

[0015] In one embodiment of the present invention, the signal output module includes a fourth transistor, the driving terminal of the fourth transistor is electrically connected to the timing generation module and receives a preset signal from the device, the first terminal of the fourth transistor is electrically connected to the second terminal of the third transistor, the second terminal of the fourth transistor is electrically connected to the output terminal of the second level shifting unit, and the second terminal of the fourth transistor is set to a low-level voltage.

[0016] In one embodiment of the present invention, the signal output module includes an adjustment transistor, the first terminal of which is electrically connected to the output terminal of the controlled inverting unit, the second terminal of which is electrically connected to the output terminal of the second level shifting unit, and the second terminal of which is set to a low level voltage. The driving terminal of the adjustment transistor is electrically connected to the output terminal of the second level shifting unit and receives the second control signal.

[0017] This invention provides an image sensor, comprising:

[0018] A pixel array comprising multiple pixel units, wherein the pixel units are arranged in rows and columns to form row circuits and column circuits; and

[0019] As described above, a row driving circuit is electrically connected to the row circuit and drives the row circuit.

[0020] As described above, this invention provides a row driving circuit capable of driving any one or more row circuits to perform operations such as charge transfer, reset, and selective activation of pixel units. According to the row driving circuit, row driving method, and image sensor provided by this invention, timing signals can be sent to multiple transistors in the row circuit to control the transistors' on or off states. Furthermore, the row driving circuit provided by this invention occupies less integrated circuit area; for image sensors with complex structures and high integration, the row driving circuit provided by this invention saves even more integrated circuit area, thus resulting in lower power consumption. Moreover, the de-driving method of the row driving circuit provided by this invention is simple and has high driving efficiency.

[0021] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the structure of an image sensor in one embodiment of the present invention.

[0024] Figure 2 This is a schematic diagram of the structure of a pixel unit in one embodiment of the present invention.

[0025] Figure 3 This is a schematic diagram of the signal output module in one embodiment of the present invention.

[0026] Figure 4 This is a schematic diagram of the structure of a downdrive circuit in one embodiment of the present invention.

[0027] Figure 5 This is a device preset signal timing diagram of the downdrive circuit in one embodiment of the present invention.

[0028] Figure 6This is a schematic diagram of the signal output module in one embodiment of the present invention.

[0029] Figure 7 This is a schematic diagram of the structure of a downdrive circuit in one embodiment of the present invention.

[0030] In the diagram: 100, pixel array; 101, pixel unit; 200, column parallel readout circuit; 300, row drive circuit; 301, first level shift unit; 302, second level shift unit; 310, row drive array; 400, signal output module; 401, first signal output module; 402, second signal output module; 403, third signal output module; 410, controlled inverting unit; 411, first transistor; 412, second transistor; 413, third transistor; 414, fourth transistor; 420, adjustment. Transistor; 500, Timing Generation Module; VDD, Supply Voltage; SF, Source Follower Transistor; PD, Photodiode; RX, Reset Transistor; TX, Transmission Transistor; SEL, Horizontal Spectrum Transistor; 1011, Charge Output Terminal; H, High Level; L, Low Level; OE(n), Horizontal Spectrum Enable Signal; SEL(n), Spectrum Timing Signal; TX(n), Transmission Timing Signal; RX(n), Reset Timing Signal; HI_B, Device Preset Signal; HI_OE(n), First Control Signal; HI_OEB(n), Second Control Signal. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] Please see Figure 1As shown, the image sensor provided by this invention is a CMOS image sensor. In this embodiment, the image sensor includes a pixel array 100. The pixel array 100 includes multiple pixel units 101. The multiple pixel units 101 are arranged in a linear array along rows to form a row circuit. The multiple pixel units 101 are also arranged in a linear array along columns to form a column circuit. In this embodiment, one end of the column circuit is electrically connected to a power supply VDD, and the other end is electrically connected to a column parallel readout circuit 200. In the pixel array 100, multiple column circuits are electrically connected to the same column parallel readout circuit 200, which can simultaneously read multiple columns of data. In this embodiment, multiple pixel units 101 on the row circuits are connected to the same row driving circuit 300. Different row circuits are connected to different row driving circuits 300. The multiple row driving circuits 300 are arranged in columns, thereby forming a row driving array 310.

[0033] Please see Figure 1 and Figure 2 As shown, in one embodiment of the present invention, pixel unit 101 includes a row select transistor SEL, a photodiode PD, a source follower transistor SF, a transmission transistor TX, and a reset transistor RX. The row select transistor SEL, photodiode PD, source follower transistor SF, transmission transistor TX, and reset transistor RX are MOS transistors. The row driving circuit 300 provided by the present invention does not limit the number of transistors in pixel unit 101. In this embodiment, one end of photodiode PD is grounded, and the other end is electrically connected to the source of transmission transistor TX. The drain of transmission transistor TX is electrically connected to the gate of source follower transistor SF and the source of reset transistor RX. The drain of reset transistor RX is electrically connected to power supply VDD, and the drain of source follower transistor SF is also electrically connected to power supply VDD. The source of source follower transistor SF is electrically connected to the drain of row select transistor SEL. The source of row select transistor SEL is electrically connected to the charge output terminal 1011 of pixel unit 101. This invention does not limit the specific type of MOSFET, nor does it limit the number of MOSFETs in pixel unit 101. In this embodiment, pixel unit 101 contains four MOSFETs. In other embodiments of this invention, the number of MOSFETs in pixel unit 101 can be, for example, three, five, six, or eight, etc. In this embodiment, the row select transistor SEL, transmission transistor TX, and reset transistor RX in pixel unit 101 are turned on and off under the control of timing signals. These timing signals are generated by the row drive circuit 300.

[0034] Please see Figures 1 to 3As shown, in one embodiment of the present invention, the pixel array 100 includes, for example, n row circuits. The output signals of the row driving circuit 300 include a strobe timing signal SEL(n), a reset timing signal RX(n), and a transmission timing signal TX(n). Here, n represents the row order in which the row circuit is located. Figure 3 This is a timing diagram of the output signal of the horizontal drive circuit 300 in one embodiment of the present invention. Figure 3 As shown, taking the strobe timing signal SEL(n) as an example, SEL(0) represents the strobe timing signal of the first row of circuits, and SEL(1) represents the strobe timing signal of the second row of circuits. Similarly, SEL(n-1) represents the strobe timing signal of the nth row of circuits. The strobe timing signal SEL(n), reset timing signal RX(n), and transmission timing signal TX(n) can be either high-level or low-level signals. A high-level strobe timing signal SEL(n) can be represented as SELH, and a low-level strobe timing signal SEL(n) can be represented as SELL. A high-level reset timing signal RX(n) can be represented as RXH, and a low-level reset timing signal RX(n) can be represented as RXL. A high-level transmission timing signal TX(n) can be represented as TXH, and a low-level transmission timing signal TX(n) can be represented as TXL. In this embodiment, the voltage level of the high-level signal is higher than the voltage level of the power supply VDD, and the voltage level of the low-level signal is lower than the voltage level of the ground terminal.

[0035] Please see Figures 1 to 4As shown, in one embodiment of the present invention, the row driving circuit 300 includes a first level shift unit 301 and a second level shift unit 302, as well as multiple signal output modules 400. The first level shift unit 301 and the second level shift unit 302 are level shifters, and the input terminal of the first level shift unit 301 is electrically connected to a controller and receives a row selection enable signal OE(n). The controller can be a central processing unit or a microprocessor. The row selection enable signal OE(n) represents the enable signal for the nth row circuit to activate the corresponding row driving unit 300. In this embodiment, the first level shift unit 301 includes a first input terminal and a second input terminal, as well as a first output terminal and a second output terminal. In this embodiment, the first input terminal of the first level shift unit 301 is used to input an initial voltage, and the second input terminal of the first level shift unit 301 is used to input a ground voltage. In the first level shift unit 301, the initial voltage is shifted to obtain a high potential level. The first level shift unit 301 does not process the ground voltage. The first output terminal of the first level shift unit 301 is used to output a high potential level, and the second output terminal of the first level shift unit 301 is used to output a ground voltage. The initial voltage is less than the supply voltage VDD and greater than the ground voltage. The high potential level is greater than the supply voltage VDD. The second level shift unit 302 includes a first input terminal and a second input terminal, as well as a first output terminal and a second output terminal. The first input terminal of the second level shift unit 302 is electrically connected to the first input terminal of the first level shift unit 301 and is used to receive the high potential level. The second input terminal of the second level shift unit 302 is electrically connected to the second input terminal of the first level shift unit 301 and is used to receive the ground voltage. In the second level shift unit 302, the ground voltage is offset to obtain a low potential level. The second level shift unit 302 maintains the output of a high-level voltage. In this embodiment, the high potential level is the highest level among the high-level signals SELH, RXH, and TXH, and the low potential level is the lowest level among the low-level signals SELL, RXL, and TXL.

[0036] Please see Figures 1 to 4As shown, in one embodiment of the present invention, the first output terminal of the second level shift unit 302 outputs a first control signal HI_OE(n), and the second output terminal of the second level shift unit 302 outputs a second control signal HI_OEB(n). The first control signal HI_OE(n) and the second control signal HI_OEB(n) are inverted signals. Specifically, when the first control signal HI_OE(n) is high, the second control signal HI_OEB(n) corresponds to a low level. When the first control signal HI_OE(n) is low, the second control signal HI_OEB(n) corresponds to a high level. The first and second control signals HI_OE(n) originate from the offset of the row strobe enable signal OE(n). Specifically, the first control signal HI_OE(n) and the row strobe enable signal OE(n) have the same level. For example, when the row strobe enable signal OE(n) corresponds to a high level, the first control signal HI_OE(n) is high.

[0037] Please see Figures 1 to 5 As shown, in one embodiment of the present invention, the horizontal drive circuit 300 includes a plurality of signal output modules 400. The plurality of signal output modules 400 are independent of each other and each outputs a different start signal. In this embodiment, the signal output module 400 has a first input terminal, a second input terminal, and a third input terminal. The first input terminal of the signal output module 400 is electrically connected to the first output terminal of the second level shift unit 302, and is used to receive a first control signal HI_OE(n). The second input terminal of the signal output module 400 is electrically connected to the second output terminal of the second level shift unit 302, and is used to receive a second control signal HI_OEB(n). The third input terminal of the signal output module 400 is electrically connected to the digital control circuit of the image sensor, and is used to receive a device preset signal HI_B. The digital control circuit is used to generate the horizontal strobe enable signal OE(n) and the device preset signal HI_B. Figure 5 As shown, the device preset signals include the strobe preset signal HI_SELB, the reset preset signal HI_RXB, and the transmission preset signal HI_TXB. Figure 5 The timing structure of a device preset signal HI_B is shown, which can be used to form Figure 3The diagram shows the gating timing signal SEL(n), the reset timing signal RX(n), and the transmission timing signal TX(n). The signal output module 400 processes the device preset signal, the first control signal, and the second control signal, and its output terminal is used to output the gating timing signal SEL(n), the reset timing signal RX(n), and the transmission timing signal TX(n). It should be noted that this invention does not limit the timing structure of the device preset signal HI_B or the number of signal output modules 400. It should also be noted that the first control signal and the second control signal are out of phase and are limited by the row gating enable signal OE(n). After offset processing by the first level shift unit 301 and the second level shift unit 302, a high-level voltage corresponds to either the first or second control signal, and a low-level voltage corresponds to either the first or second control signal.

[0038] Please see Figure 2 , Figure 4 and Figure 6 As shown, in one embodiment of the present invention, the signal output module 400 includes a controlled inverting unit 410 and an adjusting transistor 420. The controlled inverting unit 410 includes a first transistor 411, a second transistor 412, a third transistor 413, and a fourth transistor 414. The first transistor 411 and the second transistor 412 are PMOS transistors, which conduct when their gates receive a low-level signal. The third transistor 413 and the fourth transistor 414 are NMOS transistors, which conduct when their gates receive a high-level signal. In this embodiment, the first transistor 411, the second transistor 412, the third transistor 413, and the fourth transistor 414 are electrically connected end-to-end. Specifically, the drain of the first transistor 411 is electrically connected to a high-level signal H, and the source of the first transistor 411 is electrically connected to the drain of the second transistor 412. The source of the second transistor 412 is electrically connected to the drain of the third transistor 413, and the source of the third transistor 413 is electrically connected to the drain of the fourth transistor 414. The source of the fourth transistor 414 is electrically connected to a low level L. In this embodiment, one end of the regulating transistor 420 is electrically connected to the output of the controlled inverting unit 410, the other end of the regulating transistor 420 is electrically connected to a low level L, and the gate of the regulating transistor 420 is electrically connected to the second control signal HI_OEB(n). In this embodiment, the high level H can be any one of the high level signals SELH, RXH, and TXH. The low level L can be any one of the low level signals SELL, RXL, and TXL.

[0039] Please see Figure 2 , Figure 4 and Figure 6 As shown, in one embodiment of the present invention, the gates of the first transistor 411 and the fourth transistor 414 are used to receive a device preset signal HI_B, the gate of the second transistor 412 is used to receive a second control signal HI_OEB(n), and the gate of the third transistor 413 is used to receive a first control signal HI_OE(n). In this embodiment, the output terminal of the controlled inverting unit 410 is electrically connected to the source of the second transistor 412 and the drain of the third transistor 413. When the device preset signal HI_B is high, the first transistor 411 is off, and the fourth transistor 414 is on. When the first control signal HI_OE(n) is high, the second control signal HI_OEB(n) is low, and the second transistor 412 and the third transistor 413 are on. The output results of the controlled inverting unit 410 and the signal output module 400 are different depending on the different levels of the first control signal HI_OE(n) and the device preset signal HI_B.

[0040] Please see Figure 2 , Figure 4 and Figure 6As shown, in one embodiment of the present invention, when the first control signal HI_OE(n) is high and the device preset signal HI_B is high, the first transistor 411 is turned off, and the second transistor 412, the third transistor 413, and the fourth transistor 414 are turned on. Therefore, the controlled inverting unit 401 and the low-level L are at the same potential, and the controlled inverting unit 401 outputs any one of the low-level signals SELL, RXL, and TXL. At this time, the regulating transistor 420 is turned off, so the output result of the signal output module 400 is the same as the output result of the controlled inverting unit 401, and the signal output module 400 outputs any one of the low-level signals SELL, RXL, and TXL. In the second embodiment of the present invention, when the first control signal HI_OE(n) is high and the device preset signal HI_B is low, the first transistor 411, the second transistor 412, and the third transistor 413 are turned on, and the fourth transistor 414 is turned off. Therefore, the controlled inverting unit 401 is at the same potential as the high-level H, and thus the controlled inverting unit 401 outputs any one of the high-level signals SELH, RXH, and TXH. At this time, the regulating transistor 420 is off, so the output of the signal output module 400 is the same as the output of the controlled inverting unit 401, and the signal output module 400 outputs any one of the high-level signals SELH, RXH, and TXH. In the third embodiment of the invention, when the first control signal HI_OE(n) is low and the device preset signal HI_B is high, the first transistor 411, the second transistor 412, and the third transistor 413 are off, and the fourth transistor 414 is on. At this time, the regulating transistor 420 is on, so the controlled inverting unit 401 is at the same potential as the low-level L. At this time, the output signals of the signal output module 400 and the controlled inverting unit 410 are the same, and are any one of the low-level signals SELH, RXH, and TXH. In the fourth embodiment of the present invention, when the first control signal HI_OE(n) is low and the device preset signal HI_B is low, the first transistor 411 is turned on, while the second transistor 412, the third transistor 413, and the fourth transistor 414 are turned off. Meanwhile, the regulating transistor 420 is turned on, thus the controlled inverting unit 401 is at the same potential as the low-level L. At this time, the output signals of the signal output module 400 and the controlled inverting unit 410 are the same, and are any one of the low-level signals SELL, RXL, and TXL.

[0041] Please see Figure 2 and Figure 4 , Figure 6 and Figure 7As shown, in one embodiment of the present invention, when the first control signal HI_OE(n) is high, the output signal of the signal output module 400 is opposite to the output signal of the device preset signal HI_B. Specifically, when the device preset signal HI_B is high, the signal output module 400 outputs a low signal. When the device preset signal HI_B is low, the signal output module 400 outputs a high signal. When the first control signal HI_OE(n) is low, the output signal of the signal output module 400 is a low signal. The present invention includes multiple signal output modules 400, and each signal output module 400 outputs a different type of signal. For example... Figure 7 As shown, the output signal of the signal output module 400 is any one of the strobe timing signal SEL(n), the reset timing signal RX(n), and the transmission timing signal TX(n). It should be noted that this invention does not limit the type of output signal; the number of signal output modules 400 varies depending on the type and number of transistors in the pixel unit 101.

[0042] Please see Figure 2 , Figures 4 to 7 As shown, in one embodiment of the present invention, the row drive circuit 300 includes a timing generation module 500. The timing generation module 500 is used to generate a row strobe enable signal OE(n) and a device preset signal HI_B. Figure 3 and Figure 5 As shown, signal OE(n) corresponds to the row strobe enable signal for the nth row. Signals SEL(0) to SEL(n-1) correspond to the strobe timing signals for the first row circuit to the nth row circuit. The strobe timing signals can be either the high-level signal SELH or the low-level signal SELL. Figure 5In this diagram, HI_SELB is the device preset signal for the row select transistor SEL, HI_TXB is the device preset signal for the transmission transistor TX, and HI_RXB is the device preset signal for the reset transistor RX. When OE(1) is low, regardless of whether HI_SELB, HI_TXB, and HI_RXB are high or low, the gating timing signal SEL(0), the reset timing signal RX(0), and the transmission timing signal TX(0) are low. At this time, the transmission transistor TX and the row select transistor SEL are turned off, and the charge of the photodiode PD is not acquired. When OE(1) is high, the gating timing signal SEL(0) is opposite to the level of the device preset signal HI_SELB. At this time, according to different device preset signals, the corresponding transistors are turned on or off, thereby completing operations such as charge transfer, row circuit gating, and pixel unit 101 reset. The first level shifting unit 301 and the second level shifting unit 302 can complete the signal output of multiple transistors. Therefore, the row driving circuit provided by the present invention saves nearly 2 / 3 of the driving circuit area, thereby reducing the power consumption of the image sensor and improving the process yield of the image sensor.

[0043] Please see Figures 1 to 7 As shown, according to the image sensor provided by the present invention, when a row selection circuit needs to be selected, the driving row number of the row circuit to be activated is first obtained. Then, the row selection enable signal of the corresponding row circuit is set to a high level, thereby setting the first control signal to a high level and the second control signal to a low level, activating the row circuit of the corresponding row. Next, the driving signals of multiple transistors in the row circuit are set, wherein the transistor driving signals include, but are not limited to, the selection timing signal SEL(n), the transmission timing signal TX(n), and the reset timing signal RX(n). In this embodiment, the device preset signal of the device to be activated is set to a low level, thereby outputting a high-level device timing signal. When the row circuit of the corresponding row is no longer used, the row selection timing signal is set to a low level, at which time the device timing signal of the corresponding device is low, and the transistor of the corresponding row circuit is turned off.

[0044] This invention provides a row driving circuit, which includes a level shifter and multiple signal output modules. The level shifter receives a row strobe enable signal and outputs a first control signal and a second control signal, wherein the first control signal and the row strobe enable signal are in phase, and the second control signal and the first control signal are out of phase. Multiple signal output modules are electrically connected to the output terminal of the level shifter and the driving terminal of the row circuit. The input terminal of each signal output module receives the first control signal, the second control signal, and a device preset signal. When the first control signal is high, the output signal of the signal output module is out of phase with the device preset signal; when the first control signal is low, the output signal of the signal output module is a low-level signal. The number of MOS transistors in the pixel unit provided by this invention can be, for example, 3, 4, 6, or 8, etc., and this invention does not limit this. According to the row driving circuit provided by this invention, based on a set of first and second level shift units, the generation of driving signals for multiple transistors can be realized. Therefore, the row driving circuit of this invention can be applied to the formation of image sensors. The image sensor provided by this invention can drive any one or more row circuits in the pixel array of the image sensor to realize operations such as charge transfer, reset, and selective activation of pixel units. The row driving circuit and method, and the image sensor provided by this invention can send timing signals to multiple transistors in the row circuit, thereby controlling the transistors to turn on or off. Furthermore, the row driving circuit provided by this invention occupies less integrated circuit area; for image sensors with complex structures and high integration, the row driving circuit provided by this invention can save even more integrated circuit area, thus resulting in lower power consumption. Moreover, the de-driving method of the row driving circuit provided by this invention is simple and has high driving efficiency.

[0045] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A row driving circuit, characterized in that, For driving row circuits in a pixel array, the row driving circuits include: A level shifter that receives a row strobe enable signal and outputs a first control signal and a second control signal, wherein the first control signal and the row strobe enable signal are in phase, and the second control signal and the first control signal are out of phase; and Multiple signal output modules are electrically connected to the output terminal of the level shifter and the driving terminal of the horizontal circuit. The input terminal of each signal output module receives the first control signal, the second control signal, and the device preset signal. When the first control signal is high, the output signal of the signal output module is inverted with the device preset signal. When the first control signal is low, the output signal of the signal output module is a low-level signal. A timing generation module, the output of which is electrically connected to the level shifter and the signal output module, and outputs the row strobe enable signal and the device preset signal to the level shifter, wherein the device preset signal includes a strobe preset signal, a reset preset signal and a transmission preset signal.

2. The row driving circuit according to claim 1, characterized in that, The level shifter includes a first level shift unit, the input of which is electrically connected to the timing generation module, the power supply terminal, and the ground terminal, and the first level shift unit outputs a high-level voltage and a ground voltage, wherein the high-level voltage is greater than the voltage of the power supply terminal.

3. A row driving circuit according to claim 2, characterized in that, The level shifter includes a second level shift unit, the input of which is electrically connected to the first level shift unit, and the second level shift unit outputs the high-level voltage and the low-level voltage, wherein the low-level voltage is less than the voltage of the ground terminal.

4. A row driving circuit according to claim 3, characterized in that, The signal output module includes a controlled inverting unit, which includes multiple transistors connected in series.

5. A row driving circuit according to claim 4, characterized in that, The signal output module includes a first transistor, the driving terminal of the first transistor is electrically connected to the timing generation module and receives the preset signal of the device, the first terminal of the first transistor is electrically connected to the output terminal of the second level shift unit, and the first terminal of the first transistor is set to the high level voltage.

6. A row driving circuit according to claim 5, characterized in that, The signal output module includes a second transistor and a third transistor connected in series. The driving terminals of the second transistor and the third transistor are electrically connected to the output terminal of the second level shifting unit. The second transistor and the third transistor are simultaneously turned on or simultaneously turned off, and the common terminal of the second transistor and the third transistor is the output terminal of the controlled inverting unit.

7. A row driving circuit according to claim 6, characterized in that, The signal output module includes a fourth transistor. The driving terminal of the fourth transistor is electrically connected to the timing generation module and receives a preset signal from the device. The first terminal of the fourth transistor is electrically connected to the second terminal of the third transistor. The second terminal of the fourth transistor is electrically connected to the output terminal of the second level shifting unit, and the second terminal of the fourth transistor is set to a low-level voltage.

8. A row driving circuit according to claim 4, characterized in that, The signal output module includes an adjustment transistor. The first terminal of the adjustment transistor is electrically connected to the output terminal of the controlled inverting unit, and the second terminal of the adjustment transistor is electrically connected to the output terminal of the second level shifting unit. The second terminal of the adjustment transistor is set to a low-level voltage. The driving terminal of the adjustment transistor is electrically connected to the output terminal of the second level shifting unit and receives the second control signal.

9. An image sensor, characterized in that, include: A pixel array comprising multiple pixel units, wherein the pixel units are arranged in rows and columns to form row circuits and column circuits; as well as A row driving circuit as described in any one of claims 1 to 8, wherein the row driving circuit is electrically connected to the row circuit and drives the row circuit.

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