Silicon-based three-dimensional capacitor and method of making the same
By using deep silicon etching and vapor deposition techniques, a high aspect ratio capacitor structure was formed in a silicon-based three-dimensional capacitor, solving the problem of low density in existing silicon-based three-dimensional capacitors and realizing a high capacitance density silicon-based three-dimensional capacitor.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- THE 13TH RES INST OF CHINA ELECTRONICS TECH GRP CORP
- Filing Date
- 2023-09-04
- Publication Date
- 2026-06-09
AI Technical Summary
Existing silicon-based three-dimensional capacitors have low density, making it impossible to achieve a high aspect ratio and thus failing to meet the requirements of high breakdown voltage applications.
By employing deep silicon etching and vapor deposition technology, a dielectric mask layer is prepared on the surface of a silicon substrate and micropores are etched to form multiple spaced deep holes. Combined with a flow hood to change the direction of the deposition gas flow, the first polycrystalline silicon layer is closed-loop grown in the deep holes. A second deep hole is formed by deep silicon etching again, thereby improving the vertical aspect ratio.
The capacitance density of silicon-based three-dimensional capacitors has been improved, achieving aspect ratios of 30:1 to 100:1 to meet the requirements of high breakdown voltage applications.
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Figure CN117279490B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a silicon-based three-dimensional capacitor and its fabrication method. Background Technology
[0002] As integrated circuits place increasingly higher demands on capacitors, various capacitor structures have been researched to meet the application needs of different scenarios, such as ceramic capacitors, aluminum electrolytic capacitors, tantalum electrolytic capacitors, film capacitors, and silicon-based three-dimensional capacitors.
[0003] Capacitors are fundamental components in electronic systems, and ceramic capacitors, as a primary solution for miniaturized capacitors, are currently widely used in electronic systems. However, in applications requiring high breakdown voltage, ceramic capacitors suffer from low capacitance density, large size, and cannot be integrated with silicon wafer-level processes. Traditional silicon-based three-dimensional capacitors, fabricated using microelectronics technology, employ a single etching method to achieve the vertical capacitor structure. Due to limitations in etching process capabilities, a high aspect ratio cannot be achieved, resulting in low capacitance density.
[0004] How to increase the density of silicon-based three-dimensional capacitors has become an urgent technical problem to be solved. Summary of the Invention
[0005] This invention provides a silicon-based three-dimensional capacitor and its fabrication method to solve the problem of low density in current three-dimensional capacitors.
[0006] In a first aspect, embodiments of the present invention provide a method for fabricating a silicon-based three-dimensional capacitor, comprising the following steps:
[0007] A dielectric mask layer is prepared on the surface of a silicon substrate, and multiple spaced micropores are etched on the dielectric mask layer until the silicon substrate is exposed.
[0008] A deep silicon etching process is used to etch multiple spaced micro-holes to form multiple spaced first deep holes;
[0009] Remove the remaining dielectric mask layer and prepare a first polysilicon layer on a silicon substrate with multiple spaced-apart first deep holes; wherein the thickness of the first polysilicon layer in the first deep hole is less than the height of the first deep hole, and a first polysilicon layer is provided on a first region of the first deep hole, and no first polysilicon layer is filled between the first polysilicon layer in the first deep hole and the first polysilicon layer on the first region, so that the first polysilicon layer in the first deep hole grows in a closed manner, and the first region is the region on the first deep hole that is at the same height as the silicon substrate;
[0010] A deep silicon etching process is used to etch the first polysilicon layer inside the first deep hole to form a second deep hole inside the first polysilicon layer inside the first deep hole, and the bottom and side surfaces of the second deep hole are provided with the first polysilicon layer.
[0011] An insulating dielectric layer, a second polysilicon layer, and an electrode layer are sequentially grown on the first polysilicon layer on the surface of the silicon substrate and within all the spaced-apart second deep holes.
[0012] In one possible implementation, removing the remaining dielectric mask layer and fabricating a first polycrystalline silicon layer on a silicon substrate having a plurality of spaced-apart first deep holes includes:
[0013] A flow equalization hood is installed in the equipment for preparing the first polycrystalline silicon layer. The flow equalization hood is set at a first preset height on the upper surface of the silicon substrate. The flow equalization hood is provided with a plurality of inclined micropores arranged at intervals to change the airflow direction of the deposition gas so that the deposition rate of the first polycrystalline silicon layer is different at different positions.
[0014] A first polycrystalline silicon layer is prepared on a silicon substrate having a plurality of spaced-apart first deep holes.
[0015] In one possible implementation, the tilt angle of the tilted micro-holes on the flow equalization hood is 20°-70°, the diameter of the tilted micro-holes is 0.5~5mm, and the thickness of the flow equalization hood is 0.5~5mm.
[0016] In one possible implementation, the first preset height is 1~10mm.
[0017] In one possible implementation, the depth of the first deep hole is 10~50um.
[0018] In one possible implementation, the resistivity of the first polysilicon layer and the second polysilicon layer is less than 0.01 Ω*cm, the thickness of the first polysilicon layer is 5~50 μm, and the thickness of the second polysilicon layer is 1~10 μm.
[0019] In one possible implementation, the thickness of the insulating dielectric layer is 0.1~3 μm, and the insulating dielectric layer is at least one or more of silicon oxide, silicon nitride, aluminum nitride, aluminum oxide or hafnium oxide.
[0020] In one possible implementation, the resistivity of the silicon substrate is less than 0.01 Ω*cm, and the thickness is 50~500um.
[0021] In one possible implementation, the electrode layer is made of a thin film of aluminum or gold.
[0022] Secondly, embodiments of the present invention provide a silicon-based three-dimensional capacitor, fabricated using the silicon-based three-dimensional capacitor fabrication method of any one of the first aspects, including...
[0023] A silicon substrate with multiple etched deep holes on its surface;
[0024] A first polysilicon layer is provided on the bottom and sidewalls of each etched deep hole;
[0025] A first polysilicon layer is provided on the surface of a first silicon substrate, wherein the surface of the first silicon substrate does not include multiple etched deep holes;
[0026] An insulating dielectric layer is provided on the first polysilicon layer on the surface of the first silicon substrate and in each etched deep hole;
[0027] A second polysilicon layer is provided on the insulating dielectric layer, and the second polysilicon layer inside the etched deep hole is at the same height as the second polysilicon layer on the first polysilicon layer.
[0028] A metal electrode layer is provided on the second polysilicon layer.
[0029] This invention provides a silicon-based three-dimensional capacitor and its fabrication method. Building upon a vertical capacitor achieved through a single deep silicon etching process, a deposition process is employed. By altering the deposition rate of the first polysilicon layer inside and outside a first deep hole, closed-loop growth of the first polysilicon layer within the first deep hole is achieved. Furthermore, by repeating deep silicon etching, the bottom and sidewalls of a second deep hole are also provided with the first polysilicon layer, thereby improving the capacitor's aspect ratio and increasing its capacitance density. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 This is a flowchart illustrating the implementation of the method for fabricating a silicon-based three-dimensional capacitor provided in this embodiment of the invention.
[0032] Figure 2 This is a schematic diagram of the structure for fabricating a dielectric mask layer on a silicon substrate according to an embodiment of the present invention;
[0033] Figure 3 This is a schematic diagram of the structure for preparing multiple spaced-apart etched micropores provided in an embodiment of the present invention;
[0034] Figure 4 This is a schematic diagram of the structure of the first deep silicon etching provided in an embodiment of the present invention;
[0035] Figure 5 This is a schematic diagram of the structure after removing the dielectric mask layer according to an embodiment of the present invention;
[0036] Figure 6 This is a schematic diagram of the structure of the first polycrystalline silicon layer after preparation, provided in an embodiment of the present invention;
[0037] Figure 7 This is a schematic diagram of the flow equalization shroud provided in an embodiment of the present invention;
[0038] Figure 8 This is a schematic diagram of the process for preparing the first polycrystalline silicon layer provided in an embodiment of the present invention;
[0039] Figure 9 This is a schematic diagram of the structure after secondary deep silicon etching provided in an embodiment of the present invention;
[0040] Figure 10 This is a schematic diagram of the structure for preparing the insulating dielectric layer provided in an embodiment of the present invention;
[0041] Figure 11 This is a schematic diagram of the structure for preparing the second polycrystalline silicon layer provided in an embodiment of the present invention;
[0042] Figure 12 This is a schematic diagram of the structure of a silicon-based three-dimensional capacitor provided in an embodiment of the present invention. Detailed Implementation
[0043] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.
[0044] To make the objectives, technical solutions, and advantages of the present invention clearer, specific embodiments will be described below in conjunction with the accompanying drawings.
[0045] Microelectromechanical processing (MEMS) technology is developed based on semiconductor integrated circuit processing technology. Unlike traditional machining techniques, MEMS possesses the high precision characteristics of integrated circuit manufacturing technology, enabling the fabrication of high-precision three-dimensional microstructures. MEMS can be used to fabricate high-density silicon-based three-dimensional capacitors. As described in the background section, most existing high-density silicon-based three-dimensional capacitors utilize a single etching process to achieve the vertical capacitor structure. However, due to limitations in current etching capabilities, a high aspect ratio cannot be achieved, resulting in low capacitor density.
[0046] To address the problems of existing technologies, embodiments of the present invention provide a silicon-based three-dimensional capacitor and a method for fabricating the same. The method for fabricating the silicon-based three-dimensional capacitor provided in this embodiment will be described below.
[0047] like Figure 1 As shown, a method for fabricating a silicon-based three-dimensional capacitor includes the following steps:
[0048] S110. A dielectric mask layer is prepared on the surface of a silicon substrate, and multiple spaced micro-holes are etched on the dielectric mask layer until the silicon substrate is exposed.
[0049] like Figure 2 As shown, the silicon substrate 10 is a low-resistivity silicon substrate. The silicon substrate 10 can be a single-polished or double-polished wafer with a resistivity of less than 0.01 Ω*cm. The doping type can be N-type or P-type, and the thickness ranges from 50 to 500 μm. A dielectric mask layer 20 is deposited on the upper surface of the silicon substrate 10. The dielectric mask layer 20 can be silicon oxide or silicon nitride.
[0050] like Figure 3 As shown, multiple spaced-apart micropores are fabricated on the surface of the dielectric mask layer 20 using photolithography and reactive ion etching processes until the silicon substrate 10 is exposed.
[0051] S120. A deep silicon etching process is used to etch multiple spaced micro-holes to form multiple spaced first deep holes.
[0052] like Figure 4 As shown, the depth of the first deep hole 71 is 10~50um.
[0053] S130. Remove the remaining dielectric mask layer and prepare a first polycrystalline silicon layer on a silicon substrate with a plurality of spaced-apart first deep holes.
[0054] like Figure 5 As shown, a wet etching process is used to remove the remaining dielectric mask layer 20 on the surface of the silicon substrate 10.
[0055] After removing the dielectric mask layer 20, as Figure 6 and 7 As shown, a first polysilicon layer 30 is deposited on the surface of the silicon substrate 10 based on the first deep hole 71 of the vertical capacitor structure achieved by the first etching process using vapor deposition.
[0056] To improve the aspect ratio and density of the capacitor, the thickness of the first polysilicon layer 30 within the first deep hole 71 needs to be less than the thickness of the first polysilicon layer 30 on the surface of the first silicon substrate during fabrication. This allows the interior of the first deep hole 71 to be hollowed out, enabling the first polysilicon layer within the first deep hole 71 to grow in a closed manner at its upper end. The specific fabrication process is as follows:
[0057] S1301. A flow hood is installed in the equipment for preparing the first polycrystalline silicon layer. The flow hood is positioned at a first preset height on the upper surface of the silicon substrate.
[0058] like Figure 7 As shown, the flow hood 80 is provided with a plurality of spaced inclined microholes 81 to change the airflow direction of the deposition gas so that the deposition rate of the first polycrystalline silicon layer 30 is different at different positions.
[0059] The tilt angle of the inclined micro-holes on the flow equalization hood is 20°-70°, the diameter of the inclined micro-holes is 0.5~5mm, and the thickness of the flow equalization hood is 0.5~5mm.
[0060] In some embodiments, the first preset height is 1 to 10 mm. The flow direction of the deposition gas can be changed by the flow equalization hood 80, which can significantly increase the proportion of gas flow through the silicon substrate surface and into the first deep hole 71, thereby achieving the deposition of a thin layer of first polysilicon only on the sidewall inside the first deep hole 71, while a thicker layer of first polysilicon is deposited on the upper surface of the first deep hole 71, that is, at the position flush with the silicon substrate 10.
[0061] S1302. A first polycrystalline silicon layer is prepared on a silicon substrate having a plurality of spaced-apart first deep holes.
[0062] like Figure 8 As shown, Figure 8 The arrows indicate the gas flow direction. By using inclined micropores 81 spaced apart on the flow equalization hood 80, the coverage of the first polysilicon layer 30 within the first deep hole 71 can be reduced. Only a thin layer of the first polysilicon layer 30 is deposited inside the first deep hole 71 structure, while a thicker polysilicon layer is deposited on the upper surface of the microporous structure. The thickness of the first polysilicon layer 30 within the first deep hole 71 is less than the height of the first deep hole 71, and a first polysilicon layer is provided on the first region of the first deep hole 71. The space between the first polysilicon layer within the first deep hole and the first polysilicon layer on the first region is not filled with a first polysilicon layer, allowing the first polysilicon layer within the first deep hole to grow in a closed manner. Figure 6The cone shape shown is an air-formed cone shape without the first polysilicon layer filled. This is because the inclined micropores 81 spaced apart on the uniform flow hood 80 result in different deposition rates. The first polysilicon layer is easily deposited on the surface of the first deep hole 71, while it is more difficult to deposit the first polysilicon layer inside the first deep hole 71. This makes it impossible for the first deep hole 71 to be completely filled with the first polysilicon, thus achieving closed growth of the upper end of the microstructure while hollowing out the first deep hole 71.
[0063] In some embodiments, the resistivity of the first polysilicon layer is less than 0.01 Ω*cm, and the thickness of the first polysilicon layer is 5~50 μm.
[0064] S140. Using a deep silicon etching process, the first polysilicon layer inside the first deep hole is etched to form a second deep hole inside the first polysilicon layer inside the first deep hole.
[0065] The bottom and side surfaces of the second deep hole are provided with a first polycrystalline silicon layer 30.
[0066] like Figure 9 As shown, the bottom and side surfaces of the second deep hole 72 are provided with a first polysilicon layer 30. During the first deep silicon etching process, a first deep hole 71 with a relatively small aspect ratio was fabricated. By using a flow hood 80 with inclined micro-holes 81 to deposit the first polysilicon layer within the first deep hole 71, the deposition rate of the first polysilicon within the first deep hole 71 is lower than the deposition rate on the substrate surface due to the inclined micro-holes 81, thus forming a conical hollow within the first deep hole 71, allowing the upper end of the first deep hole to achieve closed growth. During the second deep silicon etching process, the second deep hole 72 is etched onto the first polysilicon layer within the first deep hole 71, and the bottom and sidewalls of the second deep hole 72 are also provided with a first polysilicon layer, thereby increasing the aspect ratio of the second deep hole 72.
[0067] The aspect ratio of current silicon-based three-dimensional capacitors is generally 20:1, while the aspect ratio of the silicon-based three-dimensional capacitors prepared in this application can be from 30:1 to 100:1.
[0068] S150, An insulating dielectric layer, a second polysilicon layer, and an electrode layer are sequentially grown on the first polysilicon layer on the surface of the silicon substrate and in all the spaced-apart second deep holes.
[0069] like Figure 10 As shown, an insulating dielectric layer 40 is grown on the first polycrystalline silicon layer on the surface of the silicon substrate and within all the spaced-apart second deep holes 72 using a vapor deposition process. This insulating dielectric layer 40 can be one or a combination of several dielectrics such as silicon oxide, silicon nitride, aluminum nitride, aluminum oxide, and hafnium oxide. The thickness is 0.1~3 μm.
[0070] like Figure 11As shown, a second polysilicon layer 50 is deposited on the surface of the insulating dielectric layer 40 using a vapor deposition process. This polysilicon layer is low-resistivity polysilicon with a resistivity of less than 0.01 Ω*cm. The doping type can be N-type or P-type, and the thickness is 1~10 μm.
[0071] The first polycrystalline silicon layer 30, the insulating dielectric layer 40, and the second polycrystalline silicon layer 50 together constitute the three-layer structure of the parallel plate capacitor: the lower electrode, the dielectric, and the upper electrode. Due to the use of a vertical microporous structure, silicon-based three-dimensional capacitors fabricated using this structure can form high-density capacitors with a large aspect ratio within a relatively small area.
[0072] like Figure 12 As shown, electrode layer lead-out patterns are fabricated on the chip surface using sputtering etching or evaporation stripping processes.
[0073] This invention enables the fabrication of silicon-based three-dimensional capacitors with higher aspect ratios, ranging from 30:1 to 100:1, by alternating between two deep silicon etching processes.
[0074] The fabrication method provided by this invention, based on the vertical capacitor achieved by a single deep silicon etching process, employs a deposition process to achieve closed growth of the first polysilicon layer inside the first deep hole by changing the deposition rate of the first polysilicon layer inside and outside the first deep hole. Furthermore, by using deep silicon etching again, the bottom and sidewalls of the second deep hole are provided with the first polysilicon layer, thereby improving the vertical aspect ratio of the capacitor and increasing the capacitance density.
[0075] Secondly, the present invention also provides a silicon-based three-dimensional capacitor, which is fabricated using the silicon-based three-dimensional capacitor fabrication method provided in the first aspect. The specific structure is as follows: Figure 12 As shown, the silicon-based three-dimensional capacitor includes a silicon substrate 10, on which a plurality of etched deep holes are formed. A first polysilicon layer 30 is formed on the bottom and sidewalls of each etched deep hole. The first silicon substrate surface is the surface of the silicon substrate 10 excluding the plurality of etched deep holes. An insulating dielectric layer 40 is formed on the first polysilicon layer 30 on the surface of the first silicon substrate and in each etched deep hole. A second polysilicon layer 50 is formed on the insulating dielectric layer 40, and the second polysilicon layer 50 in the etched deep hole is at the same height as the second polysilicon layer 50 on the first polysilicon layer 30. A metal electrode layer 60 is formed on the second polysilicon layer.
[0076] In some embodiments, the silicon substrate 10 provides support and conductivity. The resistivity of the silicon substrate 10 is less than 0.01 Ω*cm, and the doping type can be N-type or P-type, with a thickness ranging from 50 to 500 μm. This substrate material provides structural support for the capacitor and a conductive channel for the lower electrode of the capacitor. The upper surface of the substrate material has a longitudinally etched deep-hole structure fabricated using microelectromechanical processing.
[0077] The first polysilicon layer 30 is used to form the lower electrode of the capacitor. The first polysilicon layer 30 is low-resistivity polysilicon with a resistivity of less than 0.01 Ω*cm, and the doping type can be N-type or P-type. The first polysilicon layer 30 fills the structural sidewalls of the etched deep hole of the silicon substrate 10 and is deposited on the surface of the silicon substrate 10 to a certain thickness.
[0078] The insulating dielectric layer 40 is used to form the capacitor dielectric. This layer is an insulating dielectric fabricated using semiconductor technology and can be one or a combination of several dielectrics such as silicon oxide, silicon nitride, aluminum nitride, aluminum oxide, and hafnium oxide. This insulating dielectric layer fills the sidewalls of the etched deep hole structure formed by the first polysilicon layer and is deposited on the surface of the first polysilicon layer to a certain thickness.
[0079] The second polysilicon layer 50 is used to form the upper electrode of the capacitor. This polysilicon layer is low-resistivity polysilicon with a resistivity of less than 0.01 Ω*cm, and the doping type can be N-type or P-type. The second polysilicon layer 50 fills the structural sidewalls of the etched deep hole formed by the insulating dielectric layer 40 and is deposited on the surface of the insulating dielectric layer to a certain thickness.
[0080] The electrode layer 60 is used for electrical signal extraction, and this layer can be a thin film material of metal such as aluminum or gold.
[0081] The first polysilicon layer 30, the insulating dielectric layer 40, and the second polysilicon layer 50 together constitute the three-layer structure of the parallel-plate capacitor: the lower electrode, the dielectric, and the upper electrode. Due to the use of a vertically etched deep-hole structure, silicon-based three-dimensional capacitors fabricated using this structure can achieve high capacitance density within a relatively small area.
[0082] The aspect ratio of the silicon-based three-dimensional capacitor of the present invention is from 30:1 to 100:1.
[0083] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
[0084] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.
Claims
1. A method for fabricating a silicon-based three-dimensional capacitor, characterized in that, Includes the following steps: A dielectric mask layer is prepared on the surface of a silicon substrate, and a plurality of spaced-apart micropores are etched on the dielectric mask layer until the silicon substrate is exposed. A deep silicon etching process is used to etch the multiple spaced-apart micro-holes to form a multiple spaced-apart first deep hole; Remove the remaining dielectric mask layer and prepare a first polysilicon layer on a silicon substrate having the plurality of spaced-apart first deep holes; wherein the thickness of the first polysilicon layer within the first deep holes is less than the height of the first deep holes, and a first polysilicon layer is provided on a first region of the first deep holes, and no first polysilicon layer is filled between the first polysilicon layer within the first deep holes and the first polysilicon layer on the first region, so that the first polysilicon layer within the first deep holes grows in a closed manner, and the first region is a region on the first deep holes that is at the same height as the silicon substrate; A deep silicon etching process is used to etch the first polysilicon layer inside the first deep hole to form a second deep hole inside the first polysilicon layer inside the first deep hole, and the bottom and side surfaces of the second deep hole are provided with the first polysilicon layer. An insulating dielectric layer, a second polysilicon layer, and an electrode layer are sequentially grown on the first polysilicon layer on the surface of the silicon substrate and within all the spaced-apart second deep holes.
2. The preparation method according to claim 1, characterized in that, The step of removing the remaining dielectric mask layer and fabricating a first polycrystalline silicon layer on a silicon substrate having the plurality of spaced-apart first deep holes includes: A flow equalization hood is installed in the equipment for preparing the first polycrystalline silicon layer. The flow equalization hood is located at a first preset height on the upper surface of the silicon substrate. The flow equalization hood is provided with a plurality of spaced inclined micropores to change the airflow direction of the deposition gas so that the deposition rate of the first polycrystalline silicon layer is different at different positions. A first polycrystalline silicon layer is prepared on a silicon substrate having the plurality of spaced-apart first deep holes.
3. The preparation method according to claim 2, characterized in that, The tilt angle of the inclined micro-holes on the flow equalization hood is 20°-70°, the diameter of the inclined micro-holes is 0.5~5mm, and the thickness of the flow equalization hood is 0.5~5mm.
4. The preparation method according to claim 2 or 3, characterized in that, The first preset height is 1~10mm.
5. The preparation method according to any one of claims 1-3, characterized in that, The depth of the first deep hole is 10~50um.
6. The preparation method according to any one of claims 1-3, characterized in that, The resistivity of the first polysilicon layer and the second polysilicon layer is less than 0.01 Ω*cm, the thickness of the first polysilicon layer is 5~50 μm, and the thickness of the second polysilicon layer is 1~10 μm.
7. The preparation method according to any one of claims 1-3, characterized in that, The thickness of the insulating dielectric layer is 0.1~3 μm, and the insulating dielectric layer is at least one or more of silicon oxide, silicon nitride, aluminum nitride, aluminum oxide or hafnium oxide.
8. The preparation method according to any one of claims 1-3, characterized in that, The resistivity of the silicon substrate is less than 0.01 Ω*cm, and the thickness is 50~500 μm.
9. The preparation method according to any one of claims 1-3, characterized in that, The electrode layer is made of a thin film of aluminum or gold.
10. A silicon-based three-dimensional capacitor, characterized in that, The silicon-based three-dimensional capacitor is prepared using the method described in any one of claims 1-9, including... A silicon substrate, wherein multiple etched deep holes are provided on the surface of the silicon substrate; A first polysilicon layer is provided on the bottom and sidewalls of each of the etched deep holes; A first polysilicon layer is provided on the surface of a first silicon substrate, wherein the surface of the first silicon substrate does not include the plurality of etched deep holes; An insulating dielectric layer is provided on the first polysilicon layer on the surface of the first silicon substrate and in each of the etched deep holes; A second polysilicon layer is provided on the insulating dielectric layer, and the second polysilicon layer inside the etched deep hole is at the same height as the second polysilicon layer on the first polysilicon layer; A metal electrode layer is provided on the second polysilicon layer.