Memory address protection

Abstract

A method for memory protection, the method comprising receiving a burst write instruction including data and a burst write address. The data is segmented into a plurality of data blocks. One or more bits of the burst write address or a hash of the burst write address are cascaded to a corresponding data block to obtain a data and write address bit (DWAB) segment. SECDED ECC is performed on the corresponding DWAB segment to generate a corresponding plurality of sets of parity bits (DWAB‑PB). The corresponding DWAB‑PB is cascaded to the corresponding data block to generate a corresponding forward error correction (FEC) block, none of which includes the burst write address or the hash of the burst write address. A burst write command and a corresponding portion of the corresponding FEC block are sent to a corresponding memory device during a plurality of beats until all beats of the burst write have been sent.

Description

[0001] Related Applications

[0002] This application claims the benefit of the priority date of U.S. Provisional Patent Application Serial No. 63 / 195,618, filed on June 1, 2021, under 35 U.S.C. §119, the entire contents of which are incorporated by reference as if fully set forth herein. Background Art

[0003] Random access memory (RAM) is a semiconductor memory of a widely used type, and includes dynamic RAM (DRAM), synchronous DRAM (SDRAM) and double data rate (DDR) SDRAM that transmit data on both the rising and falling edges of each clock pulse. Some DDR SDRAMs (such as, for example, DDR4 SDRAM and DDR5 SDRAM) can be operated as burst memory. In burst mode, these DDR SDRAMs promote high-speed and high-throughput data transmission. For example, a processor instruction that needs to access data from a DDR SDRAM presents an address to it in a read request instruction, and then waits for the requested information in a time consistent with the clock speed of the memory operation. When locating the first block of the requested data, multiple (e.g., 32) bytes in the immediate vicinity of the first block are transmitted in the same transaction as the "burst" of the memory activity. Similarly, in order to write data, multiple (e.g., 32) bytes in the immediate vicinity of the first block are written in the same transaction as the "burst" of the memory activity.

[0004] DDR SDRAM iterations that allow burst read and write operations, such as DDR4 SDRAM and DDR5 SDRAM, are desirable because they can operate at higher bit rates and / or frequencies than earlier generations of DDR SDRAM devices. However, such memories are subject to erroneous read address events, such as address line errors, where unwanted data is recovered from an incorrect address.

[0005] Some address line errors arise from a one-bit (1-bit) flip somewhere on the affected read address. In the context of reliable operation of data centers and other entities running large amounts of data traffic, a 1-bit flip can have catastrophic consequences. In such contexts, address line errors need to be consistently detected to prevent the generation and subsequent propagation of such errors. Error correction is used to prevent or ameliorate these and related problems.

[0006] An address error (sometimes called an "address line" error or a "bad address") occurs when the data retrieved from a read operation is not the data intended to be retrieved by the read instruction due to a mismatch between the burst write address and the read address used to perform the particular read operation.

[0007] Some errors occur during the process of writing data to the DDR SDRAM, which may be referred to as "burst write-related errors". These types of errors may occur due to a mismatch between the burst write address and the address used to perform a particular write operation or due to some other error in the write process. A "poison-bit" marker is sometimes used to mark a DDR SDRAM burst as "interrupted", meaning that the burst is known to be faulty with respect to an address line error (or other error), and therefore the data is known to be corrupted with respect to the processor data request when writing the data. When a poison bit marker is used to identify a specific error, burst write-related errors or other errors known during the write process may be collectively referred to as "poison bit indication errors".

[0008] Conventional error correction methods have used a single bit from an error correction control (ECC) parity field to represent a poison bit mark. Using a parity field bit to mark a poison bit is undesirable because the number of bits available for ECC is reduced. Another conventional method flips multiple bits from a burst block as a poison bit mark. These conventional methods may result in marked blocks that cannot be decoded correctly but are indistinguishable from normal undecodable blocks (e.g., blocks with too many errors). In fact, the conventional methods thus "lose" the poison bit mark itself. These methods may not only result in completely bad blocks that cannot be corrected, but also the marked blocks are subject to error correction. More specifically, the marked blocks may be mistakenly marked as "good", but actually include completely incorrect data. As used herein, the term "error correction" involves marking a burst block for processing as including uncorrupted data corresponding to a memory address in its header, but actually including data that is irrelevant to a given address, so it is worthless and / or counterproductive for continued processing.

[0009] Another situation that may lead to miscorrection is a wrong address error that occurs when the data retrieved from a read operation is not the data intended to be retrieved by the read instruction due to a mismatch between the burst read address and the read address used to perform the particular read operation, which may be referred to as a burst read related error. This may occur due to a mismatch between the burst read address and the read address used to perform the particular read operation.

[0010] Therefore, a method and apparatus is needed that will allow address errors and poison bit indication errors to be identified and corrected to reduce the chance of uncorrectable errors caused by poison block marking and error correction while not limiting the number of bits available for storing ECC parity bits. Summary of the invention

[0011] A method for memory protection is disclosed herein, the method comprising receiving a burst write instruction. The burst write instruction comprises data and a burst write address. The data is segmented into a plurality of data blocks. One or more bits of the burst write address or a hash of the burst write address are cascaded to a corresponding data block in a plurality of data blocks to obtain a plurality of data and write address bit (DWAB) segments. A single error correction and double error detection (SECDED) error correction code (ECC) is performed on a corresponding DWAB segment in a plurality of DWAB segments to generate a corresponding plurality of groups of parity bits (DWAB-PB). The corresponding DWAB-PB is cascaded to a corresponding data block to generate a corresponding forward error correction (FEC) block. None of the FEC blocks comprises a burst write address or a hash of the burst write address. During a corresponding beat in a plurality of beats, a burst write command and a corresponding portion of a corresponding FEC block in the FEC block are sent to a corresponding memory device in a plurality of memory devices until all beats of the burst write have been sent.

[0012] In one specific implementation, concatenating one or more bits of a burst write address or a hash of a burst write address further comprises concatenating a poison indicator bit and one or more bits of a burst write address or a hash of a burst write address to corresponding data blocks in a plurality of data blocks to obtain a plurality of DWAB segments. None of the FEC blocks includes a poison indicator bit, a burst write address, or a hash of a burst write address.

[0013] A method for memory protection, the method comprising, in response to receiving a burst read instruction including a burst read address, performing a burst read by sending a burst read command to a plurality of memory devices and receiving a plurality of read forward error correction (read-FEC) blocks in response. The read FEC block is segmented to obtain a plurality of data portions and a plurality of corresponding DWAB-PBs. One or more bits of the burst read address or a hash of the burst read address are concatenated to a corresponding data portion of the plurality of data portions to obtain a plurality of data and read address bit (DRAB) segments. A corresponding DRAB segment of the plurality of DRAB segments is decoded using a corresponding DWAB-PB and a single error correction double error detection (SECDED) decoding operation to identify a data block for the corresponding DRAB segment and to identify a bit position of a corrected bit when a single event correction (SEC) has occurred. When a bit position corresponding to one or more bits of the burst read address or a hash of the burst read address has been SEC'd, it is determined that a read address error has occurred. When a read address error has occurred, the method comprises: indicating that an address error has occurred, requesting a retransmission of the burst read instruction, or indicating that an address error has occurred and requesting a retransmission of the burst read instruction.

[0014] An integrated circuit (IC) device includes a memory controller for receiving a burst write instruction. The burst write instruction includes data and a burst write address. The memory controller segments the data into a plurality of data blocks. One or more bits of a burst write address or one or more bits of a hash of a burst write address are cascaded to each of a plurality of data blocks to obtain a plurality of data and write address bit (DWAB) segments. Single error correction and double error detection (SECDED) error correction codes (ECC) are performed on corresponding DWAB segments in a plurality of DWAB segments to generate corresponding multiple groups of parity bits (DWAB-PB). A corresponding group of parity bits is cascaded to a corresponding data block to generate a corresponding forward error correction (FEC) block. None of the FEC blocks includes one or more bits of a burst write address or one or more bits of a hash of a burst write address. During a corresponding one of a plurality of beats, a burst write command and a corresponding portion of a corresponding FEC block in an FEC block are sent to a separate memory device in a plurality of memory devices until all beats of the burst write have been sent.

[0015] The method and apparatus of the present invention allow the reading of a memory device to be protected from address errors and poison bit indication errors by effectively identifying address errors when they occur, and allow poison bit indication errors to be poison bit marked in a manner that does not reduce the number of bits available for storing ECC parity bits. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Some exemplary aspects, features and elements related to exemplary implementations of the present disclosure are described herein with reference to the following description and accompanying drawings. Therefore, various ways in which the principles disclosed herein are actually achievable are described, and all aspects and equivalents thereof are intended to fall within the scope of the claimed subject matter. In conjunction with each enumerated diagram (figure) in the accompanying drawings, the foregoing and other features and uses of the present disclosure become more apparent in view of the following description. Throughout the specification of the present disclosure, similar reference numerals (as shown in each figure of the accompanying drawings) generally represent the same parts, features and / or elements.

[0017] Figure 1 A memory system is depicted.

[0018] Figure 2 A flow chart of a method for memory protection is depicted.

[0019] Figure 3 The functions of some structures of the memory system are shown.

[0020] Figure 4A An example of a DWAB segment is depicted.

[0021] Figure 4B An example of a DWAB segment including a poison indication bit is depicted.

[0022] Figure 5A Shown in Figure 4A Example of performing ECC on the DWAB segment of FIG.

[0023] Figure 5B Shown in Figure 4B Example of performing ECC on the DWAB segment of FIG.

[0024] Figure 6 An exemplary implementation of SECDED ECC on a DWAB segment is shown.

[0025] Figure 7 An exemplary implementation of SECDED ECC on a DWAB segment including a poison indicator bit is shown.

[0026] Figure 8 An example of generating an FEC block and storing the FEC block is shown.

[0027] Fig. 9 An example of storing FEC blocks on a memory device is shown.

[0028] Fig. 10A An example is shown where FEC blocks are stored on memory devices in bursts having sixteen beats such that all parity bits are stored on two separate memory devices.

[0029] Fig. 10B An example is shown where FEC blocks are stored on memory devices in bursts having sixteen beats such that all parity bits are stored on a single memory device.

[0030] Fig. 10C An example is shown where FEC blocks are stored on eighteen memory devices in bursts with eight beats.

[0031] Fig. 10D An example is shown where FEC blocks are stored on nine memory devices in bursts with eight beats.

[0032] Fig.11 A flow chart of an exemplary method for memory protection is depicted.

[0033] Fig.12 Shows about Fig.11 The method functions as some structure of the memory system.

[0034] Fig.13A An example of decoding a DRAB segment is shown.

[0035] Fig. 13B An example of decoding a DRAB segment including a poison indicator bit is shown. DETAILED DESCRIPTION

[0036] Figure 1 A system 1 is shown that includes an IC device 3 and a memory device 2. The IC device 3 includes a memory controller 5 and a memory device 2a coupled to the memory controller 5. The memory device of the system 1 may be external to the IC device 3 (e.g., memory device 2) or internal to the IC device 3 (memory device 2a), or both internal to the IC device 3 (memory device 2a) and external to the IC device 3 (memory device 2). The memory controller 5 includes a write controller 10, an encoder 11, a read controller 12, a decoder 13, a clock 14, a controller 15, a memory bus 16, and an interface 18. The interface 18 allows the IC device 3 to be communicatively coupled to one or more external devices (or other entities) external to the IC device 3. In this example, the interface 18 includes an input and output (I / O) link 19 that allows communication with an external device (such as, for example, a host computing system).

[0037] The memory bus 16 communicatively couples one or more of the write controller 10, the encoder 11, the read controller 12, the decoder 13, the clock 14, the controller 15, the interface 18, and the memory device 2-2a and thus allows data transfer between any one of these components and all of these components. The controller 15 controls one or more of the write controller 10, the encoder 11, the read controller 12, the decoder 13, the clock 14, the memory bus 16, the interface 18, and the memory device 2-2a.

[0038] The clock 14 generates a clock signal (CLK) 6, with which the memory operation of the device is synchronized. In an exemplary implementation, the memory device 2, the memory device 2a, or both the memory device 2 and the memory device 2a are capable of operating as a DDR SDRAM, and the clock 14 clocks the IC device 3 at its rising edge "Clk+" and again at its falling edge "Clk-". Two (2) consecutive words can thus be transferred on each CLK 6; the first of these words on its rising edge Clk+, and the second of these words on its falling edge Clk-. Exemplary implementations of the memory device 2-2a include (but are not limited to) DDR4 SDRAM and / or DDR5 SDRAM. In an alternative implementation, the CLK 6 is provided from an external clock source.

[0039] The decoder 13 includes a decode engine 56 and a decode logic 55 coupled together. In one example, the decode engine 56 performs a decode operation (e.g., a SECDED decode operation) on an input received from the decode logic 55. In this example, one or more of the memory controller 5, the write controller 10, the encoder 11, the read controller 12, the decoder 13, the clock 14, the controller 15, the memory bus 16, and the interface 18 include software, hardware (e.g., may include a processor), firmware, or a combination of software and hardware for performing tasks such as some or all of the steps of the methods 100, 200 shown below.

[0040] Figure 2 A flow chart of a method 100 for memory protection is shown. In one example, Figure 1 The memory controller 5 performs all steps of method 100. In the following discussion of methods 100 and 200, the memory device 2-2a being written to or read from may be internal, external, or both internal and external to the IC device performing some or all of the steps of the particular method 100 or method 200, as further described below. Figure 1 A system 1 is shown in which memory devices are shown both internally (memory device 2a) and externally (memory device 2) in order to illustrate various ways in which memory devices may be implemented in system 1. Although system 1 may include both internal memory device 2a and external memory device 2, alternatively, system 1 includes only memory device 2 external to IC device 3 (i.e., system 1 does not include memory device 2a) and performs reading and writing of methods 100 and 200 only on memory device 2. In another example, system 1 includes only internal memory device 2a (i.e., system 1 does not include memory device 2) and performs reading and writing of methods 100 and 200 only on memory device 2a.

[0041] A burst write instruction (101) is received. The burst write instruction includes data and a burst write address. Figure 1 In the embodiment of the present invention, a burst write instruction is received via I / O link 19 of interface 18 (eg, from a host computer) and coupled to write controller 10 via memory bus 16. Figure 3 An example of a burst write instruction 31 is shown that includes data 32 and a burst write address 33. In this example, the burst write instruction 31 is received at the interface 18, which is coupled to the write controller 10 via the memory bus 16, as indicated by arrow 40.

[0042] In the following discussion, a communication indicating that a burst write or burst read is to be performed may be referred to as an "instruction" or "command". There is no distinction between the meanings of the term "instruction" and the term "command" as used in this application. However, to distinguish between incoming and outgoing instructions / commands, the term "instruction" will be used for an incoming request to an IC to perform a read or write, and the term "command" will be used to refer to a request to a memory device to perform a read or write.

[0043] The data is segmented (102) into a plurality of data blocks. Figure 3 In one example (102), the write controller 10 segments the data 32 into a plurality of data blocks 34. In one example (102), the data 32 is segmented into a number of data blocks 34 equal to the number of beats of the burst write. In one example, the data 32 is segmented into a plurality of 64-bit data blocks 34. Alternatively, the data 32 is segmented into larger or smaller blocks, such as, for example, but not limited to, 128-bit or 256-bit blocks.

[0044] One or more bits of the burst write address or a hash of the burst write address are concatenated (103) to corresponding data blocks in the plurality of data blocks to obtain a plurality of data and write address bit (DWAB) segments 36. Each DWAB segment in the plurality of DWAB segments corresponds to a corresponding one of the plurality of data blocks 34. As used herein, the term "concatenate" is intended to include connecting together structures indicated to be concatenated. The write address bits 35 may be concatenated to the end of the corresponding data block 34, to the beginning of the corresponding data block 34, or to a predetermined position within the corresponding data block 34. Figure 1 In step 103, the memory controller 5 performs the cascade (e.g., one or more of the write controller 10, the controller 15, and the encoder 11 perform the cascade). When a hash of the burst write address is used, the write controller 10, the controller 15, and / or the encoder 11 calculate the hash of the burst write address. Figure 3 In the example shown, the write controller 10 concatenates one or more bits of the burst write address or a hash of the burst write address to each of the data blocks 34 to obtain the DWAB segment 36. The one or more bits of the burst write address or the hash of the burst write address may be referred to hereinafter as "write address bits" and in Figure 3 As illustrated in FIG. 3 , the term “write address bit” as used in this application includes one or more bits of a burst write address or a hash of a burst write address. Figure 3 In the example shown, the write controller 10 outputs the DWAB segment 36 to the encoder 11 as indicated by arrow 40a.

[0045] Figure 4AAn example of a DWAB segment 36 including a data block 34 is shown. In this example, the write address bits 35 have been concatenated to the end of the data block 34. However, it will be appreciated that the DWAB segment 36 may alternatively include the write address bits 35 concatenated to the beginning of the block 34, or alternatively dispersed at predetermined locations within the DWAB segment 36 such that they are dispersed between various bits of the data block 34.

[0046] Optionally, step 103 includes concatenating (104) one or more bits of the burst write address, or a hash of the burst write address and a poison indicator bit, to corresponding data blocks in the plurality of data blocks to obtain a plurality of DWAB segments. The term "poison indicator bit" as used in this application is a bit that identifies a block with a known write address error or other error at the time of the concatenation of step 104, such as an "interrupted" DDR SDRAM burst. The term "poison bit" as used in this application is a poison indicator bit having a value indicating that a particular bit has been marked as part of a burst with an error (e.g., an uncorrectable block). The term "unpoisoned bit" as used in this application is a poison indicator bit having a value indicating that a particular bit has not yet been marked as part of a burst with an error. Thus, each poison indicator bit will be a poison bit (having a poison bit value) or an unpoisoned bit (having an unpoisoned bit value). The term "poison bit indication error" as used in this application is an error that cannot be corrected by simply decoding the block, such as a write address error or other type of error, and refers to any one or more errors that are the reason for marking the poison indicator bits of a particular burst write as poison bits.

[0047] exist Figure 3In the example shown, the write controller 10 couples the DWAB segments 36 to the encoder 11, and the encoder 11 generates the poison indicator bit 30 and concatenates the write address bit 35 and the poison indicator bit 30 to each data block 34 to form the DWAB segment 36 including the poison indicator bit 30. In this example, the encoder 11 generates the poison indicator bit 30. In one example, the DWAB segment coupled from the write controller 10 to the encoder 11 includes a non-poisoned bit as a placeholder, and the encoder 11 changes the value of the received non-poisoned bit to a poisoned bit value when the DWAB segment 36 is to be marked as a poisoned bit, thereby completing the formation of the DWAB segment 36 at the encoder 11. When the burst write does not have an error, the poison indicator bit 30 in each DWAB segment 36 in the burst write is set to a first value (e.g., "0"), which can be referred to as a non-poisoned bit value. The non-poisoned bit value indicates that the burst write does not have errors that cannot be corrected by simply decoding the block (i.e., the burst write does not have uncorrectable errors), that is, the poison indication bit 30 is a non-poisoned bit. When the burst write does have errors, the poison indication bit 30 in each DWAB segment 36 in the burst write is set to a second value different from the first value (e.g., "1"), which can be referred to as a poisoned bit value. The poison bit value indicates that the burst write has errors that cannot be corrected by simply decoding the block (i.e., the burst write has uncorrectable errors), that is, the poison indication bit 30 is a poisoned bit.

[0048] Figure 4B An example is shown in which the poison indicator bit 30 has been concatenated to the end of the data block 34 to form the DWAB segment 36. However, it will be appreciated that the write address bit 35 may alternatively be concatenated to the beginning of the data block 34, or alternatively be dispersed within the DWAB segment 36 such that it is dispersed among various bits of the data block 34. Similarly, the poison indicator bit 30 may be concatenated to the beginning of the data block 34, concatenated to the end of the write address bit 35, or alternatively be dispersed among bits of the data block 34 or the write address bit 35.

[0049] A single error correction double error detection (SECDED) error correction code (ECC) is performed (105) on corresponding DWAB segments of the plurality of DWAB segments to generate a plurality of sets of DWAB parity bits (DWAB-PB). Figure 3 In the example of , encoder 11 receives DWAB segments 36 and performs a SECDED ECC operation on each DWAB segment 36 to generate a corresponding set of parity bits, illustrated as DWAB-PB 37 , for each DWAB segment 36 .

[0050] Figure 5AAn example is shown where the DWAB segment 36 includes a data block 34 and address bits 35, and where the SECDED ECC operation of step 105 forms a DWAB-PB 37. In this example, the data bits 34 and address bits 35 are reflected in the DWAB-PB 37.

[0051] Figure 5B An example is shown where the concatenation of step 104 forms a DWAB segment 36, which includes a data block 34, a poison indicator bit 30, and an address bit 35, and where the SECDED ECC operation of step 105 forms a DWAB-PB 37. In this example, the data bit 34, the poison indicator bit 30, and the address bit 35 are reflected in the DWAB-PB 37.

[0052] In one example, the SECDED ECC operation performed in step 105 is performed on a DWAB segment 36 having write address bits 35 that include the entire burst write address 33. When using a simpler SECDED ECC scheme, the maximum size of the FEC block is in some cases too small to include the entire burst write address 33, which may be, for example, a 40-bit address. In this case, an exemplary implementation includes a portion, such as a subset of the bits of the burst write address 33s or a hashed version of the burst write address 33, rather than the full burst write address 33. In this example, the SECDED ECC performed in step 105 is performed on a DWAB segment 36 having write address bits 35 that include a hash of the burst write address 33 received in step 101, the hash having a number of bits that is less than the number of bits in the entire burst write address 33.

[0053] Figure 6 An example is shown in which the data block 34 includes 64 data bits and the write address bits 35 include 6 address bits (e.g., 6 of the bits in the burst write address 33 or a hash of the burst write address 33), and in which each SECDED ECC operation performed in step 105 forms a DWAB-PB with 8 parity bits.

[0054] Figure 7 An example is shown in which a DWAB segment 36 includes a poison indication bit 30, a data block 34 having 64 data bits, and a write address bit 35 having 5 bits (e.g., 5 bits in a burst write address 33 or a hash of the burst write address 33), and in which each SECDED ECC operation performed in step 105 forms a DWAB-PB 37 having 8 parity bits.

[0055] The parity bit group generated in step 105 , ie, DWAB-PB, is concatenated ( 106 ) to the corresponding data block to generate a corresponding forward error correction (FEC) block 38 . Figure 8 An example of an FEC block 38 formed by the concatenation of steps 106 is shown. The FEC block 38 does not include a burst write address or a hash of the burst write address (106). Figure 5B As shown, when the DWAB-PB 37 is formed by performing SECDED ECC on the DWAB segment 36 including the poison indicator bit 30, the corresponding FEC block 38 does not include the poison indicator bit 30 (106). Figure 3 In , the encoder 11 concatenates the corresponding DWAB-PB 37 to the corresponding data block 34, where the data block 34 is obtained from the DWAB segment 36, to generate the corresponding FEC block 38. Figure 8 , the DWAB-PB 37 has been concatenated to the end of the data block 34. However, it should be understood that, alternatively, the FEC block 38 may include the DWAB-PB 37, which is concatenated to the beginning of the data block 34, or alternatively dispersed within the FEC block 38, such that the parity bits of the DWAB-PB 37 are dispersed between the bits of the data block 34.

[0056] The burst write command and the corresponding portion of the corresponding one of the plurality of FEC blocks 38 are sent (107) to the corresponding one of the plurality of memory devices during the corresponding one of the plurality of beats until all beats of the burst write have been sent. Figures 8 to 9 In the example shown, a burst write command and corresponding portion of a corresponding FEC block 38 are sent to a medium to be written (illustrated as medium 41), which may include memory device 2, memory device 2a, or both memory device 2 and memory device 2a.

[0057] Fig. 9 An example of a burst write stored on medium 41 is shown, the burst write including n FEC blocks 38a to 38n stored on memory device 2 or memory device 2a. In one example, n is 16, such that 16 FEC blocks 38 are stored in a single burst write. In another example, n is 8, such that 8 FEC blocks 38 are stored in a single burst write. It should be noted that none of the FEC blocks 38a to 38n in the burst write includes one or more bits of the burst write address 33, one or more bits of the hash of the burst write address 33, or the poison indicator bit 30.

[0058] In one example, the burst write instruction 31 is a DDR burst write instruction, and the number of data blocks, the number of FEC blocks (n), and the number of multiple beats are equal to eight. In another example, the number of data blocks, the number of FEC blocks (n), and the number of multiple beats are equal to sixteen. Figure 3 In the example of FIG. 4 , the encoder 11 sends the FEC block 38 to the write controller 10, as shown by arrow 40 b. In response to receiving the FEC block 38, the write controller 10 sends a burst write command and a corresponding portion of one of the FEC blocks (as shown by block 39) to a corresponding memory device in the plurality of memory devices 2 or memory devices 2 a, as shown by arrow 40 c, until all of the FEC blocks in the plurality of FEC blocks in the burst write have been sent to the medium 41.

[0059] exist Fig. 10A In the example shown, each beat forms an FEC block. In this example, the DDR burst 22 has 16 beats, numbered "0" to "15". In each beat, four (4) data bits are stored in each of eight (8) chips (e.g., DDR-5 memory devices) numbered "0" to "7", and parity bits are stored in the ninth chip 23 numbered "8" and the tenth chip 24 numbered "9". In one example, 8 parity bits are stored on each beat (e.g., in each beat, 4 parity bits are stored in chip 23 and 4 parity bits are stored in chip 24).

[0060] Fig. 10B An example is shown in which two beats are used to form each FEC block 38 and the parity is stored in a single chip. In this example, the burst 22 stores data and ECC in nine chips (e.g., 9 DDR-5 memory devices), where the data is stored in eight chips and the parity bits are stored in the ninth chip 23. In one example, each DWAB segment includes 8 parity bits (e.g., 4 parity bits stored in each beat).

[0061] exist Fig. 10CIn the example shown, a DDR burst 22 having 8 beats is used to store an entire FEC block 38 on each beat, numbered "0" through "7", for storing data bits and parity bits of a DWAB-PB 37 on eighteen chips. In this example, four (4) data bits are stored in each of sixteen (16) chips (e.g., DDR-4 memory devices), numbered "0" through "15", with parity bits for the DWAB-PB 37 stored in the seventeenth chip (chip 16) 25 and the eighteenth chip (chip 17) 26. In one example, each DWAB segment includes 8 parity bits (e.g., 4 parity bits are stored in chip 25 and 4 parity bits are stored in chip 26 in each beat).

[0062] exist Fig. 10D In the example shown, a DDR burst 22 having 8 beats is used to store an entire FEC block 38 on each beat, numbered "0" to "7", for storing data bits and parity bits of a DWAB-PB 37 on nine chips. In this example, in each beat, eight data bits are stored in each of eight chips (e.g., DDR-4 memory devices), numbered "0" to "7", with parity bits stored in the ninth chip (chip 8) 23. In one example, each DWAB segment includes 8 parity bits (e.g., in each beat, 8 parity bits are stored in chip 23).

[0063] exist FIG. 10A to FIG. 10D In the example shown, the data and parity are consecutive, with the parity bits stored on a particular chip and the data stored on other chips. However, alternatively, the parity bits may be interleaved with the data bits and not stored on a particular chip. Although the above example uses 8 parity bits, it should be understood that, alternatively, more or fewer parity bits may be used.

[0064] When performing a read of one or more FEC blocks in response to a burst read instruction including a burst read address, optionally, using the burst read address and the DWAB-PB in the one or more FEC blocks to identify (108) a read address error. When a read address error is identified, corrective action is taken. Optionally, when the DWAB segment includes a poison bit indication, using the burst read address and the DWAB-PB in the one or more FEC blocks to identify a poison bit indication error, and when a poison bit indication error is identified, corrective action is taken. In one example, using Fig.11 Some or all of the steps of the method 200 shown may be performed Figure 1 Step 108.

[0065] Fig.11A method 200 for memory protection is shown. The method 200 may be performed independently of the method 100. Alternatively, some or all steps of the method 100 and the method 200 are performed. In one example, Figure 1 The memory controller 5 executes all steps of the method 200 .

[0066] In response to receiving a burst read instruction including a burst read address, a burst read is performed (201) by sending a burst read command to a plurality of memory devices and receiving a plurality of read FEC blocks in response. Figure 1 In the example shown, in response to receiving a burst read instruction including a burst read address, the read controller 12 performs a burst read operation by sending a burst read command to the plurality of memory devices 2 or memory devices 2a, and in response, the read controller 12 receives a plurality of read FEC blocks. Fig.12 In the example shown, a burst read instruction 61 including a burst read address 63 is received at the interface 18. The burst read instruction 61 is coupled to the read controller 12 via the interface 18, as indicated by arrow 57. When the burst read instruction is received at the read controller 12, the read controller 12 sends a burst read command 66 to the medium 41 to be read, as indicated by arrow 57a. In response, the read controller 12 receives a plurality of read FEC blocks 67, as indicated by arrow 57b. In one example, the medium 41 is a memory device 2 or a memory device 2a, the burst read instruction 61 is a DDR burst read instruction received at the read controller 12, and the burst read command 66 is a DDR burst read command sent from the read controller 12 to each of the memory devices 2 or 2a.

[0067] The corresponding read FEC block for the burst read from step 201 includes read parity bits reflecting the data bits, one or more bits of the burst write address or a hash of the burst write address (write address bits), and optionally a poison indicator bit. In one example, the read FEC block is an FEC block stored in method 100 such that the address bits 35 and optionally the poison indicator bit 30 are reflected in the read parity bits 37a of each read FEC block. The read FEC block is segmented (202) to obtain multiple data portions and multiple sets of corresponding read parity bits for the corresponding data portions. Fig.12In the process of step 102, as shown by arrow 57c, the read controller 12 sends the read FEC block 67 and the burst read address 63 (or the hash of the burst read address 63) to the decoder 13. The decoder 13 segments the read FEC block to obtain data portions 64 having the same size as the data portions in the segmentation of step 102. Unless there are uncorrected errors in the decoding process, the decoding will produce the same data portions 64 as the corresponding data blocks 34 stored in step 107 and the same corresponding read parity bits 37a as the corresponding DWAB-PB 37 to be stored in step 107. In this example, the read parity bits are given numbers 37a, which are different from the numbers given to the parity bits 37 stored in method 100 to reflect the fact that errors may occur that cause the parity bits obtained from the read to be different from the originally stored parity bits 37. In an exemplary implementation, the number of data portions 64, the number of read FEC blocks 67, and the number of beats in the reading of step 201 are each equal to 8. In another exemplary implementation, the number of data portions 64, the number of read FEC blocks 67, and the number of beats in the reading of step 201 are each equal to 16.

[0068] One or more bits of the burst read address or a hash of the burst read address are concatenated (203) to corresponding data portions of the plurality of data portions to obtain a plurality of data and read address bit (DRAB) segments. Fig.12 , when hashing is required, the decode logic 55 calculates a hash of the burst read address 63. The decode logic 55 concatenates one or more bits of the burst read address 63 or the hash of the burst read address to the corresponding data portion 64 to form a corresponding DRAB segment 68. The one or more bits of the read address or the hash of the read address concatenated in step 203 may be referred to as "read address bits" and are illustrated as read address bits 65. In one example, each burst read generates 16 DRAB segments 68, which are coupled to the decode engine 56 along with the corresponding read parity bits 37a, as shown by arrow 57d. Fig.13A An example is shown in which the concatenation of step 203 produces a DRAB segment 68 including a data portion 64 and read address bits 65 .

[0069] When the DWAB-PB 37 of the FEC block reflects the poison indication bit, optionally, in step 203, one or more bits of the burst read address, or a hash of the burst read address and non-poisoned bits (bits having non-poison bit values) are concatenated to corresponding data portions of the plurality of data portions. Fig.12 In the example shown, the decode logic 55 generates a non-poisoned bit 60 (eg, set to a first value, such as "0") and performs concatenation. Fig. 13BAn example is shown where the concatenation of step 204 produces a DRAB segment 68 that includes a data portion 64, read address bits 65, and non-poisoned bits 60. In one example, the positioning of non-poisoned bits 60 is the same as that selected in step 104 above.

[0070] The concatenation of step 203 corresponds to the concatenation of step 103 or step 104, so that the size of the data portion 64 is the same as the corresponding data block 34 (and, if there is no error, they should include the same data). In addition, the DWAB segment 36 has the same number of bits as the DRAB segment 68, and optionally has a poison bit indication 30, and should be concatenated in the same order as method 100. For example, if the write address bits 35 are concatenated to the end of each data block 34 in step 103, they are concatenated to the end of each data portion 64 in step 203; if the write address bits 35 are concatenated to the beginning of each data block 34 in step 103, they are concatenated to the beginning of each data portion 64 in step 203, but are not limited to this.

[0071] A corresponding DRAB segment of the plurality of DRAB segments is decoded (204) using the corresponding read parity bit 37a and using a SECDED decoding operation to identify a corresponding data block for the corresponding DRAB segment and to identify a bit position of a corrected bit when single error correction (SEC) has occurred. Fig.12 In the example of , the decoding logic 55 sends the DRAB segment 68 and the read parity bit 37a to the decoding engine 56, as indicated by arrow 57d, and the decoding engine 56 performs the decoding of step 204. Each decoding of step 204 generates a DRAB segment 59 including the decoding of the corresponding data block, and generates a decoding status indication 62 indicating error-free decoding, double error detection (DED), or SEC, and an indication of the bit position of the corrected bit. The decoding of step 204 is performed using the DRAB segment 68 having the same number of data bits to generate a decoded DRAB segment 59, which includes the data block 34 having the same number of bits as the corresponding data block 34 stored in step 107, the read address bits 65 having the same number of bits as the corresponding write address bits 35, and optionally the non-poisoned bits 60 having the same number of bits as the poison indicator bits 30. For example, if the encoding operation of step 105 is a SECDED encoding operation on 48 bits, then the decoding of step 205 is a SECDED decoding operation on 48 bits.

[0072] exist Fig.12In the example shown, each decoded DRAB segment 59 (which will include a data block 34) and a corresponding decode status indication 62 are coupled to the decode logic 55, as shown by arrow 57e. The decode status indication may be sent in the form of a message, or may be stored in a common memory area accessible to both the decode engine 56 and the decode logic 55.

[0073] The decoding logic 55 segments the decoded DRAB segment 59 to obtain the data block 34a and the read address bit 65, and concatenates the data block 34a and the read address bit 65 to form a data word 69 coupled to the read controller 12. In this example, the data block is given a number 34a, which is different from the number 34 given to the data block 34 stored in the method 100 to reflect the fact that errors may occur to cause the data block obtained from the segmentation to be different from the original stored data block 34. When the FEC block reflects the poison indicator bit, the decoded DRAB segment 59 includes the non-poisoned bit 60, which is removed by segmentation and concatenation to generate the data word 69 that does not include the non-poisoned bit 60.

[0074] Return to reference Fig.11 , when the decoding of the DRAB segment is SEC (205) and SEC is indicated in the bit position corresponding to the poison indicator bit (210), the decoded DRAB segment is determined to be poisoned (211) and a poison bit symbol is generated at the decoder. In one example, the decoding logic 55 determines when SEC has occurred in the bit position corresponding to the poison indicator bit causing the decoded DRAB segment to be poisoned, and generates the poison bit symbol at the decoder. In one example, in place of some or all of the read address bits, the poison bit symbol is included in the data word 69 output by the decoder 13 to indicate that a particular decoded DRAB segment 68 is poisoned. Figure 7 In the example shown, if the poison indicator bit 30 is marked as a poison bit (set to a value of 1) prior to the encoding operation of step 105, the decoding operation of step 205 will have a single bit error in the bit position corresponding to the poison bit 30 (because the bit is set to 1 in the encoding operation and set to 0 in the decoding operation).

[0075] The number of poisoned DRAB segments (NPDS) in the burst read is compared to an error threshold (ET) (212). In one example, ET is set to four. Fig.12 In the example shown, the decoding logic 55 counts the number of decodes in the burst read that generate a SEC in the bit position corresponding to the poison indicator bit to determine the NPDS. In one example, the decoding logic 55 includes a counter that is reset to zero before the decoding of step 204 and incremented each time the decoding operation of a particular burst read generates a SEC in the bit position corresponding to the poison indicator bit. The decoding logic 55 then performs the comparison of steps 212 to 213.

[0076] When NPDS does not exceed ET in block 213, the data blocks in the DRAB segment are sent (219) to the read controller 12. Fig.12 In the example shown, the decode logic 55 segments the decoded DRAB segment 59 to obtain the data block 34a and the read address bits 65. The decode logic 55 concatenates the data block 34a and the read address bits 65 to form a data word 69 that is sent to the read controller 12. When the NPDS exceeds the ET (213-214), it is determined that the burst read has been marked as poisoned (214).

[0077] When it is determined in step 214 that the burst read has been marked as poisoned, a poison flag indication error is determined to have occurred, and an output is generated indicating that an error has occurred (e.g., an indication that an uncorrectable error has occurred), and the data block from the burst read is not output (215). In one example, the output generated at 215 is an error message sent from the memory controller 5 to the entity that sent the burst read instruction 61 (e.g., an error message indicating an uncorrectable error in the burst read), and the decoded block from the burst read is not sent to the entity that sent the burst read instruction 61 (e.g., the decoded block is discarded by the read controller 12).

[0078] When the decode of the DRAB segment is SEC (205) and indicates a SEC in a bit position corresponding to the read address bit (216), it is determined that a read address error has occurred (217). In one example, the decoding logic 55 determines when a SEC has occurred in a bit position corresponding to the read address bit 65 and generates a read address error symbol at the decoder. In one example, the read address error symbol is included in the data word 69 output by the decoder 13 in place of some or all of the read address bits to indicate to the read controller 12 that a read address error has occurred. When it is determined that a read address error has occurred, the decoding logic 55 also sets a flag among a plurality of flags (e.g., a read address error flag) to indicate that a read address error has occurred. Fig.12 In the example, a flag in flag 70 is set as a read address error flag.

[0079] Referring now to step 218, when it is determined that a read address error has occurred, the method includes generating an output indicating that an address error has occurred, requesting a retransmission of a burst read instruction, or generating an output indicating that an address error has occurred and requesting a retransmission of a burst read instruction. Fig.12In the example of, upon receiving the data word 69 and / or in response to the setting of the read address error flag, the read controller 12 generates an error message coupled through the interface 18 and output to the external party that sent the burst read instruction 61; generates a message requesting to retransmit the burst read instruction coupled through the interface 18 to the external party that sent the burst read instruction 61; or generates an error message output to the external party that sent the burst read instruction 61 and generates a message requesting to retransmit the burst read instruction output to the external party that sent the burst read instruction 61. When it is determined in step 217 that a read address error has occurred, the data blocks 34a in the burst read are optionally not output. In one example, they are discarded and only the message of step 218 is output.

[0080] When the decode of the DRAB segment is SEC in the bit position corresponding to the poison indicator bit or does not indicate SEC in the bit position corresponding to the read address bit, the data block in the DRAB segment is sent (219) to the read controller 12. Fig.12 In the example shown, the decode logic 55 segments the decoded DRAB segment 59 to obtain the data block 34a and the read address bits 65. The decode logic 55 concatenates the data block 34a and the read address bits 65 to form a data word 69 that is sent to the read controller 12.

[0081] When the decoding of the DRAB segment is DED (206), an uncorrectable error has occurred, and an output is generated indicating that an error has occurred (209), and the data block of the burst read is not output. Fig.12 In the example shown, the decode logic 55 determines when the decode status indication indicates DED in response to receiving the decode status indication 62, and in response sets one of four flags, such as Fig.12 In response to the setting of the decode fail flag, the read controller 12 generates an output indicating that an error has occurred and does not output the burst read data block 34a. In one example, the output generated at 209 is an error message sent from the memory controller 5 to the entity that sent the burst read instruction 61 (e.g., an error message indicating an uncorrectable error in the burst read).

[0082] Processing of the corresponding DRAB segments 68 continues (at 220, 204 and 219, 204) until a DED occurs (206) or until all DRAB segments in the burst read have been decoded (207-208). When there is no DED 206, no SEC 205, and all DRAB segments in the burst read have not been decoded 207, the data block is sent (220) to the read controller 12 (e.g., in a data word 69 including the read address bits and the data block).

[0083] When SEC 205 and DED (206) are not present in the decode of the burst read and the burst read has not been marked as poisoned (214), the burst read data block 64 is output (208) from the memory controller 5 to the entity that sent the burst read instruction 61 as a result of the read operation.

[0084] The method and apparatus of the present invention allow the read of a memory device to be protected from address errors by effectively identifying address errors when they occur, and allow poison bit marking of address errors in a manner that does not reduce the number of bits available for storing ECC parity bits. More specifically, erroneous address writes or reads detected (e.g., by a decoder) are identified, and corrective action is taken in order to prevent the erroneous data associated therewith from potentially disrupting the operation of the system.

[0085] Although the above example uses 8 parity bits, it will be appreciated that more or fewer parity bits may alternatively be used.

[0086] For the sake of clarity and brevity, and to avoid unnecessary or unhelpful confusion, obscurity, obstruction, or occlusion of features or elements of the examples of the present disclosure, certain complexities and details that are commonly known to those of ordinary skill in the relevant art have been omitted or discussed in less-than-exhaustive detail. Any such omission or discussion is not necessary for describing the examples of the present disclosure, and / or is not particularly relevant to an understanding of the salient features, functions, and aspects of the examples of the present disclosure described herein.

[0087] The term "or" is used in this document in an inclusive rather than exclusive sense (unless expressly stated to the contrary in a particular case), and the use of the term "and / or" in this document includes any and all combinations of one or more of the associated listed items combined / dissociated therewith. Within this specification, the term "including" (and / or, in some contexts, the term "having" is used in the same meaning as the term "comprising" used in the following claims, any modifications thereto that may exist, and equivalents and alternatives thereof, and / or are therefore intended to be understood as being substantially synonymous therewith.

[0088] The drawings are schematic, diagrammatic, symbolic and / or process-related representations and are therefore not necessarily drawn to scale unless expressly indicated to the contrary herein. Unless otherwise expressly indicated to the contrary with respect to any specific usage, specific terms used herein are intended to be understood in a generic and / or descriptive sense and not for any limiting purpose.

[0089] In the specification and drawings herein, exemplary implementations are described with respect to the claims set forth below. However, the present disclosure is not limited to these examples, and the specification and drawings herein are therefore intended to inspire those skilled in the art of integrated circuit-related technology to understand, appreciate and suggest alternatives and equivalents thereof.

Claims

1. A method for memory protection, the method comprising: receiving a burst write instruction for burst writing, wherein the burst write instruction includes data and a burst write address; Segmenting the data into a plurality of data blocks; concatenating one or more bits of the burst write address or a hash of the burst write address to corresponding data blocks of the plurality of data blocks to obtain a plurality of data and write address bit DWAB segments; Performing a single error correction and double error detection SECDED error correction code operation on corresponding DWAB segments among the plurality of DWAB segments to generate corresponding multiple groups of parity check bits DWAB-PB; concatenating a corresponding DWAB-PB of the plurality of DWAB-PBs to the corresponding data block to generate a corresponding forward error correction (FEC) block, the FEC block not including the burst write address or the hash of the burst write address; as well as A burst write command and a corresponding portion of a corresponding one of a plurality of FEC blocks are sent to a corresponding memory device of a plurality of memory devices during a plurality of beats until all of the plurality of FEC blocks in the burst write have been sent. 2 . The method according to claim 1 , wherein segmenting the data comprises segmenting the data into data blocks whose number is equal to the number of beats of the burst write.

3. The method according to claim 1, Wherein concatenating one or more bits of the burst write address or the hash of the burst write address further comprises concatenating corresponding poison indicator bits to obtain the DWAB segment.

4. The method according to claim 1, comprising: performing a burst read in response to receiving a burst read instruction including a burst read address; as well as The burst read address and the DWAB-PB in the corresponding FEC block are used to determine when a read address error has occurred.

5. The method according to claim 4, comprising: When it is determined that a read address error has occurred, Indicates that an address error has occurred, Request retransmission of the burst read command, or Indicates that an address error has occurred and requests a retransmission of the burst read instruction.

6. The method of claim 4, when performing the burst read and determining when a read address error has occurred, the method comprising: performing the burst read in response to receiving the burst read instruction and receiving a plurality of read FEC blocks in response; segmenting the read FEC block to obtain a plurality of read data portions and a plurality of corresponding read parity bits; concatenating one or more bits of the burst read address or a hash of the burst read address with corresponding ones of the plurality of read data portions to obtain a plurality of data and read address bit DRAB segments; decoding a corresponding DRAB segment of the plurality of DRAB segments using the corresponding read parity bits using a SECDED decoding operation to identify a data block for the corresponding DRAB segment and to identify a bit position of a corrected bit when a single event correction (SEC) has occurred, Wherein when the SEC has occurred and the bit positions of the corrected bits correspond to the one or more bits of the burst read address or a hash of the burst read address, it is determined that a read address error has occurred.

7. A method for memory protection, the method comprising: In response to receiving a burst read instruction including a burst read address, performing a burst read by sending a burst read command to a plurality of memory devices and receiving a plurality of read forward error correction (FEC) blocks in response; segmenting the read FEC block to obtain a plurality of read data portions and a plurality of corresponding sets of read parity bits; concatenating one or more bits of the burst read address or a hash of the burst read address to corresponding ones of the plurality of read data portions to obtain a plurality of data and read address bit DRAB segments; decoding a corresponding DRAB segment of the plurality of DRAB segments using the corresponding read parity bits and using a SECDED decoding operation to identify a read data block for the corresponding DRAB segment and a bit position of a corrected bit when a single event correction (SEC) has occurred; determining that a read address error has occurred when the SEC has occurred and the bit position of the corrected bit corresponds to the one or more bits of the burst read address or the hash of the burst read address, When the read address error has occurred: Indicates that an address error has occurred, Request retransmission of the burst read command, or Indicates that an address error has occurred and requests a retransmission of the burst read instruction.

8. The method of claim 7, wherein the read parity bits reflect a data block and one or more bits of a burst write address or a hash of the burst write address.

9. The method of claim 7, wherein concatenating one or more bits of the burst read address or the hash of the burst read address further comprises concatenating non-poison bits to corresponding data blocks of the plurality of data blocks to obtain the plurality of DRAB segments.

10. An integrated circuit IC device, comprising: A memory controller, the memory controller being configured to: receiving a burst write instruction for burst writing, wherein the burst write instruction includes data and a burst write address, segmenting the data into a plurality of data blocks, concatenating one or more bits of the burst write address or a hash of the burst write address to corresponding data blocks of the plurality of data blocks to obtain a plurality of data and write address bit DWAB segments, performing a single error correction and double error detection SECDED error correction code operation on corresponding DWAB segments of the plurality of DWAB segments to generate corresponding multiple groups of parity check bits DWAB-PB, concatenating a corresponding set of parity bits of the plurality of sets of parity bits to the corresponding data block to generate a corresponding forward error correction (FEC) block, the FEC block not including one or more bits of the burst write address or the hash of the burst write address, A burst write command and a corresponding portion of a corresponding one of the FEC blocks are sent to a separate memory device of a plurality of memory devices during each of a plurality of beats until all of the FEC blocks in the burst write have been sent.

11. The IC device of claim 10, wherein the memory controller comprises a write controller and an encoder coupled to the write controller, The write controller is used to: receiving the burst write instruction, concatenating the one or more bits of the burst write address or the hash of the burst write address to corresponding data blocks of the plurality of data blocks to obtain the plurality of DWAB segments, and The encoder is used to: executing the SECDED error correction code, and The corresponding set of parity bits is concatenated to the corresponding data block to generate the corresponding FEC block.

12. The IC device of claim 10, wherein the plurality of memory devices are internal to the IC device and coupled to the memory controller.

13. The IC device according to claim 10, wherein concatenating one or more bits of the burst write address or the hash of the burst write address further comprises concatenating poison indicator bits to corresponding data blocks of the plurality of data blocks to obtain the plurality of DWAB segments, Wherein none of the FEC blocks includes the poison indicator bit, the one or more bits of the burst write address, or the hash of the burst write address.

14. The IC device of claim 10, wherein segmenting the data comprises segmenting the data into a number of data blocks equal to a number of the plurality of beats. 15 . The IC device of claim 10 , wherein the one or more bits of the burst write address or the hash of the burst write address are concatenated to an end of a corresponding one of the plurality of data blocks. 16 . The IC device of claim 10 , wherein the one or more bits of the burst write address or the hash of the burst write address are concatenated to the beginning of a corresponding one of the plurality of data blocks.

17. The IC device of claim 10, wherein the plurality of memory devices are discrete double data rate (DDR) memory devices and the IC device is a discrete IC device coupled to the DDR memory devices.

18. The IC device of claim 10, wherein the memory controller is configured to: in response to receiving a burst read instruction including a burst read address, performing a burst read operation by sending a burst read command to a corresponding memory device of the plurality of memory devices and receiving a plurality of read FEC blocks in response, segmenting the plurality of read FEC blocks to obtain a plurality of read data portions and a plurality of corresponding read parity bits, concatenating one or more bits of the burst read address or a hash of the burst read address to corresponding data portions of the plurality of read data portions to obtain a plurality of data and read address bit DRAB segments, decoding a corresponding DRAB segment of the plurality of DRAB segments using the corresponding read parity bits and using a single error correction double error detection (SECDED) decoding operation to identify a data block for the corresponding DRAB segment of the plurality of DRAB segments and to identify a bit position of a corrected bit when a single event correction (SEC) has occurred, determining that a read address error has occurred when the SEC has occurred and the bit position of the corrected bit corresponds to the one or more bits of the burst read address or the hash of the burst read address, When the read address error has occurred: Indicates that an address error has occurred, Request retransmission of the burst read command, or Indicates that an address error has occurred and requests a retransmission of the burst read instruction.

19. The IC device of claim 18, wherein the memory controller comprises a read controller and a decoder coupled to the read controller, The read controller is configured to perform the burst read operation to obtain the plurality of read FEC blocks and couple the plurality of FEC blocks to the decoder, and The decoder is used to segment the read FEC block, perform the concatenation, perform the decoding, and determine that the read address error has occurred.

20. The IC device of claim 10, wherein the memory controller is configured to: in response to receiving a burst read instruction including a burst read address, performing a burst read operation by sending a burst read command to a corresponding memory device of the plurality of memory devices and receiving a plurality of read FEC blocks in response, segmenting the plurality of read FEC blocks to obtain a plurality of read data portions and a plurality of corresponding read parity bits, concatenating one or more bits of the burst read address or the hash of the burst read address to corresponding data portions of the plurality of read data portions and to non-poisoned bits to obtain a plurality of data and read address bits DRAB segment, decoding a corresponding DRAB segment of the plurality of DRAB segments using the corresponding read parity bits and using a single error correction double error detection (SECDED) decoding operation to identify a data block for the corresponding DRAB segment of the plurality of DRAB segments and to identify a bit position of a corrected bit when a single event correction (SEC) has occurred, determining that a read address error has occurred when SEC has occurred and the bit position of the corrected bit corresponds to the one or more bits of the burst read address or the hash of the burst read address, When the read address error has occurred: Indicates that an address error has occurred, Request retransmission of the burst read command, or indicating that an address error has occurred and requesting a retransmission of the burst read instruction, determining that the decoded DRAB segment is poisoned when SEC has occurred and the bit position of the corrected bit corresponds to a poison indication bit, comparing the determined number NPDS of poisoned DRAB segments in the burst read with an error threshold ET, determining that the burst read has been marked as poisoned when the determined NPDS exceeds the error threshold, When the burst read has been marked as poisoned, an output is generated that an error has occurred.

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