Display panel and display device

Abstract

A display panel and display device are disclosed. The display panel includes sub-pixel units arranged in an array along a first direction (X) and a second direction (Y), the first direction (X) and the second direction (Y) intersecting. Each sub-pixel unit includes a pixel driving circuit and a light-emitting unit (OLED). The pixel driving circuit is connected to a first electrode of the light-emitting unit (OLED). The pixel driving circuit includes a driving transistor (T3) and a capacitor (C). The first electrode of the capacitor (C) is connected to a first power line (VSS), and the second electrode of the capacitor (C) is connected to the gate of the driving transistor (T3). The display panel further includes a substrate (81), a second conductive layer, a fourth conductive layer, and a common electrode layer (6). The second conductive layer is located on one side of the substrate (81) and includes a plurality of first conductive portions (21). The first conductive part (21) and the pixel driving circuit are correspondingly disposed. The first conductive part (21) is used to form the first electrode of the capacitor (C) in the corresponding pixel driving circuit. The fourth conductive layer is located on the side of the second conductive layer away from the substrate (81). The fourth conductive layer includes multiple first power lines (VSS). The orthographic projection of the first power lines (VSS) on the substrate (81) is distributed at intervals along the first direction (X) and extends along the second direction (Y). The first conductive part (21) is connected to the first power lines (VSS) through vias. The common electrode layer (6) is located on the side of the fourth conductive layer away from the substrate (81). The common electrode layer (6) is used to form the second electrode of the light-emitting unit (OLED). The first power lines (VSS) are connected to the common electrode layer (6) through vias. This display panel can reduce the voltage drop caused by the resistance of the common electrode layer (6) itself.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] In related technologies, the pixel circuits in display panels typically include driving transistors. To ensure that the driving transistors operate in the saturation region, a large voltage difference needs to be applied between the source and drain of the driving transistors. However, due to the high sheet resistance of the common electrode layer in the display panel, a large power supply voltage is required for the display panel to achieve normal operation, resulting in high power consumption.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes sub-pixel units arrayed along a first direction and a second direction, the first direction and the second direction intersecting; each sub-pixel unit includes a pixel driving circuit and a light-emitting unit; the pixel driving circuit is connected to a first electrode of the light-emitting unit; the pixel driving circuit includes a driving transistor and a capacitor; the first electrode of the capacitor is connected to a first power line; and the second electrode of the capacitor is connected to the gate of the driving transistor; the display panel further includes: a substrate, a second conductive layer, a fourth conductive layer, and a common electrode layer; the second conductive layer is located on one side of the substrate, and the second conductive layer includes a plurality of first conductive layers. The first conductive portion and the pixel driving circuit are correspondingly disposed, and the first conductive portion is used to form the first electrode of the capacitor in the pixel driving circuit corresponding to it; the fourth conductive layer is located on the side of the second conductive layer away from the substrate, and the fourth conductive layer includes a plurality of first power lines, the first power lines are distributed at intervals along the first direction and extend along the second direction by their orthogonal projection on the substrate, and the first conductive portion is connected to the first power lines through vias; the common electrode layer is located on the side of the fourth conductive layer away from the substrate, and the common electrode layer is used to form the second electrode of the light-emitting unit, and the first power lines are connected to the common electrode layer through vias.

[0005] In one exemplary embodiment of this disclosure, at least a portion of the first conductive portions distributed in the first direction are sequentially connected to form a first conductive line, and the first conductive line connects to a plurality of the first power lines.

[0006] In one exemplary embodiment of this disclosure, all the first conductive portions distributed in the first direction are sequentially connected to form a first conductive line, and the first conductive line is connected to each of the first power lines.

[0007] In one exemplary embodiment of this disclosure, a plurality of first conductive portions distributed in the first direction form a plurality of first conductive lines spaced apart in the first direction; two first conductive lines that are adjacent in both the first and second directions are staggered in the first direction, and the two staggered first conductive lines are connected together to at least two first power lines.

[0008] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a sixth transistor, the first terminal of which is connected to the second terminal of the driving transistor, and the second terminal is connected to the first electrode of the light-emitting unit. The sixth transistor is a P-type transistor, and the first power line is used to provide a low-level power signal. The display panel further includes an active layer located between the substrate and the second conductive layer. The active layer includes a sixth active portion, which is used to form the channel region of the sixth transistor. The orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projection of the sixth active portion on the substrate.

[0009] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a second transistor, the first terminal of which is connected to the gate of the driving transistor, and the second terminal of which is connected to the second terminal of the driving transistor. The second conductive layer further includes a second conductive portion connected to a stable power supply terminal. The display panel further includes an active layer located between the substrate and the second conductive layer. The active layer includes a second active portion and a third sub-active portion. The second active portion includes a first sub-active portion and a second sub-active portion. The third sub-active portion is connected between the first sub-active portion and the second sub-active portion. The first sub-active portion is used to form a first channel region of the second transistor, and the second sub-active portion is used to form a second channel region of the second transistor. The orthographic projections of the second conductive portion and the third sub-active portion on the substrate at least partially overlap.

[0010] In one exemplary embodiment of this disclosure, the first electrode of the driving transistor is connected to a second power line, and the second conductive portion is connected to the second power line through a via; the second conductive layer includes a plurality of second conductive portions, which are disposed corresponding to the pixel driving circuit, and at least a portion of the second conductive portions distributed in the first direction are sequentially connected to form a second conductive line; the display panel further includes a plurality of second power lines, the orthographic projections of the plurality of second power lines on the substrate are distributed at intervals along the first direction and extend along the second direction, and the second conductive lines connect the plurality of second power lines.

[0011] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a first transistor, the first terminal of which is connected to a first initial signal line, and the second terminal of which is connected to the gate of the driving transistor; the active layer further includes a first active portion and a third active portion, the first active portion being used to form a channel region of the first transistor, and the third active portion being used to form a channel region of the driving transistor. The display panel further includes: a first conductive layer located between the active layer and the second conductive layer; the first conductive layer includes: a first reset signal line, a gate line, and a third conductive portion; the orthographic projection of the first reset signal line on the substrate extends along the first direction and covers the orthographic projection of the first active portion on the substrate; a portion of the structure of the first reset signal line is used to form the gate of the first transistor; the orthographic projection of the gate line on the substrate extends along the first direction and covers the orthographic projection of the second active portion on the substrate; a portion of the structure of the gate line is used to form the gate of the second transistor; the orthographic projection of the third conductive portion on the substrate covers the orthographic projection of the third active portion on the substrate; the third conductive portion is used to form the gate of the driving transistor; wherein the orthographic projection of the first reset signal line on the substrate is located on the side of the orthographic projection of the gate line on the substrate away from the orthographic projection of the third conductive portion on the substrate, and the orthographic projection of the second conductive portion on the substrate is located between the orthographic projection of the first reset signal line on the substrate and the orthographic projection of the gate line on the substrate.

[0012] In one exemplary embodiment of this disclosure, the display panel further includes: a third conductive layer, the third conductive layer being located between the second conductive layer and the fourth conductive layer, the third conductive layer including a first bridging portion, the first bridging portion being connected to the third conductive portion through a via and connected to the first electrode of the second transistor; the second conductive portion including: a first sub-conductive portion, the orthographic projection of the first sub-conductive portion on the substrate extending along the first direction, and located between the orthographic projection of the first bridging portion on the substrate and the orthographic projection of the first reset signal line on the substrate.

[0013] In one exemplary embodiment of this disclosure, the display panel further includes: a data line, the orthographic projection of which extends along the second direction on the substrate. The second conductive portion further includes: a second sub-conductive portion, the second sub-conductive portion being connected to the first sub-conductive portion, the orthographic projection of which extends along the second direction on the substrate and is located between the orthographic projection of the first bridging portion on the substrate and the orthographic projection of the data line on the substrate.

[0014] In an exemplary embodiment of this disclosure, the driving transistor is connected to a second power line. The pixel driving circuit further includes a second transistor and a fourth transistor. The first electrode of the second transistor is connected to the gate of the driving transistor, and the second electrode of the second transistor is connected to the second electrode of the driving transistor. The first electrode of the fourth transistor is connected to a data line, and the second electrode of the fourth transistor is connected to the first electrode of the driving transistor. The display panel further includes: an active layer, a first conductive layer, and a third conductive layer. The active layer is located between the substrate and the second conductive layer. The active layer includes a third active portion, which is used to form the channel region of the driving transistor. The first conductive layer is located between the active layer and the second conductive layer. The first conductive layer includes a third conductive portion. The orthographic projection of the third conductive portion on the substrate covers the orthographic projection of the third active portion on the substrate. The third conductive portion is used to form the gate of the driving transistor. The third conductive layer is located between the second conductive layer and the fourth conductive layer. The third conductive layer includes a first bridging portion. The first bridging portion is connected to the third conductive portion through a via and connected to the first electrode of the second transistor. The second direction is a column direction. In the same column pixel driving circuit, the... The orthographic projection of the second power line on the substrate extends along the second direction, and the orthographic projection of the data line on the substrate extends along the second direction. The orthographic projection of the second power line on the substrate is located between the orthographic projection of the data line on the substrate and the orthographic projection of the first bridging portion on the substrate. The orthographic projection of the first power line on the substrate is located on the side of the orthographic projection of the first bridging portion on the substrate away from the orthographic projection of the second power line on the substrate. In the adjacent column pixel driving circuit, the orthographic projection of the first power line on the substrate in the current column pixel driving circuit is located between the orthographic projection of the data line on the substrate in the adjacent column pixel driving circuit and the orthographic projection of the first bridging portion on the substrate in the current column pixel driving circuit.

[0015] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a second transistor, the first terminal of which is connected to the gate of the driving transistor, and the second terminal of which is connected to the second terminal of the driving transistor. The display panel further includes: an active layer, a first conductive layer, and a third conductive layer. The active layer is located between the substrate and the second conductive layer, and includes a third active portion for forming a channel region of the driving transistor. The first conductive layer is located between the active layer and the second conductive layer, and includes a third conductive portion. The orthographic projection of the third conductive portion on the substrate overlaps the orthographic projection of the third active portion on the substrate, and the third conductive portion is used to form the gate of the driving transistor. The third conductive layer is located between the second conductive layer and the fourth conductive layer, and includes a first bridging portion. The first bridging portion is connected to the third conductive portion through a via and is connected to the first terminal of the second transistor. The fourth conductive layer further includes a fourth conductive portion connected to the first power line, and the orthographic projection of the fourth conductive portion on the substrate at least partially overlaps the orthographic projection of the first bridging portion on the substrate.

[0016] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a first transistor and a seventh transistor. The first electrode of the first transistor is connected to a first initial signal line, and the second electrode is connected to the gate of the driving transistor. The first electrode of the seventh transistor is connected to a second initial signal line, and the second electrode is connected to the first electrode of the light-emitting unit. The display panel further includes an active layer and a first conductive layer. The active layer is located between the substrate and the second conductive layer. The active layer includes a first active portion and a seventh active portion. The first active portion is used to form the channel region of the first transistor, and the seventh active portion is used to form the channel region of the seventh transistor. A first conductive layer is located between the active layer and the second conductive layer. The first conductive layer includes a first reset signal line and a second reset signal line. The orthographic projection of the first reset signal line on the substrate extends along the first direction and covers the orthographic projection of the first active portion on the substrate. A portion of the structure of the first reset signal line is used to form the gate of the first transistor. The orthographic projection of the second reset signal line on the substrate extends along the first direction and covers the orthographic projection of the seventh active portion on the substrate. A portion of the structure of the second reset signal line is used to form the gate of the seventh transistor. The first direction is a row direction. In adjacent row pixel driving circuits, the second reset signal line in the previous row pixel driving circuit is shared as the first reset signal line in the current row pixel driving circuit.

[0017] In one exemplary embodiment of this disclosure, the active layer further includes: a third active portion, the third active portion being used to form the channel region of the driving transistor. The first conductive layer further includes: a third conductive portion, the orthographic projection of the third conductive portion on the substrate covering the orthographic projection of the third active portion on the substrate, the third conductive portion being used to form the gate of the driving transistor. The second conductive layer further includes: a first initial signal line and a second initial signal line, the orthographic projection of the first initial signal line on the substrate extending along a first direction; the orthographic projection of the second initial signal line on the substrate extending along the first direction. In the same row of pixel driving circuits, the orthographic projection of the third conductive part on the substrate is located between the orthographic projections of the first initial signal line and the second initial signal line on the substrate, and the orthographic projection of the first initial signal line on the substrate is located on the side of the first reset signal line on the substrate away from the orthographic projection of the third conductive part on the substrate; in adjacent row of pixel driving circuits, the orthographic projection of the second initial signal line in the previous row of pixel driving circuits on the substrate is located between the orthographic projections of the first initial signal line in the current row of pixel driving circuits on the substrate and the first reset signal line in the current row of pixel driving circuits on the substrate.

[0018] In an exemplary embodiment of this disclosure, the first active portion includes a fourth sub-active portion and a fifth sub-active portion, and the active layer further includes a sixth sub-active portion connected between the fourth sub-active portion and the fifth sub-active portion; the orthographic projection of the second initial signal line in the previous row pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the sixth sub-active portion in the current row pixel driving circuit on the substrate.

[0019] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; the first terminal of the first transistor is connected to a first initial signal line, and the second terminal is connected to the gate of the driving transistor; the first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal is connected to the second terminal of the driving transistor; the first terminal of the fourth transistor is connected to a data line, and the second terminal is connected to the first terminal of the driving transistor; the first terminal of the fifth transistor is connected to a second power supply line, and the second terminal is connected to the first terminal of the driving transistor; the first terminal of the sixth transistor is connected to the second terminal of the driving transistor, and the second terminal is connected to the first electrode of the light-emitting unit; the first terminal of the seventh transistor is connected to a second initial signal line, and the second terminal is connected to the first electrode of the light-emitting unit; the first transistor, the second transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are all P-type transistors.

[0020] In one exemplary embodiment of this disclosure, the display panel further includes: an active layer and a first conductive layer. The active layer is located between the substrate and the second conductive layer, and includes: a third active portion, a fourth active portion, a fifth active portion, a sixth active portion, and a seventh active portion. The third active portion is used to form the channel region of the driving transistor, the fourth active portion is used to form the channel region of the fourth transistor, the fifth active portion is used to form the channel region of the fifth transistor, the sixth active portion is used to form the channel region of the sixth transistor, and the seventh active portion is used to form the channel region of the seventh transistor. The first conductive layer is located between the active layer and the second conductive layer, and includes: a gate line, an enable signal line, a second reset signal line, and a third conductive portion. The orthographic projection of a gate line on the substrate extends along the first direction and covers the orthographic projection of the fourth active portion on the substrate. A portion of the structure of the gate line is used to form the gate of the fourth transistor. The orthographic projection of an enable signal line on the substrate extends along the first direction and covers the orthographic projections of the fifth active portion and the sixth active portion on the substrate. A portion of the structure of the enable signal line is used to form the gate of the fifth transistor, and another portion of the structure of the enable signal line is used to form the gate of the sixth transistor. The orthographic projection of a second reset signal line on the substrate extends along the first direction and covers the orthographic projection of the seventh active portion on the substrate. A portion of the structure of the second reset signal line is used to form the gate of the seventh transistor. The orthographic projection of a third conductive portion on the substrate covers the orthographic projection of the third active portion on the substrate. The third conductive portion is used to form the gate of the driving transistor. In the same row of pixel driving circuits, the orthographic projection of the enable signal line on the substrate is located between the orthographic projection of the third conductive portion on the substrate and the orthographic projection of the second reset signal line on the substrate.

[0021] According to one aspect of this disclosure, a display device is provided, wherein the display panel described above is included.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0024] Figure 1 This is a schematic diagram of the pixel driving circuit in an exemplary embodiment of the display panel disclosed herein;

[0025] Figure 2 for Figure 1 The timing diagram of each node in a driving method of the pixel driving circuit shown is shown.

[0026] Figure 3 This is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein;

[0027] Figure 4 for Figure 3 Structural layout of the second conductive layer;

[0028] Figure 5 for Figure 3 Structural layout of the fourth conductive layer;

[0029] Figure 6 for Figure 3 Structural layout of the common electrode in the middle;

[0030] Figure 7 for Figure 3 Structural layout of the second and fourth conductive layers;

[0031] Figure 8 This is a structural layout diagram of another exemplary embodiment of the display panel disclosed herein;

[0032] Figure 9 for Figure 8 Structural layout of the second conductive layer;

[0033] Figure 10 for Figure 8 Structural layout of the second and fourth conductive layers;

[0034] Figure 11 This is a structural layout diagram of another exemplary embodiment of the display panel disclosed herein;

[0035] Figure 12 for Figure 11 Structural layout of the second conductive layer;

[0036] Figure 13 for Figure 11 Structural layout of the second and fourth conductive layers;

[0037] Figure 14 This is a structural layout diagram of another exemplary embodiment of the display panel disclosed herein;

[0038] Figure 15 for Figure 14 The structural layout of the active layer;

[0039] Figure 16 for Figure 14 Structural layout of the first conductive layer;

[0040] Figure 17 for Figure 14 Structural layout of the second conductive layer;

[0041] Figure 18 for Figure 14 Structural layout of the third conductive layer;

[0042] Figure 19 for Figure 14 Structural layout of the fourth conductive layer;

[0043] Figure 20 for Figure 14 The structural layout of the active layer and the first conductive layer is shown.

[0044] Figure 21 for Figure 14 The structural layout includes an active layer, a first conductive layer, and a second conductive layer.

[0045] Figure 22 for Figure 14 The structural layout includes an active layer, a first conductive layer, a second conductive layer, and a third conductive layer.

[0046] Figure 23 for Figure 14 The diagram shows a partial cross-sectional view of the display panel cut along the dashed line AA.

[0047] Figure 24 This is a structural layout diagram of another exemplary embodiment of the display panel disclosed herein;

[0048] Figure 25 for Figure 24 Structural layout of the middle pixel electrode layer;

[0049] Figure 26 This is a structural layout of the pixel electrode layer in another exemplary embodiment of the display panel disclosed herein. Detailed Implementation

[0050] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0051] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0052] like Figure 1 The diagram shown is a schematic representation of the pixel driving circuit in an exemplary embodiment of the display panel of this disclosure. The pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. In this configuration, the first transistor T1 has its first electrode connected to the first initial signal terminal Vinit1, its second electrode connected to node N, and its gate connected to the first reset signal terminal Re1. The second transistor T2 has its first electrode connected to the gate of the driving transistor T3, and its second electrode connected to the second electrode of the driving transistor T3; its gate is connected to the gate drive signal terminal Gate. The gate of the driving transistor T3 is connected to node N. The fourth transistor T4 has its first electrode connected to the data signal terminal Da, its second electrode connected to the first electrode of the driving transistor T3, and its gate connected to the gate drive signal terminal Gate. The fifth transistor T5 has its first electrode connected to the second power supply terminal VDD, its second electrode connected to the first electrode of the driving transistor T3, and its gate connected to the enable signal terminal EM. The sixth transistor T6 has its first electrode connected to the second electrode of the driving transistor T3, and its gate connected to the enable signal terminal EM. The seventh transistor T7 has its first electrode connected to the second initial signal terminal Vinit2, its second electrode connected to the second electrode of the sixth transistor T6, and its gate connected to the second reset signal terminal Re2. The first electrode of capacitor C is connected to the first power supply terminal VSS, and the second electrode of capacitor C is connected to the gate of the driving transistor T3. The pixel driving circuit can be connected to an OLED light-emitting unit. The pixel driving circuit is used to drive the OLED to emit light. The first electrode of the OLED can be connected to the second electrode of the sixth transistor T6, and the second electrode of the OLED can be connected to the first power supply terminal VSS. Among them, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can all be P-type transistors.

[0053] like Figure 2 As shown, Figure 1The diagram shows the timing of signals at each node in a driving method of a pixel driving circuit. Here, Gate represents the timing of the Gate driving signal terminal, Re1 represents the timing of the first reset signal terminal Re1, Re2 represents the timing of the second reset signal terminal Re2, EM represents the timing of the enable signal terminal EM, and Da represents the timing of the data signal terminal Da. The driving method of this pixel driving circuit may include a reset phase t1, a compensation phase t2, and a light-emitting phase t3. In the reset phase t1: the first reset signal terminal Re1 outputs a low-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs a first initial signal to node N. In the compensation phase t2: the second reset signal terminal Re2 and the Gate driving signal terminal Gate output low-level signals, the fourth transistor T4, the second transistor T2, and the seventh transistor T7 are turned on, and simultaneously, the data signal terminal Da outputs a data signal to write a voltage Vdata+Vth to node N, where Vdata is the voltage of the data signal, Vth is the threshold voltage of the driving transistor T3, and the second initial signal terminal Vinit2 inputs a second initial signal to the second terminal of the sixth transistor T6. During the light-emitting stage t3: the enable signal terminal EM outputs a low-level signal, turning on the sixth transistor T6 and the fifth transistor T5. This drives the light-emitting unit to emit light under the influence of the voltage Vdata + Vth at node N. According to the formula for the output current of the driving transistor, I = (μWCox / 2L)(Vgs - Vth). 2 Where μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; and Vth is the threshold voltage of the driving transistor. In the pixel driving circuit of this disclosure, the output current of the driving transistor I = (μWCox / 2L)(Vdata + Vth - Vdd - Vth) 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0054] This exemplary embodiment also provides a display panel, the display panel being a sub-pixel unit, the sub-pixel unit including a pixel driving circuit and a light-emitting unit, the pixel driving circuit being connected to a first electrode of the light-emitting unit, the pixel driving circuit being as follows: Figure 1 As shown. The display panel may also include a substrate, a second conductive layer, a fourth conductive layer, and a common electrode layer stacked sequentially, such as... Figure 3-7 As shown, Figure 3 This is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein. Figure 4 for Figure 3 Layout of the second conductive layer. Figure 5 for Figure 3 The structural layout of the fourth conductive layer in the middle. Figure 6 for Figure 3 Structural layout of the common electrode in the middle, Figure 7 for Figure 3 The structural layout of the second and fourth conductive layers is shown. In this exemplary embodiment, the display panel includes a plurality of sub-pixel units arrayed along a first direction X and a second direction Y. Correspondingly, the display panel includes a plurality of pixel driving circuits arrayed along the first direction X and the second direction Y. The first direction X and the second direction Y intersect; for example, the first direction X can be a row direction, and the second direction Y can be a column direction.

[0055] like Figure 3 , 4 As shown in Figures 7 and 8, the second conductive layer may include a plurality of first conductive portions 21, the first conductive portions 21 being disposed correspondingly to the pixel driving circuit, and the first conductive portions 21 being used to form the first electrode of the capacitor C in the pixel driving circuit corresponding to them.

[0056] like Figure 3 , 5 As shown in Figure 7, the fourth conductive layer may include multiple first power lines VSS, which can provide... Figure 1 The first power supply terminal VSS is shown. The orthographic projection of the first power supply line VSS on the substrate can be distributed at intervals along the first direction X and extend along the second direction Y. The first conductive portion 21 can be connected to the first power supply line VSS through vias H. Black squares indicate the positions of vias; this exemplary embodiment only marks some of the via positions. In this exemplary embodiment, the orthographic projection of a structure on the substrate extending along a certain direction can be understood as the orthographic projection of the structure on the substrate extending in a straight line or bending along that direction.

[0057] like Figure 3 , 6 As shown, the common electrode layer 6 can be an integral structure, and the first power line VSS can be connected to the common electrode layer 6 through a via in the edge routing area of ​​the display panel.

[0058] In this exemplary embodiment, at least a portion of the structure of the first power line VSS is located in the display area of ​​the display panel. The first power line VSS can reduce the voltage drop caused by the resistance of the common electrode layer 6 itself, thereby enabling... Figure 1 The first power supply terminal VSS and the second power supply terminal VDD reduce the power consumption of the display panel while ensuring that the driving transistor operates in the saturation region. In addition, the display panel connects the first electrode (first conductive part 21) of the capacitor C to the first power supply line VSS, thereby reducing the self-resistance of the first power supply line VSS, and further reducing the voltage drop caused by the self-resistance of the common electrode layer 6.

[0059] In this exemplary embodiment, as Figure 8-10 As shown, Figure 8 This is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure. Figure 9 for Figure 8 Layout of the second conductive layer. Figure 10 for Figure 8 The structural layout of the second and fourth conductive layers.

[0060] In this exemplary embodiment, Figure 8 The display panel shown and Figure 3 The difference in the display panel shown is that all the first conductive portions 21 distributed in the first direction X are sequentially connected to form a first conductive line D1, and the first conductive line D1 connects to each of the first power lines VSS. This arrangement allows the first power lines VSS and the first conductive lines D1 to form a mesh structure, thereby further reducing the voltage drop caused by the resistance of the common electrode layer 6 itself.

[0061] It should be understood that, in other exemplary embodiments, the first conductive portions 21 distributed in the first direction X may also be partially connected sequentially to form a first conductive line, which may connect multiple first power lines. For example, as Figure 11-13 As shown, Figure 11 This is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure. Figure 12 for Figure 11 Layout of the second conductive layer. Figure 13 for Figure 11 The structural layout of the second and fourth conductive layers is shown. In this exemplary embodiment, the plurality of first conductive portions 21 distributed in the first direction X can form a plurality of first conductive lines D1 spaced apart in the first direction X. Two first conductive lines D1 that are adjacent in both the first direction X and the second direction Y can be staggered in the first direction X, that is, the area covered by the orthographic projection of two first conductive lines D1 that are adjacent in both the first direction X and the second direction Y, when moved infinitely in the second direction Y, partially intersects. The first conductive lines D1 can connect two first power lines VSS. This arrangement can also enable the first power lines VSS and the first conductive lines D1 to form a mesh structure.

[0062] It should be understood that in other exemplary embodiments, the pixel driving circuit in the display panel can also have other structures. As long as the first electrode of capacitor C in the pixel driving circuit and the common electrode of the light-emitting unit are connected to the same signal terminal, the display panel can reduce the voltage drop caused by the resistance of the common electrode itself through the above-described scheme. For example, Figure 1In the pixel driving circuit shown, the first transistor T1 and the second transistor T2 can also be N-type transistors. This setting can reduce the leakage current of node N through the first transistor T1 and the second transistor T2.

[0063] In this exemplary embodiment, the display panel may further include: an active layer, a first conductive layer, and a third conductive layer, wherein the substrate, the active layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the common electrode are sequentially stacked, and an insulating layer may be disposed between the above structural layers. Figure 14-22 As shown, Figure 14 This is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure. Figure 15 for Figure 14 The structural layout of the active layer is shown. Figure 16 for Figure 14 The structural layout of the first conductive layer in the middle. Figure 17 for Figure 14 Layout of the second conductive layer. Figure 18 for Figure 14 The structural layout of the third conductive layer in the middle. Figure 19 for Figure 14 The structural layout of the fourth conductive layer in the middle. Figure 20 for Figure 14 The structural layout includes an active layer and a first conductive layer. Figure 21 for Figure 14 The structural layout includes an active layer, a first conductive layer, and a second conductive layer. Figure 22 for Figure 14 The structural layout includes an active layer, a first conductive layer, a second conductive layer, and a third conductive layer.

[0064] like Figure 14 , 15As shown in Figure 20, the active layer may include a first active portion 71, a second active portion 72, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, and a seventh active portion 77. The first active portion 71 forms the channel region of the first transistor T1, the second active portion 72 forms the channel region of the second transistor T2, the third active portion 73 forms the channel region of the driving transistor T3, the fourth active portion 74 forms the channel region of the fourth transistor T4, the fifth active portion 75 forms the channel region of the fifth transistor T5, the sixth active portion 76 forms the channel region of the sixth transistor T6, and the seventh active portion 77 forms the channel region of the seventh transistor T7. The first active portion 71 includes a fourth sub-active portion 714 and a fifth sub-active portion 715, and the second active portion 72 includes a first sub-active portion 721 and a second sub-active portion 722. The active layer may further include a sixth sub-active section 716 connected between the fourth sub-active section 714 and the fifth sub-active section 715, a third sub-active section 723 connected between the first sub-active section 721 and the second sub-active section 722, an eighth active section 78 connected between the second active section 72 and the first active section 71, a ninth active section 79 connected to the side of the fourth active section 74 away from the third active section 73, a tenth active section 710 connected to the side of the first active section 71 away from the second active section 72, an eleventh active section 711 connected between the sixth active section 76 and the seventh active section 77, a twelfth active section 712 connected to the side of the fifth active section 75 away from the third active section 73, and a thirteenth active section 713 connected to the side of the seventh active section 77 away from the sixth active section 76. The first active layer can be formed of polycrystalline silicon material. Correspondingly, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature polycrystalline silicon thin-film transistors.

[0065] like Figure 14 , 16 As shown in Figure 20, the first conductive layer may include: a first reset signal line Re1, a second reset signal line Re2, a gate line Gate, an enable signal line EM, and a third conductive portion 13. The first reset signal line Re1 is used to provide... Figure 1 The first reset signal terminal and the second reset signal line Re2 are used to provide... Figure 1 The second reset signal terminal, the gate line Gate, is used to provide... Figure 1 The gate drive signal terminal in the middle, the enable signal line EM is used to provide Figure 1The enable signal terminal is shown in the diagram. The orthogonal projection of the first reset signal line Re1 onto the substrate extends along the first direction X and covers the orthogonal projection of the first active portion 71 onto the substrate. A portion of the structure of the first reset signal line Re1 is used to form the gate of the first transistor T1. The orthogonal projection of the second reset signal line Re2 onto the substrate extends along the first direction X and covers the orthogonal projection of the seventh active portion 77 onto the substrate. A portion of the structure of the second reset signal line Re2 is used to form the gate of the seventh transistor T7. The orthogonal projection of the enable signal line EM onto the substrate extends along the first direction X and covers the orthogonal projections of the fifth active portion 75 and the sixth active portion 76 onto the substrate. A portion of the structure of the enable signal line EM is used to form the gate of the fifth transistor T5, and the remaining portion of the structure of the enable signal line EM is used to form the gate of the sixth transistor T6. The orthographic projection of the gate line on the substrate extends along the first direction X and covers the orthographic projections of the second active portion 72 and the fourth active portion 74 on the substrate. A portion of the gate line structure is used to form the gate of the second transistor T2, and the remaining portion is used to form the gate of the fourth transistor T4. The orthographic projection of the third conductive portion 13 on the substrate covers the orthographic projection of the third active portion 73 on the substrate. The third conductive portion 13 is used to form the gate of the driving transistor T3. The third conductive portion 13 can also share the second electrode of the capacitor C. The orthographic projection of the third conductive portion 13 on the substrate can be located between the orthographic projection of the gate line on the substrate and the orthographic projection of the enable signal line EM on the substrate. The orthographic projection of the first reset signal line Re1 on the substrate can be located on the side of the gate line on the substrate away from the orthographic projection of the third conductive portion 13 on the substrate. The orthographic projection of the second reset signal line Re2 on the substrate can be located on the side of the enable signal line EM on the substrate away from the orthographic projection of the third conductive portion 13 on the substrate. In adjacent row pixel driving circuits, the second reset signal line Re2 in the previous row pixel driving circuit can be shared as the first reset signal line Re1 in the current row pixel driving circuit. This arrangement can reduce the size of the pixel driving circuit in the second direction. Furthermore, the display panel can utilize the first conductive layer as a mask to conduct the active layer, meaning that the area covered by the first conductive layer in the active layer can form the channel region of a transistor, while the area not covered by the first conductive layer in the active layer forms a conductive structure.

[0066] like Figure 14 , 17 As shown in Figure 21, the second conductive layer may include a first initial signal line Vinit1, a second initial signal line Vinit2, a first conductive portion 21, and a second conductive portion 22. The first initial signal line Vinit1 can be used to provide... Figure 1The first initial signal terminal and the second initial signal line Vinit2 can be used to provide... Figure 1 The second initial signal terminal in the circuit. The orthographic projections of the first initial signal line Vinit1 and the second initial signal line Vinit2 on the substrate can both extend along the first direction X. The orthographic projection of the first conductive portion 21 on the substrate can at least partially overlap with the orthographic projection of the third conductive portion 13 on the substrate. The first conductive portion 21 can be used to form the first electrode of the capacitor C. A plurality of first conductive portions 21 distributed along the first direction X can be sequentially connected to form a first conductive line D1. A plurality of second conductive portions 22 distributed along the first direction X can be sequentially connected to form a second conductive line D2. In the same row of pixel driving circuits, the orthographic projection of the second conductive portion 22 on the substrate can be located between the orthographic projection of the first reset signal line Re1 on the substrate and the orthographic projection of the gate line Gate on the substrate. In the same row of pixel driving circuits, the orthographic projection of the third conductive portion 13 on the substrate can be located between the orthographic projections of the first initial signal line Vinit1 and the second initial signal line Vinit2 on the substrate, and the orthographic projection of the first initial signal line Vinit1 on the substrate is located on the side of the first reset signal line Re1 on the substrate away from the orthographic projection of the third conductive portion 13 on the substrate. In adjacent row of pixel driving circuits, the orthographic projection of the second initial signal line Vinit2 in the previous row of pixel driving circuits on the substrate can be located between the orthographic projections of the first initial signal line Vinit1 and the first reset signal line Re1 in the current row of pixel driving circuits on the substrate. This arrangement can further reduce the size of the pixel driving circuit in the second direction. Figure 14 , 17 As shown in Figure 21, the second conductive portion 22 may include a third sub-conductive portion 223. The orthographic projection of the third sub-conductive portion 223 on the substrate at least partially overlaps with the orthographic projection of the third sub-active portion 723 on the substrate. The second conductive portion 22 can be connected to a stable voltage source, and the third sub-conductive portion 223 can stabilize the voltage of the third sub-active portion 723, thereby improving the problem of leakage to the source-drain of the second transistor T2 caused by voltage changes in the third sub-active portion 723. The orthographic projection of the second initial signal line Vinit2 in the previous row pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the sixth sub-active portion 716 in the current row pixel driving circuit. The second initial signal line Vinit2 can stabilize the voltage of the sixth sub-active portion 716, thereby improving the problem of leakage to the source-drain of the first transistor T1 caused by voltage changes in the sixth sub-active portion 716.

[0067] like Figure 14 , 18 As shown in Figure 22, the third conductive layer may include a second power line VDD, a first bridging portion 31, a second bridging portion 32, a third bridging portion 33, a fourth bridging portion 34, a fifth bridging portion 35, and a sixth bridging portion 36. The second power line VDD can be used to provide... Figure 1 The second power supply terminal in the pixel driving circuit shown. The orthogonal projection of the second power supply line VDD on the substrate can extend along the second direction. The second power supply line VDD can be connected to the second conductive part 22 through a via to provide a stable voltage source to the second conductive part 22. It should be understood that in other exemplary embodiments, a stable voltage source can also be provided to the second conductive part 22 through other signal lines, for example, a stable voltage source can be provided to the second conductive part 22 through the first power supply line VSS, the first initial signal line Vinit1, and the second initial signal line Vinit2. The second power supply line VDD and the second conductive line D2 can also form a mesh structure, thereby reducing the voltage drop caused by the resistance drop of the second power supply line VDD itself. The second power supply line VDD can also be connected to the twelfth active part 712 through a via to connect the first terminal and the second power supply terminal of the fifth transistor T5. The first bridging part 31 can be connected to the third conductive part 13 and the eighth active part 78 through vias H respectively to connect the gate of the driving transistor T3 and the second terminal of the first transistor T1 and the first terminal of the second transistor T2. Figure 17 As shown, an opening 211 can be provided on the first conductive part 21. The orthographic projection of the via connecting the first bridging part 31 and the third conductive part 13 on the substrate can be located within the orthographic projection of the opening 211 on the substrate, so as to avoid the conductive structure in the via connecting to the first conductive part 21. The second bridging part 32 can be connected to the first conductive part 21 through the via to connect the first electrode of the capacitor. The third bridging part 33 can be connected to the thirteenth active part 713 and the second initial signal line Vinit2 through the via to connect the first electrode and the second initial signal terminal of the seventh transistor. The fourth bridging part 34 can be connected to the tenth active part 710 and the first initial signal line Vinit1 through the via to connect the first electrode and the first initial signal terminal of the first transistor T1. The fifth bridging part 35 can be connected to the eleventh active part 711 through the via to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The sixth bridging part 36 can be connected to the ninth active part 79 through the via to connect the first electrode of the fourth transistor T4. Figure 14 , 17As shown in Figures 18 and 22, the second conductive portion 22 may further include a first sub-conductive portion 221. The first sub-conductive portion 221 is connected to the third sub-conductive portion 223. The orthographic projection of the first sub-conductive portion 221 on the substrate can extend along the first direction X and is located between the orthographic projection of the first bridging portion 31 on the substrate and the orthographic projection of the first reset signal line Re1 on the substrate. That is, the area covered by the orthographic projection of the first sub-conductive portion 221 on the substrate moving infinitely in the second direction Y and the area covered by the orthographic projection of the first bridging portion 31 on the substrate moving infinitely in the second direction Y intersect at least partially. The first sub-conductive portion 221 can shield the noise influence of the first reset signal line Re1 on the first bridging portion 31, thereby improving... Figure 1 The stability of the voltage at node N in the pixel driving circuit shown. In this exemplary embodiment, the area covered by the orthographic projection of the first sub-conductive portion 221 on the substrate moving infinitely in the second direction Y can cover the area covered by the orthographic projection of the first bridging portion 31 on the substrate moving infinitely in the second direction Y.

[0068] like Figure 14 , 19 As shown, the fourth conductive layer may include: a first power line VSS, a data line Da, and a seventh bridging portion 47. The first power line VSS is used to provide... Figure 1 The first power supply terminal in the pixel driving circuit shown is used to provide data line Da. Figure 1 The data signal terminal in the pixel driving circuit shown. The orthographic projection of the first power line VSS onto the substrate and the orthographic projection of the data line Da onto the substrate can both extend along the second direction Y. Each column of pixel driving circuits can correspondingly provide one first power line VSS and one data line Da. It should be understood that in other exemplary embodiments, multiple column pixel driving circuits can also correspondingly provide one first power line VSS. The first power line VSS can be connected to the second bridge portion 32 via a via to connect the first power terminal and the first electrode of the capacitor C. The data line Da can be connected to the sixth bridge portion 36 via a via to connect the first electrode of the fourth transistor T4 and the data signal terminal. Figure 14 , 19 As shown, the fourth conductive layer may further include a fourth conductive portion 44, which is connected to the first power line VSS. The orthographic projection of the fourth conductive portion 44 on the substrate may at least partially overlap with the orthographic projection of the first bridging portion 31 on the substrate. The fourth conductive portion 44 may shield the first bridging portion 31 from noise interference from other signal lines. In this exemplary embodiment, the orthographic projection of the fourth conductive portion 44 on the substrate may cover the orthographic projection of the first bridging portion 31 on the substrate. Figure 14As shown, the orthographic projection of the second power line VDD on the substrate can be located between the orthographic projection of the data line Da on the substrate and the orthographic projection of the first bridging portion 31 on the substrate. The orthographic projection of the first power line VSS on the substrate can be located on the side of the first bridging portion 31 on the substrate away from the orthographic projection of the second power line VDD on the substrate. The orthographic projection of the first power line VSS in this column of pixel driving circuit is located between the orthographic projection of the data line Da in the adjacent column of pixel driving circuit and the orthographic projection of the first bridging portion 31 in this column of pixel driving circuit. The second power line VDD can shield the noise influence of the data line Da in this column of pixel driving circuit on the first bridging portion 31 in this column of pixel driving circuit. The first power line VSS can shield the noise influence of the data line Da in the adjacent column of pixel driving circuit on the first bridging portion 31 in this column of pixel driving circuit. The orthographic projection of the first power line VSS on the substrate can also at least partially overlap with the orthographic projection of the sixth active portion 76 on the substrate. In this exemplary embodiment, the first power line VSS can provide a low-level power signal, which can improve the response speed of the sixth transistor T6. The first power line VSS can also be connected to the common electrode layer via a via.

[0069] like Figure 14 , 17 As shown in Figures 18 and 22, the second conductive part 22 may also be a second sub-conductive part 222. The second sub-conductive part 222 is connected to the side of the first sub-conductive part 221 away from the third sub-conductive part 223. The orthographic projection of the second sub-conductive part 222 on the substrate can extend along the second direction Y and is located between the orthographic projection of the first bridging part 31 on the substrate and the orthographic projection of the data line Da on the substrate. That is, the area covered by the orthographic projection of the second sub-conductive part 222 on the substrate that moves infinitely in the first direction X and the area covered by the orthographic projection of the first bridging part 31 on the substrate that moves infinitely in the first direction X intersect at least partially. The second sub-conductive part 222 can shield the noise influence of the data line Da on the first bridging part 31.

[0070] It should be noted that, as Figure 14 , 22 As shown, the black squares drawn on the side of the third conductive layer facing away from the substrate represent vias connecting the third conductive layer to other layers facing the substrate; the black squares drawn on the side of the fourth conductive layer facing away from the substrate represent vias connecting the fourth conductive layer to other layers facing the substrate. These black squares only indicate the location of the vias; different vias represented by black squares at different locations can penetrate different insulating layers.

[0071] like Figure 23 As shown, Figure 14The diagram shows a partial cross-sectional view of the display panel taken along the dashed line AA. The display panel may further include a buffer layer 82, a first insulating layer 83, a second insulating layer 84, a first dielectric layer 85, a passivation layer 86, and a second dielectric layer 87, wherein the substrate 81, buffer layer 82, active layer, first insulating layer 83, first conductive layer, second insulating layer 84, second conductive layer, first dielectric layer 85, third conductive layer, passivation layer 86, second dielectric layer 87, and fourth conductive layer are sequentially stacked. The first insulating layer 83 and second insulating layer 84 may be silicon oxide layers, the first dielectric layer 85 and second dielectric layer 87 may be silicon nitride layers, and the passivation layer 86 and buffer layer 82 may be made of silicon oxide, silicon nitride, etc. The substrate 81 may include a glass substrate, a barrier layer, and a polyimide layer sequentially stacked, and the barrier layer may be an inorganic material. The materials of the first conductive layer and the second conductive layer may be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy, or a stack thereof. The materials of the third and fourth conductive layers can include metallic materials, such as molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacks, or titanium / aluminum / titanium stacks.

[0072] The display panel may also include a pixel electrode layer located between the fourth conductive layer and the common electrode layer. For example... Figure 24 , 25 As shown, Figure 24 This is a structural layout diagram of another exemplary embodiment of the display panel disclosed herein. Figure 25 for Figure 24The structural layout of the pixel electrode layer. The pixel electrode layer may include multiple electrode portions, which can be used to form the first electrode of the light-emitting unit. The multiple electrode portions include: multiple R electrode portions R, multiple G electrode portions G, and multiple B electrode portions B. Among the multiple electrode portions connected to the same row of pixel driving circuits, the R electrode portions, G electrode portions, B electrode portions, and B electrode portions are alternately distributed in the row direction. In two adjacent columns of pixel driving circuits, the multiple R electrode portions and the multiple B electrode portions are connected to the same column of pixel driving circuits, and the R electrode portions and B electrode portions connected to the same column of pixel driving circuits are alternately distributed in the column direction. The multiple G electrode portions are connected to another column of pixel driving circuits. The minimum distance S1 of the orthogonal projection of two G electrode portions connected to adjacent pixel driving circuit rows and connected to the same pixel driving circuit column on the substrate in the column direction is less than the dimension S2 of the orthogonal projection of the R electrode portion on the substrate in the column direction or the dimension S3 of the orthogonal projection of the B electrode portion on the substrate in the column direction. The display panel may further include a pixel definition layer located on the side of the electrode layer facing away from the substrate. The orthographic projection of the R electrode on the substrate coincides with the orthographic projection of its corresponding opening on the substrate in the pixel definition layer. The orthographic projection of the G electrode on the substrate coincides with the orthographic projection of its corresponding opening on the substrate in the pixel definition layer. The orthographic projection of the B electrode on the substrate coincides with the orthographic projection of its corresponding opening on the substrate in the pixel definition layer. Each electrode can be connected to the seventh bridge portion 47 via a via to connect to the second electrode of the sixth transistor T6.

[0073] like Figure 24 , 25 As described above, the R electrode portion R and the B electrode portion B are hexagonal, and the G electrode portion G is pentagonal. It should be understood that in other exemplary embodiments, the corners of the R electrode portion R, the B electrode portion B, and the G electrode portion G can also be arc-shaped. This setting can improve the technical problem of color deviation in the display panel.

[0074] Furthermore, in other exemplary embodiments, the electrode portion may also have other structures and distribution methods, such as... Figure 26The diagram shows a structural layout of a pixel electrode layer in another exemplary embodiment of the display panel of this disclosure. The pixel electrode layer may include multiple electrode portions: R electrode portion R, G electrode portion G, and B electrode portion B. Each electrode portion can be connected to a seventh bridge portion 47 via a via to connect to the second electrode of a sixth transistor. Among the multiple electrode portions connected to the same row of pixel driving circuits, the R electrode portion, G electrode portion, B electrode portion, and G electrode portion are alternately distributed in the row direction. In two adjacent columns of pixel driving circuits, multiple R electrode portions and multiple B electrode portions are connected to the same column of pixel driving circuits, and the R electrode portions and B electrode portions connected to the same column of pixel driving circuits are alternately distributed in the column direction. Multiple G electrode portions are connected to another column of pixel driving circuits. The minimum distance S1 of the orthogonal projection of two G electrode portions connected to adjacent pixel driving circuit rows and the same pixel driving circuit column on the substrate in the column direction is greater than the dimension S2 of the orthogonal projection of the R electrode portion on the substrate in the column direction or the dimension S3 of the orthogonal projection of the B electrode portion on the substrate in the column direction. In this configuration, the orthographic projection of the R electrode on the substrate coincides with the orthographic projection of its corresponding opening on the pixel definition layer; the orthographic projection of the G electrode on the substrate coincides with the orthographic projection of its corresponding opening on the pixel definition layer; and the orthographic projection of the B electrode on the substrate coincides with the orthographic projection of its corresponding opening on the pixel definition layer.

[0075] It should be noted that the scale of the accompanying drawings in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channels, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The accompanying drawings described in this disclosure are merely schematic diagrams of the structure. Furthermore, the qualifiers such as "first" and "second" are only used to define different structural names and do not imply a specific order.

[0076] This exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, tablet computer, television, or other display device.

[0077] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0078] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A display panel, wherein, The display panel includes sub-pixel units arrayed along a first direction and a second direction, the first direction and the second direction intersecting. Each sub-pixel unit includes a pixel driving circuit and a light-emitting unit. The pixel driving circuit is connected to a first electrode of the light-emitting unit. The pixel driving circuit includes a driving transistor and a capacitor. The first electrode of the capacitor is connected to a first power line, and the second electrode of the capacitor is connected to the gate of the driving transistor. The display panel further includes: Substrate; The second conductive layer is located on one side of the substrate. The second conductive layer includes a plurality of first conductive portions. The first conductive portions are correspondingly disposed with the pixel driving circuit. The first conductive portions are used to form the first electrode of the capacitor in the pixel driving circuit corresponding to them. A fourth conductive layer is located on the side of the second conductive layer away from the substrate. The fourth conductive layer includes a plurality of first power lines. The orthographic projection of the first power lines on the substrate is distributed at intervals along the first direction and extends along the second direction. The first conductive portion is connected to the first power lines through vias. A common electrode layer is located on the side of the fourth conductive layer opposite to the substrate. The common electrode layer is used to form the second electrode of the light-emitting unit. The first power line is connected to the common electrode layer through a via. At least a portion of the first conductive portions distributed in the first direction are sequentially connected to form a first conductive line, and the first conductive line connects to a plurality of the first power lines.

2. The display panel according to claim 1, wherein, All the first conductive parts distributed in the first direction are connected in sequence to form a first conductive line, and the first conductive line is connected to each of the first power lines.

3. The display panel according to claim 1, wherein, A plurality of first conductive portions distributed in the first direction are formed into a plurality of first conductive lines spaced apart in the first direction; Two first conductive lines that are adjacent in both the first and second directions are staggered in the first direction, and the two staggered first conductive lines are connected to at least two first power lines.

4. The display panel according to claim 1, wherein, The pixel driving circuit further includes a sixth transistor, the first terminal of which is connected to the second terminal of the driving transistor, and the second terminal is connected to the first electrode of the light-emitting unit. The sixth transistor is a P-type transistor, and the first power line is used to provide a low-level power signal. The display panel also includes: An active layer is located between the substrate and the second conductive layer. The active layer includes a sixth active portion, which is used to form the channel region of the sixth transistor. The orthographic projection of the first power line on the substrate overlaps at least partially with the orthographic projection of the sixth active part on the substrate.

5. The display panel according to claim 1, wherein, The pixel driving circuit further includes a second transistor, wherein the first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal is connected to the second terminal of the driving transistor; The second conductive layer further includes: The second conductive part is connected to a stable power supply terminal; The display panel also includes: An active layer is located between the substrate and the second conductive layer. The active layer includes a second active portion and a third sub-active portion. The second active portion includes a first sub-active portion and a second sub-active portion. The third sub-active portion is connected between the first sub-active portion and the second sub-active portion. The first sub-active portion is used to form a first channel region of the second transistor, and the second sub-active portion is used to form a second channel region of the second transistor. Wherein, the orthographic projection of the second conductive part on the substrate and the orthographic projection of the third active part on the substrate at least partially overlap.

6. The display panel according to claim 5, wherein, The first terminal of the driving transistor is connected to the second power line, and the second conductive part is connected to the second power line through a via. The second conductive layer includes a plurality of second conductive portions, which are disposed corresponding to the pixel driving circuit. At least a portion of the second conductive portions distributed in the first direction are sequentially connected to form a second conductive line. The display panel further includes multiple second power lines, the projections of which on the substrate are distributed at intervals along the first direction and extend along the second direction, and the second conductive lines connect the multiple second power lines.

7. The display panel according to claim 5, wherein, The pixel driving circuit further includes a first transistor, wherein the first terminal of the first transistor is connected to a first initial signal line and the second terminal is connected to the gate of the driving transistor; The active layer further includes a first active portion and a third active portion, wherein the first active portion is used to form the channel region of the first transistor, and the third active portion is used to form the channel region of the driving transistor. The display panel also includes: A first conductive layer is located between the active layer and the second conductive layer, and the first conductive layer includes: A first reset signal line extends along the first direction and covers the orthogonal projection of the first active portion on the substrate, and a portion of the structure of the first reset signal line is used to form the gate of the first transistor. A gate line, whose orthogonal projection on the substrate extends along the first direction and covers the orthogonal projection of the second active portion on the substrate, wherein a portion of the structure of the gate line is used to form the gate of the second transistor; The third conductive portion, the orthogonal projection of the third conductive portion on the substrate covers the orthogonal projection of the third active portion on the substrate, the third conductive portion being used to form the gate of the driving transistor; Wherein, the orthogonal projection of the first reset signal line on the substrate is located on the side of the orthogonal projection of the gate line on the substrate away from the orthogonal projection of the third conductive part on the substrate, and the orthogonal projection of the second conductive part on the substrate is located between the orthogonal projection of the first reset signal line on the substrate and the orthogonal projection of the gate line on the substrate.

8. The display panel according to claim 7, wherein, The display panel also includes: A third conductive layer is located between the second conductive layer and the fourth conductive layer. The third conductive layer includes a first bridging portion, which is connected to the third conductive portion and the first electrode of the second transistor through a via. The second conductive part includes: The first sub-conductive portion extends along the first direction in the orthographic projection of the first sub-conductive portion on the substrate and is located between the orthographic projection of the first bridging portion on the substrate and the orthographic projection of the first reset signal line on the substrate.

9. The display panel according to claim 8, wherein, The display panel also includes: The data line extends along the second direction in its orthogonal projection onto the substrate. The second conductive part further includes: The second sub-conductive portion is connected to the first sub-conductive portion. The orthographic projection of the second sub-conductive portion on the substrate extends along the second direction and is located between the orthographic projection of the first bridging portion on the substrate and the orthographic projection of the data line on the substrate.

10. The display panel according to claim 1, wherein, The driving transistor is connected to the second power line. The pixel driving circuit also includes a second transistor and a fourth transistor. The first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal of the second transistor is connected to the second terminal of the driving transistor. The first terminal of the fourth transistor is connected to the data line, and the second terminal of the fourth transistor is connected to the first terminal of the driving transistor. The display panel also includes: An active layer is located between the substrate and the second conductive layer. The active layer includes a third active portion, which is used to form the channel region of the driving transistor. A first conductive layer is located between the active layer and the second conductive layer. The first conductive layer includes a third conductive portion. The orthographic projection of the third conductive portion on the substrate covers the orthographic projection of the third active portion on the substrate. The third conductive portion is used to form the gate of the driving transistor. A third conductive layer is located between the second conductive layer and the fourth conductive layer. The third conductive layer includes a first bridging portion, which is connected to the third conductive portion and the first electrode of the second transistor through a via. The second direction is the column direction. In the same column pixel driving circuit, the orthographic projection of the second power line on the substrate extends along the second direction, the orthographic projection of the data line on the substrate extends along the second direction, and the orthographic projection of the second power line on the substrate is located between the orthographic projection of the data line on the substrate and the orthographic projection of the first bridging portion on the substrate. The orthographic projection of the first power line on the substrate is located on the side of the orthographic projection of the first bridging portion on the substrate that is away from the orthographic projection of the second power line on the substrate. In the adjacent column pixel driving circuit, the orthographic projection of the first power line in the current column pixel driving circuit onto the substrate is located between the orthographic projection of the data line in the adjacent column pixel driving circuit onto the substrate and the orthographic projection of the first bridging portion in the current column pixel driving circuit onto the substrate.

11. The display panel according to claim 1, wherein, The pixel driving circuit further includes a second transistor, wherein the first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal is connected to the second terminal of the driving transistor; The display panel also includes: An active layer is located between the substrate and the second conductive layer. The active layer includes a third active portion, which is used to form the channel region of the driving transistor. A first conductive layer is located between the active layer and the second conductive layer. The first conductive layer includes a third conductive portion. The orthographic projection of the third conductive portion on the substrate covers the orthographic projection of the third active portion on the substrate. The third conductive portion is used to form the gate of the driving transistor. A third conductive layer is located between the second conductive layer and the fourth conductive layer. The third conductive layer includes a first bridging portion, which is connected to the third conductive portion and the first electrode of the second transistor through a via. The fourth conductive layer further includes: A fourth conductive portion is connected to the first power line, and the orthographic projection of the fourth conductive portion on the substrate at least partially overlaps with the orthographic projection of the first bridging portion on the substrate.

12. The display panel according to claim 1, wherein, The pixel driving circuit further includes a first transistor and a seventh transistor. The first terminal of the first transistor is connected to a first initial signal line, and the second terminal is connected to the gate of the driving transistor. The first terminal of the seventh transistor is connected to a second initial signal line, and the second terminal is connected to the first terminal of the light-emitting unit. The display panel also includes: An active layer is located between the substrate and the second conductive layer. The active layer includes a first active portion and a seventh active portion. The first active portion is used to form the channel region of the first transistor, and the seventh active portion is used to form the channel region of the seventh transistor. A first conductive layer is located between the active layer and the second conductive layer, and the first conductive layer includes: A first reset signal line extends along the first direction in the orthogonal projection on the substrate and covers the orthogonal projection of the first active portion on the substrate. A portion of the structure of the first reset signal line is used to form the gate of the first transistor. The second reset signal line extends along the first direction in the orthogonal projection on the substrate and covers the orthogonal projection of the seventh active portion on the substrate. A portion of the structure of the second reset signal line is used to form the gate of the seventh transistor. Wherein, the first direction is the row direction, and in adjacent row pixel driving circuits, the second reset signal line in the previous row pixel driving circuit is shared as the first reset signal line in the current row pixel driving circuit.

13. The display panel according to claim 12, wherein, The active layer also includes; The third active portion is used to form the channel region of the driving transistor; The first conductive layer further includes: The third conductive portion, the orthogonal projection of the third conductive portion on the substrate covers the orthogonal projection of the third active portion on the substrate, the third conductive portion being used to form the gate of the driving transistor; The second conductive layer further includes: The first initial signal line extends along the first direction in the orthographic projection onto the substrate. The second initial signal line extends along the first direction in the orthogonal projection onto the substrate. In the same row of pixel driving circuits, the orthographic projection of the third conductive part on the substrate is located between the orthographic projection of the first initial signal line on the substrate and the orthographic projection of the second initial signal line on the substrate, and the orthographic projection of the first initial signal line on the substrate is located on the side of the first reset signal line on the substrate away from the orthographic projection of the third conductive part on the substrate. In adjacent row pixel driving circuits, the orthographic projection of the second initial signal line in the previous row pixel driving circuit onto the substrate is located between the orthographic projection of the first initial signal line in the current row pixel driving circuit onto the substrate and the orthographic projection of the first reset signal line in the current row pixel driving circuit onto the substrate.

14. The display panel according to claim 13, wherein, The first active part includes a fourth sub-active part and a fifth sub-active part, and the active layer further includes a sixth sub-active part connected between the fourth sub-active part and the fifth sub-active part; The orthographic projection of the second initial signal line in the previous row pixel driving circuit onto the substrate overlaps at least partially with the orthographic projection of the sixth sub-active part in the current row pixel driving circuit onto the substrate.

15. The display panel according to claim 1, wherein, The pixel driving circuit further includes a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; The first terminal of the first transistor is connected to the first initial signal line, and the second terminal is connected to the gate of the driving transistor. The first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal is connected to the second terminal of the driving transistor; The first terminal of the fourth transistor is connected to the data line, and the second terminal is connected to the first terminal of the driving transistor. The first terminal of the fifth transistor is connected to the second power supply line, and the second terminal is connected to the first terminal of the driving transistor. The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting unit. The first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode is connected to the first electrode of the light-emitting unit. The first transistor, the second transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are all P-type transistors.

16. The display panel according to claim 15, wherein, The display panel also includes: An active layer is located between the substrate and the second conductive layer. The active layer includes a third active portion, a fourth active portion, a fifth active portion, a sixth active portion, and a seventh active portion. The third active portion is used to form the channel region of the driving transistor, the fourth active portion is used to form the channel region of the fourth transistor, the fifth active portion is used to form the channel region of the fifth transistor, the sixth active portion is used to form the channel region of the sixth transistor, and the seventh active portion is used to form the channel region of the seventh transistor. A first conductive layer is located between the active layer and the second conductive layer, and the first conductive layer includes: A gate line, whose orthogonal projection on the substrate extends along the first direction and covers the orthogonal projection of the fourth active portion on the substrate, wherein a portion of the structure of the gate line is used to form the gate of the fourth transistor; An enable signal line extends along the first direction in the orthographic projection on the substrate and covers the orthographic projections of the fifth active portion and the sixth active portion on the substrate. A portion of the structure of the enable signal line is used to form the gate of the fifth transistor, and another portion of the structure of the enable signal line is used to form the gate of the sixth transistor. The second reset signal line extends along the first direction in the orthogonal projection on the substrate and covers the orthogonal projection of the seventh active portion on the substrate. A portion of the structure of the second reset signal line is used to form the gate of the seventh transistor. The third conductive portion, the orthogonal projection of the third conductive portion on the substrate covers the orthogonal projection of the third active portion on the substrate, the third conductive portion being used to form the gate of the driving transistor; In the same row of pixel driving circuits, the orthogonal projection of the enable signal line on the substrate is located between the orthogonal projection of the third conductive part on the substrate and the orthogonal projection of the second reset signal line on the substrate.

17. A display device, wherein, Includes the display panel as described in any one of claims 1-16.

Images