Reading timing control method and device and computer readable storage medium

Abstract

A read timing control method, device and computer readable storage medium, the read timing control device includes an on-chip memory, the read timing control method includes: writing input data into the on-chip memory; performing frame tail detection on the input data; after detecting the frame tail, counting the input data lines, and generating a read timing according to a preset porch parameter; determining whether the on-chip memory will be read empty or written full according to the input data line count and the generated read timing; when the on-chip memory will be read empty or written full, adjusting the read timing until the on-chip memory will not be read empty or written full, and reading data of the on-chip memory according to the read timing and outputting.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display driver technology, and in particular to a read timing control method, apparatus, and computer-readable storage medium. Background Technology

[0002] When the display interface transmits data, there is a certain positional relationship between the valid data and the start signal (frame synchronization signal Vs / line synchronization signal Hs). This relationship is usually characterized by a set of Porch parameters. For example, Porch parameters include total horizontal lines (HTotal), active horizontal lines (HActive), horizontal synchronization (HSYNC), horizontal back edge clamp (HBackPorch, HBP), horizontal front edge clamp (HFront Porch, HFP), horizontal blanking (HBlanking), active video end (EAV), active video start (SAV), total vertical lines (VTotal), active vertical lines (VActive), vertical front edge clamp (VFront Porch, VFP), vertical blanking interval (VBI), vertical back edge clamp (VBack Porch, VBP), and vertical blanking (VBlanking), etc. Wherein, VBP represents the number of invalid lines after the frame synchronization signal at the beginning of a frame, VFP represents the number of invalid lines before the frame synchronization signal at the end of a frame, HBP represents the number of clock signals between the start of the line synchronization signal and the start of valid data in a line, and HFP represents the number of clock signals between the end of valid data in a line and the start of the next line synchronization signal.

[0003] like Figure 1 As shown, when using a Field Programmable Gate Array (FPGA) as the display driver, a "Porch conversion" operation is typically performed on the data—after receiving data input from the front end according to Porch parameter A, the data is sent out with a preset Porch parameter B. The advantage of this operation is that during display debugging, it is often necessary to adjust the relative position of the data source and the array substrate row driver (GOA) to improve the display effect, which can be easily achieved based on "Porch conversion" (by modifying preset Porch parameters). Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a read timing control method applied to a read timing control device, the read timing control device including on-chip memory, and the read timing control method comprising:

[0006] Write the input data to the on-chip memory;

[0007] Perform frame end detection on the input data;

[0008] After detecting the end of the frame, the input data lines are counted, and a read timing sequence is generated according to the preset Porch parameters;

[0009] Based on the input data row count and the generated read timing, it is determined whether the on-chip memory will be read empty or written full;

[0010] When the on-chip memory is read empty or written full, the read timing is adjusted until the on-chip memory is not read empty or written full, and the data in the on-chip memory is read and output according to the read timing.

[0011] In some exemplary embodiments, the step of detecting the end of a frame in the input data includes:

[0012] Detect the width of the low level of the input DE signal;

[0013] When the width of the low level of the input DE signal is greater than or equal to the preset first width threshold, the position of the current input data is determined to be the end of the frame.

[0014] In some exemplary embodiments, counting the input data rows includes counting the input data rows based on the rising edge of the input DE signal.

[0015] In some exemplary embodiments, generating read timings based on preset Porch parameters includes:

[0016] Starting from the end of the frame, the output row counter and the output column counter are counted according to the preset Porch parameters. When the output data is at the end of the row, the output row counter is reset and the count restarts when the next row of data is output. When the output data is at the end of the frame, the output column counter is reset and the count restarts when the next frame of data is output.

[0017] The read timing is generated based on the values ​​of the output row counter and the output column counter.

[0018] In some exemplary embodiments, generating the read timing based on the values ​​of the output row counter and the output column counter includes:

[0019] The first range and the second range are determined according to the preset Porch parameters, wherein the first range represents the effective data column of the display panel, the second range represents the effective data row of the display panel, and the first range and the second range represent the effective data area of ​​the display panel.

[0020] When the output row counter is in the first range and the output column counter is in the second range, the read control signal is set to high level;

[0021] When the output row counter is outside the first range or the output column counter is outside the second range, the read control signal is set to low level.

[0022] In some exemplary embodiments, the first range is determined based on the total number of horizontal rows Htotal, the horizontal trailing edge clamp HBP, and the horizontal leading edge clamp HFP, and the second range is determined based on the total number of vertical rows Vtotal, the vertical leading edge clamp VFP, and the vertical trailing edge clamp VBP.

[0023] In some exemplary embodiments, adjusting the read timing when the on-chip memory is read-empty or written-full includes:

[0024] When the on-chip memory is about to be read out, increase the vertical trailing edge clamp VBP to delay the high-level read control signal;

[0025] When the on-chip memory is full, reduce the vertical trailing edge clamp (VBP) to advance the high-level read control signal.

[0026] In some exemplary embodiments, adjusting the read timing when the on-chip memory is read-empty or written-full includes:

[0027] When the on-chip memory is about to be read out, increase the vertical leading edge clamp VFP to delay the high-level read control signal;

[0028] When the on-chip memory is full, the vertical leading edge clamp (VFP) is reduced to advance the high-level read control signal.

[0029] In some exemplary embodiments, the on-chip memory includes either a first-in-first-out (FIFO) memory or a random block memory (BRAM).

[0030] This disclosure also provides a read timing control device, including: a read / write control circuit and an on-chip memory, wherein: the read / write control circuit is configured to write input data into the on-chip memory, perform frame end detection on the input data, count the input data lines after detecting the frame end, generate a read timing sequence according to a preset Porch parameter, determine whether the on-chip memory will be read empty or written full based on the input data line count and the generated read timing sequence, adjust the read timing sequence until the on-chip memory will not be read empty or written full when the on-chip memory is likely to be read empty or written full, and read data from the on-chip memory according to the read timing sequence for output; the on-chip memory is configured to store input data.

[0031] In some exemplary embodiments, the read timing control device further includes timing circuitry, wherein,

[0032] The timing circuit is configured to generate line synchronization signals and frame synchronization signals according to preset Porch parameters, and to generate data valid signals according to the read timing adjusted by the read / write control circuit.

[0033] This disclosure also provides a read timing control device, including a memory; and a processor connected to the memory, the memory being used to store instructions, the memory further including on-chip memory, and the processor being configured to execute the steps of the read timing control method according to any embodiment of this disclosure based on the instructions stored in the memory.

[0034] This disclosure also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the read timing control method described in any embodiment of this disclosure.

[0035] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0036] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0037] Figure 1 This is a schematic diagram of an exemplary display driver control system architecture;

[0038] Figure 2 This is a schematic diagram of an exemplary implementation of a Porch conversion circuit;

[0039] Figure 3A schematic diagram of a read timing control device provided for an exemplary embodiment of this disclosure;

[0040] Figure 4 A flowchart illustrating an automatic timing adjustment method provided for an exemplary embodiment of this disclosure;

[0041] Figure 5 A flowchart illustrating a read timing control method provided for an exemplary embodiment of this disclosure;

[0042] Figure 6A and Figure 6B This is a schematic diagram illustrating two cases of unreasonable read / write timing intervals exemplified in this disclosure;

[0043] Figure 7A In response to Figure 6A The diagram shows the improved effect after adopting the read timing control flow of the present disclosure embodiment;

[0044] Figure 7B In response to Figure 6B The diagram shows the improved effect after adopting the read timing control flow of the present disclosure embodiment;

[0045] Figure 8 A flowchart illustrating another read timing control method provided for an exemplary embodiment of this disclosure;

[0046] Figure 9 This is a schematic diagram of a read timing control device provided as an exemplary embodiment of the present disclosure. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be arbitrarily combined with each other.

[0048] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" indicate that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, but do not exclude other elements or objects.

[0049] A Porch conversion scheme can be summarized as "frame buffer + double data rate synchronous dynamic random access memory (DDR)," and its system implementation architecture is as follows: Figure 2 As shown. The implementation principle of this method is: based on the preset Porch parameters (i.e. Figure 1The Porch parameter B in the sequence is used by the timing (Sync_gen) circuit to generate DE / Hs / Vs signals, where DE is the data valid signal, Hs is the line synchronization signal, and Vs is the frame synchronization signal. Based on the preset Porch parameters, the write / read control circuit generates the read control signal for the DDR memory. The DDR memory then outputs the data signal Data according to the read control signal. Since Data and DE / Hs / Vs are essentially generated based on the Porch parameters, synchronization can be achieved in principle. In other words, the output data will indeed satisfy this set of preset Porch parameters.

[0050] Because it uses a "frame buffer," meaning the data is stored in units of frames, it minimizes the connection between the front-end (player) input and the back-end (display panel). The front-end and back-end operate according to their respective timing sequences, with almost no overlap except for data transmission. However, implementing a "frame buffer" requires a large storage space, so DDR is generally chosen as the storage solution. But DDR read / write operations are complex, resulting in long programming and debugging cycles, which is one of the main factors limiting the application of this solution.

[0051] This disclosure proposes a read timing control method and apparatus. Since it uses on-chip memory resources as the implementation method, the implementation difficulty is greatly reduced, and debugging is basically not required, thus effectively reducing the debugging cycle.

[0052] like Figure 3 As shown, this disclosure provides a read timing control device, including: a read / write control circuit 301 and an on-chip memory 302, wherein:

[0053] The read / write control circuit 301 is configured to write input data into the on-chip memory 302, perform frame end detection on the input data, count the input data lines after the frame end is detected, generate read timing according to the preset Porch parameters, determine whether the on-chip memory 302 will be empty or full based on the input data line count and the generated read timing, and adjust the read timing when the on-chip memory 302 will be empty or full, and read the data from the on-chip memory 302 according to the read timing for output.

[0054] On-chip memory 302 is configured to store input data.

[0055] The read timing control device of this disclosure uses on-chip memory as the storage medium. On-chip memory is the storage resource built into the read timing control device, which greatly simplifies the read and write control timing, greatly reduces the difficulty of implementation, and basically eliminates the need for debugging, thus effectively reducing the debugging cycle.

[0056] In some exemplary embodiments, the storage capacity of the on-chip memory 302 can be set; however, this disclosure does not limit this. Since the on-chip memory 302 typically has a limited storage capacity, compared to the "frame buffer + DDR" scheme, the read timing control device of this disclosure can be summarized as "line buffer + on-chip memory," requiring that the on-chip memory be "not emptied by reading and not filled by writing." In other words, the correlation between read and write timings needs to be considered (relatively speaking, the read and write timings of the DDR scheme are basically independent), and a reasonable time interval should be maintained between read and write timings. An excessively large interval will cause the on-chip memory 302 to be filled, resulting in the loss of valid data; an excessively small interval will cause the on-chip memory 302 to be emptied, resulting in errors mixed in with the valid data. To address this problem, the read timing control device of this disclosure employs an automatic read / write timing adjustment method to adjust the read timing, ensuring that the read and write timings are within a reasonable time interval.

[0057] Figure 2 and Figure 3 Although the read / write control circuits in the two systems share the same name, their functions differ. In the DDR memory solution, the read / write control circuit controls the input and output of the DDR memory, making it more complex. In the on-chip memory solution, the read / write control circuit 301 controls the input and output of the on-chip memory 302 and automatically adjusts the read timing, resulting in a simpler overall design.

[0058] In some exemplary implementations, such as Figure 3 As shown, the read timing control device also includes a timing circuit 303, which is configured to generate Hs signal and Vs signal according to preset Porch parameters, and generate DE signal according to the read timing adjusted by the read / write control circuit 303.

[0059] Figure 2 The function of the timing circuit in the middle is to generate the DE signal, Hs signal and Vs signal according to the preset Porch parameters; Figure 3 The timing circuit 303 in the middle is used to generate Hs and Vs signals according to the preset Porch parameters, and to generate DE signal according to the read timing adjusted by the read / write control circuit 301. Therefore, the functions of the two are not entirely the same.

[0060] The read timing control device of this disclosure can be implemented by a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), or by other programmable devices. This disclosure does not limit its implementation.

[0061] In some exemplary embodiments, the read / write control circuit 301, the on-chip memory 302, and the timing circuit 303 can all be implemented using an FPGA.

[0062] The timing circuit 303 and the read / write control circuit 301 in this disclosure can be implemented by various FPGA code logics. This disclosure only limits the functions of the timing circuit 303 and the read / write control circuit 301, and does not limit the specific code logic.

[0063] In some exemplary embodiments, the on-chip memory 302 may include memory such as FIFO (First Input First Output) and Block Random Access Memory (BRAM).

[0064] For example, the on-chip memory 302 can be implemented using the FIFO IP core that comes with the FPGA. The FIFO IP core that comes with the FPGA usually has an empty / full flag signal (Empty, Full), which can be used as a basis for determining whether the read timing is reasonable.

[0065] For example, the on-chip memory 302 can be implemented using BRAM. BRAM is a built-in memory unit of the FPGA chip, and like FIFO, it is a small-capacity storage device. Therefore, both BRAM and FIFO can be used as row caches. To prevent the memory from being filled or read empty, strict control of read and write timing is required, which is a problem faced by both BRAM and FIFO. Since operations on BRAM usually involve both addresses and data, they are slightly more complex than FIFO operations (which only involve data). However, the operational difficulty of both is much lower than that of DDR.

[0066] The read timing control device of this disclosure can be applied to the Porch conversion circuit in the display driver, or to any other scenario that requires Porch conversion or read timing control. This disclosure does not limit it.

[0067] like Figure 1 and Figure 3 As shown, the timing circuit 303 operates according to preset Porch parameters (i.e., ... Figure 1 The Porch parameter B and the read timing adjusted by the read / write control circuit 301 generate the DE2, Hs2, and Vs2 signals. Before the read timing control device, data is transmitted according to the Porch parameter A, that is, the input signals of the Porch conversion circuit are the Data1, DE1, Hs1, and Vs1 signals. The DE1, Hs1, and Vs1 signals are generated by the front end according to the Porch parameter A. The output signals of the read timing control device are the Data2, DE2, Hs2, and Vs2 signals.

[0068] During the data transmission process, the Vs signal is used to identify the starting position of each frame of data, and the Hs signal is used to identify the starting position of each line of data.

[0069] In the video signal input to the display panel, the valid video signal (valid RGB signal) only occupies a portion of the signal cycle, and the row and column blanking periods do not contain valid video data. Therefore, some circuits must distinguish between the intervals containing valid video signals and the blanking intervals that do not. To differentiate between valid and invalid video signals, a DE signal is used in the circuit. The DE signal is a high-level active signal, and the video data signal corresponding to the high-level period of the DE signal is considered a valid data signal.

[0070] Among the five types of signals—DE, Hs, Vs, CLK (clock signal), and Data—DE, Hs, and Vs are synchronization signals, CLK is a clock signal, and Data is a data signal. They generally appear simultaneously, and DE, Hs, Vs, and Data are synchronized with the clock signal CLK.

[0071] When the DE signal is high, and at the rising or falling edge of the clock signal CLK, the relevant circuits read the RGB data to ensure the correctness of the read data. The condition of the DE signal being high during data reading actually means the selection of valid data; that is, for the back-end circuits, the read control signal generated according to the read timing is the DE signal.

[0072] In some exemplary implementations, the width of the high level of the DE signal is equal to the value of the horizontal active row number Hactive. For example, if the horizontal active row number Hactive = 100, then the width of the high level of the DE signal is 100 clock units.

[0073] In some exemplary embodiments, frame end detection of the input data includes:

[0074] Detect the width of the low level of the input DE signal;

[0075] When the width of the low level of the input DE signal is greater than or equal to the preset first width threshold, the position of the current input data is determined as the end of the frame.

[0076] In this embodiment, frame end detection can be performed on the input data based on the width of the low level of the input DE signal. For example, such as... Figure 4 As shown, frame end detection can be performed on the input data based on the interval between the falling edge of the previous square wave and the rising edge of the next square wave in the input DE signal.

[0077] For example, between lines, the width of the low level of the DE signal is approximately several hundred clock intervals, for example, 100 to 200 clock intervals. Between frames, the width of the low level of the DE signal is approximately several thousand clock intervals, for example, 1000 to 2000 clock intervals. Therefore, the first width threshold can be set to x clock intervals, for example, x can be 800; however, this disclosure is not limited thereto.

[0078] In some exemplary implementations, the number of input data rows is counted based on the rising edge of the input DE signal.

[0079] Edge detection of signals is widely used in digital circuits. Therefore, the rising edge of the input DE signal can be used as the basis for counting input data rows, such as... Figure 4 As shown, each time a rising edge of the DE signal is detected, it is considered that a new row of input data has been added, that is, the input data row counter is incremented by 1.

[0080] In this embodiment of the disclosure, the input data row count only counts valid data and does not count data that has been obscured. For example... Figure 6A As shown in Figure 6B, the input data has eight channels. The data from the first to the eighth channels constitute one frame of data. 000000 represents the annulment data. In the annulment data area, the input data line counter is always 0; in the valid data area, the input data line counter increments from 1 to the maximum number of lines (for example, the maximum number of lines can be 63). Then, the next frame of data is transmitted, and the input data line counter is reset to zero and starts counting again.

[0081] In some exemplary implementations, such as Figure 5 As shown, the read timing is generated based on the preset Porch parameters, including:

[0082] Design one output row counter (H-direction counter) and one output column counter (V-direction counter);

[0083] Starting from the end of the frame, the output row counter and output column counter are counted according to the preset Porch parameters. When the output data is at the end of the line, the output row counter is reset (i.e., the value of the output row counter is cleared to zero) and the output row counter restarts counting when the next line of data is output. When the output data is at the end of the frame, the output column counter is reset (i.e., the value of the output column counter is cleared to zero) and the output column counter restarts counting when the next frame of data is output.

[0084] The read timing is generated based on the values ​​of the output row counter and the output column counter.

[0085] In this embodiment of the disclosure, after the end of a frame is detected, the input data row counter does not start counting immediately. It needs to wait for the next frame of valid data to be transmitted and then increment by 1 after each row is transmitted. The output row counter (H-direction counter) and the output column counter (V-direction counter) will start counting from the time point when the end of the frame is detected.

[0086] In this embodiment of the disclosure, the H-direction counter counts from 0 to HTotal, and the V-direction counter counts from 0 to VTotal. However, the output data is valid only when the H-direction counter is in the first range and the V-direction counter is in the second range. For example, the first range can be determined based on the values ​​of the total horizontal row count Htotal, the horizontal trailing edge clamp HBP, and the horizontal leading edge clamp HFP. The second range can be determined based on the values ​​of the total vertical row count Vtotal, the vertical leading edge clamp VFP, and the vertical trailing edge clamp VBP.

[0087] In some exemplary embodiments, generating read timing based on the values ​​of the output row counter and the output column counter includes:

[0088] The first range and the second range are determined according to the preset Porch parameters, wherein the first range represents the effective data column of the display panel, the second range represents the effective data row of the display panel, and the first range and the second range represent the effective data area of ​​the display panel.

[0089] When the output row counter is in the first range and the output column counter is in the second range, enable the read control signal (i.e., set the read control signal to high level);

[0090] When the output row counter is outside the first range or the output column counter is outside the second range, the read control signal is disabled (i.e., the read control signal is set to low).

[0091] In this embodiment of the disclosure, the positional relationship between the input data row count and the generated read timing sequence is detected to determine whether it will cause the on-chip memory to be read empty or written full; when the positional relationship between the input data row count and the generated read timing sequence will cause the on-chip memory to be read empty or written full, the generated read timing sequence is unreasonable.

[0092] For example, suppose that during design, the on-chip memory capacity is designed to cache only one line of data (in actual use, the on-chip memory capacity can be designed to cache multiple lines of data; however, this disclosure does not limit this). And... Figure 4 In this case, because the read timing (relative to the number of input data rows) is enabled relatively late, the amount of data that needs to be cached exceeds one row (e.g., Figure 4 If the reading timing is incorrect (as shown in the gray shaded area), the high-level read control signal in the reading timing should be moved forward.

[0093] Figure 6A and Figure 6B This diagram illustrates two scenarios of unreasonable read / write timing intervals exemplified in this disclosure. The first type of unreasonable timing occurs when the on-chip memory is completely read out, such as... Figure 6A As shown, the high-level read control signal is too early (the valid data has not yet appeared when the read begins); the second type is unreasonable, corresponding to the on-chip memory being full, such as... Figure 6B As shown, the high-level read control signal is too delayed (by the time the read begins, several lines of valid data have already passed, and the number of lines has exceeded the capacity of the on-chip memory).

[0094] In some exemplary embodiments, when the on-chip memory is read-empty or written-full, the read timing is adjusted, including:

[0095] When the on-chip memory is about to be read out, increase the vertical trailing edge clamp VBP to delay the high-level read control signal;

[0096] When the on-chip memory is about to be filled, reduce the vertical trailing edge clamp (VBP) to advance the high-level read control signal.

[0097] For example, after adopting the method of automatically adjusting read / write timing to address the two types of unreasonableness mentioned above, the actual improvement is as follows: Figure 7A and Figure 7B As shown. For the first category of unreasonable cases, such as... Figure 7A As shown, increasing VBP will automatically delay the high-level read control signal in the read timing; for the second type of unreasonable behavior, such as... Figure 7B As shown, reducing VBP will automatically advance the high-level read control signal in the read timing sequence. This adjustment ensures that the time interval between read and write operations is within a reasonable range, thus guaranteeing error-free data transmission.

[0098] In other exemplary embodiments, when the on-chip memory is read-empty or written-full, the read timing is adjusted, including:

[0099] When the on-chip memory is about to be read out, increase the vertical leading edge clamp VFP to delay the high-level read control signal;

[0100] When the on-chip memory is about to be filled, reduce the vertical leading edge clamp (VFP) to advance the high-level read control signal.

[0101] like Figure 8 As shown in the embodiments of this disclosure, a read timing control method is also provided, including the following steps:

[0102] Step 801: Write the input data into the on-chip memory;

[0103] Step 802: Perform frame end detection on the input data;

[0104] Step 803: After detecting the end of the frame, count the input data lines and generate the read timing sequence according to the preset Porch parameters;

[0105] Step 804: Determine whether the on-chip memory will be read empty or written full based on the input data row count and the generated read timing sequence;

[0106] Step 805: When the on-chip memory is about to be empty or full, adjust the read timing until the on-chip memory is not about to be empty or full, and read the data from the on-chip memory according to the read timing for output.

[0107] The read timing control method of this disclosure uses on-chip memory as the storage medium, which is the storage resource built into the read timing control device. Therefore, the read and write control timing of this disclosure is greatly simplified, thus greatly reducing the difficulty of implementation and requiring almost no debugging, thereby effectively reducing the debugging cycle.

[0108] The read timing control method of this disclosure can be implemented by a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), or by other programmable devices. This disclosure does not limit its implementation.

[0109] The read timing control method of this disclosure can be implemented by various FPGA code logics. This disclosure only limits the flow of the method and does not limit the specific code logic.

[0110] The read timing control method of this disclosure can be used in the Porch conversion circuit in the display driver, or in other scenarios that require Porch conversion or read timing control. This disclosure does not limit it.

[0111] In some exemplary embodiments, frame end detection of the input data includes:

[0112] Detect the width of the low level of the input DE signal;

[0113] When the width of the low level of the input DE signal is greater than or equal to the preset first width threshold, the position of the current input data is determined to be the end of the frame.

[0114] In some exemplary embodiments, counting the input data rows includes counting the input data rows based on the rising edge of the input DE signal.

[0115] In some exemplary embodiments, the read timing is generated based on preset Porch parameters, including:

[0116] Starting from the end of the frame, the output row counter and the output column counter are counted according to the preset Porch parameters. When the output data is at the end of the row, the output row counter is reset and the count restarts when the next row of data is output. When the output data is at the end of the frame, the output column counter is reset and the count restarts when the next frame of data is output.

[0117] The read timing is generated based on the values ​​of the output row counter and the output column counter.

[0118] In some exemplary embodiments, generating read timing based on the values ​​of the output row counter and the output column counter includes:

[0119] The first range and the second range are determined according to the preset Porch parameters, wherein the first range represents the effective data column of the display panel, the second range represents the effective data row of the display panel, and the first range and the second range represent the effective data area of ​​the display panel.

[0120] When the output row counter is in the first range and the output column counter is in the second range, set the read control signal to high level;

[0121] When the output row counter is outside the first range or the output column counter is outside the second range, the read control signal is set to low level.

[0122] In some exemplary embodiments, the first range is determined based on the total number of horizontal rows Htotal, the horizontal trailing edge clamp HBP, and the horizontal leading edge clamp HFP, and the second range is determined based on the total number of vertical rows Vtotal, the vertical leading edge clamp VFP, and the vertical trailing edge clamp VBP.

[0123] In some exemplary embodiments, when the on-chip memory is read-empty or written-full, the read timing is adjusted, including:

[0124] When the on-chip memory is about to be read out, increase the vertical trailing edge clamp VBP to delay the high-level read control signal;

[0125] When the on-chip memory is about to be filled, reduce the vertical trailing edge clamp (VBP) to advance the high-level read control signal.

[0126] In some exemplary embodiments, when the on-chip memory is read-empty or written-full, the read timing is adjusted, including:

[0127] When the on-chip memory is about to be read out, increase the vertical leading edge clamp VFP to delay the high-level read control signal;

[0128] When the on-chip memory is about to be filled, reduce the vertical leading edge clamp (VFP) to advance the high-level read control signal.

[0129] In some exemplary embodiments, the on-chip memory includes either a first-in-first-out (FIFO) memory or a random block memory (BRAM).

[0130] This disclosure also provides a read timing control device, which may include a processor and a memory storing a computer program executable on the processor. When the processor executes the computer program, it implements the steps of the read timing control method as described in any of the preceding claims of this disclosure.

[0131] like Figure 9 As shown, in one example, the read timing control device may include: a processor 910, a memory 920, and a bus system 930, wherein the processor 910 and the memory 920 are connected via the bus system 930, the memory 920 is used to store instructions, and the memory 920 also includes on-chip memory, the processor 910 is used to execute the instructions stored in the memory 920 to write input data into the on-chip memory; perform frame end detection on the input data; after detecting the frame end, count the input data lines and generate read timing according to preset Porch parameters; determine whether the on-chip memory will be empty or full based on the input data line count and the generated read timing; when the on-chip memory will be empty or full, adjust the read timing and read the data from the on-chip memory according to the read timing for output.

[0132] It should be understood that processor 910 can be a Central Processing Unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), off-the-shelf programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0133] Memory 920 may include read-only memory and random access memory, and provides instructions and data to processor 910. A portion of memory 920 may also include non-volatile random access memory. For example, memory 920 may also store device type information.

[0134] In addition to a data bus, the bus system 930 may also include a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 9 The general labeled all buses as Bus System 930.

[0135] In implementation, the processing performed by the processing device can be accomplished through integrated logic circuits in the hardware of the processor 910 or through software instructions. That is, the method steps of this embodiment can be executed by a hardware processor, or by a combination of hardware and software modules within the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other storage media. This storage medium is located in memory 920, and the processor 910 reads information from memory 920 and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, further details are omitted here.

[0136] This disclosure also provides a computer-readable storage medium storing executable instructions. When executed by a processor, these executable instructions can implement the read timing control method provided in any of the above embodiments of this disclosure. This read timing control method can write input data into on-chip memory; perform frame end detection on the input data; after detecting the frame end, count the input data lines and generate a read timing sequence based on preset Porch parameters; determine whether the on-chip memory will be empty or full based on the input data line count and the generated read timing sequence; when the on-chip memory is about to be empty or full, adjust the read timing sequence and read data from the on-chip memory according to the read timing sequence for output. This greatly simplifies the read / write control timing, significantly reduces the implementation difficulty, and requires virtually no debugging, thus effectively reducing the debugging cycle. The method of driving read timing control by executing executable instructions is basically the same as the read timing control method provided in the above embodiments of this disclosure, and will not be described in detail here.

[0137] In some possible implementations, various aspects of the read timing control method provided in this application can also be implemented as a program product, which includes program code. When the program product is run on a computer device, the program code is used to cause the computer device to perform the steps in the read timing control method according to various exemplary embodiments of this application described above. For example, the computer device can execute the read timing control method described in the embodiments of this application.

[0138] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0139] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0140] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit the invention. Any person skilled in the art may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope of this disclosure; however, the patent protection scope of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A read timing control method, applied to a read timing control device, the read timing control device including on-chip memory, the read timing control method comprising: Write the input data to the on-chip memory; Perform frame end detection on the input data; After detecting the end of the frame, the input data lines are counted, and a read timing sequence is generated according to the preset Porch parameters; The step of generating read timing based on preset Porch parameters includes: starting from the end of a frame, counting the output row counter and the output column counter according to the preset Porch parameters; resetting the output row counter when the output data is at the end of a row, and restarting the counting when the next row of data is output; resetting the output column counter when the output data is at the end of a frame, and restarting the counting when the next frame of data is output; and generating read timing based on the values ​​of the output row counter and the output column counter. Based on the input data row count and the generated read timing, it is determined whether the on-chip memory will be read empty or written full; When the on-chip memory is about to be empty or full, the read timing is adjusted until the on-chip memory is no longer about to be empty or full, and the data in the on-chip memory is read and output according to the read timing.

2. The read timing control method according to claim 1, wherein, The step of detecting the end of a frame in the input data includes: The width of the low level of the valid input data signal; When the width of the low level of the valid input data signal is greater than or equal to the preset first width threshold, the position of the current input data is determined to be the end of the frame.

3. The read timing control method according to claim 1, wherein, Counting the input data rows includes: counting the input data rows based on the rising edge of the input data valid signal.

4. The read timing control method according to claim 1, wherein, The step of generating the read timing based on the values ​​of the output row counter and the output column counter includes: The first range and the second range are determined according to the preset Porch parameters, wherein the first range represents the effective data column of the display panel, the second range represents the effective data row of the display panel, and the first range and the second range represent the effective data area of ​​the display panel. When the output row counter is in the first range and the output column counter is in the second range, the read control signal is set to high level; When the output row counter is outside the first range or the output column counter is outside the second range, the read control signal is set to low level.

5. The read timing control method according to claim 4, wherein, The first range is determined based on the total number of horizontal rows Htotal, the horizontal trailing edge clamp HBP, and the horizontal leading edge clamp HFP. The second range is determined based on the total number of vertical rows Vtotal, the vertical leading edge clamp VFP, and the vertical trailing edge clamp VBP.

6. The read timing control method according to claim 5, wherein, The adjustment of read timing when the on-chip memory is read-empty or written-full includes: When the on-chip memory is about to be read out, increase the vertical trailing edge clamp VBP to delay the high-level read control signal; When the on-chip memory is full, reduce the vertical trailing edge clamp (VBP) to advance the high-level read control signal.

7. The read timing control method according to claim 5, wherein, The adjustment of read timing when the on-chip memory is read-empty or written-full includes: When the on-chip memory is about to be read out, increase the vertical leading edge clamp VFP to delay the high-level read control signal; When the on-chip memory is full, the vertical leading edge clamp (VFP) is reduced to advance the high-level read control signal.

8. The read timing control method according to claim 1, wherein, The on-chip memory includes either a first-in-first-out (FIFO) memory or a block random access memory (BRAM).

9. A read timing control apparatus, comprising a memory; and a processor connected to the memory, the memory being used to store instructions, the memory further comprising on-chip memory, the processor being configured to perform the steps of the read timing control method as claimed in any one of claims 1 to 8 based on the instructions stored in the memory.

10. A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the read timing control method as described in any one of claims 1 to 8.

11. A read timing control device, comprising: Read / write control circuitry and on-chip memory, including: The read / write control circuit is configured to write input data into the on-chip memory, perform frame end detection on the input data, count the input data lines after detecting the frame end, generate a read timing sequence according to a preset Porch parameter, determine whether the on-chip memory will be read empty or written full based on the input data line count and the generated read timing sequence, and adjust the read timing sequence until the on-chip memory will not be read empty or written full when the on-chip memory is about to be read empty or written full, and read the data from the on-chip memory according to the read timing sequence for output. The on-chip memory is configured to store input data; The read / write control circuit generates a read timing sequence based on preset Porch parameters, including: starting from the end of a frame, counting the output row counter and the output column counter according to the preset Porch parameters; resetting the output row counter when the output data is at the end of a row, and restarting the counting when the next row of data is output; resetting the output column counter when the output data is at the end of a frame, and restarting the counting when the next frame of data is output; and generating a read timing sequence based on the values ​​of the output row counter and the output column counter.

12. The read timing control device according to claim 11, further comprising a timing circuit, wherein, The timing circuit is configured to generate line synchronization signals and frame synchronization signals according to preset Porch parameters, and to generate data valid signals according to the read timing adjusted by the read / write control circuit.

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