Memory devices and systems with parallel impedance adjustment circuitry and methods of operation thereof

Abstract

The present disclosure relates to memory devices and systems with parallel impedance adjustment circuitry and methods of operation thereof. The present disclosure provides methods, systems, and apparatuses related to memory operations over a common clock signal. A memory device or system containing one or more memory devices can operate over a common clock signal without incurring a delay from turning on or off a termination on a die. For example, a memory device can include first and second impedance adjustment circuitry, the first impedance adjustment circuitry configured to provide a first impedance to a received clock signal having a clock impedance, the second impedance adjustment circuitry configured to provide a second impedance to the received clock signal. The first impedance and the second impedance can be configured to provide a combined impedance approximately equal to the clock impedance when the first impedance adjustment circuitry and the second impedance adjustment circuitry are connected in parallel to the received clock signal.

Description

[0001] Information related to divisional application

[0002] This application is a divisional application of Chinese Patent Application No. 201880078539.5, filed on July 21, 2018, entitled "Memory device and system having a parallel impedance adjustment circuit system and a method of operation thereof".

[0003] Cross-references to related applications

[0004] This application claims the benefit of U.S. Provisional Application No. 62 / 583,608, filed November 9, 2017, which is incorporated herein by reference in its entirety. Technical Field

[0005] This disclosure relates generally to memory devices, and more specifically to memory devices and systems having a parallel impedance adjustment circuit system and methods of operating thereof. Background Technology

[0006] Memory devices are widely used to store information related to various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming different states of memory cells. Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), and synchronous dynamic RAM (SDRAM). Memory devices can be volatile or non-volatile. Improvements to memory devices typically include increasing memory cell density, increasing read / write speeds or otherwise reducing operation latency, increasing reliability, increasing data retention, reducing power consumption or manufacturing costs, and other metrics. Summary of the Invention

[0007] In one aspect, this disclosure relates to a memory device comprising: a plurality of impedance adjustment circuit systems, each impedance adjustment circuit system being configured to provide a corresponding impedance to a received clock signal having a clock impedance; wherein the corresponding impedance of the plurality of impedance adjustment circuit systems provides a combined impedance based on the clock impedance during a read operation relating to a memory cell corresponding to one of the plurality of impedance adjustment circuit systems, and wherein the corresponding impedance of each of the plurality of impedance adjustment circuit systems is an integer multiple of the clock impedance.

[0008] On the other hand, this disclosure relates to a method comprising: receiving a clock signal having a clock impedance at a first memory device; receiving the clock signal having the clock impedance at a second memory device; and during a read operation relating to a memory cell of the first memory device, adjusting a first impedance at the first memory device and a second impedance at the second memory device to provide a combined impedance at least in part based on the clock impedance, wherein each of the first impedance and the second impedance is an integer multiple of the clock impedance.

[0009] In another aspect, this disclosure relates to a memory device comprising: a first impedance adjustment circuit system configured to provide a first impedance to a received clock signal having a clock impedance; and a second impedance adjustment circuit system configured to provide a second impedance to the received clock signal; wherein the first impedance adjustment circuit system includes an impedance detection circuit system configured to detect the clock impedance, and wherein the first impedance and the second impedance are configured to provide a combined impedance at least in part based on the detected clock impedance.

[0010] In another aspect, this disclosure relates to a memory system comprising: a first memory device including a first impedance adjustment circuit system configured to provide a first impedance to a received clock signal having a clock impedance; and a second memory device including a second impedance adjustment circuit system configured to provide a second impedance to the received clock signal; wherein the first impedance adjustment circuit system includes an impedance detection circuit system configured to detect the clock impedance, and wherein when the first impedance adjustment circuit system and the second impedance adjustment circuit system are connected in parallel to the received clock signal, the first impedance and the second impedance are configured to provide a combined impedance equal to the detected clock impedance.

[0011] In another aspect, this disclosure relates to a method comprising: receiving a clock signal having a clock impedance at a first clock terminal of a first memory device; receiving the clock signal having the clock impedance at a second clock terminal of a second memory device; detecting the clock impedance at the first clock terminal; and adjusting the first impedance at the first clock terminal and the second impedance at the second clock terminal to provide a combined impedance at least in part based on the detected clock impedance. Attached Figure Description

[0012] Figure 1 This is a simplified block diagram schematically illustrating a memory device according to an embodiment of the technology of the present invention.

[0013] Figure 2a and 2b This is a simplified block diagram schematically illustrating a memory device according to an embodiment of the technology of the present invention.

[0014] Figure 3-6 This is a simplified block diagram schematically illustrating a memory device according to an embodiment of the technology of the present invention.

[0015] Figure 7-10 This is a simplified block diagram schematically illustrating a memory system according to an embodiment of the technology of the present invention.

[0016] Figure 11-13 This is a flowchart illustrating a method for operating a memory device and a memory system according to an embodiment of the present invention. Detailed Implementation

[0017] Memory devices and memory systems may comprise multiple individually addressable memory arrays, memory columns, memory groups, memory channels, or other sub-partitions of memory capacity. In some such devices and systems, separate data clock terminals may be provided (e.g., for receiving applied read data clocks such as WCK) to correspond to each individually addressable memory array, memory column, memory group, memory channel, or other sub-partition. This approach allows individual clock signals to be provided to different sub-partitions of the memory only when needed. Alternatively, a single clock signal may be provided to multiple terminals, but this approach may involve turning on and off the on-die termination at each terminal depending on whether the corresponding memory sub-partition is being accessed. The latter approach may simplify the design of the memory host or controller (e.g., reducing the number of discrete clock signals it provides), but may undesirably increase latency when switching between accessing one sub-partition of the memory and another (e.g., due to the time required to adjust impedances at different clock terminals). Therefore, it is desirable to provide a way to share a common clock signal across multiple clock terminals in a memory device or system without the latency associated with turning on and off the on-die termination caused by accessing different corresponding portions of the memory device or system.

[0018] Therefore, several embodiments of the present invention relate to memory devices, systems including memory devices, and methods of operating memory devices, wherein a common signal can be connected in parallel to multiple terminals without turning the terminals on and off on the die (e.g., without delay in adjusting impedance at different terminals). In one embodiment, a memory device is provided comprising: a first impedance adjustment circuit system configured to provide a first impedance to a received clock signal having a clock impedance; and a second impedance adjustment circuit system configured to provide a second impedance to the received clock signal. When the first impedance adjustment circuit system and the second impedance adjustment circuit system are connected in parallel to the received clock signal, the first impedance and the second impedance can be configured to provide a combined impedance approximately equal to the clock impedance.

[0019] Figure 1 This is a block diagram schematically illustrating a memory device 100 according to an embodiment of the present invention. The memory device 100 may include an array of memory cells, such as a memory array 150. The memory array 150 includes multiple groups (e.g., Figure 1 The examples are groups 0-15, each group containing multiple word lines (WL), multiple bit lines (BL), and multiple memory cells arranged at the intersections of the word lines and bit lines. The selection of word lines WL is performed by row decoder 140, and the selection of bit lines BL is performed by column decoder 145. A sense amplifier (SAMP) is provided for the corresponding bit line BL, and the sense amplifier is connected to at least one corresponding local I / O line pair (LIOT / B), which is in turn coupled to at least one corresponding main I / O line pair (MIOT / B) through a transmission gate (TG) acting as a switch.

[0020] The memory device 100 may employ multiple terminals (e.g., external terminals, pins, pads, interconnections that may be located externally or internally to the device), including command and address terminals coupled to the command bus and address bus to receive command signal CMD and address signal ADDR, respectively. The memory device may further include a chip select terminal for receiving a chip select signal CS; a clock terminal for receiving clock signals CK and CKF; a data clock terminal for receiving data clock signals WCK and WCKF; data terminals DQ, RDQS, DBI, and DMI; and power supply terminals VDD, VSS, VDDQ, and VSSQ.

[0021] Address signals and group address signals can be supplied externally to the command and address terminals. The address signals and group address signals supplied to the address terminals are transmitted to the address decoder 110 via the command / address input circuit 105. The address decoder 110 receives the address signals and supplies decoded row address signals (XADD) to the row decoder 140 and decoded column address signals (YADD) to the column decoder 145. The address decoder 110 also receives group address signals (BADD) and supplies group address signals to both the row decoder 140 and the column decoder 145.

[0022] Command signals CMD, address signals ADDR, and chip select signals CS can be supplied from the memory controller to the command and address terminals. The command signals can represent various memory commands from the memory controller (e.g., access commands, which may include read and write commands). The select signal CS can be used to select the memory device 100 to respond to commands and addresses supplied to the command and address terminals. When an activation CS signal is provided to the memory device 100, the commands and addresses are decoded and memory operations are performed. The command signal CMD can be provided to the command decoder 115 via the command / address input circuitry 105 in the form of an internal command signal ICMD. The command decoder 115 includes circuitry for decoding the internal command signal ICMD to generate various internal signals and commands for performing memory operations, such as row command signals for selecting word lines and column command signals for selecting bit lines. The internal command signals can also include output activation commands and input activation commands, such as the timing command CMDCK.

[0023] When a read command is issued and row and column addresses are supplied in a timely manner along with the read command, read data is read from the memory cells specified by these row and column addresses in the memory array 150. The read command is received by a command decoder 115, which provides an internal command to the input / output circuitry 160, causing the read data to be output externally from the data terminals DQ, RDQS, DBI, and DMI according to the RDQS clock signal through the read / write amplifier 155 and the input / output circuitry 160. The read data is then stored in a memory device 100 (e.g., in a mode register). Figure 1 The read wait time information RL (not shown in the diagram) defines the time provided. The read wait time information RL can be defined based on the clock cycle of the CK clock signal. For example, when associated read data is provided, the read wait time information RL can be multiple clock cycles of the CK signal after the memory device 100 receives the read command.

[0024] When a write command is issued and the row and column addresses are supplied in a timely manner along with the command, write data is supplied to the data terminals DQ, DBI, and DMI according to the WCK and WCKF clock signals. The write command is received by the command decoder 115, which provides an internal command to the input / output circuit 160, causing the write data to be received by the data receiver in the input / output circuit 160 and supplied to the memory array 150 through the input / output circuit 160 and the read / write amplifier 155. The write data is written to the memory cell specified by the row and column addresses. The write data is provided to the data terminals for a time defined by the write latency information WL. The write latency information WL can be programmed in the memory device 100, for example, in the mode register ( Figure 1 (Not shown in the image). The write wait time WL information can be defined based on the clock cycle of the CK clock signal. For example, when associated write data is received, the write wait time information WL can be multiple clock cycles of the CK signal after the memory device 100 receives the write command.

[0025] Power supply potentials VDD and VSS are supplied to the power terminals. These power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 generates various internal potentials VPP, VOD, VARY, VPERI, etc., based on the power supply potentials VDD and VSS. The internal potential VPP can be used in the line decoder 140, the internal potentials VOD and VARY can be used in the sense amplifier included in the memory array 150, and the internal potential VPERI can be used in many other circuit blocks.

[0026] A power supply potential VDDQ is also supplied to the power supply terminals. Power supply potential VDDQ, together with power supply potential VSS, is supplied to the input / output circuit 160. In one embodiment of the invention, the potential of power supply potential VDDQ can be the same as the potential of power supply potential VDD. In another embodiment of the invention, the potential of power supply potential VDDQ can be different from the potential of power supply potential VDD. However, using a dedicated power supply potential VDDQ for the input / output circuit 160 prevents power supply noise generated by the input / output circuit 160 from propagating to other circuit blocks.

[0027] External clock signals and complementary external clock signals are supplied to the clock and data clock terminals. The external clock signals CK, CKF, WCK, and WCKF can be supplied to the clock input circuit 120. The CK and CKF signals are complementary, and the WCK and WCKF signals are also complementary. The complementary clock signals have opposite clock levels and transition between opposite clock levels simultaneously. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Furthermore, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and vice versa.

[0028] An input buffer included in clock input circuit 120 receives an external clock signal. For example, when enabled by the CKE signal from command decoder 115, the input buffer receives CK and CKF signals, as well as WCK and WCKF signals. Clock input circuit 120 can receive an external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK is supplied to internal clock circuit 130. Internal clock circuit 130 provides an internal clock signal with various phase and frequency controls based on the received internal clock signal ICLK and the clock enable signal CKE from command / address input circuit 105. For example, internal clock circuit 130 may include a clock path ( Figure 1 (Not shown in the diagram), the clock path receives the internal clock signal ICLK and provides various clock signals to the command decoder 115. The internal clock circuit 130 further provides input / output (I / O) clock signals. The I / O clock signals are supplied to the input / output circuit 160 and used as timing signals to determine the output timing for reading data and the input timing for writing data. The I / O clock signals can be provided at multiple clock frequencies, allowing data to be output from and input to the memory device 100 at different data rates. Higher clock frequencies may be desirable when high memory speeds are desired. Lower clock frequencies may be desirable when lower power consumption is desired. The internal clock signal ICLK is also supplied to the timing generator 135, and thus various internal clock signals can be generated.

[0029] like Figure 1 Memory devices such as memory device 100 can provide memory capacity having multiple memory arrays or a single array subdivided into multiple individually addressable portions (e.g., subdivided into multiple channels, groups, etc.). Alternatively, the memory system can include multiple memory devices, such as Figure 1The memory device 100, wherein each memory device represents an individually addressable sub-partition (e.g., column, etc.) of the system's memory capacity. Therefore, a memory device or a memory system having multiple memory devices, memory columns, memory channels, memory groups, etc., may include multiple external data clock terminals (e.g., other clock terminals) dedicated to one or more, but fewer than all, individually addressable portions. For example, a multi-channel memory device may include multiple external data clock terminals corresponding to the multiple memory channels. According to embodiments of the invention, in Figure 2a and 2b A simplified schematic diagram illustrates such a memory device.

[0030] For reference Figure 2a and 2b As can be seen, the memory device 200 includes a memory array 210, which is subdivided into a first plurality of memory cells 222 corresponding to a first channel and a second plurality of memory cells 224 corresponding to a second channel. The memory device 200 further includes a first external data clock terminal 232 and a second external data clock terminal 234 corresponding to the first and second channels, respectively. The first and second external data clock terminals have each been shown as a single terminal, but the following description applies to differential clock arrangements, where two terminals are provided for each complementary pair of clock signals (e.g., WCK and WCKF). For clarity, a memory device 200 without many other features of the memory device has been shown, with reference above. Figure 1 The memory device is described in more detail.

[0031] When operating the memory device 200, different external data clock signals can be provided to each of the first external data clock terminal 232 and the second external data clock terminal 234 to facilitate individual interaction with the first and second channels of the memory array 210. However, such an arrangement increases the complexity of the host or memory controller that must provide different external data clock signals. However, providing the same data clock signal WCK to both external data clock terminals 232 and 234 can present challenges in terms of impedance matching. In this regard, to reduce unwanted noise on the data clock path that may be caused by impedance mismatch between the external data clock signal WCK and the memory device 200, the memory device 200 can use on-die termination to change the impedance of each internal data clock path. In this regard, the memory device 200 may include impedance adjustment circuitry (e.g., termination circuitry), such as a first impedance adjustment circuitry 242 connected to the first external data clock terminal 232 and a second impedance adjustment circuitry 244 connected to the second external data clock terminal 234. When a connected host or memory controller accesses the first plurality of memory cells 222 on the first channel, the memory device 200 can utilize the first impedance adjustment circuitry 242 to adjust the impedance at the corresponding data clock terminal 232 to match the impedance of the data clock signal WCK (e.g., adjusting the impedance "seen" at said terminal to 20Ω), and can utilize the second impedance adjustment circuitry 244 to adjust the impedance at another data clock terminal 234 to a sufficiently high value (e.g., ∞Ω or close to ∞Ω) such that it contributes almost nothing to the combined impedance when the two terminals are connected in parallel. Figure 2a As shown.

[0032] refer to Figure 2b The disadvantages of this method of switching on and off the on-die terminals become more apparent, where the host or memory controller subsequently interacts with a second plurality of memory cells 224 on the second channel of array 210. There is a delay before the external data clock signal WCK can propagate to the data clock tree of the memory device 200 connected to the second external terminal 234, during which the memory device 200 reduces the impedance at terminal 234 from a high value (e.g., ∞Ω or near ∞Ω) to an impedance matching the impedance of the applied data clock signal WCK (e.g., "turning off" the on-die terminals by adjusting the impedance "seen" at the terminal to 20Ω), and during this delay, the impedance at the first terminal 232 increases to a high value (e.g., increases to a value of ∞Ω or near ∞Ω). This delay in adjusting impedance can offset the benefits of sharing a common external data clock signal.

[0033] Embodiments of the present invention can solve the above-mentioned problems (etc.) by providing a shared common external clock signal without causing delays in turning on and off the terminals on the die. Go to Figure 3 A simplified block diagram schematically illustrating a memory device 300 according to an embodiment of the present invention is provided. The memory device 300 includes a memory array 310, subdivided into a first plurality of memory cells 322 corresponding to a first channel and a second plurality of memory cells 324 corresponding to a second channel. The memory device 300 further includes a first external data clock terminal 332 and a second external data clock terminal 334 corresponding to the first and second channels, respectively. The first external data clock terminal 332 and the second external data clock terminal 334 have each been shown as a single terminal; however, the following description applies to differential clock arrangements, where two terminals are provided for each complementary pair of clock signals (e.g., WCK and WCKF). The memory device 300 may further include impedance adjustment circuitry systems, such as a first impedance adjustment circuitry system 342 connected to the first external data clock terminal 332 and a second impedance adjustment circuitry system 344 connected to the second external data clock terminal 334. For clarity, a memory device 300 without numerous other features of the memory device has been shown, with reference above. Figure 1 The memory device is described in more detail.

[0034] For reference Figure 3 As can be seen, a common external data clock signal WCK is provided to each of the parallel-connected first terminals 332 and second terminals 334. The memory device 300 is configured (e.g., using the first impedance adjustment circuitry 342 and the second impedance adjustment circuitry 344) to provide an impedance to each of the external clock terminals 332 and 334 that is greater than the impedance of the applied external data clock signal WCK, rather than providing a sufficiently high impedance (e.g., ∞Ω or close to ∞Ω) to one of these terminals to prevent a significant contribution to the combined impedance when the terminals are connected in parallel and to provide an impedance to the other terminal that matches the impedance of the external data clock signal WCK (e.g., Z0Ω or approximately Z0Ω). In this respect, since the external data clock signal is provided to the two parallel-connected terminals 332 and 334, the first impedance adjustment circuitry 342 and the second impedance adjustment circuitry 344 are configured to provide an impedance of 2Z0Ω, twice the impedance of the external data clock signal WCK (Z0Ω), to each corresponding terminal 332 and 334. Therefore, the combined impedance of the two terminals 332 and 334 connected in parallel is approximately equal to the impedance of the external data clock signal WCK (e.g., 2Z0Ω). -1 +(2Z0Ω) -1 ) -1=Z0Ω). The combined impedance of the two terminals 332 and 334 can be described as equal to the impedance of the external data clock signal WCK, because although the value may not be exactly the same, the value can perform the same function or otherwise be effectively equal to the impedance of the external data clock signal WCK or a similar value.

[0035] Using this configuration, data clock signals WCK can be provided simultaneously to two data clock paths of the memory device 300, allowing a connected host or memory controller to sequentially access a first plurality of memory cells 322 or a second plurality of memory cells 324 without experiencing latency caused by die-on termination switching between sequential accesses. Although due to (e.g., when with...) Figure 2a and 2b Compared to the on-die termination switching method shown, the impedance at each external terminal 332 and 334 increases, and the propagation of the data clock signal WCK within each clock tree may be slightly reduced. However, this can be addressed using clock tree optimization, and the benefits of sharing a common data clock signal without experiencing the delay associated with on-die termination may outweigh these design costs.

[0036] According to one aspect of this disclosure, the impedance adjustment circuitry system of a memory device, such as impedance adjustment circuitry systems 342 and 344 of memory device 300, may include an impedance detection circuitry system for detecting (e.g., determining) the impedance of an applied signal. In one aspect of the invention, each impedance adjustment circuitry system may include a separate impedance detection circuitry system, while in another aspect, multiple impedance adjustment circuitry systems may share one (or more) impedance detection circuitry systems. The impedance adjustment circuitry system may further include one or more impedance multipliers and / or impedance dividers, configurable impedance tuners, etc., to provide a controllable impedance (e.g., any value that is an integer multiple of, proportional to, or greater than, the detected impedance) corresponding to the detected impedance of the applied clock signal.

[0037] Although the above example embodiments have demonstrated memory devices with two channels (and two corresponding external data clock terminals), the above method of impedance to external clock signals applied to multiple terminals in parallel is applied to memory devices with more than two external terminals. For example, Figure 4A simplified block diagram of a memory device 400 provided according to an embodiment of the present invention is schematically shown. The memory device 400 includes a memory array 410 subdivided into a first plurality of memory cells to a fourth plurality of memory cells 422, 424, 426, and 428, respectively corresponding to a first channel to a fourth channel. The memory device 400 further includes a first external data clock terminal to a fourth external data clock terminal 432, 434, 436, and 438, also respectively corresponding to the first channel to the fourth channel. The first external data clock terminal to the fourth external data clock terminal 432, 434, 436, and 438 have each been shown as a single terminal; however, the following description applies to differential clock arrangements, wherein two terminals are provided for each complementary pair of clock signals (e.g., WCK and WCKF). The memory device 400 may further include impedance adjustment circuitry systems, such as a first impedance adjustment circuitry system 442 connected to a first external data clock terminal 432, a second impedance adjustment circuitry system 444 connected to a second external data clock terminal 434, a third impedance adjustment circuitry system 446 connected to a third external data clock terminal 436, and a fourth impedance adjustment circuitry system 448 connected to a fourth external data clock terminal 438. For clarity, a memory device 400 without numerous other features has been shown, with reference to the above. Figure 1 The memory device is described in more detail.

[0038] For reference Figure 4As can be seen, a common external data clock signal WCK is provided to each of the parallel external data clock terminals 432, 434, 436, and 438. The memory device 400 is configured to provide an impedance to each of the external clock terminals 432, 434, 436, and 438 that is greater than the impedance of the applied external data clock signal WCK, rather than providing a sufficiently high impedance (e.g., ∞Ω or close to ∞Ω) to three of these terminals to prevent a significant contribution to the combined impedance when the terminals are connected in parallel, and to provide an impedance (e.g., Z0Ω or approximately Z0Ω) to the remaining terminals that matches the impedance of the external data clock signal WCK. In this respect, since the external data clock signal is provided to the four parallel terminals 432, 434, 436, and 438, each of the impedance adjustment circuit systems 342, 344, 346, and 348 is configured to provide an impedance of 4Z0Ω, which is four times the impedance of the external data clock signal WCK, to each corresponding terminal 432, 434, 436, and 438. Therefore, the combined impedance of the four terminals 432, 434, 436, and 438 connected in parallel is approximately equal to the impedance of the external data clock signal WCK (e.g., 4Z0Ω). -1 +(4Z0Ω) -1 +(4Z0Ω) -1 +(4Z0Ω) -1 ) -1 =Z0Ω). Using this configuration, a data clock signal WCK is simultaneously provided to all data clock paths of the memory device 400, allowing a connected host or memory controller to sequentially access any of the first to fourth memory cells 422, 424, 426, or 428 without experiencing delays due to die-on termination switching between sequential accesses. Although due to (e.g., when with...) Figure 2a and 2b Compared to the on-die termination switching method shown, the impedance at each external terminal 432, 434, 436, and 438 increases, and the propagation of the data clock signal WCK within each clock tree may be slightly reduced. However, this can be addressed using clock tree optimization, and the benefits of sharing a common data clock signal without experiencing the delays associated with on-die termination may outweigh these design costs.

[0039] Although the examples above have shown and described memory devices having multiple external data clock terminals with the same impedance, in other embodiments of the invention, the memory device may be configured with multiple external terminals with different impedances, which, when connected in parallel, provide a combined impedance matching the impedance of the applied signal. For example, Figure 5 A simplified block diagram of a memory device 500 provided according to an embodiment of the present invention is schematically shown. The memory device 500 includes a memory array 510, subdivided into a first plurality of memory cells 522 corresponding to a first channel and a second plurality of memory cells 524 corresponding to a second channel. The memory device 500 further includes a first external data clock terminal 532 and a second external data clock terminal 534 corresponding to the first channel and the second channel, respectively. The first external data clock terminal 532 and the second external data clock terminal 534 have each been shown as a single terminal; however, the following description applies to differential clock arrangements, where two terminals are provided for each complementary pair of clock signals (e.g., WCK and WCKF). The memory device 500 may further include impedance adjustment circuitry, such as a first impedance adjustment circuitry 542 connected to the first external data clock terminal 532 and a second impedance adjustment circuitry 544 connected to the second external data clock terminal 534. For clarity, a memory device 500 without numerous other features of the memory device has been shown, with reference above. Figure 1 The memory device is described in more detail.

[0040] For reference Figure 5As can be seen, a common external data clock signal WCK is provided to each of the first terminals 532 and the second terminal 534 connected in parallel. The memory device 500 is configured to provide an impedance greater than the applied external data clock signal WCK to each external clock terminal 532 and 534, and the external clock terminals, when connected in parallel, provide a combined impedance approximately equal to the impedance Z0Ω of the external data clock signal WCK, rather than providing a sufficiently high impedance (e.g., ∞Ω or close to ∞Ω) to one of these terminals to prevent a significant contribution to the combined impedance when the terminals are connected in parallel and to provide an impedance matching the impedance of the external data clock signal WCK to the other terminal (e.g., Z0Ω or approximately Z0Ω). In this regard, the first impedance adjustment circuitry 542 is configured to provide an impedance of 1.5Z0Ω to the first terminal 532, approximately 1.5 times the impedance Z0Ω of the external data clock signal WCK, while the second impedance adjustment circuitry 544 is configured to provide an impedance of 3Z0Ω to the second terminal 534, approximately three times the impedance Z0Ω of the external data clock signal WCK. Therefore, the combined impedance of the two terminals 532 and 534 connected in parallel is approximately equal to the impedance of the external data clock signal WCK (e.g., 1.5Ω). -1 +(3Z0Ω) -1 ) -1 =Z0Ω). Using this configuration, a data clock signal WCK is simultaneously provided to both data clock paths of the memory device 500, allowing a connected host or memory controller to sequentially access either the first plurality of memory cells 522 or the second plurality of memory cells 524 without experiencing delays caused by die-on termination switching between sequential accesses. Although due to (e.g., when with...) Figure 2a and 2b Compared to the on-die termination switching method shown, the anode reactance at each external terminal 532 and 534 is increased, and the propagation of the data clock signal WCK within each clock tree may be slightly reduced. However, this can be addressed using clock tree optimization, and the benefits of sharing a common data clock signal without experiencing the delay associated with on-die termination may outweigh these design costs.

[0041] Alternatively, in another embodiment, the memory device 500 may be configured to, depending on which channel is accessed by the host or memory controller, make... Figure 5The impedance reversal shown (e.g., such that the first terminal 532 is configured to have an impedance of 3Z0Ω, approximately three times the impedance Z0Ω of the external data clock signal WCK, and the second terminal 534 is configured to have an impedance of 1.5Z0Ω, approximately 1.5 times the impedance Z0Ω of the external data clock signal WCK). In this respect, the delay in adjusting the impedance value at the external terminal from 3Z0Ω to 1.5Z0Ω or vice versa can be significantly reduced compared to the delay in adjusting the impedance value at the external terminal from ∞Z0Ω or near ∞Z0Ω to Z0Ω or vice versa.

[0042] In another embodiment, the memory device may have multiple external data clock terminals, some of which have the same impedance value, while others have different values ​​(e.g., in a hybrid of the methods described above). For example, Figure 6 A simplified block diagram of a memory device 600 provided according to an embodiment of the present invention is shown schematically. The memory device 600 includes a memory array 610 subdivided into a first plurality of memory cells to a fourth plurality of memory cells 622, 624, 626, and 628, respectively corresponding to a first channel to a fourth channel. The memory device 600 further includes a first external data clock terminal to a fourth external data clock terminal 632, 634, 636, and 638, also respectively corresponding to the first channel to the fourth channel. The first external data clock terminal to the fourth external data clock terminal 632, 634, 636, and 638 have each been shown as a single terminal; however, the following description applies to differential clock arrangements, wherein two terminals are provided for each complementary pair of clock signals (e.g., WCK and WCKF). The memory device 600 may further include impedance adjustment circuitry systems, such as a first impedance adjustment circuitry system 642 connected to a first external data clock terminal 632, a second impedance adjustment circuitry system 644 connected to a second external data clock terminal 634, a third impedance adjustment circuitry system 646 connected to a third external data clock terminal 636, and a fourth impedance adjustment circuitry system 648 connected to a fourth external data clock terminal 638. For clarity, a memory device 600 without numerous other features has been shown, with reference above. Figure 1 The memory device is described in more detail.

[0043] For reference Figure 6As can be seen, a common external data clock signal WCK is provided to each of the four external data clock terminals 632, 634, 636, and 638 connected in parallel. The memory device 600 is configured such that each external clock terminal 632, 634, 636, and 638 provides an impedance greater than the impedance of the applied external data clock signal WCK, and that the external clock terminals, when connected in parallel, provide a combined impedance approximately equal to the impedance Z0Ω of the external data clock signal WCK, rather than providing sufficiently high impedances (e.g., ∞Ω or close to ∞Ω) to three of these terminals to prevent a significant contribution to the combined impedance when the terminals are connected in parallel, and providing an impedance (e.g., Z0Ω or approximately Z0Ω) to the remaining terminals that matches the impedance of the external data clock signal WCK. In this regard, the first impedance adjustment circuit system 642 and the second impedance adjustment circuit system 644 are configured such that each of the corresponding first terminals 632 and 634 provides an impedance of approximately four times the impedance Z0Ω of the external data clock signal WCK, i.e., 4Z0Ω; the third impedance adjustment circuit system 646 is configured such that the third terminal 636 provides an impedance of approximately three times the impedance Z0Ω of the external data clock signal WCK, i.e., 3Z0Ω; and the fourth impedance adjustment circuit system 648 is configured such that the fourth terminal 638 provides an impedance of approximately six times the impedance Z0Ω of the external data clock signal WCK, i.e., 6Z0Ω. Therefore, the combined impedance when the four terminals 632, 634, 636, and 638 are connected in parallel is approximately equal to the impedance of the external data clock signal WCK (e.g., 4Z0Ω). -1 +(4Z0Ω) -1 +(3Z0Ω) -1 +(6Z0Ω) -1 ) -1 =Z0Ω). Using this configuration, a data clock signal WCK is simultaneously provided to all data clock paths of the memory device 600, allowing a connected host or memory controller to sequentially access any of the first to fourth memory cells 622, 624, 626, or 628 without experiencing delays due to die-on termination switching between sequential accesses. Although due to (e.g., when with...) Figure 2a and 2b Compared to the on-die termination switching method shown, the impedance at each external terminal 632, 634, 636, and 638 increases, and the propagation of the data clock signal WCK within each clock tree may be slightly reduced. However, this can be addressed using clock tree optimization, and the benefits of sharing a common data clock signal without experiencing the delays associated with on-die termination may outweigh these design costs.

[0044] Although in the above examples a single clock signal is shown as multiple parallel terminals connected to a single memory device, in another embodiment of the invention, a memory system with multiple memory devices can share a common clock signal and can be configured with one or more external terminals for each memory device whose impedance is greater than the impedance of the external clock signal, and said one or more external terminals, when connected in parallel, provide a combined impedance approximately equal to the impedance of the external clock signal. For example, Figure 7 A memory system 700 according to an embodiment of the present invention is illustrated schematically. The memory system 700 includes two memory devices 702 and 704, each of which includes memory arrays 712 and 714 having corresponding plurality of memory cells 722 and 724 arranged in a single channel. Each memory device 702 and 704 further includes a single external data clock terminal 732 and 734. The external data clock terminals 732 and 734 have each been shown as a single terminal, but the following description applies to differential clock arrangements, wherein two terminals are provided for each complementary pair of clock signals (e.g., WCK and WCKF). Each memory device 702 and 704 may further include impedance adjustment circuitry, such as a first impedance adjustment circuitry 742 connected to the first external data clock terminal 732 and a second impedance adjustment circuitry 744 connected to the second external data clock terminal 734. For clarity, memory devices 702 and 704 without numerous other features of the memory devices have been shown, as referenced above. Figure 1 The memory device is described in more detail.

[0045] For reference Figure 7As can be seen, a common external data clock signal WCK is provided to each of the terminals 332 and 334 of the parallel memory devices 702 and 704. The memory system 700 is configured such that each memory device 702 and 704 provides an impedance to its external clock terminals 732 and 734 that is greater than the impedance of the applied external data clock signal WCK, rather than providing a sufficiently high impedance (e.g., ∞Ω or close to ∞Ω) to one of these terminals to prevent a significant contribution to the combined impedance when the terminals are connected in parallel, and providing an impedance (e.g., Z0Ω or approximately Z0Ω) to the other terminal that matches the impedance of the external data clock signal WCK. In this respect, since the external data clock signal is provided to the two parallel terminals 732 and 734, each of the first impedance adjustment circuit system 742 and the second impedance adjustment circuit system 744 is configured such that the corresponding terminals 732 and 734 provide an impedance of 2Z0Ω, which is twice the impedance of the external data clock signal WCK (Z0Ω). Therefore, the combined impedance of the two terminals 732 and 734 connected in parallel is approximately equal to the impedance of the external data clock signal WCK (e.g., 2Z0Ω). -1 +(2Z0Ω) -1 ) -1 =Z0Ω). Using this configuration, a data clock signal WCK is simultaneously provided to the data clock path of each of the two memory devices 702 and 704, allowing a connected host or memory controller to sequentially access multiple memory cells 722 or 724 without experiencing latency due to die-on termination switching between sequential accesses. Furthermore, the connected host or memory controller can also be configured to access both memory devices 702 and 704 simultaneously, which is another benefit of various embodiments of the invention. Although due to (e.g., when with...) Figure 2a and 2b Compared to the on-die termination switching method shown, the impedance at each external terminal 732 and 734 increases, and the propagation of the data clock signal WCK within the clock tree of each memory device 702 and 704 may be slightly reduced. However, this can be addressed using clock tree optimization, and the benefits of sharing a common data clock signal without experiencing the delay associated with on-die termination may outweigh these design costs.

[0046] While the examples described above illustrate a memory system with multiple single-channel memory devices sharing a common clock signal, in other embodiments of the invention, the memory system may comprise multiple memory devices, each having multiple channels, all of which share a common clock signal. For example, Figure 8A memory system 800 according to an embodiment of the present invention is illustrated schematically. The memory system 800 includes two memory devices 802 and 804, each of which includes memory arrays 812 and 814. The memory array 812 of the first memory device 802 is subdivided into a first plurality of memory cells 822 corresponding to a first channel and a second plurality of memory cells 823 corresponding to a second channel. The memory array 814 of the second memory device 804 is subdivided into a third plurality of memory cells 824 corresponding to a third channel and a fourth plurality of memory cells 825 corresponding to a fourth channel. The first memory device 802 includes a first external data clock terminal 832 and a second external data clock terminal 833 corresponding to the first and second channels, and the second memory device 804 includes a third external data clock terminal 834 and a fourth external data clock terminal 835 corresponding to the third and fourth channels. The first external data clock terminals to the fourth external data clock terminals 832-835 have each been shown as a single terminal; however, the following description applies to differential clock arrangements, where two terminals are provided for each complementary pair of clock signals (e.g., WCK and WCKF). Each memory device 802 and 804 may further include an impedance adjustment circuit system, such as a first impedance adjustment circuit system 842 connected to a first external data clock terminal 832, a second impedance adjustment circuit system 843 connected to a second external data clock terminal 833, a third impedance adjustment circuit system 844 connected to a third external data clock terminal 834, and a fourth impedance adjustment circuit system 845 connected to a fourth external data clock terminal 835. For clarity, memory devices 802 and 804 without numerous other features of a memory device have been shown, as referenced above. Figure 1 The memory device is described in more detail.

[0047] For reference Figure 8As can be seen, a common external data clock signal WCK is provided to each of the terminals 832-835 of the parallel memory devices 802 and 804. The memory system 800 is configured such that each memory device 802 and 804 provides an impedance to its external clock terminals 832-835 that is greater than the impedance of the applied external data clock signal WCK, rather than providing a sufficiently high impedance (e.g., ∞Ω or close to ∞Ω) to one of these terminals to prevent a significant contribution to the combined impedance when the terminals are connected in parallel, and providing an impedance (e.g., Z0Ω or approximately Z0Ω) to the other remaining terminal that matches the impedance of the external data clock signal WCK. In this respect, since the external data clock signal is provided to the four parallel terminals 832-835, each terminal (e.g., through its corresponding impedance adjustment circuitry 842-845) is configured to have an impedance of 4Z0Ω, which is four times the impedance Z0Ω of the external data clock signal WCK. Therefore, the combined impedance of the four terminals 832-835 connected in parallel is approximately equal to the impedance of the external data clock signal WCK (e.g., 40Ω). -1 +(4Z0Ω) -1 +(4Z0Ω) -1 +(4Z0Ω) -1 ) -1 =Z0Ω). Using this configuration, a data clock signal WCK is simultaneously provided to two data clock paths of each of the two memory devices 802 and 804, allowing a connected host or memory controller to sequentially access multiple memory cells in the memory devices without experiencing latency due to die-on terminal switching between sequential accesses. Furthermore, the connected host or memory controller can also be configured to simultaneously access one of the channels on each memory device 802 and 804, which is another benefit of various embodiments of the invention. Although due to (e.g., when with...) Figure 2a and 2b Compared to the on-die termination switching method shown, the impedance at each external terminal 832-835 increases, and the propagation of the data clock signal WCK within the clock tree of each memory device 802 and 804 may be slightly reduced. However, this can be addressed using clock tree optimization, and the benefits of sharing a common data clock signal without experiencing the delay associated with on-die termination may outweigh these design costs.

[0048] Despite Figure 7 and 8In the examples described above, a memory system having a memory device (having a plurality of external data clock terminals with the same impedance) has been shown and described. However, in other embodiments of the invention, the memory system may include a memory device configured with a plurality of external terminals having different impedances, which, when connected in parallel, provide a combined impedance matching the impedance of the applied signal. For example, Figure 9 A simplified block diagram of a memory system 900 provided according to an embodiment of the present invention is schematically shown. The memory system 900 includes two memory devices 902 and 904, each of which includes memory arrays 912 and 914. The memory array 912 of the first memory device 902 is subdivided into a first plurality of memory cells 922 corresponding to a first channel and a second plurality of memory cells 923 corresponding to a second channel. The memory array 914 of the second memory device 904 is subdivided into a third plurality of memory cells 924 corresponding to a third channel and a fourth plurality of memory cells 925 corresponding to a fourth channel. The first memory device 902 includes a first external data clock terminal 932 and a second external data clock terminal 933 corresponding to the first and second channels, and the second memory device 904 includes a third external data clock terminal 934 and a fourth external data clock terminal 935 corresponding to the third and fourth channels. The first external data clock terminals to the fourth external data clock terminals 932-935 have each been shown as a single terminal; however, the following description applies to differential clock arrangements where two terminals are provided for each complementary pair of clock signals (e.g., WCK and WCKF). Each memory device 902 and 904 may further include impedance adjustment circuitry systems such as a first impedance adjustment circuitry system 942 connected to the first external data clock terminal 932, a second impedance adjustment circuitry system 943 connected to the second external data clock terminal 933, a third impedance adjustment circuitry system 944 connected to the third external data clock terminal 934, and a fourth impedance adjustment circuitry system 945 connected to the fourth external data clock terminal 935. For clarity, memory devices 902 and 904 without numerous other features of a memory device have been shown, as referenced above. Figure 1 The memory device is described in more detail.

[0049] For reference Figure 9As can be seen, a common external data clock signal WCK is provided to each of the terminals 932-935 of the parallel memory devices 902 and 904. The memory system 900 is configured such that each memory device 902 and 904 (e.g., using its corresponding impedance adjustment circuitry 942-945) provides an impedance to the external clock terminals 932-935 of each memory device that is greater than the impedance of the applied external data clock signal WCK, rather than providing a sufficiently high impedance (e.g., ∞Ω or close to ∞Ω) to one of these terminals to prevent a significant contribution to the combined impedance when the terminals are connected in parallel, and providing an impedance (e.g., Z0Ω or approximately Z0Ω) to the other remaining terminal that matches the impedance of the external data clock signal WCK. In this respect, the first terminal 932 and the second terminal 933 are each configured to have an impedance of 3Z0Ω, which is three times the impedance Z0Ω of the external data clock signal WCK, and the third terminal 934 and the fourth terminal 935 are each configured to have an impedance of 6Z0Ω, which is six times the impedance Z0Ω of the external data clock signal WCK. Therefore, the combined impedance of the four terminals 932-935 connected in parallel is approximately equal to the impedance of the external data clock signal WCK (e.g., 3Z0Ω). -1 +(3Z0Ω) -1 +(6Z0Ω) -1 +(6Z0Ω) -1 ) -1 =Z0Ω). Using this configuration, a data clock signal WCK is simultaneously provided to both data clock paths of each of the two memory devices 902 and 904, allowing a connected host or memory controller to sequentially access multiple memory cells in the memory devices without experiencing latency due to die-on terminal switching between sequential accesses. Furthermore, the connected host or memory controller can also be configured to simultaneously access one of the channels on each memory device 902 and 904, which is another benefit of various embodiments of the invention. Although due to (e.g., when with...) Figure 2a and 2b Compared to the on-die termination switching method shown, the impedance at each external terminal 932-935 increases, and the propagation of the data clock signal WCK within the clock tree of each memory device 902 and 904 may be slightly reduced. However, this can be addressed using clock tree optimization, and the benefits of sharing a common data clock signal without experiencing the delay associated with on-die termination may outweigh these design costs.

[0050] Despite Figure 7-9In the examples described above, the memory system has been depicted and shown as sharing a single common clock signal. However, in other embodiments of the invention, the memory system may comprise multiple memory devices, each with multiple clock signals shared with more than one but fewer external clock terminals of the memory system. For example, Figure 10 A memory system 1000 according to an embodiment of the present invention is illustrated schematically. The memory system 1000 includes two memory devices 1002 and 1004, each of which includes memory arrays 1012 and 1014. The memory array 1012 of the first memory device 1002 is subdivided into a first plurality of memory cells 1022 corresponding to a first channel and a second plurality of memory cells 1023 corresponding to a second channel. The memory array 1014 of the second memory device 1004 is subdivided into a third plurality of memory cells 1024 corresponding to a third channel and a fourth plurality of memory cells 1025 corresponding to a fourth channel. The first memory device 1002 includes a first external data clock terminal 1032 and a second external data clock terminal 1033 corresponding to the first and second channels, and the second memory device 1004 includes a third external data clock terminal 1034 and a fourth external data clock terminal 1035 corresponding to the third and fourth channels. The first external data clock terminals to the fourth external data clock terminals 1032-1035 have each been shown as a single terminal; however, the following description applies to differential clock arrangements where two terminals are provided for each complementary pair of clock signals (e.g., WCK and WCKF). Each memory device 1002 and 1004 may further include impedance adjustment circuitry systems such as a first impedance adjustment circuitry system 1042 connected to the first external data clock terminal 1032, a second impedance adjustment circuitry system 1043 connected to the second external data clock terminal 1033, a third impedance adjustment circuitry system 1044 connected to the third external data clock terminal 1034, and a fourth impedance adjustment circuitry system 1045 connected to the fourth external data clock terminal 1035. For clarity, memory devices 1002 and 1004 without numerous other features of a memory device have been shown, as referenced above. Figure 1 The memory device is described in more detail.

[0051] For reference Figure 10As can be seen, a first external data clock signal WCK0 is provided to the first terminal 1032 of the first memory device 1002 and the third terminal 1034 of the second memory device 1004, and a second external data clock signal WCK1 is provided to the second terminal 1033 of the first memory device 1002 and the fifth terminal 1035 of the second memory device 1004. The memory system 1000 is configured such that each memory device 1002 and 1004 provides an impedance to its external clock terminals 1032-1035 that is greater than the impedance of the corresponding applied external data clock signals WCK0 and WCK1, rather than providing a sufficiently high impedance (e.g., ∞Ω or close to ∞Ω) to one terminal of each pair of common-connected terminals to prevent a significant contribution to the combined impedance when the terminals are connected in parallel, and providing an impedance (e.g., Z0Ω or approximately Z0Ω) to the other terminal that matches the impedance of the corresponding external data clock signal WCK0 or WCK1. In this respect, each terminal (e.g., via its corresponding impedance adjustment circuitry 1042-1045) is configured to have an impedance of 2Z0Ω, which is twice the impedance of its corresponding external data clock signal WCK0 or WCK1 (Z0Ω). Therefore, the combined impedance when each pair of terminals for common connection is connected in parallel is approximately equal to the impedance of the external data clock signal WCK (e.g., 2Z0Ω). -1 +(2Z0Ω) -1 ) -1 =Z0Ω).

[0052] Figure 11 This is a flowchart illustrating a method of operating a memory device according to an embodiment of the present invention. The method includes receiving clock signals having clock impedances at a first clock terminal corresponding to a first channel of the memory device and at a second clock terminal corresponding to a second channel of the memory device (block 1110). For example, in one embodiment of the present invention, the features of block 1110 may be performed by a CLK input circuit 120 and / or various terminals connected thereto. The method may further include detecting clock impedances at one or more of the first and second clock terminals (block 1120), and adjusting the first impedance at the first clock terminal and the second impedance at the second clock terminal to provide a combined impedance approximately equal to the clock impedance (block 1130). For example, in one embodiment of the present invention, the features of blocks 1120 and 1130 may be performed by the CLK input circuit 120. According to one aspect of the present invention, both the first impedance and the second impedance may be greater than the clock impedance. According to another aspect of the present invention, the first impedance and the second impedance may be approximately equal or may be different.

[0053] Figure 12This is a flowchart illustrating a method of operating a memory system having a first memory device and a second memory device according to an embodiment of the present invention. The method includes receiving a clock signal having a clock impedance at a first clock terminal of the first memory device and a second clock terminal of the second memory device (block 1210). For example, in one embodiment of the present invention, the feature of block 1210 may be performed by a plurality of CLK input circuits 120 of a plurality of memory devices 100 and / or various terminals connected thereto. The method may further include detecting the clock impedance at the first clock terminal and the second clock terminal (block 1220) and adjusting the first impedance at the first clock terminal and the second impedance at the second clock terminal to provide a combined impedance approximately equal to the clock impedance (block 1230). For example, in one embodiment of the present invention, the features of blocks 1220 and 1230 may be performed by a plurality of CLK input circuits 120 of a plurality of memory devices 100. According to one aspect of the present invention, both the first impedance and the second impedance may be greater than the clock impedance. According to another aspect of the present invention, the first impedance and the second impedance may be approximately equal or may be different.

[0054] Figure 13 This is a flowchart illustrating a method for operating a memory device according to an embodiment of the present invention. The method includes detecting a first impedance (block 1310) of a clock signal applied to the memory device and adjusting a second impedance of the memory device to be greater than the first impedance (block 1320). According to one aspect of the present invention, the second impedance may be an integer multiple of the first impedance, wherein the integer multiple is two or greater.

[0055] It should be noted that the methods described above describe possible implementations and can be rearranged or otherwise modified in operation and steps, and other implementations are possible. Furthermore, embodiments of two or more methods described may be combined.

[0056] The information and signals described herein can be represented using any of a variety of different processes and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof. Some figures may show signals as single signals; however, those skilled in the art will understand that signals can represent signal buses, where buses can have various bit widths.

[0057] The devices containing memory devices discussed herein can be formed on semiconductor substrates or dies such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping using a variety of chemicals (including, but not limited to, phosphorus, boron, or arsenic). Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0058] The functionality described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of this disclosure and the appended claims. Features implementing the functionality can also be physically located at various locations, including distributions such that portions of the functionality are implemented at different physical locations.

[0059] As used herein (including in the claims), "or" as used in a list of items (e.g., a list of items ending with phrases such as "at least one of..." or "one or more of...") indicates an inclusive list, such that at least one of, for example, lists A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0060] Based on the foregoing, it should be understood that specific embodiments of the invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the invention. Rather, numerous specific details have been discussed in the preceding description to provide a thorough and enabling description of embodiments of the invention. However, those skilled in the art will recognize that this disclosure may be practiced without one or more of these specific details. In other instances, well-known structures or operations typically associated with memory systems and devices have not been shown or described in detail to avoid obscuring other aspects of the invention. Generally, it should be understood that various other devices, systems, and methods, besides the specific embodiments disclosed herein, may also fall within the scope of the invention.

Claims

1. A memory device comprising: Multiple impedance adjustment circuit systems, each configured to provide a corresponding impedance to a received clock signal having a clock impedance; The respective impedances of the plurality of impedance adjustment circuit systems provide a combined impedance based on the clock impedance during a read operation involving a memory cell corresponding to one of the plurality of impedance adjustment circuit systems, and The respective impedance of each of the plurality of impedance adjustment circuit systems is an integer multiple of the clock impedance.

2. The memory device according to claim 1, wherein the clock signal is a differential clock signal.

3. The memory device according to claim 1, wherein the clock signal includes a data clock signal WCK.

4. The memory device according to claim 3, further comprising: Multiple terminals, each of which is coupled to a corresponding one of the multiple impedance adjustment circuit systems and configured to receive the data clock signal WCK.

5. The memory device of claim 1, wherein when the plurality of impedance adjustment circuit systems are connected to the received clock signal and are connected in parallel with each other, the combined impedance is equal to the clock impedance.

6. The memory device of claim 1, wherein each of the plurality of impedance adjustment circuit systems includes an impedance detection circuit configured to detect the clock impedance.

7. The memory device of claim 1, wherein each of the plurality of impedance adjustment circuit systems includes an impedance multiplier circuit system configured to generate the respective impedance as a multiple of the clock impedance.

8. The memory device of claim 1, wherein a single semiconductor die includes the plurality of impedance adjustment circuit systems.

9. The memory device of claim 1, wherein the first semiconductor die includes a first of the plurality of impedance adjustment circuit systems, and the second semiconductor die includes a second of the plurality of impedance adjustment circuit systems.

10. The memory device of claim 1, wherein the respective impedances of the plurality of impedance adjustment circuit systems are equal.

11. The memory device of claim 1, wherein the corresponding impedance of the first of the plurality of impedance adjustment circuit systems is different from the corresponding impedance of the second of the plurality of impedance adjustment circuit systems.

12. The memory device of claim 1, wherein the memory device is a dynamic random access memory (DRAM) device.

13. A method comprising: A clock signal with clock impedance is received at the first memory device; The clock signal having the clock impedance is received at the second memory device; as well as During a read operation involving a memory cell corresponding to the first memory device, a first impedance at the first memory device and a second impedance at the second memory device are adjusted to provide a combined impedance at least partially based on the clock impedance. Each of the first impedance and the second impedance is an integer multiple of the clock impedance.

14. The method of claim 13, wherein the clock signal is a differential clock signal.

15. The method of claim 13, wherein the clock signal includes a data clock signal WCK.

16. The method of claim 15, wherein: Receiving the clock signal at the first memory device includes receiving a data clock signal WCK at a first terminal of the first memory device; as well as Receiving the clock signal at the second memory device includes receiving the data clock signal WCK at a second terminal of the second memory device.

17. The method of claim 13, further comprising: The clock impedance at the first memory device and at the second memory device is detected.

18. The method of claim 13, wherein the first impedance is equal to the second impedance.

19. The method of claim 13, wherein the first impedance is different from the second impedance.

20. A memory device comprising: A first impedance adjustment circuit system is configured to provide a first impedance to a received clock signal having a clock impedance. as well as A second impedance adjustment circuit system is configured to provide a second impedance to the received clock signal; The first impedance adjustment circuit system includes an impedance detection circuit system configured to detect the clock impedance, and The first impedance and the second impedance are configured to provide a combined impedance that is at least partially based on the detected clock impedance.

21. The memory device of claim 20, wherein when the first impedance adjustment circuit system and the second impedance adjustment circuit system are connected to the received clock signal and are connected in parallel with each other, the combined impedance is equal to the clock impedance.

22. The memory device of claim 20, wherein both the first impedance and the second impedance are greater than the clock impedance.

23. The memory device of claim 20, wherein the first impedance adjustment circuit system and the second impedance adjustment circuit system comprise an impedance multiplier circuit system configured to generate the first impedance as a multiple of the clock impedance.

24. The memory device of claim 20, wherein the first impedance is equal to the second impedance.

25. The memory device of claim 20, wherein the received clock signal is a data clock signal.

26. The memory device of claim 20, further comprising: A first terminal is coupled to the first impedance adjustment circuit system and is configured to receive the clock signal; as well as The second terminal is coupled to the second impedance adjustment circuit system and is configured to receive the clock signal.

27. The memory device of claim 20, wherein the received clock signal is a differential clock signal, the differential clock signal comprising a first clock signal and a complementary second clock signal.

28. The memory device of claim 20, wherein a single semiconductor die includes the first impedance adjustment circuit system and the second impedance adjustment circuit system.

29. The memory device of claim 20, wherein the first semiconductor die includes the first impedance adjustment circuit system, and the second semiconductor die includes the second impedance adjustment circuit system.

30. The memory device of claim 20, wherein the memory device is a dynamic random access memory (DRAM) device.

31. A memory system comprising: A first memory device, the first memory device including a first impedance adjustment circuit system configured to provide a first impedance to a received clock signal having a clock impedance. as well as A second memory device, the second memory device including a second impedance adjustment circuit system configured to provide a second impedance to the received clock signal; The first impedance adjustment circuit system includes an impedance detection circuit system configured to detect the clock impedance, and When the first impedance adjustment circuit system and the second impedance adjustment circuit system are connected in parallel to the received clock signal, the first impedance and the second impedance are configured to provide a combined impedance equal to the detected clock impedance.

32. The memory system of claim 31, wherein both the first impedance and the second impedance are greater than the clock impedance.

33. The memory system of claim 31, wherein the first impedance adjustment circuit system and the second impedance adjustment circuit system comprise an impedance multiplier circuit system configured to generate the first impedance as a multiple of the clock impedance.

34. The memory system of claim 31, wherein the first impedance is equal to the second impedance.

35. The memory system of claim 31, wherein the received clock signal is a data clock signal.

36. The memory system according to claim 31, wherein: The first memory device further includes a third impedance adjustment circuit system configured to provide a third impedance to the received clock signal; The second memory device further includes a fourth impedance adjustment circuit system configured to provide a fourth impedance to the received clock signal; and When the first impedance adjustment circuit system, the second impedance adjustment circuit system, the third impedance adjustment circuit system, and the fourth impedance adjustment circuit system are connected in parallel to the received clock signal, the first impedance, the second impedance, the third impedance, and the fourth impedance are configured to provide the combined impedance equal to the clock impedance.

37. The memory system of claim 36, wherein the first impedance, the second impedance, the third impedance, and the fourth impedance are each equal to one another.

38. The memory system of claim 36, wherein at least one of the first impedance, the second impedance, the third impedance, or the fourth impedance is different from at least one of the first impedance, the second impedance, the third impedance, or the fourth impedance.

39. A method comprising: A clock signal with clock impedance is received at the first clock terminal of the first memory device; The clock signal having the clock impedance is received at the second clock terminal of the second memory device; The clock impedance is detected at the first clock terminal; as well as The first impedance at the first clock terminal and the second impedance at the second clock terminal are adjusted to provide a combined impedance based at least in part on the detected clock impedance.

40. The method of claim 39, wherein both the first impedance and the second impedance are greater than the clock impedance.

41. The method of claim 39, wherein the first impedance is equal to the second impedance.

42. The method of claim 39, wherein the received clock signal is a data clock signal.

43. The method of claim 39, wherein the received clock signal is a differential clock signal, the differential clock signal comprising a first clock signal and a complementary second clock signal.

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