High dynamic range CMOS image sensor pixels

Abstract

The present application relates to a high dynamic range CMOS image sensor pixel having a reverse-biased metal-insulator-metal lateral overflow integrator capacitor (LOFIC) for reducing image streak. A pixel circuit includes a transfer transistor coupled between a photodiode and a floating diffusion to transfer image charge from the photodiode to the floating diffusion. The LOFIC includes an insulating region between a first metal electrode and a second metal electrode, the second metal electrode coupled to a first reset transistor and selectively coupled to the floating diffusion. A second reset transistor and a bias voltage source are coupled to the first metal electrode. During an idle period, the first reset transistor is configured to turn on, the second reset transistor is configured to turn off, and the bias voltage source is configured to provide a first bias voltage to the first metal electrode to reverse bias the LOFIC. The first bias voltage is less than a reset voltage provided by the reset voltage source.

Description

Technical Field

[0001] The present disclosure relates generally to image sensors, and particularly, but not exclusively, to high dynamic range (HDR) complementary metal oxide semiconductor (CMOS) image sensors. Background Art

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cell phones, surveillance cameras, as well as in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, there is a desire to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range, etc.) through both device architecture design and image acquisition processing. The technology used to manufacture image sensors has continued to advance rapidly. For example, the demand for higher resolution and lower power consumption has driven the further miniaturization and integration of these devices.

[0003] A typical complementary metal-oxide semiconductor (CMOS) image sensor operates in response to image light from an external scene incident on the image sensor. The image sensor includes an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and, upon absorbing the image light, photogenerate image charge. The image charge photogenerated by the pixels can be measured as an analog output image signal on a column bit line that varies with the incident image light. In other words, the amount of photogenerated image charge is proportional to the intensity of the image light. This charge is read out as an analog signal from the column bit line and converted into a digital value to produce a digital image representing the external scene (i.e., image data).

[0004] Standard image sensors have a limited dynamic range of approximately 60 to 70 dB. However, the real-world dynamic range of brightness is much greater. For example, natural scenes often span a range of 90 dB and greater. To simultaneously capture details in bright highlights and dim shadows, high dynamic range (HDR) technology has been used in image sensors to increase the captured dynamic range. A common technique for increasing dynamic range is to combine multiple exposures captured using a standard (low dynamic range) image sensor at different exposure settings into a single linear HDR image, which produces an image with a much larger dynamic range than a single exposure image. Summary of the Invention

[0005] In one aspect, the present application provides a pixel circuit comprising: a photodiode configured to photogenerate image charge in response to incident light; a floating diffusion coupled to receive the image charge from the photodiode; a transfer transistor coupled between the photodiode and the floating diffusion to transfer the image charge from the photodiode to the floating diffusion; a first reset transistor coupled between a reset voltage source and the floating diffusion, wherein the first reset transistor is configured to switch in response to a first reset control signal; a lateral overflow integrator capacitor (LOFIC) comprising an insulating region disposed between a first metal electrode and a second metal electrode, The second metal electrode is coupled to the first reset transistor and selectively coupled to the floating diffusion; a second reset transistor coupled between the reset voltage source and the first metal electrode, wherein the second reset transistor is configured to switch in response to a second reset control signal; and a bias voltage source coupled to the first metal electrode, wherein during an idle period, the first reset transistor is configured to be turned on, the second reset transistor is configured to be turned off, and the bias voltage source is configured to provide a first bias voltage to the first metal electrode to reverse bias the LOFIC, wherein the first bias voltage is less than the reset voltage provided from the reset voltage source.

[0006] In another aspect, the present application provides an imaging system comprising: a pixel array including a plurality of pixel circuits arranged in a plurality of rows and a plurality of columns, wherein each of the pixel circuits includes: a photodiode configured to photogenerate image charge in response to incident light; a floating diffusion coupled to receive the image charge from the photodiode; a first reset transistor coupled between a reset voltage source and the floating diffusion, wherein the first reset transistor is configured to switch in response to a first reset control signal; a lateral overflow integrator capacitor (LOFIC) including an insulating region disposed between a first metal electrode and a second metal electrode, wherein the second metal electrode is coupled to the first reset transistor and selectively coupled to the floating diffusion; a second reset transistor coupled between the reset voltage source and the first metal electrode, wherein the second reset transistor is configured to switch in response to a second reset control signal; and a bias voltage source coupled to the first metal electrode, wherein during an idle period, the first reset transistor is configured to be turned on, the second reset transistor is configured to be turned off, and the bias voltage source is configured to provide a first bias voltage to the first metal electrode to reverse bias the LOFIC, wherein the first bias voltage is less than the reset voltage provided from the reset voltage source; a control circuit system coupled to the pixel array to control the operation of the pixel array; and a readout circuit system coupled to the pixel array to read out image data from a plurality of pixel cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0008] Figure 1 One example of an imaging system including a pixel array according to the teachings of the present invention is described.

[0009] Figure 2A A schematic diagram illustrating one example of a pixel circuit including a lateral overflow integration capacitor (LOFIC) during an idle period in accordance with the teachings of the present disclosure.

[0010] Figure 2B A schematic diagram illustrating one example of a pixel circuit including a LOFIC during a pre-charge cycle according to the teachings of the present disclosure.

[0011] Figure 3 One example of a timing diagram illustrating example signal values in an example pixel circuit including a LOFIC during idle, precharge, integration, and readout periods according to the teachings of the present disclosure.

[0012] Throughout the several views of the drawings, corresponding reference symbols indicate corresponding components. Those skilled in the art will appreciate that the elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to help improve understanding of the various embodiments of the present invention. Additionally, to facilitate a more intuitive understanding of these various embodiments of the present invention, common but well-understood elements that are useful or necessary in commercially viable embodiments are generally not depicted. DETAILED DESCRIPTION

[0013] This document describes an imaging system having a pixel array including pixel circuitry with LOFIC that provides reduced image streaking. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. However, one skilled in the relevant art will recognize that the techniques described herein can be practiced without one or more of these specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0014] Reference throughout this specification to "one example" or "one embodiment" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Thus, the appearances of the phrases "in one example" or "in one embodiment" in multiple places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.

[0015] For ease of description, spatially relative terms (e.g., "below," "beneath," "above," "down," "above," "up," "top," "bottom," "left," "right," "center," "middle," and the like) may be used herein to describe the relationship of one element or feature relative to another element or feature, as illustrated in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation depicted in the figures. For example, if the device in the figures is rotated or flipped, an element described as being "below," "beneath," or "beneath" another element or feature would be oriented "above" the other element or feature. Thus, the exemplary terms "below" and "beneath" can encompass both above and below orientations. The device can be oriented in other ways (rotated ninety degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. Additionally, it should be understood that when an element is referred to as being "between" two other elements, it can be the only element between the two other elements, or one or more intervening elements may also be present.

[0016] Throughout this specification, several terms from the art are used. These terms have their ordinary meanings in the art, unless specifically defined herein or the context of their use clearly indicates otherwise. It should be noted that throughout this document, element names and symbols are used interchangeably (e.g., Si versus silicon); however, both have the same meaning.

[0017] As will be discussed, various examples of imaging systems include a pixel array having a pixel circuit that includes a lateral overflow integration capacitor (LOFIC) configured to provide reduced image streak. It will be appreciated that the LOFIC can be included in the pixel circuit to increase the full well capacity of the pixel circuit and thereby improve the high dynamic range capability of the corresponding image sensor. The LOFIC capacitance is positively correlated with the full well capacity. Therefore, as the capacitance of the LOFIC used in the pixel circuit increases, the full well capacity of the pixel circuit also increases. In view of this, a higher LOFIC capacitance is generally desired. However, due to the significant RC load as the capacitance of the LOFIC increases, the time required for the row driver of the imaging system to charge and / or reset the LOFIC also increases. Therefore, as the capacitance of the LOFIC in the pixel circuit increases, the image streak also increases, which results in a slower frame rate.

[0018] It should be understood that image streaking caused by LOFIC may be associated with insulating materials having high dielectric constants, or high-k materials included in the insulating materials of metal-insulator-metal (MIM) LOFICs, due to the hysteresis properties and slow relaxation behavior of high-k materials, which require long discharge times (e.g., at least one hundred milliseconds), while the frame duration for a typical frame rate of 30 frames per second is approximately 33 milliseconds. The relaxation behavior of high-k materials can cause image quality degradation, for example, due to image streaking due to a number of mechanisms, including well-to-well tunneling, structural relaxation, coupling to phonon energy, etc.

[0019] At a fixed readout speed and frame readout speed of the image sensor, according to the teachings of the present invention, it should be understood that the LOFIC included in the pixel circuit can be reset during the idle period as well as the precharge period and reset level signal readout operation to reduce image tailing. As will be shown in various examples described herein, the LOFIC included in the pixel circuit is reverse biased during the idle period, which compensates or cancels the residual charge in the LOFIC to further reduce the LOFIC discharge time and thus reduce image tailing. In various examples, the LOFIC is also discharged as needed during the precharge period and the LOFIC reset operation during the readout period. By forcing the LOFIC to automatically return to zero during the precharge period and the reset level signal readout period, the LOFIC can be used as a common metal line with low parasitic capacitance. As a result, the row driver control line coupled to the LOFIC can be reset without encountering a large RC load, which can reduce horizontal stripe noise (H-noise).

[0020] Thus, as will be shown in various examples below, an example pixel circuit includes a photodiode configured to photogenerate image charge during an integration period in response to incident light. A floating diffusion is coupled to receive image charge from the photodiode during a readout period. A first reset transistor is coupled between a reset voltage source and the floating diffusion. The first reset transistor is configured to switch in response to a first reset control signal. A second metal electrode of a LOFIC is coupled to the first reset transistor and selectively coupled to the floating diffusion and a second reset transistor coupled between the reset voltage source and the first metal electrode of the LOFIC. The second reset transistor is configured to switch in response to a second reset control signal. A bias voltage source is coupled to the first metal electrode. During an idle period, the first reset transistor is configured to turn on, the second reset transistor is configured to turn off, and the bias voltage source is configured to provide a first bias voltage to the first metal electrode to reverse bias the LOFIC. The first bias voltage is less than a reset voltage provided by the reset voltage source.

[0021] To illustrate, Figure 1 One example of an imaging system 100 having a pixel array with pixel circuitry including LOFIC that provides reduced image streaking in accordance with the teachings of the present invention is shown. In particular, Figure 1 1 illustrates an imaging system 100 including a pixel array 102, bit lines 112, control circuitry 110, readout circuitry 106, and function logic 108. In one example, pixel array 102 is a two-dimensional (2D) array including a plurality of pixel circuits 104 (e.g., P1, P2, . . . , Pn) arranged in rows (e.g., R1 through Ry) and columns (e.g., C1 through Cx) to acquire image data of a person, place, object, etc., which can then be used to present an image of the person, place, object, etc.

[0022] In various examples, each pixel circuit 104 may include one or more photodiodes configured to photogenerate image charge in response to incident light. The image charge generated in the one or more photodiodes is transferred to a floating diffusion included in each pixel circuit 104, where it can be converted into an image signal, which is then read out from each pixel circuit 104 via column bit lines 112 by readout circuitry 106. As will be discussed, in various examples, pixel circuits 104 are also configured to provide HDR image signals, in which case the image charge generated by the one or more photodiodes under bright lighting conditions may also be transferred to a LOFIC and / or an additional floating diffusion in each pixel circuit 104 to store the image charge. For example, each pixel circuit 104 may include a LOIFC configured to store overflow image charge received from the coupled one or more photodiodes. As will be shown in various examples, in accordance with the teachings of the present invention, the LOFIC is reverse biased during idle periods, which compensates or cancels out residual charge in the LOFIC to further reduce the discharge time of the LOFIC, thereby reducing image streaking. In various examples, readout circuitry 106 can be configured to read out image signals via column bit lines 112. In various examples, readout circuitry 106 can include current sources, routing circuitry, and comparators, which can be included in analog-to-digital converters or otherwise.

[0023] In an example, the digital image data values produced by the analog-to-digital converter in readout circuitry 106 may then be received by function logic 108. Function logic 108 may simply store the digital image data or even manipulate the digital image data by applying post-image effects (e.g., cropping, rotating, removing red eye, adjusting brightness, adjusting contrast, or otherwise).

[0024] In one example, control circuitry 110 is coupled to pixel array 102 to control the operation of a plurality of photodiodes in pixel array 102. For example, control circuitry 110 may generate a rolling shutter or shutter signal for controlling image acquisition. In other examples, image acquisition is synchronized with a lighting effect, such as a flash.

[0025] In one example, imaging system 100 is implemented on a single semiconductor wafer. In another example, imaging system 100 is on stacked semiconductor wafers. For example, pixel array 102 is implemented on a pixel wafer, and readout circuitry 106, control circuitry 110, and function logic 108 are implemented on an application-specific integrated circuit (ASIC) wafer, wherein the pixel wafer and the ASIC wafer are stacked and interconnected by bonding (hybrid bonding, oxide bonding, or the like) or one or more through-substrate vias (TSVs). As another example, pixel array 102 and control circuitry 110 are implemented on a pixel wafer, and readout circuitry 106 and function logic 108 are implemented on an ASIC wafer, wherein the pixel wafer and the ASIC wafer are stacked and interconnected by bonding (hybrid bonding, oxide bonding, or the like) or one or more through-substrate vias (TSVs).

[0026] In one example, the imaging system 100 may be included in a digital cell phone, a laptop computer, an endoscope, a surveillance camera, an imaging device in an automobile, or the like. Additionally, the imaging system 100 may be coupled to other hardware, such as a processor (general purpose or otherwise), memory elements, outputs (USB ports, wireless transmitters, HDMI ports, etc.), lighting / flashlights, electrical inputs (keyboards, touch displays, trackpads, mice, microphones, etc.), and / or displays. The other hardware may deliver instructions to the imaging system 100, extract image data from the imaging system 100, or manipulate the image data supplied by the imaging system 100.

[0027] Figure 2A Schematic diagram illustrating one example of a pixel circuit 204 including a LOFIC during an idle period according to the teachings of the present disclosure. It should be understood that Figure 2A The pixel circuit 204 may be as follows Figure 1 An example of one of the pixel circuits 104 included in the pixel array 102 is shown in FIG. 1 , and similarly named and numbered elements described above are similarly coupled and function below.

[0028] As shown in the depicted example, pixel circuit 204 includes a photodiode 214 configured to photogenerate image charge in response to incident light. In the depicted example, pixel circuit 204 also includes a first floating diffusion FD1 218 coupled to receive image charge from photodiode 214 through transfer transistor 216. In the example, transfer transistor 216 is coupled to be controlled in response to transfer control signal TX 236 to transfer image charge from photodiode 214 to first floating diffusion FD1 218, such as during a readout cycle associated with pixel circuit 204. Figure 2A, it should be noted that during idle periods, excess image charge photogenerated in response to bright lighting conditions is also configured to overflow from photodiode 214 to first floating diffusion FD1 218 through transfer transistor 216. Source follower transistor 220 has a gate coupled to first floating diffusion FD1 218, and row select transistor 222 is coupled to source follower transistor SF 220, such that source follower transistor SF 220 and row select transistor 222 are coupled between a power line and bit line 212 to output an image signal from pixel circuit 204 in response to row select control signal RS 246 and the amount of charge at the gate of source follower transistor SF 220.

[0029] exist Figure 2A In the example illustrated in FIG, a dual floating diffusion DFD transistor 224 is coupled between a first floating diffusion FD1 218 and a second capacitor 228. The second capacitor 228 is further coupled to receive a floating diffusion capacitor signal FDC 240. In one example, the second capacitor 228 may be a junction capacitor combined with a metal capacitor or a metal oxide semiconductor capacitor (MOSCAP) for additional charge storage and joined at a node between the second capacitor 228 and the drain of the dual floating diffusion DFD transistor 224 (which may also be referred to as the second floating diffusion FD2). The second capacitor 228 is coupled to receive excess image charge overflow from the photodiode 214 via the transfer transistor 216 and the dual floating diffusion DFD transistor 224. A low conversion gain transistor 230 is coupled between the second capacitor 228 and a reset transistor 234. The first reset transistor 234 is coupled between a reset voltage source (e.g., PIXVDD) and the low conversion gain transistor 230. First reset transistor 234 is coupled to be controlled in response to reset control signal RSTG 244 , and low switching gain transistor 230 is coupled to be controlled in response to low switching control signal LFG 242 .

[0030] like Figure 2A, a lateral overflow integrator capacitor (LOFIC) 232 is also coupled between the second reset transistor 250 and the first reset transistor 234. In this example, the second reset transistor 250 is coupled between a reset voltage source (e.g., PIXVDD) and the LOFIC 232 and is controlled in response to a second reset control signal RST2 252. The LOFIC 232 is coupled to receive excess image charge overflow from the photodiode 214 via the transfer transistor 216, the double floating diffusion (DFD) transistor 224, and the low conversion gain transistor 230. In this example, the LOFIC 232 is implemented as a metal-insulator-metal capacitor comprising an insulating material having a high dielectric constant or a high-k insulating material disposed between a first metal electrode and a second metal electrode. In various examples, the insulating material disposed between the first and second metal electrodes of the LOFIC 232 can be formed from a single layer of high-k material or a multi-layer stack of high-k materials. The precise composition and overall thickness of the high-k material can depend on the desired LOFIC capacitance. In various examples, the high-k material may include one of aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2 ), hafnium oxide (HfO), or a combination thereof.

[0031] In one example, it should be understood that the first metal electrode of LOFIC 232 can be referred to as capacitor top metal (CTM), and the second metal electrode of LOFIC 232 can be referred to as capacitor bottom metal (CBM). Thus, the first metal electrode (e.g., CTM) of LOFIC 232 is coupled to the source of second reset transistor 250, and the second metal electrode (e.g., CBM) is coupled to the source of first reset transistor 234 and the drain of low conversion gain transistor 230. Thus, it should also be understood that the second metal electrode (e.g., CBM) of LOFIC 232 is selectively coupled to first floating diffusion FD1 218 through low conversion gain transistor 230 and through dual floating diffusion transistor 224.

[0032] LOFIC 232 may have a capacitance greater than the capacitance of first floating diffusion FD1 218 or second capacitor 228. In one example, the capacitance (or charge storage capacity) of first floating diffusion FD1 218 and the capacitance (or charge storage capacity) of second capacitor 228 are configured to be the same. In another example, the capacitance of second capacitor 228 is configured to be greater than the capacitance of first floating diffusion FD1 218. LOFIC 232 may have a charge storage capacity greater than the charge storage capacity of photodiode 214.

[0033] During an idle or integration period, excess photogenerated image charge in response to a bright light condition (e.g., LED light or IR light) is configured to overflow from the photodiode 214 through the transfer transistor 216 to the first floating diffusion FD1 218 when the photodiode 214 is saturated, to overflow to the second capacitor 228 (the additional floating diffusion) through the double floating diffusion transistor 224 when the first floating diffusion FD1 218 is also full, and then to overflow to the LOFIC 232 through the low conversion gain transistor 230 when the second capacitor 228 is also full.

[0034] Figure 2A The example depicted in FIG2 also illustrates a bias voltage source 248 configured to provide a bias voltage VCAP to a first metal electrode (e.g., CTM) of LOFIC 232. In the example, bias voltage source 248 is further configured to have a high impedance state via switch SW1 249, which, when disconnected, decouples the first metal electrode (e.g., CTM) of LOFIC 232 from receiving bias voltage VCAP from bias voltage source 248. In various examples, bias voltage source 248 may include a voltage buffer coupled to the first metal electrode (e.g., CTM) of LOFIC 232 via switch SW1 249 for selectively providing a high capacitor bias voltage or a low capacitor bias voltage to the first metal electrode (e.g., CTM) of LOFIC 232. In one example, the high capacitor bias voltage is greater than the low capacitor bias voltage. In one example, the high capacitor bias voltage may be between 2.0V and 3.5V, and the low capacitor bias voltage may be between 0V and 2.0V. It should be appreciated that, in various examples, the voltage levels of the high capacitor bias voltage and the low capacitor bias voltage may be determined with consideration given to the stability range of the high-k material.

[0035] In one example, the first reset transistor 234 and the second reset transistor 250 can be disposed adjacent to each other and share a common drain junction in a semiconductor material coupled to a reset voltage source (e.g., PIXVDD) for pixel scaling considerations, wherein the semiconductor material can be a silicon substrate, a silicon-germanium alloy, germanium, a silicon carbide alloy, an indium-gallium-arsenic alloy, any other alloy formed from Group III-V compounds, other suitable semiconductor materials or alloys, combinations thereof, bulk substrates thereof, or wafers thereof. In this example, the first reset transistor 234 and the second reset transistor 250 can be arranged adjacent to each other.

[0036] It should be understood that the first reset transistor 234 and the second reset transistor 250 can be configured to have similar device characteristics. For example, the first reset transistor 234 and the second reset transistor can have at least one of substantially the same gate length, gate width, gate oxide thickness, and threshold voltage.

[0037] It should be further understood that the first reset transistor 234 and the second reset transistor 250 can be disposed between adjacent photodiodes. For example, the first reset transistor 234 and the second reset transistor 250 can be disposed in the same or different transistor regions arranged between a photodiode (e.g., photodiode 214) and an adjacent photodiode. The first reset transistor 234 and the second reset transistor 250 can be isolated from the photodiode by a shallow isolation trench structure, an isolation implant region, or a combination thereof. For example, a shallow isolation trench structure having an isolation depth greater than the junction depth of the source and drain associated with each respective first reset transistor 234 and second reset transistor 250 is disposed between the source and drain of each respective first reset transistor 234 and second reset transistor 250 and a photodiode (e.g., photodiode 214 and an adjacent photodiode) to provide electrical isolation.

[0038] The source and drain of the second reset transistor 250 may further be disposed in the same well region (eg, a P-well region) in the semiconductor material as the source follower 220 and / or the row select transistor 222 and have a common reference potential for device operation.

[0039] Figure 2A The example illustrated in illustrates the pixel circuit 204 during an idle period. In various examples described herein, the idle period occurs before a precharge period, which occurs before an integration period, which occurs before a readout period, which occurs before the next idle period, and so on.

[0040] In operation, during an idle period, first reset transistor 234 is configured to be turned on, second reset transistor 250 is configured to be turned off, and bias voltage source 248 is configured to provide a first bias voltage, VCAPLO, to a first metal electrode (e.g., CTM) of LOFIC 232. In one example, first bias voltage VCAPLO is a low capacitor bias voltage that is less than a reset voltage provided from a reset voltage source (e.g., PIXVDD). Thus, LOFIC 232 is reverse biased during the idle period in accordance with the teachings of the present invention. By reverse biasing LOFIC 232 during the idle period, it is understood that residual charge in LOFIC 232 is compensated or canceled in LOFIC 232 during the idle period, which shortens the discharge time of LOFIC 232 in accordance with the teachings of the present invention.

[0041] Figure 2B Schematic diagram illustrating one example of a pixel circuit 204 including a LOFIC during a pre-charge cycle according to the teachings of the present disclosure. It should be understood that Figure 2B The pixel circuit 204 may be as follows Figure 11 and 2. An example of one of the pixel circuits 104 included in the pixel array 102 shown in FIG. 1 is provided, and similarly named and numbered elements described above are similarly coupled and function below. It should also be understood that Figure 2B The pixel circuit 204 depicted in FIG is substantially similar to the pixel circuit 204 discussed in detail above. Figure 2A Pixel circuit 204 as depicted in FIG, except that: Figure 2B The pixel circuit 204 illustrated in FIG is depicted during a pre-charge cycle, which occurs at Figure 2A After the idle period described in and before the integration period and the readout period.

[0042] To illustrate, Figure 2B Pixel circuit 204 is shown including a photodiode 214 and a first floating diffusion FD1 218 coupled to receive image charge from photodiode 214 through transfer transistor 216. In the example, transfer transistor 216 is coupled to be controlled in response to transfer control signal TX 236 to transfer image charge from photodiode 214 to first floating diffusion FD1 218 during a readout period, and excess image charge photogenerated in response to bright lighting conditions (e.g., LED light or IR light) is also configured to overflow from photodiode 214 to first floating diffusion FD1 218 through transfer transistor 216 during the integration period when photodiode 214 is saturated.

[0043] Source follower transistor SF 220 has a gate coupled to the first floating diffusion portion FD1 218, and row select transistor 222 is coupled to source follower transistor SF 220, so that source follower transistor SF 220 and row select transistor 222 are coupled between the power line and the bit line 212 to output an image signal from the pixel circuit 204 in response to the row select control signal RS 246 and the amount of charge at the gate of source follower transistor SF 220.

[0044] exist Figure 2BIn the example illustrated in FIG, the dual floating diffusion DFD transistor 224 is also coupled between the first floating diffusion FD1 230 and the second capacitor 228 (e.g., an additional floating diffusion). The second capacitor 228 is coupled to receive the floating diffusion capacitor signal FDC 240. The low conversion gain transistor 230 is coupled between the second capacitor 228 and the first reset transistor 234. The low conversion gain transistor 230 is also coupled between the second capacitor 228 (e.g., an additional floating diffusion) and the second metal electrode (e.g., CBM) of the LOFIC 232. The first reset transistor 234 is coupled between a reset voltage source (e.g., PIXVDD) and the low conversion gain transistor 230. The first reset transistor 234 is coupled to be controlled in response to a reset control signal RSTG 244, and the low conversion gain transistor 230 is coupled to be controlled in response to a low conversion control signal LFG 242.

[0045] like Figure 2B , LOFIC 232 is also coupled between second reset transistor 250 and first reset transistor 234. In this example, second reset transistor 250 is coupled between a reset voltage source (e.g., PIXVDD) and LOFIC 232 and is controlled in response to a second reset control signal RST2 252. In this example, LOFIC 232 is implemented using a metal-insulator-metal capacitor comprising an insulating material having a high dielectric constant or a high-k insulating material disposed between a first metal electrode and a second metal electrode. In one example, it should be understood that the first metal electrode of LOFIC 232 may be referred to as capacitor top metal (CTM), and the second metal electrode of LOFIC 232 may be referred to as capacitor bottom metal (CBM). Thus, the first metal electrode (e.g., CTM) of LOFIC 232 is coupled to the source of second reset transistor 250, and the second metal electrode (e.g., CBM) is coupled to the source of first reset transistor 234 and the drain of low conversion gain transistor 230. Thus, it should also be understood that the second metal electrode (eg, CBM) of LOFIC 232 is selectively coupled to the first floating diffusion FD1 218 through the low conversion gain transistor 230 and through the double floating diffusion transistor 224 . Figure 2B The example depicted in also illustrates the bias voltage source 248 in a high impedance state with the switch SW1 249 in an open state, which decouples the first metal electrode (eg, CTM) of the LOFIC 232 from receiving the bias voltage VCAP from the bias voltage source 248 .

[0046] Figure 2BThe example illustrated in FIG2 illustrates a pixel circuit 204 during a precharge period that occurs between an idle period and an integration period. In operation, during the precharge period, the first reset transistor 234 is configured to be on, the second reset transistor 250 is configured to be on, and the bias voltage source 248 is configured to be in a high impedance state, with the switch SW1 249 in an off state. In the example, both the first and second metal electrodes (e.g., CTM and CBM electrodes) of the LOFIC 232 are locally shorted to a reset voltage source (e.g., PIXVDD) through the first reset transistor 234 and the second reset transistor 250 in the pixel circuit 204. Thus, in accordance with the teachings of the present invention, the LOFIC 232 is locally discharged or auto-zeroed in the pixel circuit 204 during the precharge period, thereby reducing the load on the bias voltage source 248 without a power supply short between the bias voltage source 248 and the reset voltage source (e.g., PIXVDD). In one example, it should also be understood that the photodiode 214, the first floating diffusion FD1 218, and the second capacitor 228 are also reset by the first reset transistor 234 during the precharge cycle and during the reset operation that occurs during the readout cycle. Thus, it should therefore be understood that the first reset transistor RST 234 is also selectively coupled to the photodiode 214, the first floating diffusion FD1 218, and the second capacitor 228 through the transfer transistor 216, the double floating diffusion transistor 224, and the low conversion gain transistor 230 as appropriate to reset the pixel circuit 204, e.g., in accordance with the teachings of the present invention, to reset the photodiode 214, the first floating diffusion FD1 218, and the second capacitor 228. In various examples, the PIXVDD voltage can be in the range of 1.2 volts to 3.6 volts.

[0047] Figure 3 An example of a timing diagram illustrating example signal values in an example pixel circuit including a LOFIC during idle, precharge, integration, and readout periods according to the teachings of the present disclosure. It should be understood that Figure 3 The signal depicted in can be Figures 2A to 2B , and similarly named and numbered elements described above are similarly coupled and function below.

[0048] Referring now to the depicted example, Figure 3 The first reset control signal RST 344, the bias voltage VCAP 348, the double floating diffusion control signal DFD 338, the low conversion gain control signal LFG 342, the transfer control signal TX 336, the floating diffusion capacitor signal FDC 340, the second reset control signal RST2 352 and the row select control signal RS 346 are configured to control the above-mentioned Figures 2A to 2B The corresponding circuit elements are discussed in detail in . Figure 3The example depicted in also illustrates the idle, precharge, integration, and readout periods that the pixel circuit cycles through when generating image data.

[0049] As shown, in Figure 3 During the idle period depicted in FIG, the first reset control signal RST 344 turns on the first reset transistor 234, the bias voltage source 248 is configured to output a low bias voltage VCAP 348 signal (e.g., 1 to 2 volts), and the second reset control signal RST2 352 turns off the second reset transistor 250. Thus, it should be understood that according to the teachings of the present invention, the LOFIC 232 is reverse biased during the idle period, which compensates or cancels the residual charge in the LOFIC 232 to reduce the discharge time of the LOFIC 232 and the problem of image tailing. Figure 3 The example depicted in also shows that dual floating diffusion control signal DFD 338, low conversion gain control signal LFG 342, transfer control signal TX 336, floating diffusion capacitor signal FDC 340, and row select control signal RS 346 are all configured to have low values (eg, 0 volts) during idle periods.

[0050] In various examples, the idle period can be configured to range from 3 milliseconds to 23 milliseconds based on the necessary auto-zero discharge time and / or the required exposure or integration time required for the LOFIC 232. The duration of the idle period can be configured to be greater than the duration of the pre-charge period. For example, the idle period can be configured to be 3 milliseconds and the pre-charge period can be configured to be less than or equal to 5 microseconds.

[0051] Figure 3 The example depicted in FIG shows that during a precharge cycle that occurs after an idle period, the row select signal RS 346 turns on the row select transistor 222. Next, the first reset control signal RST 344 and the second reset control signal RST 2352 are configured to transition to a high voltage value that turns on the first and second reset transistors 234, 250 (e.g., operates in a conductive state), and the bias voltage source 248 providing the bias voltage VCAP 348 enters a high impedance state (e.g., HiZ) that allows the LOFIC 232 to be driven by the reset voltage source (e.g., PIXVDD). In one example, the bias voltage source 248 can enter a high impedance state by opening the switch SW1 249, as shown in FIG. Figure 2B3. The example depicted in FIG. Next, low conversion gain control signal LFG 342 turns on low conversion gain transistor 230, and next, dual floating diffusion control signal DFD 338 turns on dual floating diffusion transistor 224, and next, transfer control signal TX 336 turns on transfer transistor 216. At this point, during the precharge period, photodiode 214, first floating diffusion FD1 218, and second capacitor 228 are all reset (e.g., to a reset voltage provided by a reset voltage source) by first reset transistor 234. At this point, during the precharge period, both the first and second metal electrodes (e.g., CTM and CBM) of LOFIC 232 are locally shorted to the reset voltage source (e.g., PIXVDD) by first reset transistor 234 and second reset transistor 250, which discharges or auto-zeros LOFIC 232 and shortens the discharge time of LOFIC 232 in accordance with the teachings of the present invention. It should be understood that during the pre-charge cycle, the first reset control signal RST 344 and the second reset control signal RST2 352 need to be configured to transition from a high voltage level to a low voltage level, thereby turning off the corresponding first and second reset transistors 234, 250 and starting to bias the second metal electrode (e.g., CBM) of the LOFIC 232 with the bias voltage VCAP 348 before the bias voltage source 248 switches from a high impedance state (e.g., HiZ) to a normal bias voltage VCAP 348 supply state (e.g., when the switch SW1 249 is closed) in order to prevent power supply shorting issues, for example, avoiding a short between the bias voltage source 248 and the reset voltage source (e.g., PIXVDD).

[0052] Thereafter, the transfer control signal TX 336 turns off the transfer transistor 216, and then the first reset control signal RST 344 turns off the first reset transistor 234, and then the bias voltage source 248 transitions from a high impedance state (e.g., HiZ) back to supplying the bias voltage VCAP 348 by closing the switch SW1 249. In the example, the bias voltage source 248 is configured to supply the bias voltage VCAP 348 at a low VCAP value (e.g., 1 to 2 volts), and then the dual floating control signal DFD 338 turns off the dual floating diffusion transistor 224, and then the low conversion gain control signal LFG 342 turns off the low conversion gain transistor 230, and then the row select signal RS 346 turns off the row select transistor 222.

[0053] Figure 3The example depicted in FIG shows that during the integration period, which occurs after the precharge period, all control signals are low, wherein the bias voltage source 248 is configured to supply a bias voltage VCAP 348 of a low VCAP value (e.g., 1-2 volts). During the integration period, the photodiode 214 generates image charge in response to incident light. The pixel circuit 204 is configured so that excess photogenerated charge can overflow from the photodiode 214 to the LOFIC 232 through the dual floating diffusion transistor 224 and the low conversion gain transistor 230 for storage under strong or bright light conditions (e.g., LED light or IR light).

[0054] In one example, during the integration period, photogenerated excess image charge is configured to overflow from the photodiode 214 to the second capacitor 228 through the double floating diffusion DFD transistor 224 when the first floating portion FD1 218 is saturated and to overflow to the LOFIC 232 through the double floating diffusion DFD transistor and the low conversion gain transistor 230 when the second capacitor 228 is also saturated.

[0055] Figure 3 The example depicted in shows that during a readout cycle occurring after an integration period, row select signal RS 346 turns on row select transistor 222, and then, low conversion gain control signal LFG 342 turns on low conversion gain transistor 230, and then, double floating diffusion control signal DFD 338 turns on double floating diffusion transistor 224, and then, bias voltage source 248 provides bias voltage VCAP 348 that biases the signal, which transitions to a high value.

[0056] Next, a dual conversion gain (DCG) readout of the photodiode occurs during the time that a medium conversion gain (MCG) readout of the reset value (R) from photodiode 214 occurs. Next, floating diffusion capacitor signal FDC 340 is pulsed while dual floating diffusion control signal DFD 338 turns off dual floating diffusion transistor 224. Next, a high conversion gain (HCG) readout of the reset value (R) from photodiode 214 occurs. Next, floating diffusion capacitor signal FDC 340 transitions to a high value, and transfer control signal TX 336 turns on transfer transistor 216, during which time the image charge in photodiode 214 is transferred to first floating diffusion FD1 218. Next, a high conversion gain (HCG) readout of the signal value (S) can occur. Next, dual floating diffusion control signal DFD 338 turns on dual floating diffusion transistor 224, floating diffusion capacitor signal FDC 340 transitions to a high value, and transfer control signal TX 336 turns on transfer transistor 216, during which time the image charge in photodiode 214 is transferred to first floating diffusion FD1 218 and second capacitor 228. A medium conversion gain (MCG) readout of the signal value (S) can then occur.

[0057] Next, a LOFIC readout of photodiode 214 and LOFIC 232 occurs, during which time low conversion gain control signal LFG 342 turns on low conversion gain transistor 230, and next, transfer control signal TX 336 turns on transfer transistor 216, during which time the image charge in photodiode 214 is transferred to first floating diffusion FD1 218, second capacitor 228, and LOFIC 232. Next, a low conversion gain (LCG) readout of the signal value (S) may occur. Next, the first reset control signal RST 344 turns on the first reset transistor 234, the second reset control signal RST2 352 turns on the second reset transistor 250, and the bias voltage source 248 enters a high impedance state (e.g., HiZ), wherein the switch SW1 249 is opened, thereby preventing a short from occurring between the reset voltage source (e.g., PIXVDD) and the bias voltage source 248. During this time, the photodiode 214, the first floating diffusion FD1 218, the second capacitor 228, and the LOFIC 232 are all reset by the first reset transistor 234 and the second reset transistor 250, as previously described. Next, the first reset control signal RST 344 turns off the first reset transistor 234, the second reset control signal RST2 352 turns off the second reset transistor 250, and the bias voltage source 248 transitions from a high impedance state (e.g., HiZ) to provide a bias voltage VCAP 348, wherein the switch SW1 is closed and configured to provide a high VCAP signal value to the first metal electrode (e.g., CTM) of the LOFIC 232. It should be understood that the switch SW1 is not closed to provide the bias voltage VCAP 348 until the first reset control signal RST 344 turns off the first reset transistor 234 and the second reset control signal RST2 352 turns off the second reset transistor 250. Next, a low conversion gain (LCG) readout of the reset value (R) occurs, after which time the transfer control signal TX 336 turns off the transfer transistor 216, and then the bias voltage VCAP 348 transitions to a low value (e.g., 0 volts), and then the double floating diffusion control signal DFD 338 turns off the double floating diffusion transistor 224, and then the low conversion gain control signal LFG 342 turns off the low conversion gain transistor 230.

[0058] then, Figure 3 The process described in loops back to the idle period, during which time the LOFIC 232 may again be reverse biased, which compensates or cancels out the residual charge in the LOFIC 232 as the cycle repeats to further reduce the LOFIC 232 discharge time in accordance with the teachings of the present invention.

[0059] The above description of the illustrated embodiments of the present invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Although specific embodiments of the present invention are described herein for illustrative purposes, those skilled in the relevant art will recognize that various modifications are possible within the scope of the invention.

[0060] These modifications may be made to examples of the present invention in light of the above detailed description. The terms used in the appended claims should not be construed to limit the invention to the specific examples disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the appended claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims

1. A pixel circuit, comprising: a photodiode configured to photogenerate image charge in response to incident light; a floating diffusion coupled to receive the image charge from the photodiode; a transfer transistor coupled between the photodiode and the floating diffusion to transfer the image charge from the photodiode to the floating diffusion; a first reset transistor coupled between a reset voltage source and the floating diffusion, wherein the first reset transistor is configured to switch in response to a first reset control signal; a lateral overflow integrator capacitor LOFIC comprising an insulating region disposed between a first metal electrode and a second metal electrode, wherein the second metal electrode is coupled to the first reset transistor and selectively coupled to the floating diffusion; a second reset transistor coupled between the reset voltage source and the first metal electrode, wherein the second reset transistor is configured to switch in response to a second reset control signal; and a bias voltage source coupled to the first metal electrode, wherein during an idle period, the first reset transistor is configured to be turned on, the second reset transistor is configured to be turned off, and the bias voltage source is configured to provide a first bias voltage to the first metal electrode to reverse bias the LOFIC, wherein the first bias voltage is less than a reset voltage provided from the reset voltage source.

2. A pixel circuit according to claim 1, wherein during a pre-charge period, the first reset transistor and the second reset transistor are configured to be turned on and the bias voltage source is configured to be in a high impedance state to provide a zero bias voltage across the LOFIC to discharge the LOFIC while resetting the pixel circuit during the pre-charge period, wherein the pre-charge period occurs between the idle period and the integration period.

3. The pixel circuit of claim 2 , wherein during the pre-charge period, the first reset transistor and the second reset transistor are configured to be turned off before the bias voltage source is configured to transition from the high impedance state to provide the first bias voltage to the first metal electrode during the integration period.

4. The pixel circuit of claim 3 , wherein during a readout period, the first reset transistor and the second reset transistor are configured to be turned off, and the bias voltage source is configured to provide a second bias voltage to the first metal electrode, wherein the first bias voltage is a low capacitor bias voltage, wherein the second bias voltage is a high capacitor bias voltage greater than the low capacitor bias voltage, and wherein the readout period occurs after the integration period.

5. A pixel circuit according to claim 4, wherein the first reset transistor and the second reset transistor are configured to be turned on and the bias voltage source is configured to be in the high impedance state to provide a zero bias voltage across the LOFIC to discharge the LOFIC while resetting the pixel circuit during the readout period before reading out the reset signal value from the LOFIC. 6 . The pixel circuit of claim 2 , wherein a duration of the idle period is configured to be greater than a duration of the pre-charge period.

7. The pixel circuit of claim 1 , wherein the LOFIC is a first capacitor, wherein the pixel circuit further comprises: a double floating diffusion (DFD) transistor coupled between the floating diffusion and the second metal electrode, wherein the DFD transistor is configured to switch in response to a DFD control signal; a second capacitor, wherein the DFD transistor is coupled between the floating diffusion and the second capacitor; and A low conversion gain (LFG) transistor is coupled between the second capacitor and the second metal electrode, wherein the LFG transistor is configured to switch in response to a LFG control signal.

8. The pixel circuit according to claim 7, further comprising: a source follower transistor having a gate coupled to the floating diffusion; and A row select transistor is coupled to the source follower transistor, wherein the source follower transistor and the row select transistor are coupled between a power line and a bit line.

9. An imaging system comprising: A pixel array comprising a plurality of pixel circuits arranged in a plurality of rows and a plurality of columns, wherein each of the pixel circuits comprises: a photodiode configured to photogenerate image charge in response to incident light; a floating diffusion coupled to receive the image charge from the photodiode; a first reset transistor coupled between a reset voltage source and the floating diffusion, wherein the first reset transistor is configured to switch in response to a first reset control signal; a lateral overflow integrator capacitor LOFIC comprising an insulating region disposed between a first metal electrode and a second metal electrode, wherein the second metal electrode is coupled to the first reset transistor and selectively coupled to the floating diffusion; a second reset transistor coupled between the reset voltage source and the first metal electrode, wherein the second reset transistor is configured to switch in response to a second reset control signal; and a bias voltage source coupled to the first metal electrode, wherein during an idle period, the first reset transistor is configured to be turned on, the second reset transistor is configured to be turned off, and the bias voltage source is configured to provide a first bias voltage to the first metal electrode to reverse bias the LOFIC, wherein the first bias voltage is less than a reset voltage provided from the reset voltage source; control circuitry coupled to the pixel array to control operation of the pixel array; and Readout circuitry is coupled to the pixel array to read out image data from the plurality of pixel cells.

10. The imaging system of claim 9, further comprising: Function logic is coupled to the readout circuitry to store the image data from each of the plurality of pixel cells.

11. The imaging system of claim 9 , wherein during a pre-charge period, the first reset transistor and the second reset transistor are configured to be turned on and the bias voltage source is configured to be in a high impedance state to provide a zero bias voltage across the LOFIC to discharge the LOFIC while resetting the pixel circuit during the pre-charge period, wherein the pre-charge period occurs between the idle period and the integration period.

12. The imaging system of claim 11 , wherein during the pre-charge period, the first reset transistor and the second reset transistor are configured to be turned off before the bias voltage source is configured to transition from the high impedance state to provide the first bias voltage to the first metal electrode during the integration period.

13. The imaging system of claim 12 , wherein during a readout period, the first reset transistor and the second reset transistor are configured to be turned off, and the bias voltage source is configured to provide a second bias voltage to the first metal electrode, wherein the first bias voltage is a low capacitor bias voltage, wherein the second bias voltage is a high capacitor bias voltage, wherein the readout period occurs after the integration period, and wherein the low capacitor bias voltage is less than the high capacitor bias voltage.

14. The imaging system of claim 13 , wherein the first reset transistor and the second reset transistor are configured to be turned on and the bias voltage source is configured to be in the high impedance state to provide a zero bias voltage across the LOFIC to discharge the LOFIC while resetting the pixel circuit during the readout period prior to reading a reset signal value from the LOFIC.

15. The imaging system of claim 11, wherein a duration of the idle period is configured to be greater than a duration of the pre-charge period.

16. The imaging system of claim 9, wherein the LOFIC is a first capacitor, wherein each of the pixel circuits further comprises: a double floating diffusion (DFD) transistor coupled between the floating diffusion and the second metal electrode, wherein the DFD transistor is configured to switch in response to a DFD control signal; a second capacitor, wherein the DFD transistor is coupled between the floating diffusion and the second capacitor; and A low conversion gain (LFG) transistor is coupled between the second capacitor and the second metal electrode, wherein the LFG transistor is configured to switch in response to a LFG control signal.

17. The imaging system of claim 16, wherein each of the pixel circuits further comprises: a source follower transistor having a gate coupled to the floating diffusion; and A row select transistor is coupled to the source follower transistor, wherein the source follower transistor and the row select transistor are coupled between a power line and a bit line.

18. The imaging system of claim 9, wherein the first reset transistor and the second reset transistor share a drain coupled to the reset voltage source.

Images