Semiconductor device

Abstract

In the active region side in the active region (1a) and the non-active region (1b), between the 1st deep layer (14) and the 1st current dispersion layer (13) and the base region (18), there is provided the 2nd deep layer (17) having the 2nd strip-shaped portion (171) in which a plurality of lines are arranged, which is connected to the base region and the 1st deep layer and is provided extending in the same direction as the length direction of the trench (21). In addition, there is provided the 2nd current dispersion layer (15) formed between the 1st current dispersion layer and the base region and arranged between the plurality of lines constituting the 2nd strip-shaped portion. Furthermore, each line constituting the 1st strip-shaped portion (141) included in the 1st deep layer includes a top end portion (141a) connected to the frame-shaped portion (142) and an inner side portion (141b) on the inner side than the top end portion, and the width of the top end portion is equal to or greater than the width of the inner side portion.

Description

[0001] Cross-referencing of related applications

[0002] This application is based on Japanese Patent Application No. 2021-082800, filed on May 14, 2021, the contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor devices having a trench gate configuration. Background Technology

[0004] Conventionally, in silicon carbide (SiC) semiconductor devices, trench gate structures are used to increase channel density and enable the flow of large currents. In SiC semiconductor devices with trench gate structures, there is a possibility of insulation breakdown of the gate insulating film caused by applying electric field stress to the bottom of the trench. Therefore, Patent Document 1 proposes a SiC semiconductor device that suppresses insulation breakdown of the gate insulating film by suppressing the application of a high electric field to the bottom of the trench.

[0005] This SiC semiconductor device employs a structure in which an n-type first current dispersing layer and a p-type first deep layer are alternately arranged in strips below the trench gate structure. The first deep layer is connected to the p-type base region via a second deep layer disposed on both sides of the trench gate structure and is fixed at the source potential.

[0006] With this structure, the rise of the equipotential line towards the trench gate structure side is suppressed by the first deep layer, and the application of a high electric field to the bottom of the trench gate structure is suppressed, thus preventing the insulation breakdown of the gate insulating film.

[0007] Existing technical documents

[0008] Patent documents

[0009] Patent Document 1: Japanese Patent Application Publication No. 2019-46908 Summary of the Invention

[0010] In a cell region with a trench gate structure, if the region where the element operates is defined as an active region, the remaining region in the cell region becomes a non-active region that does not operate, arranged in a manner that surrounds the active region. Regarding the structure of Patent Document 1 mentioned above, a structure was studied in which the rise of the equipotential line is suppressed based on the electric field mitigation effect brought about by the first deep layer by setting the non-active region on a large scale.

[0011] The results confirmed that in the first deep layer, the portion of the strip-shaped cell region (hereinafter referred to as the strip portion) connected to the portion of the outer edge region surrounding it (hereinafter referred to as the frame portion) has an increased range of non-first deep layer portions. If such an increased range of non-first deep layer portions exists, the electric field mitigation effect in that portion decreases, and the rise of the equipotential line cannot be suppressed, thus raising concerns about a decrease in gate lifetime.

[0012] Furthermore, it was confirmed that the spacing between the frame-shaped portion and the strip-shaped portion, more specifically, between the portion of the frame-shaped portion parallel to the strip-shaped portion and the outermost line of the strip-shaped portion opposite to it, is larger than the spacing between the lines constituting the strip-shaped portion. With this increased spacing between the frame-shaped portion and the strip-shaped portion, the electric field mitigation effect is reduced, making it impossible to suppress the rise of the equipotential line, thus raising concerns about a decrease in gate lifetime.

[0013] Furthermore, when a structure is adopted in which the first and second deep layers are formed into strips and intersect, the portion of the first deep layer that intersects with the trench gate structure becomes a factor hindering the current path. Therefore, there is a problem of increasing the on-resistance.

[0014] Furthermore, it was confirmed that in a SiC semiconductor device having an n-type drift layer and a p-type base region, the forward voltage Vf varies due to the influence of holes generated when the formed PN diode is energized.

[0015] Furthermore, while an example of a SiC semiconductor device using SiC as the semiconductor material is given here, the same principle applies to semiconductor devices using semiconductor materials other than SiC.

[0016] The first objective of this disclosure is to provide a semiconductor device capable of suppressing the decrease in gate lifetime caused by the rise of the equipotential line. Furthermore, the second objective is to provide a semiconductor device capable of suppressing the increase in on-resistance. Furthermore, the third objective is to provide a semiconductor device capable of suppressing fluctuations in the forward voltage Vf.

[0017] According to a first aspect of this disclosure, a semiconductor device is provided, having an active region and an active region surrounding the active region. The active region is formed with a semiconductor switching element having a plurality of trench gate structures to perform element operation, while the active region does not perform element operation. The semiconductor device includes a semiconductor switching element having: a semiconductor region of a first conductivity type or a second conductivity type; a first impurity region of the first conductivity type formed on the semiconductor region, with an impurity concentration lower than that of the semiconductor region; a base region of the second conductivity type formed on the first impurity region; a second impurity region of the first conductivity type formed on the base region, with an impurity concentration higher than that of the first impurity region; a plurality of trench gate structures having a gate insulating film formed on the inner wall surface of the trench and a gate electrode formed on the gate insulating film within the trench, the trenches extending in one direction from the surface of the second impurity region to a position deeper than the base region; a first electrode electrically connected to the second impurity region and electrically connected to the base region; and a second electrode formed on the back side of the semiconductor region and electrically connected to the semiconductor region.

[0018] In addition, it includes: a first current dispersing layer of the first conductivity type, formed between the first impurity region and the base region, wherein the impurity concentration is higher than that of the first impurity region; and a first deep layer of the second conductivity type, having a first strip-shaped portion and a frame-shaped portion, wherein the first strip-shaped portion extends along the length direction in one direction on the active region side in both the active and non-active regions and is provided with a plurality of lines arranged thereon, and the frame-shaped portion is formed in the non-active region, surrounding the first strip-shaped portion and being connected to each line constituting the first strip-shaped portion.

[0019] It also includes: a second deep layer of a second conductivity type, having a second strip-shaped portion, which is formed between the first deep layer and the first current dispersing layer and the base region on the active region side of the active region and the non-active region, and is connected to the base region and the first deep layer, and has a plurality of lines arranged extending in the same direction as the length direction of the trench; and a second current dispersing layer of the first conductivity type, formed between the first current dispersing layer and the base region, disposed between the plurality of lines constituting the second strip-shaped portion. In this structure, each line constituting the first strip-shaped portion includes a top portion connected to the frame-shaped portion and an inner portion inside the top portion, the width of the top portion being greater than or equal to the width of the inner portion.

[0020] In this way, the width of the tip portion of each line in the first stripe portion of the first deep layer is greater than or equal to the width of the inner portion. That is, even assuming that the portion of the mask used in the formation of the first deep layer corresponding to the tip portion of the first deep layer is narrower, the width of the tip portion can still be greater than or equal to the width of the inner portion. Therefore, the tip portion of the first current dispersion layer can be kept from becoming too large, and the rise of the electric field in that portion can be suppressed by the electric field mitigation effect of the first deep layer, thus suppressing the decrease in breakdown voltage and lifetime of the gate insulating film.

[0021] According to the second aspect of the semiconductor device disclosed herein, each line constituting the second strip includes a top portion and an inner portion that is closer to the top portion, wherein the width of the top portion is greater than the width of the inner portion.

[0022] This makes the width of the top portion of the second deep layer larger than the width of the inner portion. Therefore, even if the spacing between the frame-shaped and strip-shaped portions of the first deep layer is wider than the spacing between the lines, thus reducing the electric field mitigation effect of the first deep layer, the electric field mitigation effect of the second deep layer can push back the equipotential lines, making it difficult for high electric fields to penetrate. Thus, even if the spacing between the frame-shaped and strip-shaped portions of the first deep layer is wider than the spacing between the lines, the rise of the electric field in some areas can be suppressed. Therefore, the reduction in the breakdown voltage and lifetime of the gate insulating film can be suppressed.

[0023] According to the third aspect of the present disclosure, in a semiconductor device, the length direction of the trench intersects the length direction of each line constituting the first strip portion of the first deep layer, and each line constituting the first strip portion is provided with a missing portion and is truncated to be a dashed line, and the trench gate structure is a structure that passes through the missing portion provided in each line.

[0024] In this way, the first stripe intersects with the trench grid structure, and each line is partially cut off by a missing section, allowing the trench grid structure to pass through the missing section. This reduces the intersection of the first deep layer and the trench grid structure compared to the case without missing sections, thus suppressing an increase in conduction resistance.

[0025] According to the fourth aspect of the present disclosure, a semiconductor device has a third deep layer of a second conductivity type below the first deep layer and the first current dispersing layer, which has a third strip-shaped portion having a plurality of lines arranged in a direction that is the same as the length direction of the trench.

[0026] This creates a three-layer structure, consisting of a first layer, a second layer, and a third layer. This structure lengthens the carrier movement path, allowing more carriers to recombine and dissipate. Consequently, it suppresses increases in on-resistance and fluctuations in the forward voltage Vf. Attached Figure Description

[0027] Figure 1This is a perspective cross-sectional view of the SiC semiconductor device according to the first embodiment.

[0028] Figure 2 It is equivalent to Figure 3 The cross-sectional view of the outer edge of the unit region and the outer peripheral region surrounding the unit region in section II-II.

[0029] Figure 3 Viewed from above Figure 2 Layout diagram at the time.

[0030] Figure 4 It is about Figure 3 The area IV, enclosed by the dashed line, is a magnified view of the upper surface layout, representing the boundary between the strip-shaped and frame-shaped portions of the first deep layer.

[0031] Figure 5A It means Figure 1 The diagram shows a cross-sectional view of the manufacturing process of a SiC semiconductor device.

[0032] Figure 5B It continues Figure 5A The diagram shows a cross-sectional view of the manufacturing process of a SiC semiconductor device.

[0033] Figure 5C It continues Figure 5B The diagram shows a cross-sectional view of the manufacturing process of a SiC semiconductor device.

[0034] Figure 5D It continues Figure 5C The diagram shows a cross-sectional view of the manufacturing process of a SiC semiconductor device.

[0035] Figure 5E It continues Figure 5D The diagram shows a cross-sectional view of the manufacturing process of a SiC semiconductor device.

[0036] Figure 5F It continues Figure 5E The diagram shows a cross-sectional view of the manufacturing process of a SiC semiconductor device.

[0037] Figure 5G It continues Figure 5F The diagram shows a cross-sectional view of the manufacturing process of a SiC semiconductor device.

[0038] Figure 6A This is a diagram illustrating a design example of the mask pattern used to form the first deep layer.

[0039] Figure 6B It means according to Figure 6A The diagram shows the design values ​​of the mask when the mask has been laid out.

[0040] Figure 6CIt means according to Figure 6A The design example of a mask pattern is shown in the image of a mask in the case where the mask is actually laid out.

[0041] Figure 7 It is a cross-sectional view of the rising electric field.

[0042] Figure 8A It is a diagram showing the relationship between the spacing of the lines in the strip section of the first deep layer and the pressure resistance.

[0043] Figure 8B This is a graph showing the relationship between the spacing of the lines in the strip section of the first deep layer and the gate electric field strength.

[0044] Figure 9A This is a diagram showing the layout of the upper surface of the strip-shaped portion of the first deep layer as described in a variation of the first embodiment.

[0045] Figure 9B This is a diagram showing the layout of the upper surface of the strip-shaped portion of the first deep layer as described in a variation of the first embodiment.

[0046] Figure 10 This diagram shows the upper surface layout of the second deep layer of the SiC semiconductor device according to the second embodiment, which is equivalent to... Figure 3 The graph shows the region X represented by the dashed line.

[0047] Figure 11A This is a diagram showing the layout of the upper surface of the strip-shaped portion of the second deep layer as described in the modified example of the second embodiment.

[0048] Figure 11B This is a diagram showing the layout of the upper surface of the strip-shaped portion of the second deep layer as described in the modified example of the second embodiment.

[0049] Figure 12 This is a diagram showing the layout of the first deep layer, the second deep layer, and the upper surface of the trench gate structure of the SiC semiconductor device according to the third embodiment.

[0050] Figure 13 This is a graph showing the relationship between the gate current Ig and the drain voltage Vd when gate breakdown occurs.

[0051] Figure 14A This is a top surface layout diagram showing the top shape of the cut-off portion of each line in the first deep layer as described in the modified example of the third embodiment.

[0052] Figure 14B This is a top surface layout diagram showing the top shape of the cut-off portion of each line in the first deep layer as described in the modified example of the third embodiment.

[0053] Figure 15AThis is a top surface layout diagram of the case where each point of the strip-shaped portion of the first deep layer described in the modified example of the third embodiment is set to a circle.

[0054] Figure 15B This is a top surface layout diagram showing the case where the points of the strip-shaped portion in the first deep layer described in the modified example of the third embodiment are set as hexagons.

[0055] Figure 16 This is a perspective cross-sectional view of the SiC semiconductor device according to the fourth embodiment.

[0056] Figure 17 It means Figure 16 A diagram showing the movement path of the cavities in section XVII-XVII.

[0057] Figure 18 This is a perspective cross-sectional view of the SiC semiconductor device described in a variation of the fourth embodiment.

[0058] Figure 19 It means Figure 18 A diagram showing the movement path of the cavities in the XIX-XIX section.

[0059] Figure 20 This is a perspective cross-sectional view of the SiC semiconductor device described in a variation of the fourth embodiment.

[0060] Figure 21 It means Figure 20 A diagram showing the movement path of the cavities in the XXI-XXI section.

[0061] Figure 22 This is a perspective cross-sectional view of the SiC semiconductor device described in a variation of the fourth embodiment.

[0062] Figure 23 It means Figure 22 A diagram showing the movement path of the cavities in section XXIII-XXIII. Detailed Implementation

[0063] Hereinafter, embodiments of the present disclosure will be described based on the accompanying drawings. Furthermore, in each of the following embodiments, the same reference numerals will be used to describe parts that are identical or equivalent to each other.

[0064] (First Embodiment)

[0065] Reference Figures 1-4 The first embodiment will be described. The SiC semiconductor device of this embodiment is as follows: Figures 1-4 As shown, a MOSFET with a reverse-type trench gate structure is included, serving as a semiconductor switching element, comprising a cell region 1 and an outer peripheral region 2 with an outer peripheral withstand voltage structure surrounding the cell region 1. Furthermore, Figure 1 This is a three-dimensional cross-sectional view of one cell in cell region 1 of the MOSFET.

[0066] like Figure 1 , Figure 2 As shown, SiC semiconductor devices use n-type semiconductors made of SiC. + A substrate 11 of type 11 is formed. For the substrate 11, for example, an off-angle of 0–8° relative to the (0001) Si plane is used, and the concentration of n-type impurities such as nitrogen and phosphorus is, for example, 1.0 × 10⁻⁶. 19 / cm 3 A substrate with a thickness of approximately 300 μm.

[0067] In addition, Figures 1-3 In this diagram, the surface direction of substrate 11 is defined as the xy plane, the direction <11-20> in the xy plane is defined as the y-axis direction, and the direction orthogonal to the y-axis direction is defined as the x-axis direction. Furthermore, the normal direction of the surface direction of substrate 11 is defined as the z-axis direction.

[0068] On the surface of substrate 11, n-type impurities such as nitrogen and phosphorus are formed at a concentration of, for example, 5.0 to 10.0 × 10⁻⁶. 15 / cm 3 n-type SiC with a thickness of approximately 10–15 μm - Type 12. This n - The impurity concentration in the 12-layer structure can be constant in the depth direction, but it is preferable to impart a slope to the concentration distribution, such that n - The portion of the model layer 12 on the substrate 11 side has a higher concentration than the side farther from the substrate 11. For example, n can be made - The impurity concentration in the portion of the model layer 12 approximately 3–5 μm from the surface of the substrate 11 is 2.0 × 10⁻⁶ higher than in other portions. 15 / cm 3 Left and right. By adopting this structure, n can be reduced. - The internal resistance of the molding layer 12 can reduce the on-resistance. Additionally, in this embodiment, n - Type layer 12 corresponds to the first impurity region.

[0069] In cell region 1, at n - The surface portion of the type layer 12 is formed with a density greater than n. - The first current dispersion layer 13 of the n-type with high impurity concentration and introduced with n-type impurities such as nitrogen and phosphorus, and the first deep layer 14 of the p-type with introduced p-type impurities such as Al.

[0070] The first current dispersing layer 13 is composed of an n-type layer containing n-type impurities such as nitrogen and phosphorus, and has a depth of 0.3 to 1.5 μm. In this embodiment, the first current dispersing layer 13 is formed only in unit region 1. That is, in this embodiment, the n-type impurities are dispersed in the n-type layer. - The region on the surface of the top layer 12 where the first current dispersing layer 13 is formed is designated as unit region 1, and n - The area on the surface of the first current dispersing layer 13 where it is not formed is designated as the outer peripheral region 2. Furthermore, the first deep layer 14, while shallower than the first current dispersing layer 13, is set to a depth of approximately the same as it, 0.3 to 1.4 μm. That is, the first deep layer 14 is formed such that its bottom is located within the first current dispersing layer 13, and its depth is approximately equal to that of the first current dispersing layer 13. - The first current dispersing layer 13 is formed between the two types of layers 12.

[0071] The first current dispersing layer 13 and the first deep layer 14 are provided to extend along the x-axis and are arranged at equal intervals along the y-axis in a strip-like manner, where multiple lines are alternately arranged in the active region 1a where the MOSFET operates. The strip-like portion in the first deep layer 14 corresponds to the first strip-like portion, which will be referred to as strip-like portion 141 below.

[0072] The width of each line in the strip-shaped portion of the first current dispersing layer 13 is, for example, 0.25 μm, and the n-type impurity concentration is, for example, 5.0 × 10⁻⁶. 16 ~2.0×10 18 / cm 3 The width of each line constituting the strip 141 is, for example, 0.9 μm, and the p-type impurity concentration is, for example, 3.0 × 10⁻⁶. 17 ~1.0×10 18 / cm 3 In this embodiment, the concentration of p-type impurities in the first deep layer 14 is constant in the depth direction. Furthermore, the concentration of p-type impurities in the first deep layer 14 is related to the concentration of n-type impurities. - The surface on the opposite side of the type layer 12 is on the same plane as the surface of the first current dispersing layer 13.

[0073] In addition, such as Figure 3 As shown, the first deep layer 14 is also formed in the non-active region 1b, which is located between the active region 1a and the outer peripheral region 2 and is configured to surround the active region 1a, and does not operate as a MOSFET. Near the active region 1a in the non-active region 1b, the first deep layer 14 is configured to have a strip-shaped portion 141 identical to that of the active region 1a, and on its outer side, it is formed to the boundary position with the outer peripheral region 2, thereby forming a frame-shaped portion 142. The frame-shaped portion 142 surrounds the strip-shaped portion 141 and connects to the lines constituting the strip-shaped portion 141.

[0074] In this embodiment, the first deep layer 14 is formed by ion implantation as described later. Furthermore, considering the processing limitations of photolithography during ion implantation, the width of each line constituting the strip-shaped portion 141, i.e., the length in the y-axis direction, is set to 0.3 μm or more, for example, 0.9 μm as described above. The width of each line constituting the strip-shaped portion 141 (hereinafter referred to as the width of the first deep layer 14) is as follows: Figure 4 As shown, the width of the two top portions 141a is greater than or equal to the width of the inner portion 141b, as detailed later. Furthermore, the width of the inner portion 141b is, for example, 0.9 μm, and the width of the top portions 141a is greater than or equal to this width. Therefore, the spacing between the lines constituting the strip-shaped portion 141, i.e., the width of the first current dispersing layer 13 along the y-axis direction (hereinafter referred to as the width of the first current dispersing layer 13), is less than or equal to the width of the portion at both ends of the first current dispersing layer 13 that is its inner side. Additionally, in Figure 4 In the diagram, the trench gate structure described later is indicated by dashed lines. Here, it is assumed that the top portion 141a overlaps with the trench gate structure, but this overlap is not mandatory.

[0075] A second current dispersion layer 15 is formed on the first current dispersion layer 13 and the first deep layer 14. The concentration of n-type impurities such as nitrogen and phosphorus in the second current dispersion layer 15 is, for example, 1.0 × 10⁻⁶. 16 ~5.0×10 17 The thickness is 0.5–2 μm. In this embodiment, besides the second current dispersing layer 15, n - The type layer 12 and the first current dispersing layer 13 also constitute part of the drift layer 16.

[0076] Furthermore, a plurality of second depth layers 17 are formed in the second current dispersing layer 15 such that the second current dispersing layer 15 extends through it. The concentration of p-type impurities such as Al in the second depth layers 17 is, for example, 2.0 × 10⁻⁶. 17 ~2.0×10 18 The thickness is equal to that of the second current dispersing layer 15. In this embodiment, the second deep layer 17 is provided in the form of strips with multiple lines arranged in the active region 1a where the MOSFET operates, extending along the y-axis and arranged at equal intervals along the x-axis. The strip-shaped portion in the second deep layer 17 corresponds to the second strip portion, which will be referred to as the strip portion 171 below. Each line of the strip portion 171 of the second deep layer 17 extends in a direction intersecting with the strip portion 141 of the first deep layer 14, and each line of the strip portion 171 is configured with a width of, for example, 0.7 to 1.6 μm.

[0077] In addition, such as Figure 3As shown, the second deep layer 17 is also formed in the non-active region 1b located between the active region 1a and the outer peripheral region 2. Near the active region 1a in the non-active region 1b, the second deep layer 17 has a structure with strip-shaped portions 171 identical to those in the active region 1a, and on its outer side, it extends to the boundary with the outer peripheral region 2 to form a frame-shaped portion 172. The frame-shaped portion 172 surrounds the strip-shaped portion 171 and connects to the lines constituting the strip-shaped portion 171.

[0078] Furthermore, the portions of each second deep layer 17 that intersect with the stripe portion 141 at the stripe portion 171 and those that overlap with the frame portion 142 at the frame portion 172 are respectively connected to the first deep layer 14. Additionally, the stripe portion 171 is formed in a manner that clamps the groove 21 described later. That is, the stripe portion 171 is formed away from the groove 21. Furthermore, since the second current dispersing layer 15 is positioned between the lines of the stripe portions 171 in the second deep layer 17, the second current dispersing layer 15 is also stripe-shaped.

[0079] A p-type base region 18 is formed on the second current dispersing layer 15 and the second deep layer 17. An n-type base region is formed on top of the base region 18. + Type 19 and p + The contact layer 20 is of the type described later. The source region 19 is disposed on both sides of the trench gate structure, and the contact layer 20 sandwiches the source region 19 and is disposed on the opposite side of the trench gate structure. Furthermore, in this embodiment, the source region 19 corresponds to the second impurity region.

[0080] The base region 18 has a p-type impurity concentration of Al, for example, 5.0 × 10⁻⁶. 16 ~2.0×10 19 / cm 3 It is constructed with a thickness of approximately 0.5 μm. The surface layer of the source region 19 contains, for example, 1.0 × 10⁻⁶ n-type impurities such as nitrogen and phosphorus, at a concentration of 1.0 × 10⁻⁶. 20 / cm 3 It is constructed with a thickness of approximately 0.3 μm. For example, the surface concentration of p-type impurities such as Al in the contact layer 20 is 1.0 × 10⁻⁶. 21 / cm 3 It is composed of a thickness of about 0.3μm.

[0081] Furthermore, a trench 21 with a width of, for example, 0.5 to 1.0 μm is formed such that it penetrates the base region 18 and the source region 19 to reach the second current dispersion layer 15, and its bottom surface is located within the second current dispersion layer 15. The trench 21 is formed such that it does not reach the first current dispersion layer 13 and the first deep layer 14, that is, the first current dispersion layer 13 and the first deep layer 14 are located below the bottom surface of the trench 21. In addition, since the trench 21 is formed to penetrate the base region 18 and the source region 19, the base region 18 and the source region 19 are in contact with the side surface of the trench 21.

[0082] The trench 21 is filled with a gate insulating film 22 formed on its inner wall surface and a gate electrode 23 made of doped polysilicon (Poly-Si) formed on the surface of the gate insulating film 22. This constitutes a trench gate structure. Although not particularly limited, the gate insulating film 22 is formed by thermal oxidation of the inner wall surface of the trench 21, and its thickness is about 100 nm on both the side and bottom sides of the trench 21.

[0083] In addition, trench 21 Figure 1 The groove 21 extends along the y-axis direction, i.e., the <-1120> direction, as its length direction. By extending the groove 21 in the <11-20> direction, the sidewall surface of the groove 21, i.e., the (1-100) surface, can be used as a channel, thus reducing the influence of channel migration rate dependence. Furthermore, as... Figure 3 As shown, the trenches 21 are arranged in multiple strips along the x-axis. Furthermore, the top of each trench 21 is semi-circular, with two adjacent trenches 21 forming a group, and the trenches 21 in each group are connected to each other at their tops. The source region 19 and the contact layer 20 extend along the extension direction of the trenches 21.

[0084] A source electrode 24 and a gate wiring (not shown) are formed on the surface of the source region 19, the contact layer 20, and the gate electrode 23. In this embodiment, the source electrode 24 corresponds to the first electrode.

[0085] The source electrode 24 and the gate wiring are made of multiple metals, such as Ni / Al, and at least the portion that contacts the n-type SiC (i.e., the source region 19, in the case of n-doped gate electrode 23) is made of a metal capable of ohmic contact with n-type SiC. Furthermore, the portions of the source electrode 24 and the gate wiring that contact the p-type SiC (i.e., the contact layer 20, in the case of p-doped gate electrode 23) are made of a metal capable of ohmic contact with p-type SiC.

[0086] Furthermore, these source electrodes 24 and gate wirings are electrically insulated by being formed on the interlayer insulating film 25. The source electrode 24 is electrically connected to the source region 19 and the contact layer 20 via contact holes 25a formed in the interlayer insulating film 25. Thus, the first deep layer 14 is maintained at the same potential as the source electrode 24 via the contact layer 20, the base region 18, and the second deep layer 17. Furthermore, in relation to... Figure 1 , Figure 2 In different cross-sections, the gate wiring is electrically connected to the gate electrode 23 via a contact hole 25a formed in the interlayer insulating film 25.

[0087] A drain electrode 26 electrically connected to the substrate 11 is formed on the back side of the substrate 11. Furthermore, in this embodiment, the substrate 11 functions as a drain layer. Additionally, in this embodiment, the drain electrode 26 corresponds to the second electrode.

[0088] As explained above, a MOSFET with an n-channel inverted trench gate structure is formed in cell region 1. Furthermore, as... Figure 3 As shown, in cell region 1, the portion with the trench gate structure, source region 19 and contact layer 20 is designated as active region 1a, and the area between active region 1a and outer peripheral region 2 is designated as non-active region 1b. Component operation is performed in active region 1a.

[0089] The outer peripheral region 2 is configured to enclose the active region 1a and the non-active region 1b within the unit region 1. In the outer peripheral region 2, as... Figure 2 and Figure 3 As shown, in n - On the type layer 12, a second deep layer 17 formed in the unit region 1 extends. Furthermore, in n - The surface portion of the first deep layer 14 is formed with a plurality of p-shaped protective rings 27 that are connected to the second deep layer 17 and surround the unit region 1. In this embodiment, the protective rings 27 and the first deep layer 14 have the same impurity concentration and the same depth.

[0090] The SiC semiconductor device of this embodiment is configured as described above. Next, details regarding the width of the first deep layer 14 and the width of the first current dispersing layer 13 will be explained.

[0091] As described above, the first deep layer 14 is a strip-shaped portion 141 with multiple lines arranged in the active region 1a. Furthermore, in the non-active region 1b, the first deep layer 14 is a frame-shaped portion 142 formed across its entire surface, except near the active region 1a, extending to the boundary with the outer peripheral region 2. Moreover, the width of the two end portions 141a of each line in the strip-shaped portion 141 of the first deep layer 14 is greater than or equal to the width of the inner portion 141b. That is, the width of both ends of the first current dispersing layer 13 is less than or equal to the width of its inner portion.

[0092] In this embodiment, the width of the inner portion 141b is set to a fixed size, for example, 0.9 μm, and the width of the top portion 141a gradually increases towards the top. Specifically, the top portion 141a gradually widens towards the top with an equal increase ratio on both sides in the width direction, and at the very top position, the width of the top portion 141a increases by about 0.1 to 0.2 μm on each side compared to the inner portion 141b. Therefore, the two sides of the top portion 141a are straight in the width direction. Furthermore, since the width of the top portion 141a gradually increases towards the top, conversely, the width of the top portion of the first current dispersing layer 13 gradually decreases towards the top, and the top shape is trapezoidal.

[0093] Next, the operation of the SiC semiconductor device configured as described above will be explained.

[0094] First, in the aforementioned SiC semiconductor device, in the off state before a gate voltage is applied to the gate electrode 23, no inversion layer is formed in the base region 18. Therefore, even if a positive voltage, such as 1600V, is applied to the drain electrode 26, electrons do not flow from the source region 19 into the base region 18, and no current flows between the source electrode 24 and the drain electrode 26.

[0095] Furthermore, before the gate voltage is applied to the gate electrode 23, an electric field acts between the drain and the gate, and electric field concentration may occur at the bottom of the gate insulating film 22. However, in the SiC semiconductor device described above, a first deep layer 14 and a first current dispersing layer 13 are provided at a depth deeper than the trench 21. Therefore, through the depletion layer formed between the first deep layer 14 and the first current dispersing layer 13, the high electric field caused by the drain voltage is difficult to penetrate into the gate insulating film 22. In particular, by setting the width of the top portion 141a of the first deep layer 14 to be greater than or equal to the width of the inner portion 141b, and setting the width of the top portion of the first current dispersing layer 13 to be less than or equal to the width of its inner portion, the rise of the equipotential line caused by the increased width of the top portion of the first current dispersing layer 13 can be suppressed, and the high electric field is even more difficult to penetrate into the gate insulating film 22. Therefore, in this embodiment, breakdown of the gate insulating film 22 can be suppressed.

[0096] Furthermore, if a predetermined gate voltage, such as 20V, is applied to the gate electrode 23, a channel is formed on the surface of the base region 18 that is in contact with the trench 21. Therefore, electrons injected from the source electrode 24 flow from the source region 19 through the channel formed in the base region 18 to the second current dispersion layer 15. And electrons flowing into the second current dispersion layer 15 pass through the first current dispersion layer 13 and flow to the n... -The current flows through the source electrode 12 and then through the substrate 11, which serves as the drain layer, to the drain electrode 26. As a result, current flows between the source electrode 24 and the drain electrode 26, and the SiC semiconductor device becomes conductive. Furthermore, in this embodiment, electrons that have passed through the channel pass through the second current dispersion layer 15, the first current dispersion layer 13, and the n-type current dispersion layer 16. - The current flows from the type layer 12 to the substrate 11, so the current is dispersed by the second current dispersion layer 15, the first current dispersion layer 13 and n - The type layer 12 constitutes the drift layer 16.

[0097] Next, refer to Figures 5A to 5G This embodiment describes a method for manufacturing a SiC semiconductor device. Additionally, Figures 5A to 5G It means equivalent to Figure 1 A cross-sectional perspective view of a portion of the manufacturing process.

[0098] First, such as Figure 5A As shown, prepare n + A substrate 11 of type 11. Furthermore, on the surface of this substrate 11, an n-type structure made of SiC is formed. - Layer 12 is epitaxially grown. Then, in n... - A mask (not shown) is formed on the surface of the first current dispersing layer 12, and the mask is patterned by photolithography or the like in a manner that opens the planned formation area of ​​the first current dispersing layer 13. Specifically, the mask is patterned so that only the cell region 1 is open. Then, n-type impurity ions such as nitrogen or phosphorus are implanted from the mask and heat-treated to form the first current dispersing layer 13 only in the cell region 1. The mask is then removed. For example, an LTO (Low Temperature Oxide) film is used as the mask. Furthermore, in this embodiment, masks are also used in the processes described later, and for each mask, an LTO film is used, for example.

[0099] In this embodiment, the first current dispersing layer 13 is formed by ion implantation. Therefore, compared with the case where the first current dispersing layer 13 is formed from an epitaxial film, the control of the impurity concentration of the first current dispersing layer 13 becomes easier, and deviations in characteristics can be suppressed.

[0100] Next, as Figure 5B As shown, a mask 3 is formed, and the mask 3 is patterned using photolithography or the like to open the planned formation area of ​​the first deep layer 14. At this time, although not shown, the mask 3 is also opened for the planned formation area of ​​the guard ring 27 regarding the outer peripheral region 2. Furthermore, p-type impurity ions such as Al are implanted from the mask 3 and heat-treated to form the first deep layer 14 and the guard ring 27. Although the first deep layer 14 and the guard ring 27 are formed in the same process here, they can also be formed through different processes.

[0101] In this embodiment, the lines of the strip-shaped portions 141 of the first deep layer 14 are configured such that the width of the top portion 141a is greater than or equal to the width of the inner portion 141b. That is, with Figure 4 The layout design of the mask 3 shown is such that the width of the portion of the opening of the mask 3 corresponding to the top portion 141a is larger than the width of the portion corresponding to the inner portion 141b. Even if the width of the top portion 141a is narrower than the design value, it is set to be greater than the width of the inner portion 141b.

[0102] Assuming in such Figure 6A As shown, if the mask 3 is designed so that the width of each line of the strip portion 141 is the same as the width of the top portion 141a as the inner portion 141b, the design value of the mask 3 after layout becomes Figure 6B The shape shown. That is, as shown. Figure 6B As shown, the portion of the opening 3a of the mask 3 corresponding to the top portion 141a narrows, and the mask 3 remains in a semi-circular shape at the position corresponding to the top portion of the first current dispersing layer 13. Figure 6C The actual appearance of the mask 3 is shown, revealing that the portion of the opening 3a corresponding to the top end 141a narrows. Furthermore, the white portion surrounding the opening 3a indicates the portion of the mask 3 that remains in a cone shape. Additionally, Figure 6A , Figure 6B Although not a cross-sectional view, the part that becomes mask 3 is shown with shadow lines for ease of understanding.

[0103] Thus, the portion of the opening 3a of the mask 3 corresponding to the tip portion 141a becomes a narrower residual state. Therefore, if p-type impurity ions are implanted using the mask 3, the tip portion 141a is formed with a narrower width than the inner portion 141b. Consequently, the tip portion of the first current dispersion layer 13 becomes a wider state, such as... Figure 7 As shown, the rise in electric field becomes uncontrollable in this region, resulting in drain-source leakage, a decrease in breakdown voltage, and a voltage rise at the bottom of the trench gate structure. Furthermore, a localized breakdown voltage region is created, failing to achieve avalanche withstand capability and switching withstand capability, leading to a reduction in the lifetime of the gate insulating film 22.

[0104] This phenomenon occurs because the density of the etchant solution during the etching process of the mask 3 near the top portion 141a is lower than in other areas, resulting in resist residue and preventing the formation of an opening along the shape of the top portion 141a. Since the mask 3 remains in a semi-circular shape at the position corresponding to the top portion of the first current dispersing layer 13, the width of the top portion 141a of each line of the strip portion 141 becomes narrower. The extent to which the spacing of each line of the strip portion 141 at the top portion 141a has actually increased was confirmed, and the result is an increase of 40-50% relative to the design value.

[0105] The relationship between the spacing of the lines in the strip 141 and the withstand voltage, as well as the electric field strength applied to the gate insulating film 22, was studied through simulation. Specifically, the spacing of each line was set to 100% as designed, and the withstand voltage and the electric field strength applied to the gate insulating film 22 were calculated when the spacing of each line increased. Figure 8A and Figure 8B The results are shown in these figures. It can be seen that when the spacing between the lines increases by 40% relative to the design value, i.e., becomes 140%, the withstand voltage decreases by approximately 400V relative to the design value of 1200V, while the electric field strength applied to the gate insulating film 22 increases by approximately 330%. Based on these simulation results, there is also concern about a reduction in the lifetime of the gate insulating film 22.

[0106] In contrast, in this embodiment, the width of the portion corresponding to the top end 141a in the opening of the mask 3 is larger than the width of the portion corresponding to the inner end 141b. Even if the width of the top end 141a is narrower than the design value, it is set to be greater than the width of the inner end 141b. Therefore, the top end of the first current dispersing layer 13 can be kept constant, and the rise of the electric field in that portion can be suppressed. Thus, the voltage drop and lifetime reduction of the gate insulating film 22 can be suppressed.

[0107] Next, as Figure 5C As shown, in n - A second current-dispersing layer 15, made of SiC, is epitaxially grown on the first current-dispersing layer 12, the first current-dispersing layer 13, and the first deep layer 14. This forms a structure with n... - The drift layer 16 of the first current dispersion layer 12, the first current dispersion layer 13, and the second current dispersion layer 15.

[0108] Next, a mask (not shown) is formed, and the mask is patterned using photolithography or the like to open the planned formation area of ​​the second deep layer 17. Then, p-type impurity ions such as Al are implanted onto the mask and heat-treated to form the second deep layer 17. At this time, the second deep layer 17 is extended in a direction intersecting the extension direction of the first deep layer 14. Therefore, even if there is slight misalignment during the formation of the second deep layer 17, the undesirable situation of the first deep layer 14 and the second deep layer 17 not being connected can be suppressed.

[0109] Next, as Figure 5D As shown, a base region 18 is formed on the second current dispersive layer 15 and the second deep layer 17 by epitaxially growing a p-type impurity layer. Next, a source region 19 is formed on the base region 18 by epitaxially growing an n-type impurity layer.

[0110] And, as Figure 5EAs shown, a mask (not shown) is formed, and the mask is patterned using photolithography or the like to create openings in the planned areas of the contact layer 20. Then, p-type impurity ions such as Al are implanted onto the mask and thermally treated to form the contact layer 20.

[0111] Next, as Figure 5F As shown, after forming a mask (not shown), the mask is patterned to open the planned formation area of ​​trench 21. Then, anisotropic etching is performed to form trench 21. Specifically, trench 21 is formed such that the source region 19 and base region 18 are connected and the bottom is located within the second current dispersing layer 15. That is, trench 21 is formed such that the first current dispersing layer 13 and the first deep layer 14 are below the bottom surface of trench 21. Furthermore, after anisotropic etching, isotropic etching and sacrificial layer oxidation can be performed as needed.

[0112] Next, as Figure 5G As shown, a gate insulating film 22 is formed in the area including the trench 21. For example, the gate insulating film 22 is formed by thermal oxidation, specifically by gate oxidation based on a pyrogenic method utilizing a humid atmosphere. Next, after forming a polysilicon layer doped with n-type impurities on the surface of the gate insulating film 22 at a temperature of 600°C and a thickness of 440 nm, an etching process is performed to leave the gate insulating film 22 and the gate electrode 23 in the trench 21. Thus, a trench gate structure is formed.

[0113] The subsequent processes are the same as those in the past, including the formation of the interlayer insulating film 25, the formation of the contact hole 25a, the formation of the source electrode 24 and the gate wiring, and the formation of the drain electrode 26 on the back side of the substrate 11. Therefore, they are not shown in the figures. Thus, the SiC semiconductor device of this embodiment is manufactured.

[0114] As explained above, in this embodiment, for each line of the strip 141 of the first deep layer 14, the width of the top portion 141a is greater than or equal to the width of the inner portion 141b. That is, even assuming that the portion of the mask 3 corresponding to the top portion 141a is narrower, the width of the top portion 141a can still be greater than or equal to the width of the inner portion 141b. Therefore, the top portion of the first current dispersing layer 13 can be kept constant, the rise of the electric field in that portion can be suppressed, and thus the decrease in the breakdown voltage and lifetime of the gate insulating film 22 can be suppressed.

[0115] (A variation of the first embodiment)

[0116] In the first embodiment described above, the width of the tip portion 141a gradually increases towards the tip, and both sides of the tip portion 141a are straight in the width direction. In other words, the tip of the first current dispersing layer 13 is trapezoidal. Alternatively, it can be as follows... Figure 9A As shown, for example, the top end of the first current dispersing layer 13 can be an ellipse including a circle, such that the width of the top end 141a gradually increases towards the top, and the two sides of the width direction of the top end 141a are elliptical arcs or other curves. Alternatively, it can be as follows... Figure 9B As shown, the width sides of the top portion 141a are straight lines, and the top of the first current dispersing layer 13 is triangular. Furthermore, the width sides of the top portion 141a may not be the same shape, and the expansion method may also be different.

[0117] Furthermore, in this embodiment, the length direction of each line in the strip portion 141 is orthogonal to the length direction of the trench grid structure, but it can also be an intersecting direction other than orthogonal, or it can be a parallel direction. In addition, when the length direction of each line in the strip portion 141 is parallel to the length direction of the trench grid structure, the spacing between each line and the forming interval that becomes the second deep layer 17 can be equal.

[0118] (Second Implementation)

[0119] The second embodiment will be described. In this embodiment, the layout of the strip-shaped portion 171 in the second deep layer 17 is specified, which is different from the first embodiment. Therefore, only the parts that are different from the first embodiment will be described.

[0120] In the first embodiment, a solution is provided to address the reduction in gate lifetime caused by the narrowing width at the tip of each line in the strip portion 141, resulting in a wider tip of the first current dispersing layer 13. On the other hand, as described above, it has been confirmed that the spacing between the frame portion 142 and the strip portion 141 is larger than the spacing between the lines constituting the strip portion 141. Even with this increased spacing between the frame portion 142 and the strip portion 141, the rise of the equipotential line cannot be suppressed, raising concerns about a reduction in gate lifetime. In this embodiment, a solution is provided to address this reduction in gate lifetime.

[0121] like Figure 10As shown, in this embodiment, the tip portion 171a of each line of the strip portion 171 in the second deep layer 17 is wider than the inner portion 171b located inside it. That is, the width of the second current dispersing layer 15 is narrower at both ends than its inner portion. For example, the inner portion 171b is about 0.7 to 1.6 μm, and the tip portion 171a, relative to the inner portion 171b, gradually increases in width towards the tip on both sides until it reaches a certain width. Therefore, the second current dispersing layer 15 is a rectangle with a certain width at the tip and a 90° corner at the tip. The increase in width of the tip portion 171a relative to the inner portion 171b is arbitrary, but preferably about 10 to 30%, for example, an increase of about 0.1 μm on each side in the width direction. Furthermore, the top portion 171a in the so-called second deep layer 17 is the portion located within the non-active region 1b. Within the non-active region 1b, the width of the top portion 171a is greater than the width of the inner portion 171b.

[0122] The starting point for expanding the top portion 171a is arbitrary, but preferably it starts from the line closest to the frame portion 142 in the strip portion 141 of the first deep layer 14.

[0123] As described above, the spacing between the frame-shaped portion 142 and the strip-shaped portion 141 may be larger than the spacing between the lines constituting the strip-shaped portion 141. It is possible that the rise of the equipotential line cannot be suppressed even between the frame-shaped portion 142 and the strip-shaped portion 141 with this increased spacing, thereby reducing the gate lifetime.

[0124] In contrast, in this embodiment, the top portion 171a of the second deep layer 17 is also wider than the inner portion 171b. Therefore, the gap between the frame-shaped portion 142 and the strip-shaped portion 141 of the second deep layer 17 can be narrowed. Thus, even if the electric field mitigation effect of the first deep layer 14 is reduced due to the expansion between the frame-shaped portion 142 and the strip-shaped portion 141, the electric field mitigation effect of the second deep layer 17 can push back the equipotential line, making it difficult for a high electric field to penetrate. This suppresses the decrease in breakdown voltage and lifetime of the gate insulating film 22.

[0125] (A variation of the second embodiment)

[0126] In the second embodiment described above, the width of the tip portion 171a gradually increases towards the tip and then becomes a fixed width. In other words, the tip of the second current dispersing layer 15 is rectangular, meaning the corners of the tip are 90 degrees. Alternatively, it could be as follows... Figure 11A As shown, the width sides of the top portion 171a are straight, and the top of the first current dispersing layer 13 is triangular. Alternatively, it can be as follows... Figure 11BAs shown, the width of the top portion 171a gradually increases towards the top, and the two sides of the top portion 171a in the width direction are curved in an arc shape, for example, the top of the first current dispersing layer 13 is made into an ellipse including a circle. Furthermore, the two sides of the top portion 171a in the width direction may not be the same shape, and the expansion method may also be different.

[0127] (Third Implementation)

[0128] The third embodiment will be described. This embodiment changes the layout of the strip portion 141 in the first deep layer 14 compared to the first and second embodiments. The rest is the same as the first and second embodiments, so only the parts that are different from the first and second embodiments will be described.

[0129] In a configuration where the strip 141 of the first deep layer 14 intersects with the strip 171 of the second deep layer 17, the portion of the strip 141 that intersects with the trench gate configuration becomes an obstacle to the current path. This increases the on-resistance. In this embodiment, measures are taken to address this increase in on-resistance.

[0130] like Figure 12 As shown, in this embodiment, the strip-shaped portion 141 intersects with the trench grid structure, and each of the locally rectangular short strips is truncated by a missing portion 14a, making each line a dashed line. Furthermore, by allowing the trench grid structure to pass through the missing portion 14a, a path for current flow is ensured in that portion.

[0131] The location of the missing portions 14a provided for each line in the strip-shaped portion 141 is arbitrary, but preferably as follows: Figure 12 The arrangement is staggered as shown. That is, in adjacent lines, the missing portions 14a are formed by offsetting the groove grid structures along the length of the line by an interval, and every other line, the missing portion 14a is formed in the portion corresponding to the same groove grid structure. In this way, the strip-shaped portions 141 can be arranged at a position below each groove grid structure every other line, and the in-plane distribution of the missing portions 14a is uniform.

[0132] As explained above, in this embodiment, the strip 141 intersects with the trench grid structure, and each line is partially cut off by a missing portion 14a, allowing the trench grid structure to pass through the missing portion 14a. In this way, the intersection portion between the first deep layer 14 and the trench grid structure can be reduced compared to the first and second embodiments, and the increase in conduction resistance can be suppressed.

[0133] Here, the size of the missing portion 14a of the lines in the strip 141, i.e., the spacing between the lines that are truncated in the length direction, is preferably 2.6 μm or less. The breakdown voltage was studied by varying the size of this missing portion 14a. Specifically, the drain voltage Vd at which gate breakdown occurs was determined based on the change in the gate current Ig. Figure 13 The graph represents the results, showing the results for cases where the line spacing is 2.6μm, 4.8μm, and 9.6μm.

[0134] like Figure 13 As shown, the larger the spacing between the lines, the lower the breakdown voltage. Furthermore, if a breakdown voltage of 950V is preferred for a SiC semiconductor device, then a spacing of at least 2.6μm or less between the lines can satisfy this requirement. Of course, the spacing between the lines can be set to a lower limit based on the required breakdown voltage; if the required breakdown voltage is 950V or less, a spacing of 4.8μm between the lines is also possible.

[0135] Furthermore, while the spacing between lines truncated in the length direction is described here, this spacing can be said to be the same in the y-direction spacing of lines arranged every other adjacent line in the missing portion 14a. That is, Figure 12 The diameter φ of the circle centered on the center of the missing part 14a, as shown by the dashed line, is set to φ2.6μm. It can be a layout in which lines exist on both sides, either grounded to the circle or adjacent to the missing part 14a on its inner side.

[0136] (A variation of the third embodiment)

[0137] In the third embodiment described above, the angle of the corner of each line dividing the strip 141 is 90°, and each cut-off portion is a short rectangular strip. Alternatively, each cut-off portion of the line can be shaped such that its width gradually decreases towards the top, for example... Figure 14A As shown, it includes semi-circular ovals, Figure 14B A triangle as shown. Furthermore, the width of the top of each truncated section of the lines may not be the same on both sides.

[0138] Alternatively, instead of making the truncated portions of each line into short strips as in the third embodiment, they can be made into dots. Specifically, each dot can be set as an ellipse including a circle. For example, if as in... Figure 15A By making each point a circle as shown, the lines constituting the strip 141 can be arranged in a dotted pattern. Alternatively, each point can be a polygon. For example, if... Figure 15BBy making each point hexagonal as shown, the lines constituting the strip 141 can be arranged in a honeycomb pattern. In this way, even if the truncated portions of each line constituting the strip 141 are made into points, the withstand voltage can be ensured and the increase in on-resistance can be reduced.

[0139] (Fourth implementation)

[0140] The fourth embodiment will be described. This embodiment changes the deep structure compared to the first to third embodiments, but is otherwise the same as the first to third embodiments. Therefore, only the parts that are different from the first to third embodiments will be described.

[0141] In the first to third embodiments described above, the deep layer is a two-layer structure with the first deep layer 14 and the second deep layer 17 overlapping. However, it has been found that the forward voltage Vf varies due to the influence of holes generated when the PN diode formed by the parasitic ground is energized. Furthermore, it has been found that in the case of the deep layer with the two-layer structure of the first deep layer 14 and the second deep layer 17, the basal dislocations (hereinafter referred to as BPDs) present in SiC expand into stacking faults, becoming a factor that hinders the current path and increases the on-resistance. In this embodiment, these variations in the forward voltage Vf and the increase in on-resistance are addressed.

[0142] like Figure 16 As shown, in this embodiment, a third deep layer 30 is provided. That is, the deep layer has a three-layer structure, which includes a first deep layer 14, a second deep layer 17, and a third deep layer 30.

[0143] In this embodiment, the third deep layer 30 is disposed below the first current dispersing layer 13 and the first deep layer 14. Specifically, the third deep layer 30 is disposed below the first deep layer 14, at a position corresponding to the second current dispersing layer 15, that is, directly below the trench gate structure. Regarding the third deep layer 30, it may also be formed on n - Within layer 12, this area is adjacent to the third deep layer 30 and possesses the characteristics of n. - The third current dispersing layer 31 has a higher concentration of n-type impurities than the n-type layer 12. Both the third deep layer 30 and the third current dispersing layer 31 are configured to have strip-shaped portions in which multiple lines are arranged in a strip shape, and the lines constituting each strip-shaped portion are arranged alternately.

[0144] Furthermore, the third deep layer 30 is configured as a strip-shaped portion in the active region 1a, with multiple lines arranged in the same direction as the length direction of the trench 21. This strip-shaped portion in the third deep layer 30 is equivalent to the third strip-shaped portion. In addition, although not shown, the third deep layer 30 is configured as a strip-shaped portion only on the active region 1a side in the non-active region 1b, and in the region outside it, the entire surface is formed to the outer peripheral region 2, forming a frame-shaped portion that surrounds the strip-shaped portion, but it may also be just a strip-shaped portion.

[0145] The SiC semiconductor device of this embodiment includes a MOSFET. The MOSFET has a parasitic PN diode parasitically formed in its structure. Specifically, a parasitic PN diode is formed by a PN junction of a p-type layer (such as the base region 18) and an n-type layer (such as the second current dispersing layer 15) that forms a drift layer. Therefore, when the MOSFET is used in an inverter or similar device, by using this parasitic PN diode as a freewheeling diode, a separate freewheeling diode can be eliminated, thus reducing the number of components (hereinafter, this parasitic PN diode is referred to as the parasitic FWD).

[0146] Here, when the parasitic FWD operates as a diode, holes, which diffuse from the base region 18 side into the drift layer and become minority carriers, recombine with electrons in the drift layer. Due to the influence of holes generated when the parasitic FWD is energized, the forward voltage Vf fluctuates, affecting device operation. Furthermore, due to the energy of hole-electron recombination, the BPD in the drift layer formed by the epitaxial film is amplified and becomes a stacking fault. Since BPDs are linear defects, they occupy a small area in the cell region of the semiconductor device and have almost no impact on device operation. However, if they become stacking faults, their area in the cell region increases, and their impact on device operation increases. In particular, if a large current flows through the parasitic FWD, holes will reach the substrate 11, etc., located below the drift layer. The BPD defect density in the substrate 11 is significantly larger than that in the drift layer, so the area occupied by stacking faults further increases, increasing the on-resistance.

[0147] In contrast, the SiC semiconductor device of this embodiment has a three-layer structure, comprising a first deep layer 14, a second deep layer 17, and a third deep layer 30. By having a three-layer structure for the deep layers, holes generated in the base region 18, such as... Figure 17 As shown by the middle arrow, the movement path of holes from the second current dispersion layer 15 through the first current dispersion layer 13 and through the third current dispersion layer 31. Therefore, in the case of a 3-layer structure, compared with the case of a 2-layer structure, corresponding to the amount shown by the dashed line in the figure, the movement path of holes becomes longer, allowing more holes to recombine and disappear. Thus, holes disappear before reaching the substrate 11, suppressing fluctuations in the positive voltage Vf due to the influence of holes. Furthermore, the propagation of BPD towards stacking faults can be suppressed. In particular, since the third deep layer 30 is adjacent to n - Compared to the third current dispersion layer 31, which has a higher concentration of n-type impurities, the n-type layer 12 can further facilitate hole recombination and easy disappearance, thus further suppressing the formation of stacking faults.

[0148] As explained above, in the SiC semiconductor device of this embodiment, the deep layers are configured as a three-layer structure, including a first deep layer 14, a second deep layer 17, and a third deep layer 30. This suppresses the influence of changes in the forward voltage Vf on device operation, inhibits the propagation of BPD towards stacking faults, and suppresses the increase in on-resistance.

[0149] (A variation of the fourth embodiment)

[0150] In the first embodiment described above, an example of a three-layer structure is shown, but other three-layer structures are also possible. For example, it is possible to set it to... Figure 18 The structure shown. Figure 18 The structure shown is Figure 16 Compared to the structure shown, the spacing between the lines forming the strip-shaped portions in the third deep layer 30 and the third current dispersing layer 31 is narrower. Specifically, compared to the spacing between the lines forming the strip-shaped portions 171 in the second deep layer 17 and the strip-shaped second current dispersing layer 15, the spacing between the lines forming the strip-shaped portions in the third deep layer 30 and the third current dispersing layer 31 is narrower.

[0151] Under this configuration, the holes generated in the base region 18 are also as Figure 19 As shown, the hole travels from the second current dispersion layer 15 through the first current dispersion layer 13 and then through the third current dispersion layer 31. Therefore, the hole's travel path is lengthened, allowing more holes to recombine and disappear, achieving the same effect as in the fourth embodiment.

[0152] In addition, it can also be set to Figure 20 The structure shown. Figure 20 The structure shown is relative to Figure 16 Instead of placing the second deep layer 17 at a position away from the trench gate structure, it is placed directly below the trench gate structure. The second deep layer 17 is positioned in contact with the bottom of the trench 21, and the second current dispersing layer 15 is positioned on both sides of the trench gate structure. Furthermore, the structure is configured such that the second current dispersing layer 15 is in contact with the side of the trench 21 at a position lower than the base region 18 on the side of the trench gate structure, that is, the second current dispersing layer 15 exists between the base region 18 and the second deep layer 17.

[0153] Furthermore, when the second deep layer 17 is positioned directly below the trench gate structure, it is necessary to connect the second deep layer 17 to the base region 18. Therefore, the contact layer 20 is formed to intersect the trench gate structure and reach the depth of the second deep layer 17. For example, a trench is formed that penetrates both the source region 19 and the base region 18, reaching the depth of the second deep layer 17. Then, p is filled into the trench. +The film is formed by etching back the mold layer or by high-acceleration ion implantation using a mask not shown. Figure 20 The contact layer 20 shown is constructed as described.

[0154] Under this configuration, the holes generated in the base region 18 are also as Figure 21 As shown, the hole travels through the second current dispersion layer 15, bypasses the second deep layer 17, passes through the first current dispersion layer 13, and then moves towards the third current dispersion layer 31. Therefore, the hole's travel path is lengthened, allowing more holes to recombine and disappear, achieving the same effect as in the fourth embodiment.

[0155] Furthermore, in the case where the second deep layer 17 is positioned directly below the trench gate structure, such as Figure 22 As shown, it can also be configured such that the second deep layer 17 exits from the bottom of the trench 21. In such a configuration, the holes generated in the base region 18 are also as... Figure 23 As shown, the hole travels through the second current dispersion layer 15, bypasses the second deep layer 17, passes through the first current dispersion layer 13, and then moves towards the third current dispersion layer 31. Therefore, the hole's travel path is lengthened, allowing more holes to recombine and disappear, achieving the same effect as in the fourth embodiment.

[0156] In addition, Figure 20 , Figure 22 In the construction shown, as Figure 18 As shown, the spacing between the lines constituting the strip-shaped portions in the third deep layer 30 and the third current dispersing layer 31 is narrower. Alternatively, as in the fourth embodiment, the spacing between the lines constituting the strip-shaped portions 171 of the second deep layer 17 and the strip-shaped second current dispersing layer 15 can be the same as the spacing between the lines constituting the strip-shaped portions in the third deep layer 30 and the third current dispersing layer 31.

[0157] (Other implementation methods)

[0158] The present disclosure has been described based on the above embodiments, but is not limited to these embodiments, and includes various modifications and equivalent variations. In addition, various combinations and forms, and even combinations and forms that include only one element or more of them, also fall within the scope and spirit of the present disclosure.

[0159] For example, in the embodiments described above, an n-channel MOSFET with an n-type first conductivity type and a p-type second conductivity type was used as an example. However, this disclosure can also be applied to p-channel MOSFETs where the conductivity types of each component are reversed. Furthermore, in the embodiments described above, a trench-gate MOSFET was used as an example of a semiconductor switching element. However, this disclosure can also be applied to IGBTs with the same trench-gate structure. The IGBT differs from the embodiments described above only in that the conductivity type of the substrate 11 is changed from n-type to p-type; the other structures and manufacturing methods are the same as in the embodiments described above.

[0160] Furthermore, in the above embodiments, the strip-shaped portion 141 of the first deep layer 14 may, for example, extend along the y-axis direction. That is, the first deep layer 14 may also extend in the same direction as the second deep layer 17. Furthermore, in the above embodiments, the second current dispersing layer 15 may, for example, extend along the y-axis direction. - The type layer 12 has the same impurity concentration. In addition, the first current dispersion layer 13 may be formed not only in the unit region 1 but also in the outer peripheral region 2.

[0161] Furthermore, in the above embodiments, a frame-shaped portion 172 is provided for the second deep layer 17 in the non-active region 1b, but as long as the first deep layer 14 has a frame-shaped portion 142, the second deep layer 17 may only be a strip-shaped portion 171.

[0162] Furthermore, in the above embodiments, a SiC semiconductor device using SiC as the semiconductor material has been described as an example. However, for semiconductor devices using other semiconductor materials such as Si, the same effect can be obtained by applying the same structure as in the above embodiments.

[0163] Furthermore, while the above embodiments describe the case where the substrate 11 constitutes a semiconductor region, the semiconductor region may not necessarily be constituted by the substrate 11. For example, when silicon is used as the semiconductor material, the portion corresponding to the first impurity region can be formed using a silicon substrate, and a high-concentration region with a higher impurity concentration than the silicon substrate can be formed on the back side of the silicon substrate by ion implantation or the like. In this case, the high-concentration region formed on the back side of the silicon substrate constitutes the semiconductor region.

[0164] In addition, when indicating the orientation of a crystal, a horizontal bar (-) should normally be added above the desired number, but due to the limitations of electronic application representation, a horizontal bar is added before the desired number in this specification.

Claims

1. A semiconductor device having an active region and an active region surrounding the active region, wherein the active region is configured to form semiconductor switching elements having a plurality of trench gate structures for element operation, and the active region does not perform element operation, characterized in that, The semiconductor switching element described above has the following characteristics: Semiconductor regions of the first or second conductivity type; A first impurity region of a first conductivity type is formed on the semiconductor region, and the impurity concentration is lower than that of the semiconductor region. The base region of the second conductivity type is formed on the first impurity region mentioned above; The second impurity region of the first conductivity type is formed on the base region, and the impurity concentration is higher than that of the first impurity region. The plurality of the above-mentioned trench gate structures have a gate insulating film formed on the inner wall surface of the trench and a gate electrode formed on the gate insulating film in the trench, wherein the trench is formed from the surface of the second impurity region to a position deeper than the base region in one direction as the length direction. The first electrode is electrically connected to the second impurity region and to the base region; and The second electrode is formed on the back side of the semiconductor region and is electrically connected to the semiconductor region. The aforementioned semiconductor device also includes: A first current-dispersing layer of the first conductivity type is formed between the first impurity region and the base region, and the impurity concentration is higher than that of the first impurity region. The first deep layer of the second conductivity type has a first strip-shaped portion and a frame-shaped portion. The first strip-shaped portion extends in one direction as the length direction in the active region and the non-active region, and is arranged with multiple lines. The frame-shaped portion is formed in the non-active region, surrounds the first strip-shaped portion and is connected to each line constituting the first strip-shaped portion. The second deep layer of the second conductivity type has a second strip-shaped portion, which is formed between the first deep layer and the first current dispersing layer and the base region in the active region and the non-active region, and is connected to the base region and the first deep layer. The second strip-shaped portion has a plurality of lines extending in the same direction as the length direction of the trench. A second current-dispersing layer of the first conductivity type is formed between the first current-dispersing layer and the base region, and disposed between the plurality of lines constituting the second strip portion. Each line constituting the first strip-shaped portion includes a top portion connected to the frame-shaped portion and an inner portion that is closer to the inside of the top portion, wherein the width of the top portion is greater than or equal to the width of the inner portion.

2. The semiconductor device as claimed in claim 1, characterized in that, The width of the aforementioned top portion gradually increases towards the top, and the top of the aforementioned first current dispersion layer is one of trapezoidal, triangular, or elliptical shapes.

3. The semiconductor device as claimed in claim 1, characterized in that, The length direction of the aforementioned groove intersects with the length direction of each line constituting the aforementioned first strip-shaped portion of the aforementioned first deep layer; Each line constituting the first strip-shaped portion is cut off by a missing portion, thus becoming a dashed line. The groove grid structure is a structure that passes through the missing portion provided on each of the above lines.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The third deep layer having a second conductivity type is disposed below the first deep layer and the first current dispersing layer. The third deep layer has a third strip-shaped portion having a plurality of lines arranged extending in the same direction as the length direction of the trench.

5. A semiconductor device having an active region and an active region surrounding the active region, wherein the active region is configured to form a semiconductor switching element having a plurality of trench gate structures for element operation, and the active region does not perform element operation, characterized in that... The semiconductor switching element described above has the following characteristics: Semiconductor regions of the first or second conductivity type; A first impurity region of a first conductivity type is formed on the semiconductor region, and the impurity concentration is lower than that of the semiconductor region. The base region of the second conductivity type is formed on the first impurity region mentioned above; The second impurity region of the first conductivity type is formed on the base region, and the impurity concentration is higher than that of the first impurity region. The plurality of the above-mentioned trench gate structures have a gate insulating film formed on the inner wall surface of the trench and a gate electrode formed on the gate insulating film in the trench, wherein the trench is formed from the surface of the second impurity region to a position deeper than the base region in one direction as the length direction. The first electrode is electrically connected to the second impurity region and to the base region; and The second electrode is formed on the back side of the semiconductor region and is electrically connected to the semiconductor region. The aforementioned semiconductor device also includes: A first current-dispersing layer of the first conductivity type is formed between the first impurity region and the base region, and the impurity concentration is higher than that of the first impurity region. The first deep layer of the second conductivity type has a first strip-shaped portion and a frame-shaped portion. The first strip-shaped portion extends in one direction as the length direction in the active region and the non-active region, and is arranged with multiple lines. The frame-shaped portion is formed in the non-active region, surrounds the first strip-shaped portion and is connected to each line constituting the first strip-shaped portion. The second deep layer of the second conductivity type has a second strip-shaped portion, which is formed between the first deep layer and the first current dispersing layer and the base region in the active region and the non-active region, and is connected to the base region and the first deep layer. The second strip-shaped portion has a plurality of lines extending in the same direction as the length direction of the trench. A second current-dispersing layer of the first conductivity type is formed between the first current-dispersing layer and the base region, and disposed between the plurality of lines constituting the second strip portion. Each line constituting the second strip-shaped portion includes a top portion and an inner portion that is closer to the inside of the top portion, wherein the width of the top portion is greater than the width of the inner portion.

6. The semiconductor device as claimed in claim 5, characterized in that, The width of the aforementioned top portion gradually increases towards the top, and the top of the aforementioned second current dispersion layer is one of a rectangle, triangle, or ellipse.

7. The semiconductor device as claimed in claim 5, characterized in that, The length direction of the aforementioned groove intersects with the length direction of each line constituting the aforementioned first strip-shaped portion of the aforementioned first deep layer; Each line constituting the first strip-shaped portion is cut off by a missing portion, thus becoming a dashed line. The groove grid structure is a structure that passes through the missing portion provided on each of the above lines.

8. The semiconductor device according to any one of claims 5 to 7, characterized in that, The third deep layer having a second conductivity type is disposed below the first deep layer and the first current dispersing layer. The third deep layer has a third strip-shaped portion having a plurality of lines arranged extending in the same direction as the length direction of the trench.

9. A semiconductor device having an active region and an active region surrounding the active region, wherein the active region is configured to form semiconductor switching elements having a plurality of trench gate structures for element operation, and the active region does not perform element operation, characterized in that, The semiconductor switching element described above has the following characteristics: Semiconductor regions of the first or second conductivity type; A first impurity region of a first conductivity type is formed on the semiconductor region, and the impurity concentration is lower than that of the semiconductor region. The base region of the second conductivity type is formed on the first impurity region mentioned above; The second impurity region of the first conductivity type is formed on the base region, and the impurity concentration is higher than that of the first impurity region. The plurality of the above-mentioned trench gate structures have a gate insulating film formed on the inner wall surface of the trench and a gate electrode formed on the gate insulating film in the trench, wherein the trench is formed from the surface of the second impurity region to a position deeper than the base region in one direction as the length direction. The first electrode is electrically connected to the second impurity region and to the base region; and The second electrode is formed on the back side of the semiconductor region and is electrically connected to the semiconductor region. The above-mentioned semiconductor device has: A first current-dispersing layer of the first conductivity type is formed between the first impurity region and the base region, and the impurity concentration is higher than that of the first impurity region. The first deep layer of the second conductivity type has a first strip-shaped portion and a frame-shaped portion. The first strip-shaped portion extends in one direction as the length direction in the active region and the non-active region, and is arranged with multiple lines. The frame-shaped portion is formed in the non-active region, surrounds the first strip-shaped portion and is connected to each line constituting the first strip-shaped portion. The second deep layer of the second conductivity type has a second strip-shaped portion, which is formed between the first deep layer and the first current dispersing layer and the base region in the active region and the non-active region, and is connected to the base region and the first deep layer. The second strip-shaped portion has a plurality of lines extending in the same direction as the length direction of the trench. A second current-dispersing layer of the first conductivity type is formed between the first current-dispersing layer and the base region, and disposed between the plurality of lines constituting the second strip portion. The length direction of the aforementioned groove intersects with the length direction of each line constituting the aforementioned first strip-shaped portion of the aforementioned first deep layer; Each line constituting the first strip-shaped portion is cut off by a missing portion, thus becoming a dashed line. The groove grid structure is a structure that passes through the missing portion provided on each of the above lines.

10. The semiconductor device as claimed in claim 9, characterized in that, The size of the missing portion of each of the above lines is less than 2.6 μm; The layout is set as follows: the diameter φ of the circle centered on the center of the missing part of each of the above lines is set to 2.6μm, and there are two lines arranged adjacent to each other, either grounded to the circle or sandwiched between the missing parts inside the circle.

11. The semiconductor device as claimed in claim 9 or 10, characterized in that, The truncated portions of the above-mentioned dashed lines are short strips, and the missing portions of adjacent lines are staggered and interleaved along the length of the lines.

12. The semiconductor device as claimed in claim 9 or 10, characterized in that, The truncated portions of the above-mentioned dashed lines are circular dots, and the missing portions of adjacent lines are staggered and interleaved along the length of the lines.

13. The semiconductor device as claimed in claim 9 or 10, characterized in that, The truncated portions of the dashed lines are points of polygons, and the missing portions of adjacent lines are staggered along the length of the lines.

14. The semiconductor device as claimed in claim 9 or 10, characterized in that, The third deep layer having a second conductivity type is disposed below the first deep layer and the first current dispersing layer. The third deep layer has a third strip-shaped portion having a plurality of lines arranged extending in the same direction as the length direction of the trench.

15. A semiconductor device having an active region and an active region surrounding the active region, wherein the active region is configured to form semiconductor switching elements having a plurality of trench gate structures for element operation, and the active region does not perform element operation, characterized in that, The semiconductor switching element described above has the following characteristics: Semiconductor regions of the first or second conductivity type; A first impurity region of a first conductivity type is formed on the semiconductor region, and the impurity concentration is lower than that of the semiconductor region. The base region of the second conductivity type is formed on the first impurity region mentioned above; The second impurity region of the first conductivity type is formed on the base region, and the impurity concentration is higher than that of the first impurity region. The plurality of the above-mentioned trench gate structures have a gate insulating film formed on the inner wall surface of the trench and a gate electrode formed on the gate insulating film in the trench, wherein the trench is formed from the surface of the second impurity region to a position deeper than the base region in one direction as the length direction. The first electrode is electrically connected to the second impurity region and to the base region; and The second electrode is formed on the back side of the semiconductor region and is electrically connected to the semiconductor region. The aforementioned semiconductor device also includes: A first current-dispersing layer of the first conductivity type is formed between the first impurity region and the base region, and the impurity concentration is higher than that of the first impurity region. The first deep layer of the second conductivity type has a first strip-shaped portion and a frame-shaped portion. The first strip-shaped portion extends in one direction as the length direction in the active region and the non-active region, and is arranged with multiple lines. The frame-shaped portion is formed in the non-active region, surrounds the first strip-shaped portion and is connected to each line constituting the first strip-shaped portion. The second deep layer of the second conductivity type has a second strip-shaped portion, which is formed between the first deep layer and the first current dispersing layer and the base region in the active region and the non-active region, and is connected to the base region and the first deep layer. The second strip-shaped portion is arranged with a plurality of lines extending in the same direction as the length direction of the trench. A second current-dispersing layer of the first conductivity type is formed between the first current-dispersing layer and the base region, and disposed between the plurality of lines constituting the second strip portion; and The third deep layer of the second conductivity type is disposed below the first deep layer and the first current dispersing layer, and has a third strip-shaped portion having a plurality of lines arranged in a direction that extends in the same direction as the length direction of the trench.

16. The semiconductor device as claimed in claim 15, characterized in that, Each line constituting the third strip is positioned at a position corresponding to the second current dispersion layer.

17. The semiconductor device as claimed in claim 15, characterized in that, The formation interval of the lines constituting the third stripe is narrower than the formation interval of the lines constituting the second stripe.

18. The semiconductor device according to any one of claims 15 to 17, characterized in that, It has a third current-dispersing layer of a second conductivity type disposed between the lines constituting the third strip portion and having a higher concentration than the first impurity region.

19. The semiconductor device according to any one of claims 15 to 17, characterized in that, Each line constituting the second strip extends directly below the groove.

20. The semiconductor device as claimed in claim 19, characterized in that, The lines constituting the second strip are arranged directly below the groove and connected to it.

21. The semiconductor device as claimed in claim 19, characterized in that, The lines constituting the second strip are arranged directly below the groove and exit from the groove.

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