Package and method of forming the same

Abstract

An embodiment is a package comprising: a package substrate; a package assembly bonded to the package substrate, the package assembly comprising: an interposer; an optical die bonded to the interposer, the optical die comprising an optical coupler; and an integrated circuit die bonded to the interposer adjacent to the optical die; a lens adapter bonded to the optical die with a first optical glue; a mirror bonded to the lens adapter with a second optical glue, the mirror aligned with the optical coupler of the optical die; and an optical fiber located on the lens adapter, a first end of the optical fiber facing the mirror, the optical fiber configured such that an optical data path extends from the first end of the optical fiber through the mirror, the second optical glue, the lens adapter, and the first optical glue to the optical coupler of the optical die. Embodiments of the present application also relate to methods of forming a package.

Description

Technical Field

[0001] Embodiments of this application relate to packages and methods of forming the same. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, these improvements in integration density stem from iterative reductions in the minimum component size, allowing more components to be integrated into a given area. The increasing demand for miniaturized electronics has led to a need for smaller and more innovative semiconductor die packaging technologies. Summary of the Invention

[0003] Some embodiments of this application provide a package comprising: a package substrate; a package assembly bonded to the package substrate, the package assembly including: an interposer; an optical die bonded to the interposer, the optical die including an optical coupler; and an integrated circuit die bonded to the interposer adjacent to the optical die; a lens adapter bonded to the optical die with a first optical adhesive; a mirror bonded to the lens adapter with a second optical adhesive, the mirror being aligned with the optical coupler of the optical die; and an optical fiber located on the lens adapter, a first end of the optical fiber facing the mirror, the optical fiber being configured such that an optical data path extends from the first end of the optical fiber through the mirror, the second optical adhesive, the lens adapter, and the first optical adhesive to the optical coupler of the optical die.

[0004] Other embodiments of this application provide a package comprising: a package substrate; a package assembly bonded to the package substrate; a heat sink attached to the package substrate and covering the package assembly, the heat sink including an opening in which a portion of the package assembly is located; a lens adapter located in the opening of the heat sink and attached to the package assembly; a mirror located in the opening of the heat sink and attached to the lens adapter; and an optical fiber extending into the opening in the heat sink, the optical fiber being located on the lens adapter, wherein the package assembly includes: an optical die including an optical coupler adjacent to a first sidewall of the optical die, the first sidewall of the optical die and a first sidewall of the package assembly being located in the opening of the heat sink, a first end of the optical fiber facing the mirror, the optical fiber being configured such that an optical data path extends from the first end of the optical fiber through the mirror and the lens adapter to the optical coupler of the optical die.

[0005] Further embodiments of this application provide a method for forming a package, comprising: forming a package assembly, wherein forming the package assembly includes: bonding an optical die to an interposer, the optical die including an optical coupler adjacent to a first sidewall of the optical die; bonding a logic die to the interposer; depositing a first underfill between the optical die, the logic die, and the interposer; and forming a sealant on the optical die, the logic die, and the first underfill; bonding the package assembly to a package substrate; and attaching a heat sink to the package substrate and the package assembly. The heat sink includes an opening in which a portion of the encapsulation assembly is located; a support structure is attached to the encapsulation substrate in the opening of the heat sink; a lens adapter is attached to the portion of the encapsulation assembly located in the opening and the support structure in the opening; a mirror is attached to the lens adapter; and an optical fiber is attached to the mirror, the optical fiber being located on the lens adapter, the optical fiber being configured such that an optical data path extends from a first end of the optical fiber through the mirror and the lens adapter to the optical coupler of the optical die. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 A cross-sectional view of an integrated circuit die according to some embodiments is shown.

[0008] Figure 2 A cross-sectional view of an integrated circuit die according to some embodiments is shown.

[0009] Figure 3 A cross-sectional view of an integrated circuit die according to some embodiments is shown.

[0010] Figures 4 to 9 , Figure 10A , Figure 10B and Figures 11 to 15 Plan and cross-sectional views of intermediate stages in the manufacturing of packaged components according to some embodiments are shown.

[0011] Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 17E , Figure 17F , Figure 17G , Figure 17H , Figure 18A , Figure 18B and Figure 18C An enlarged cross-sectional view of a packaged component according to some embodiments is shown.

[0012] Figure 19 A cross-sectional view of a packaged component according to some embodiments is shown.

[0013] Figure 20 A cross-sectional view of a packaged component according to some embodiments is shown.

[0014] Figure 21 A cross-sectional view of a packaged component according to some embodiments is shown.

[0015] Figure 22 A cross-sectional view of a packaged component according to some embodiments is shown.

[0016] Figure 23 A cross-sectional view of a packaged component according to some embodiments is shown.

[0017] Figure 24 A cross-sectional view of a packaged component according to some embodiments is shown.

[0018] Figure 25 A cross-sectional view of a packaged component according to some embodiments is shown. Detailed Implementation

[0019] The following disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to limit this disclosure. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0021] The embodiments, namely integrated circuit packages and methods of forming thereof, will be described with reference to embodiments in the specific context. In the various embodiments presented herein, the package includes a package assembly mounted on a package substrate. The package assembly may include an optical integrated circuit die attached to a redistribution structure or interposer. The optical integrated circuit die may include an optical coupler, such as a grating coupler. The various embodiments presented herein allow for the integration of optical integrated circuit dies including grating couplers, enabling high bandwidth with ultra-low power consumption, and broad integration for co-packages. Embodiments include lens adapters, support structures, and mirrors. By including these components in a particular configuration, the package structure can be more compact and utilizes a lateral entry fiber to the package structure and a top-side entry to the optical engine for the optical data path from the fiber. Furthermore, optical loss from the fiber to the mirror is reduced compared to other structures. Additionally, the lens adapter and mirror allow the disclosed embodiments to be widely used in various package configurations, such as multi-chip modules (MCMs), chip-on-a-substrate packages, or integrated fan-out (InFO) packages.

[0022] Figure 1 A cross-sectional view of an integrated circuit die 50 according to some embodiments is shown. The integrated circuit die 50 will be packaged in subsequent processing to form an integrated circuit package. Each integrated circuit die 50 may be a logic device (e.g., an application-specific integrated circuit (ASIC) die, a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, etc.), a memory device (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management device (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a microelectromechanical system (MEMS) device, a signal processing device (e.g., a digital signal processing (DSP) die), a front-end device (e.g., an analog front-end (AFE) die), etc., or a combination thereof (e.g., a system-on-a-chip (SoC) die). The integrated circuit die 50 may be formed in a wafer, which may include different die regions that are diced in subsequent steps to form multiple integrated circuit dies 50. The integrated circuit die 50 includes a semiconductor substrate 52, interconnect structures 54, and conductive connections 56.

[0023] Semiconductor substrate 52 may be an active layer of a doped or undoped silicon substrate or a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 52 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof. Other substrates, such as multilayer substrates or gradient substrates, may also be used. Semiconductor substrate 52 has an active surface or front surface (e.g., an upward-facing surface) and an active surface or back surface (e.g., a downward-facing surface). Devices are located at the active surface of semiconductor substrate 52. Devices may be active devices (e.g., transistors, diodes, etc.) and / or passive devices (capacitors, resistors, inductors, etc.). The active surface may be free of devices.

[0024] Interconnect structure 54 is located above the active surface of semiconductor substrate 52 and is used to electrically connect devices on semiconductor substrate 52 to form an integrated circuit. Interconnect structure 54 may include one or more dielectric layers and corresponding metallization layers within the dielectric layers. Acceptable dielectric materials for dielectric layers include low-k dielectric materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Acceptable dielectric materials for dielectric layers also include oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; etc.; or combinations thereof, such as silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, silicon carbonitride, etc. Other dielectric materials may also be used, such as polymers such as polybenzoxazole (PBO), polyimide, benzocyclobutene-based polymers, etc. The metallization layer may include conductive vias and / or wires to interconnect devices on semiconductor substrate 52. The metallization layer can be formed from conductive materials, such as metals, such as copper, cobalt, aluminum, gold, or combinations thereof. The interconnect structure 54 can be formed using damascene processes, such as single damascene processes, double damascene processes, etc.

[0025] A conductive connector 56 is formed on the front side 50F of the integrated circuit die 50. The conductive connector 56 may include an under-bump metal (UBM) 56A and a solder region 56B above the UBM 56A. The UBM 56A may be a conductive pillar, pad, etc. In some embodiments, the UBM 56A may be formed by forming a seed layer above the interconnect structure 54. The seed layer may be a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer may be formed using, for example, PVD. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the UBM 56A. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating. The conductive material can include metals such as copper, titanium, tungsten, aluminum, nickel, etc. Then, the portion of the photoresist and seed layer on which the conductive material is not formed is removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process. The remaining portion of the seed layer and conductive material forms the UBM 56A.

[0026] In some embodiments, UBM 56A may comprise three layers of conductive material, such as a titanium layer, a copper layer, and a nickel layer. Other arrangements of materials and layers, such as a chromium / chromium-copper alloy / copper / gold arrangement, a titanium / titanium-tungsten / copper arrangement, or a copper / nickel / gold arrangement, may be used to form UBM 56A. Any suitable material or material layer that may be used in UBM 56A is fully intended to be included within the scope of this application.

[0027] Solder region 56B may include solder material and may be formed over UBM 56A by dipping, printing, plating, etc. Solder material may include, for example, lead-based solders and lead-free solders, such as Pb-Sn composition for lead-based solders; lead-free solders including InSb; tin, silver, and copper (SAC) composition; and other eutectic materials having a common melting point and forming conductive solder connections in electrical applications. As examples, for lead-free solders, SAC solders with varying compositions may be used, such as SAC 105 (Sn 98.5%, Ag 1.0%, Cu 0.5%), SAC 305, and SAC 405. Lead-free solders may also further include SnCu compounds instead of silver (Ag). Lead-free solders may also include tin and silver, Sn-Ag, instead of copper. In some embodiments, a reflow process may be implemented, giving solder region 56B a partially spherical shape in some embodiments. In other embodiments, solder region 56B may have other shapes, such as non-spherical shapes.

[0028] In some embodiments, solder region 56B can be used to perform chip probe (CP) testing on integrated circuit die 50. For example, the solder region can be a solder ball, solder bump, etc., used to attach the chip probe to the conductive connector 56. Chip probe testing can be performed on integrated circuit die 50 to determine whether integrated circuit die 50 is a known good die (KGD). Therefore, only integrated circuit die 50 (which is KGD) undergoes subsequent processing and is packaged, and dies that fail the chip probe test are not packaged. In some embodiments, solder region 56B can be removed in a subsequent processing step after testing.

[0029] Figure 2 A cross-sectional view of an integrated circuit die 60 according to some embodiments is shown. The integrated circuit die 60 is a stacked device comprising a plurality of semiconductor substrates 52. For example, the integrated circuit die 60 may be a memory device comprising a plurality of memory dies, such as a hybrid memory cube (HMC) device, a high-bandwidth memory (HBM) device, etc. In such embodiments, the integrated circuit die 60 includes a plurality of semiconductor substrates 52 interconnected via substrate vias (TSVs) such as through-silicon vias (not shown). Each of the semiconductor substrates 52 may (or may not) have a different interconnect structure.

[0030] Figure 3A cross-sectional view of an integrated circuit die 70 according to some embodiments is shown. The integrated circuit die 70 may be an optical integrated circuit die, such as an optical engine die. The integrated circuit die 70 may include an electrical integrated circuit (EIC) 70A bonded to a photonic integrated circuit (PIC) 70B. The EIC 70A may include a semiconductor substrate 52, active and / or passive electronics on the active side of the semiconductor substrate 52, an interconnect structure 54 on the active side of the semiconductor substrate 52, and a lens 74 on the back side of the semiconductor substrate 52. The lens 74 may be formed by patterning the back side of the semiconductor substrate 52. The lens 74 may be formed to protrude from the back side of the semiconductor substrate 52 (see example...). Figure 3 ) or formed recessed into the back side of the semiconductor substrate 52 (see, for example) Figure 25 EIC 70A can be referenced above. Figure 1 The integrated circuit die 50 described herein is formed in a similar manner, and will not be described again here.

[0031] The PIC 70B may include optical components such as waveguides, modulators, etc. The PIC 70B may also include an optical coupler 72, such as a grating coupler. In some embodiments, the optical coupler 72 may include a dielectric material (such as silicon nitride, etc.) and may be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), etc. In other embodiments, the optical coupler 72 may include a semiconductor layer (such as a silicon layer, etc.) and may be formed from an SOI substrate. The optical coupler 72 may be disposed within the PIC 70B. As described in more detail below, the optical coupler 72 provides optical coupling between the integrated circuit die 70 and an optical fiber coupled to the integrated circuit die 70.

[0032] Integrated circuit dies 70 can be formed in a wafer, which may include different die regions that are diced in subsequent steps to form a plurality of integrated circuit dies 70. In some embodiments, the wafer can be formed by co-bonding EIC wafers (including a plurality of EIC 70A) to PIC wafers (including a plurality of PIC 70B).

[0033] Figures 4 to 15 Top and cross-sectional views of an intermediate stage in the fabrication of a package assembly 400 according to some embodiments are shown. The package assembly 400 may be a chip-on-wafer (CoW) package assembly. Figures 4 to 10A and Figures 11 to 15 A cross-sectional view is shown, and Figure 10B A floor plan is shown. Specifically, Figures 4 to 6The formation of a wafer-level packaging assembly 200 according to some embodiments is illustrated. In some embodiments, the wafer-level packaging assembly 200 includes a plurality of packaging regions (such as region 200A) corresponding to a packaging assembly (such as packaging assembly 400). The plurality of packaging regions of the wafer-level packaging assembly 200 are divided to form separate packaging assemblies 400, as follows. Figure 7 As described in the text.

[0034] exist Figure 4 In this process, an interposer wafer 200 is obtained or formed. The interposer wafer 200 includes multiple packaging regions, such as packaging region 200A. The interposer wafer 200 includes an interposer layer 202 in the packaging regions (such as packaging region 200A), which will be segmented in subsequent processing to be included in a packaging assembly 400. In some embodiments, the interposer layer 202 includes a substrate 204, interconnect structures 206, and conductive vias 208.

[0035] Substrate 204 can be used with the reference above. Figure 1 The semiconductor substrate 52 described is formed using similar materials and methods, and will not be repeated here. In some embodiments, the substrate 204 typically does not include active devices, but the interposer layer 202 may include active surfaces or the front side of the substrate 204 (e.g., Figure 4 Passive devices may be formed on the front side (or the surface facing upwards) of the substrate 204. In other embodiments, active devices such as transistors, capacitors, resistors, diodes, etc., may be formed on the front side (or the surface facing upwards) of the substrate 204.

[0036] Interconnect structure 206 is formed over the front side of substrate 204 and is used for electrically connecting devices (if any) to substrate 204. Interconnect structure 206 may include one or more dielectric layers and corresponding metallization layers within the dielectric layers. Interconnect structure 206 may use the same as referenced above. Figure 1 The interconnect structure 54 described uses similar materials and methods to form, and will not be described again here.

[0037] In addition, Figure 4In this embodiment, conductive connectors 120 are formed on the front side 200FS of the interposer wafer 200, which are in electrical contact with the interconnect structure 206. The conductive connectors 120 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-plating and electroless palladium-plating immersion gold (ENEPIG) techniques, etc. The conductive connectors 120 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, the conductive connectors 120 are formed by initially forming a solder layer through evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed on the structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connectors 120 include metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal capping layer is formed on top of the metal pillar. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or combinations thereof, and may be formed by a plating process.

[0038] In some embodiments, the conductive connector 120 includes a UBM 120A and a solder region 120B above the UBM 120A. The UBM 120A can use the same as referenced above. Figure 1 The materials and methods described for forming the UBM 56A are similar and will not be repeated here. Solder area 120B can be formed using the same materials and methods described in the above reference. Figure 1 The solder area 56B described is formed using similar materials and methods, and will not be described again here.

[0039] Conductive vias 208 extend into interconnect structures 206 and / or substrates 204. Conductive vias 208 are electrically connected to the metallization layer of interconnect structures 206. Conductive vias 208 are sometimes also referred to as substrate vias (TSVs). As an example of forming conductive vias 208, grooves can be formed in interconnect structures 206 and / or substrates 204 by, for example, etching, milling, laser technology, combinations thereof. Thin dielectric materials can be formed in the grooves, such as by using oxidation techniques. Thin barrier layers can be conformally deposited in the openings, such as by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, combinations thereof. The barrier layers can be formed from oxides, nitrides, carbides, combinations thereof. Conductive materials can be deposited over the barrier layers and in the openings. Conductive materials can be formed by electrochemical plating processes, CVD, ALD, PVD, combinations thereof. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, combinations thereof. Excess conductive material and barrier layer are removed from the surface of interconnect structure 206 or substrate 204 by, for example, chemical mechanical polishing (CMP). The remaining portion of the barrier layer and conductive material forms conductive vias 208.

[0040] exist Figure 5 In the diagram, integrated circuit dies 50, 60, and 70 are attached to interconnect structure 206. In the cross-sectional view shown, each package region of wafer-level packaging assembly 200 (such as...) Figure 5 Region 200A shown includes a single integrated circuit die 50, a single integrated circuit die 60, and a single integrated circuit die 70. Integrated circuit die 50 can be a logic device, such as an application-specific integrated circuit (ASIC) die, a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), or a microcontroller; or integrated circuit die 50 can be a memory device, such as a dynamic random-access memory (DRAM) die, a static random-access memory (SRAM) die, etc. In some embodiments, multiple integrated circuit dies 50 may be present, and one may be a logic device while another may be a memory device. In some embodiments, multiple integrated circuit dies 50 may be included, and they may be dies of the same type, such as SoC dies, ASIC dies, etc. Although in Figure 5 The cross-sectional view shows a single integrated circuit die 60 and a single integrated circuit die 70, but multiple integrated circuit dies 60 and multiple single integrated circuit dies 70 may exist in each package region (such as region 200A) of the wafer-level packaging assembly 200.

[0041] In some embodiments, integrated circuit dies 50, 60, and 70 use conductive connector 56 (see...). Figures 1 to 3) and 120 are attached to interconnect structure 206. Integrated circuit dies 50, 60 and 70 can be placed on interconnect structure 206 using, for example, pick-and-place tools. After placing integrated circuit dies 50, 60 and 70 on interconnect structure 206, solder area 56B of conductive connector 56 (see Figures 1 to 3 The corresponding solder area 120B of the corresponding conductive connector 120 is in physical contact with the corresponding conductive connector 120. After placing the integrated circuit dies 50, 60 and 70 on the interconnect structure 206, a reflow process is performed on the conductive connectors 56 and 120 (see...). Figures 1 to 4 The reflow process melts solder regions 56B and 120B and merges them into solder joint 124. Solder joint 124 electrically and mechanically couples integrated circuit dies 50, 60, and 70 to interconnect structure 206.

[0042] In addition, Figure 5 An underfill 126 can be formed around the solder joint 124 and in the gaps between the interconnect structure 206 and the integrated circuit dies 50, 60, and 70. The underfill 126 can reduce stress and protect the solder joint 124. The underfill 126 can be formed from an underfill material, such as molding compound, epoxy resin, etc. The underfill 126 can be formed by a capillary flow process after the integrated circuit dies 50, 60, and 70 are attached to the interconnect structure 206, or by a suitable deposition method before the integrated circuit dies 50, 60, and 70 are attached to the interconnect structure 206. The underfill 126 can be applied in a liquid or semi-liquid form and then subsequently cured. In some embodiments, the underfill 126 partially or completely fills the gaps between adjacent integrated circuit dies 50, 60, and 70, such that the underfill 126 extends along the sidewalls of the integrated circuit dies 50, 60, and 70.

[0043] In addition, Figure 5In this process, a sealant 132 is formed on and around integrated circuit dies 50, 60, and 70. After formation, the sealant 132 seals the integrated circuit dies 50, 60, and 70 as well as the underfill 126. The sealant 132 can be a molding compound, epoxy resin, etc. The sealant 132 may not include the underfill. The sealant 132 can be applied by compression molding, transfer molding, etc., and formed over the wafer-level package assembly 200, thereby burying or covering the integrated circuit dies 50, 60, and 70. The sealant 132 can be applied in liquid or semi-liquid form and then subsequently cured. The sealant 132 can be thinned to expose the integrated circuit dies 50, 60, and 70. The thinning process can be a polishing process, CMP, etch-back, a combination thereof, etc. After the thinning process, the top surfaces of the integrated circuit dies 50, 60, and 70 and the sealant 132 are coplanar (within process variations), thereby making them flush with each other. Thinning is performed until the desired amount of integrated circuit dies 50, 60 and 70 and / or sealant 132 has been removed.

[0044] exist Figure 6 middle, Figure 5 The wafer-level packaging assembly is flipped and attached to carrier wafer 210. Carrier wafer 210 serves as a platform or support for the packaging processes described below. In some embodiments, carrier wafer 210 includes semiconductor materials (such as silicon), dielectric materials (such as glass, ceramic materials, quartz, etc.), combinations thereof, etc. In some embodiments, the wafer-level packaging assembly is attached to carrier wafer 210 using an adhesive (not shown).

[0045] The substrate 204 can be thinned to expose the conductive via 208. Exposure of the conductive via 208 can be achieved through thinning processes such as polishing, CMP, etch-back, or combinations thereof. In some embodiments (not shown separately), the thinning process for exposing the conductive via 208 includes CMP, and the conductive via 208 protrudes at the back side 200BS of the wafer 200 due to the depression that occurs during CMP. In such embodiments, an insulating layer (not shown separately) can optionally be formed on the back side of the substrate 204 to surround the protruding portion of the conductive via 208. The insulating layer can be formed of a silicon-containing insulator, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and can be formed by suitable deposition methods such as spin coating, CVD, plasma-enhanced CVD (PECVD), high-density plasma CVD (HDP-CVD), etc. After thinning the substrate 204, the conductive via 208 and the insulating layer (if present) or the exposed surface of the substrate 204 are coplanar (within process variations), so that they are flush with each other and exposed at the back side 200BS of the interposer wafer 200.

[0046] After a thinning process (if applicable) to expose the conductive via 208, a conductive connector 134 is formed on the back side 200BS of the interposer wafer 200. The conductive connector 134 is electrically coupled to the conductive via 208 and / or the integrated circuit die 104. The conductive connector 134 can be a ball grid array (BGA) connector, solder ball, metal pillar, controlled collapse chip connection (C4) bump, microbump, bump formed by electroless nickel plating and electroless palladium immersion gold plating (ENEPIG), etc. The conductive connector 134 can use the same as the one referenced above. Figure 4 The conductive connector 120 described herein is formed using similar materials and methods, and will not be repeated here. In the illustrated embodiment, the conductive connector 134 includes a UBM 134A and a solder region 134B above the UBM 134A. The UBM 134A and the solder region 134B can respectively use materials and methods similar to those described above. Figure 4 The materials and methods used to form the UBM 120A and solder area 120B are similar and will not be repeated here.

[0047] Furthermore, a partitioning process is performed by cutting along a scribing area, for example, around the package region 200A. The partitioning process can include sawing, etching, dicing, and combinations thereof. For example, the partitioning process can include sawing the sealant 132, the interconnect structure 206, and the substrate 204. The partitioning process divides the package region 200A from adjacent package regions to form a partitioned package assembly 400, such as... Figure 7 As shown in the diagram. The segmented package assembly 400 originates from package region 200A. The segmentation process forms the interposer 202 from the segmented portion of the interposer wafer 200. Due to the segmentation process, the outer sidewalls of the interposer 202 and the sealant 132 share a common end laterally (within process variations), as shown. Figure 7 As shown in the image.

[0048] Figures 8 to 15 Plan and cross-sectional views of an intermediate stage in the manufacturing of package 600 according to some embodiments are shown. In particular, Figure 8 , Figure 9 , Figure 10A , Figure 11 , Figure 12 and Figure 13 A cross-sectional view is shown. Figure 10B A floor plan is shown. Figure 14 and Figure 15 It shows Figure 13 A magnified view of region 564.

[0049] exist Figure 8In this embodiment, a packaging assembly 400 is placed on a packaging substrate 500. The packaging substrate 500 includes a substrate core 502, which may be made of a semiconductor material such as silicon, germanium, diamond, etc. Optionally, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide, gallium phosphide indium, combinations thereof, etc., may also be used. Furthermore, the substrate core 502 may be an SOI substrate. Typically, an SOI substrate includes a semiconductor material layer such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In another embodiment, the substrate core 502 is an insulating core, such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin, such as FR4. Optional materials for the core material include bismaleimide-triazine (BT) resin, or alternatively other printed circuit board (PCB) materials or films.

[0050] In some embodiments, substrate core 502 may include active and passive devices (not shown separately). Devices such as transistors, capacitors, resistors, combinations thereof, etc., can be used to meet the structural and functional requirements of the system design. Devices can be formed using any suitable method. In some embodiments, substrate core 502 is substantially devoid of active and passive devices. In some embodiments, substrate core 502 also includes conductive vias 504, which may also be referred to as TSVs. In some embodiments, conductive vias 504 can be used with reference to the above-referenced... Figure 4 The conductive via 208 described uses similar materials and methods for formation, and will not be repeated here.

[0051] The packaging substrate 500 may also include a redistribution structure. In some embodiments, the redistribution structure may be formed of alternating layers of dielectric material (e.g., a low-k dielectric material) and conductive material (e.g., copper), wherein vias interconnect the conductive material layers, and may be formed by any suitable process (e.g., deposition, damascene, etc.). In other embodiments, the redistribution structure may be formed of alternating layers of dielectric material (e.g., a polymer film such as Ajinomoto polymer (ABF) or other laminated materials) and conductive material (e.g., copper), wherein vias interconnect the conductive material layers, and may be formed by any suitable process (e.g., lamination, plating, etc.).

[0052] In the illustrated embodiment, the packaging substrate 500 includes redistribution structures 506 and 508 formed on opposing surfaces of a substrate core 502, such that the substrate core 502 is situated between the redistribution structures 506 and 508. A conductive via 504 electrically couples the redistribution structure 506 to the redistribution structure 508. In some embodiments, either the redistribution structure 506 or the redistribution structure 508 may be omitted.

[0053] In some embodiments, bonding pads 510 and solder mask 512 are formed on the redistribution structure 506, wherein the bonding pads 510 are exposed by openings formed in the solder mask 512. The bonding pads 510 may be part of the redistribution structure 506 and may be formed together with other conductive components of the redistribution structure 506. The solder mask 512 may include a suitable insulating material (such as a dielectric material, polymer material, etc.) and may be formed using any suitable deposition method.

[0054] In some embodiments, the conductive connector 514 extends through an opening in the solder mask layer 512 and contacts the bonding pad 510. The conductive connector 514 may be a ball grid array (BGA) connector, solder ball, metal pillar, controlled collapse chip connection (C4) bump, microbump, bump formed by electroless nickel-plating palladium-plating immersion gold (ENEPIG), etc. The conductive connector 514 may use the same type as referenced above. Figure 4 The conductive connector 120 described is formed using similar materials and methods, and will not be repeated here. In the illustrated embodiment, the conductive connector 514 comprises solder balls.

[0055] In some embodiments, bonding pads 516 and a solder mask layer 518 are formed on the redistribution structure 508, wherein the bonding pads 516 are exposed by openings formed in the solder mask layer 518. The bonding pads 516 may be part of the redistribution structure 508 and may be formed together with other conductive components of the redistribution structure 508. The solder mask layer 518 may include a suitable insulating material (such as a dielectric material, polymer material, etc.) and may be formed using any suitable deposition method.

[0056] In some embodiments, the conductive connector 520 extends through an opening in the solder mask layer 518 and contacts the bonding pad 516. The conductive connector 520 may be a ball grid array (BGA) connector, solder ball, metal pillar, controlled collapse chip connection (C4) bump, microbump, bump formed by electroless nickel-palladium immersion gold (ENEPIG) technology, etc. The conductive connector 520 may use the same type as referenced above. Figure 4 The conductive connector 120 described is formed using similar materials and methods, and will not be repeated here. In the illustrated embodiment, the conductive connector 520 comprises solder balls.

[0057] In some embodiments, the package assembly 400 may be placed on the package substrate 500 using, for example, a pick-and-place tool. After the package assembly 400 is placed on the package substrate 500, the conductive connector 134 comes into physical contact with the corresponding conductive connector 514, such that the solder region 134B of the conductive connector 134 comes into physical contact with the corresponding conductive connector 514.

[0058] exist Figure 9 In the process of placing the package assembly 400 on the package substrate 500, a reflow process is performed to mechanically and electrically attach the package assembly 400 to the package substrate 500. The reflow process reflows the solder areas 134B of the conductive connector 134 (see...) Figure 8 The corresponding solder materials for the conductive connector 514 (see) Figure 8 The solder joints 524 are melted and merged into a solder joint 524. The solder joint 524 electrically and mechanically couples the package assembly 400 to the package substrate 500.

[0059] In some embodiments, underfill 526 may be formed around solder joint 524 and in the gap between package assembly 400 and package substrate 500. Underfill 526 may use materials similar to those referenced above. Figure 5 The underfill 126 described herein is formed using similar materials and methods, and will not be repeated here. In some embodiments, the underfill 526 extends along and is in physical contact with the sidewall 400L of the encapsulation assembly 400, wherein the sidewall 400L is opposite to the sidewall 400R.

[0060] Figure 10A and Figure 10B Cross-sectional and planar views are shown after the warp control structure 530 is attached to the packaging substrate 500. The warp control structure 530 can be attached to the packaging substrate 500 via adhesive 528, such that the adhesive 528 is positioned between the warp control structure 530 and the solder mask layer 512. The adhesive 528 can be any suitable adhesive, epoxy resin, etc. The warp control structure 530 can be a ring structure (see...). Figure 10B The package assembly 400 may be disposed in the hole 531 of the warp control structure 530. The warp control structure 530 may include a metal, a metal alloy, a dielectric material, a semiconductor material, etc.

[0061] exist Figure 10A In the middle, the carrier wafer 100 (see Figure 9 The carrier wafer 100 is peeled off from the wafer-level packaging assembly 200, thereby peeling the carrier wafer 100 from the sealant 108 and the integrated circuit die 104. In some embodiments, the peeling process may also remove the adhesive 106 from the integrated circuit die 104. Subsequently, the wafer-level packaging assembly 200 is flipped and attached to the carrier wafer 300. The carrier wafer 300 can be used with reference to the above. Figure 4 The carrier wafer 100 is formed using similar materials and methods, and will not be described again here. In some embodiments, the wafer-level packaging assembly 200 is attached to the carrier wafer 300 using an adhesive (not shown).

[0062] After attaching the wafer-level packaging assembly 200 to the carrier wafer 300, a conductive connector 134 is formed over the integrated circuit die 104 and the sealant 108. The conductive connector 134 is electrically coupled to the conductive via 102 and / or the integrated circuit die 104. The conductive connector 134 can be a ball grid array (BGA) connector, solder ball, metal pillar, controlled collapse chip connection (C4) bump, microbump, bump formed by electroless nickel plating and electroless palladium immersion gold plating (ENEPIG), etc. The conductive connector 134 can use the same as the one referenced above. Figure 6 The conductive connector 120 described herein is formed using similar materials and methods, and will not be repeated here. In the illustrated embodiment, the conductive connector 134 includes a UBM 134A and a solder region 134B above the UBM 134A. The UBM 134A and the solder region 134B can respectively use materials and methods similar to those described above. Figure 6 The materials and methods used to form the UBM 120A and solder area 120B are similar and will not be repeated here.

[0063] Furthermore, a dicing process is performed on the wafer-level packaging assembly 200 by cutting along, for example, a scribe line region around region 200A. The dicing process can include sawing, etching, dicing, combinations thereof, etc. For example, the dicing process can include sawing sealants 108 and 132, redistribution structure 110, and optical adhesive 128. The dicing process divides region 200A from adjacent regions to form... Figure 10A and Figure 10B The segmented encapsulation component 400 is shown in the diagram. The segmented encapsulation component 400 originates from region 200A.

[0064] Figure 10A and Figure 10B Top and cross-sectional views of a package assembly 400 according to some embodiments are shown. In particular, Figure 10A A cross-sectional view is shown, and Figure 10B A top view is shown. Furthermore, for clarity, in... Figure 10B The top view does not show all the components of the encapsulation assembly 400. This is due to the reference above. Figure 7 The described segmentation process, the lateral common ends of the outer walls of sealants 108 and 132, redistribution structure 110, and optical adhesive 128 (within process variations), such as Figure 10A As shown in the diagram. After the dicing process, the sealant 132 has a thickness T1 on the sidewall 70E of the integrated circuit die 70. The thickness T1 can be between about 5 mm and about 10 mm. In some embodiments, the dam structure 122 has a rectangular shape in plan view, as shown in the diagram. Figure 10BAs shown in the illustration. In other embodiments, the dam structure 122 can have any desired shape in the plan view based on the design requirements of the package component 400. In the illustrated embodiment, the dam structure 122 overlaps with the corresponding integrated circuit die 70, such that the sidewall 122L of the dam structure 122 is covered by the corresponding integrated circuit die 70, while the sidewall 122R (opposite to the sidewall 122L) of the dam structure 122 is not covered by the corresponding integrated circuit die 70, as shown in the illustration. Figure 10B As shown in the image.

[0065] exist Figure 11 In this embodiment, a heat sink 534 is attached to a warpage control structure 530. In some embodiments, the heat sink 534 comprises a high thermal conductivity material, such as a metal, a metal alloy, etc. The heat sink 534 can be attached to the cover by an adhesive, a thermal interface material, or other means of attaching the two structures. In some embodiments, the heat sink 534 and the warpage control structure 530 are an integral structure and are placed on both the package substrate 500 and the package assembly 400. In some embodiments, a thermal interface material 532 is located between the top surface of the package assembly 400 and the heat sink 534. The thermal interface material 532 can comprise a thermal interface material having high thermal conductivity. In some embodiments, the heat sink 534 includes an opening 536 exposing a lens 74 of the optical engine 70. This allows the subsequently formed optical path to have access to the optical engine 70.

[0066] Figure 12 A support structure 540 is shown, in which a solder resist layer 512 of a package substrate 500 is attached to an opening 536 of a heat sink 534 using an adhesive 541. The support structure 540 may include semiconductor materials (such as, for example, silicon), dielectric materials, combinations thereof, etc. The adhesive 541 may be formed using materials and methods similar to those used for adhesive 528.

[0067] Figure 13 , Figure 14 and Figure 15 Further processing is shown in the figure, in which Figure 14 and Figure 15 It shows Figure 13An enlarged view of region 564. Lens adapter 550 is attached to package assembly 400 and support structure 540. Lens adapter 550 provides an interface between lens 74 of integrated circuit die 70 and optical fiber 558 and mirror 562 attached to lens adapter 550. Lens adapter 550 can be attached to the top surface of package assembly 400 using optical adhesive 542, thereby making physical contact between optical adhesive 542 and the top surface of integrated circuit die 70 and sealant 132. Lens adapter 550 can be attached to the top surface of support structure 540 using optical adhesive 544. In some embodiments, optical adhesives 542 and 544 comprise polymeric materials, such as epoxy acrylate oligomers. The polymeric materials may have a refractive index between about 1 and about 3. In some embodiments, optical adhesive 544 can be replaced with an adhesive similar to adhesive 528 described above.

[0068] Lens adapter 550 includes a lens 552, which is positioned above and aligned with lens 74 of integrated circuit die 70. In some embodiments, lens adapter 550 comprises glass, silicon, or combinations thereof. A reflector 562 is positioned above lens adapter 550 and attached to it with optical adhesive 548, and optical fiber 558 is attached to both the lens adapter and reflector 562 with optical adhesive 548. In some embodiments, reflector 562 comprises glass, silicon, quartz, acrylic, plastic, or combinations thereof. Reflector 562 allows for a more compact package because it enables the laterally extending optical fiber 558 to utilize the top surface inlet of optical engine 70. Furthermore, lens adapter 550 and support structure 540 achieve this compact structure by supporting the optical fiber and reflector 562. Optical fiber 558 extends from mechanical transmission structure 554. Mechanical transmission structure 554 is attached to heat sink 534 with optical adhesive 546. In some embodiments, optical adhesive 546 can be replaced with an adhesive similar to adhesive 528 described above.

[0069] An optical data path 566 is formed from optical fiber 558 to optical coupler 72 of integrated circuit die 70 via optical adhesive 548, reflector 562, lens adapter 550, lens 552, optical adhesive 542, and lens 74. Each of the lens 552 of the lens adapter and the lens 74 of the optical engine 70 can have dimensions ranging from 50 μm to 500 μm, with curvature ranging from 10 μm to 300 μm. Lens 552 can be formed of dielectric or semiconductor materials, such as silicon, glass, quartz, or combinations thereof.

[0070] The package structure can be more compact by having a lens adapter 550, a support structure 540 and a reflector 562, while still utilizing the lateral entry fiber 558 and the top entry to the optical engine 70 for the optical data path 566 from the fiber 558.

[0071] like Figure 15 As shown, the reflector 562 has a height H1, a width W1, and extends in and out. Figure 15 The length of the cross-sectional view (not shown). In some embodiments, the length is in the range of 2 mm to 20 mm, the height H1 is in the range of 0.3 mm to 5 mm, and the width W1 is in the range of 0.3 mm to 5 mm. The reflector 562 has a reflective surface 562A that forms a first angle with the input optical data path 566 from the optical fiber 558. In some embodiments, the first angle is substantially 45 degrees (within process variations).

[0072] Further as Figure 15 As shown, the lens adapter has a height H2, a width W2, and extends in and out. Figure 15 The length of the cross-sectional view (not shown). In some embodiments, the length is in the range of 2 mm to 30 mm, the height H2 is in the range of 0.3 mm to 2 mm, and the width W2 is in the range of 0.5 mm to 50 mm.

[0073] Figures 16A to 16B A cross-sectional view of a lens adapter 550 and an optical fiber 558 according to some embodiments is shown. Figures 16A to 16B The cross-sectional view in the middle is along the length direction, thus making Figure 15 The cross-sectional view in the middle is along Figures 16A to 16B It was taken from line AA in the middle. Figures 16A to 16B An embodiment of a lens adapter 550 with a slotted top surface is shown, wherein an optical fiber 558 is located in one of the slots. In some embodiments, multiple optical fibers 558 are present on a single lens adapter, wherein each optical fiber 558 is located in a different slot of the lens adapter 550. In these embodiments, the optical fibers 558 may be connected to one or more optical engines 70 of the encapsulation structure.

[0074] exist Figure 16A In this design, the groove is V-shaped, having a depth D1, and the surface of the groove forms an angle A1 with the vertical line. In some embodiments, the depth D1 ranges from 50 μm to 250 μm, and the angle A1 is substantially 45 degrees (within process variations). Figure 16A In the middle, the groove is U-shaped, and the groove has a depth D1.

[0075] Figures 17A to 17HAn enlarged cross-sectional view of a reflector 562 and surrounding components according to some embodiments is shown. While previous embodiments have shown the reflector 562 as not including any lenses, in some embodiments, the reflector 562 may include one or more lenses. Figure 17A In the middle, the reflector 562 includes a convex lens 562B facing the optical fiber 558. Figure 17B In the middle, the reflector 562 includes a convex lens 562B facing the optical engine 70. Figure 17C In the process, the reflecting surface 562A of the reflector 562 includes a convex lens 562B. Figure 17D In the process, the reflector 562 includes two lenses: a convex lens 562B1 facing the optical fiber 558, and the reflecting surface 562A of the reflector 562 includes the convex lens 562B2. Figure 17E In the middle, the reflector 562 includes a concave lens 562B facing the optical fiber 558. Figure 17F In the middle, the reflector 562 includes a concave lens 562B facing the optical engine 70. Figure 17G In the process, the reflecting surface 562A of the mirror 562 includes a concave lens 562B. Figure 17H In the mirror 562, there are two lenses: a concave lens 562B1 facing the optical fiber 558, and a reflecting surface 562A of the mirror 562 including a concave lens 562B2.

[0076] exist Figures 17A to 17H In each of the embodiments, lens 562B has a size range from 50 μm to 500 μm, wherein the curvature ranges from 10 μm to 300 μm. Other embodiments may include Figures 17A to 17H Variations of the embodiments include multiple concave lenses, combinations of convex lenses and concave lenses, and various other combinations of the embodiments.

[0077] Figures 17A to 17H The lens embodiments illustrate the flexibility of lens design, demonstrating that a combination of concave or convex lenses can be used based on design requirements. In the embodiments, different alignment requirements can be addressed. Figures 17A to 17H Any combination of lenses shown. Concave and convex lenses have different light-guiding properties, and these types of lenses can be positioned anywhere based on the alignment requirements of the design.

[0078] Figures 18A to 18C An enlarged cross-sectional view of a reflector 562, an optical fiber 558, and surrounding components according to some embodiments is shown. Figure 18C This is a cross-sectional view of reflector 562 along its length. Figures 18A to 18CIn one embodiment, the reflector 562 has a groove 562C, allowing the optical fiber 558 to be inserted into the reflector 562. In this embodiment, the optical adhesive between the reflector 562 and the optical fiber 558 can be omitted, as the insertion holds the components together.

[0079] like Figure 18B and Figure 18C As shown, the groove 562C of the reflector 562 has a height H3, a length L1, and a depth D2. In some embodiments, the length L1 is in the range of 2 mm to 20 mm, the height H3 is in the range of 0.08 mm to 2 mm, and the depth D1 is in the range of 0.08 mm to 2 mm.

[0080] Figures 16A to 18C The embodiments can be used in any packaging structure of the embodiments of this disclosure.

[0081] Figure 19 An enlarged cross-sectional view of a package assembly 700 according to some embodiments is shown. Package assembly 700 is similar to package assembly 600 (see...). Figure 13 and Figure 14 ( ), where identical components are labeled with the same reference numerals, and descriptions of identical components are not repeated here. In some embodiments, the encapsulation component 700 may use the same reference numerals as those above. Figures 1 to 14 The process steps described are similar to those used in the formation process and will not be repeated here. In the illustrated embodiment, the lens adapter 550 extends from the optical engine 70 to the heat sink 534 / warpage control structure 530.

[0082] Figure 20 An enlarged cross-sectional view of a package assembly 700' according to some embodiments is shown. Package assembly 700' is similar to package assembly 700 (see...). Figure 19 (i) where identical components are labeled with the same reference numerals, and descriptions of identical components will not be repeated here. In the illustrated embodiment, the lens adapter 550 extends from the optical engine 70 to the heat sink 534 / warp control structure 530, and the support structure 540 is omitted.

[0083] Figure 21 and Figure 22 A cross-sectional view of a package assembly 800 according to some embodiments is shown. Package assembly 800 is similar to package assembly 600 (see...). Figure 13 and Figure 14 ( ), where identical components are labeled with the same reference numerals, and descriptions of identical components are not repeated here. In some embodiments, the encapsulation component 800 may use the same reference numerals as those above. Figures 1 to 14 The process steps described are similar to those described in the original text, and will not be repeated here.

[0084] exist Figure 21 In this configuration, passive component 570 is bonded to packaging substrate 500 between support structure 540 and heat sink 534 / warpage control structure 530. Figure 22 In this configuration, passive component 570 is bonded to packaging substrate 500 between support structure 540 and packaging component 400. Passive component 570 is located below optical fiber 558.

[0085] Passive component 570 may include one or more passive devices, such as capacitors, resistors, inductors, etc. Passive component 570 may be formed in a manner similar to that of integrated circuit die 50, and will not be described again here. Passive component 570 may be bonded to conductive parts of package substrate 500 via connector 572. Connector 572 may be similar to conductive connector 134 described above, and will not be described again here. Passive component 570 may be bonded to package substrate 500 and has underfill 574 surrounding connector 572. The bonding process of passive component 570 may be similar to the bonding process of package component 400 described above, and will not be described again here. Underfill 574 may be similar to underfill 526 described above, and will not be described again here.

[0086] Figure 23 A cross-sectional view of a package assembly 900 according to some embodiments is shown. Package assembly 900 is similar to package assembly 600 (see...). Figure 13 and Figure 14 ( ), where identical components are labeled with the same reference numerals, and descriptions of identical components are not repeated here. In some embodiments, the encapsulation component 900 may use the same reference numerals as those above. Figures 1 to 14 The process steps described are similar to those used in the formation process and will not be repeated here. In the illustrated embodiment, the package assembly 400 is a multi-chip module, wherein the optical engine 70 is a different module from dies 50 and 60. In this embodiment, the package including dies 50 and 60 and the optical engine 70 are respectively bonded to the package substrate 500.

[0087] Figure 24 A cross-sectional view of a package assembly 1000 according to some embodiments is shown. Package assembly 1000 is similar to package assembly 600 (see...). Figure 13 and Figure 14 ( ), where identical components are labeled with the same reference numerals, and descriptions of identical components are not repeated here. In some embodiments, the encapsulation component 1000 may use the same reference numerals as those above. Figures 1 to 14The process steps described are similar to those used to form the package, and will not be repeated here. In the illustrated embodiment, the package assembly 400' is an integrated fan-out (InFO) package, rather than a chip-on-wafer package. For example, in this embodiment, the interposer 200 is replaced by a redistribution structure 200'.

[0088] In some embodiments, the redistribution structure 200' may be formed of alternating layers of dielectric material (e.g., a low-k dielectric material) and conductive material (e.g., copper), wherein vias interconnect the conductive material layers, and may be formed by any suitable process (e.g., deposition, damascene, etc.). In other embodiments, the redistribution structure 200' may be formed of alternating layers of dielectric material (e.g., a polymer film such as Ajinomoto polymer (ABF) or other laminated materials) and conductive material (e.g., copper), wherein vias interconnect the conductive material layers, and may be formed by any suitable process (e.g., lamination, plating, etc.).

[0089] Figure 25 An enlarged cross-sectional view of a package assembly 1100 according to some embodiments is shown. Package assembly 1100 is similar to package assembly 600 (see...). Figure 13 and Figure 14 ( ), where identical components are labeled with the same reference numerals, and descriptions of identical components are not repeated here. In some embodiments, the encapsulation component 1100 may use the same reference numerals as those above. Figures 1 to 14 The process steps described are similar to those used in the formation process and will not be repeated here. In the illustrated embodiment, the lens 74 on the optical engine 70 is recessed into the optical engine 70.

[0090] The implementation can achieve advantages. This is achieved by forming a package including a lens adapter, support structure, and reflector as described above (such as, for example, Figure 13 and Figure 14 The package 600 shown herein offers various advantages. By including these components in a specific configuration, the package structure can be more compact, and the optical data path from the optical fiber is utilized through both the lateral entry fiber to the package structure and the top entry fiber to the optical engine. This results in improved coupling between the coupler of the optical integrated circuit die and the optical fiber. The various embodiments presented herein allow for the integration of optical integrated circuit dies including grating couplers, achieving high bandwidth with ultra-low power consumption via edge couplers, and broad integration for co-packaged optics. Furthermore, optical losses from the fiber to the mirror are reduced compared to other structures. Additionally, the lens adapter and mirror allow the disclosed embodiments to be widely used in various package configurations, such as multi-chip modules (MCMs), chip-on-a-substrate packages, or integrated fan-out (InFO) packages.

[0091] The embodiment includes a package comprising a packaging substrate. The package also includes a packaging assembly bonded to the packaging substrate, the packaging assembly including an interposer. The package also includes an optical die bonded to the interposer, the optical die including an optical coupler. The package also includes an integrated circuit die bonded to an interposer adjacent to the optical die. The package also includes a lens adapter bonded to the optical die with a first optical adhesive. The package also includes a mirror bonded to the lens adapter with a second optical adhesive, the mirror being aligned with the optical coupler of the optical die. The package also includes an optical fiber on the lens adapter, a first end of the optical fiber facing the mirror, the optical fiber being configured such that an optical data path extends from the first end of the optical fiber through the mirror, the second optical adhesive, the lens adapter, and the first optical adhesive to the optical coupler of the optical die.

[0092] The embodiment may include one or more of the following components: An optical die includes a first lens located on the back side of the optical die, the back side of the optical die facing away from the package substrate, through which an optical data path passes. A lens adapter includes a second lens located on a lower surface of the lens adapter, through which the optical data path passes. A mirror includes a third lens through which the optical data path passes. The mirror is made of glass, silicon, quartz, acrylic, plastic, or a combination thereof. The package further includes a support structure bonded to the package substrate, with the lens adapter located above the support structure and bonded to the support structure. A heat sink includes an opening, a portion of the optical die located in the opening, with the lens adapter bonded to the portion of the optical die located in the opening. The lens adapter extends across the opening in the heat sink and is bonded to an outer portion of the heat sink. The package further includes a second underfill located between the package substrate and the package assembly. The package assembly further includes a first underfill located between the optical die, the integrated circuit die, and an interposer; and a sealant sealing the optical die, the integrated circuit die, and the first underfill, with the lens adapter bonded to the sealant. The lens adapter has a slot in its top surface, and the optical fiber is located in one of the slots. The reflector includes a groove, and the optical fiber is located in the groove of the reflector.

[0093] The embodiment is a package including a packaging substrate. The package also includes a package assembly bonded to the packaging substrate. The package also includes: a heat sink attached to the packaging substrate and covering the package assembly, the heat sink including an opening, a portion of the package assembly being located in the opening of the heat sink. The package also includes a lens adapter located in the opening of the heat sink, the lens adapter being attached to the package assembly. The package also includes a mirror located in the opening of the heat sink, the mirror being attached to the lens adapter. The package also includes an optical fiber extending into the opening in the heat sink, the optical fiber being located on the lens adapter, wherein the package assembly includes an optical die, the optical die including an optical coupler, the optical coupler being close to a first sidewall of the optical die, the first sidewall of the optical die and the first sidewall of the package assembly being located in the opening of the heat sink, a first end of the optical fiber facing the mirror, the optical fiber being configured such that an optical data path extends from the first end of the optical fiber through the mirror and the lens adapter to the optical coupler of the optical die.

[0094] The embodiment may include one or more of the following components. The package further includes: a support structure located on the package substrate within an opening in the heat sink, and a lens adapter attached to the support structure. The optical die includes a first lens located on the back side of the optical die, the back side of the optical die facing away from the package substrate; the lens adapter includes a second lens located on a lower surface of the lens adapter; and a mirror includes a third lens, through which an optical data path passes. The optical data path is reflected in the mirror. The package assembly further includes: an interposer to which the optical die is bonded; a logic die to which the interposer is bonded; a memory die to which the interposer is bonded; a first underfill located between the optical die, the logic die, the memory die, and the interposer; and a sealant sealing the optical die, the logic die, the memory die, and the first underfill, with the lens adapter attached to the sealant.

[0095] The embodiments include a method of forming a package assembly, wherein forming the package assembly includes bonding an optical die to an interposer, the optical die including an optical coupler adjacent to a first sidewall of the optical die. The method also includes bonding a logic die to the interposer. The method also includes depositing a first underfill between the optical die, the logic die, and the interposer. The method also includes forming a sealant on the optical die, the logic die, and the first underfill. The method also includes bonding the package assembly to a package substrate. The method also includes attaching a heat sink to the package substrate and the package assembly, the heat sink including an opening in which a portion of the package assembly is located. The method also includes attaching a support structure to the package substrate in the opening of the heat sink. The method also includes attaching a lens adapter to the portion of the package assembly located in the opening and the support structure in the opening. The method also includes attaching a mirror to the lens adapter. The method also includes attaching an optical fiber to the mirror, the optical fiber being located on the lens adapter, the optical fiber being configured such that an optical data path extends from a first end of the optical fiber through the mirror and the lens adapter to an optical coupler of the optical die.

[0096] The embodiments may include one or more of the following methods. An optical die includes a first lens located on the back side of the optical die, the back side of the optical die being opposite to the packaging substrate; a lens adapter includes a second lens located on a lower surface of the lens adapter; and a mirror includes a third lens. An optical data path passes through the first lens, the second lens, and the third lens. The lens adapter extends across an opening in a heat sink and is attached to an external portion of the heat sink.

[0097] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of this disclosure.

Claims

1. A package comprising: Packaging substrate; A packaging assembly, bonded to the packaging substrate, the packaging assembly comprising: Intermediate layer; An optical die, bonded to the interposer, the optical die including an optical coupler; and An integrated circuit die, bonded to the interposer layer adjacent to the optical die; A lens adapter is bonded to the optical core using a first optical adhesive. A reflector, bonded to the lens adapter with a second optical adhesive, is aligned with the optical coupler of the optical die; and An optical fiber, located on the lens adapter, has a first end facing the mirror. The optical fiber is configured such that an optical data path extends from the first end of the optical fiber through the mirror, the second optical adhesive, the lens adapter, and the first optical adhesive to the optical coupler of the optical die.

2. The packaging component according to claim 1, wherein, The optical die includes a first lens located on the back side of the optical die, the back side of the optical die being away from the packaging substrate, and the optical data path passing through the first lens.

3. The packaging component according to claim 2, wherein, The lens adapter includes a second lens located on the lower surface of the lens adapter, through which the optical data path passes.

4. The packaging component according to claim 2, wherein, The reflector includes a third lens through which the optical data path passes.

5. The package according to claim 1, wherein, The reflector is made of glass, silicon, quartz, acrylic, plastic, or a combination thereof.

6. The package according to claim 1, further comprising: A support structure is bonded to the packaging substrate, and the lens adapter is located above the support structure and bonded to the support structure.

7. The package according to claim 1, further comprising: A heat sink is attached to the packaging substrate and covers the packaging assembly, wherein the heat sink includes an opening in which a portion of the optical die is located, and the lens adapter is bonded to the portion of the optical die located in the opening.

8. The package according to claim 7, wherein, The lens adapter extends across the opening in the heat sink and is bonded to the outer portion of the heat sink.

9. The package according to claim 1, wherein, The packaging component further includes: A first bottom filler is located between the optical die, the integrated circuit die, and the interposer; and A sealant is used to seal the optical die, the integrated circuit die, and the first bottom filler, and the lens adapter is bonded to the sealant.

10. The package according to claim 8, further comprising: A second bottom filler is located between the packaging substrate and the packaging assembly.

11. The package according to claim 1, wherein, The lens adapter has a slot in its top surface, and the optical fiber is located in one of the slots.

12. The package according to claim 1, wherein, The reflector includes a groove, and the optical fiber is located in the groove of the reflector.

13. A package comprising: Packaging substrate; The packaging component is bonded to the packaging substrate; A heat sink is attached to the packaging substrate and covers the packaging assembly, the heat sink including an opening in which a portion of the packaging assembly is located; A lens adapter is located in the opening of the heat sink and is attached to the package assembly; A reflector is located in the opening of the heat sink cover, and the reflector is attached to the lens adapter; as well as An optical fiber extends into the opening in the heat sink, the optical fiber being located on the lens adapter, wherein the encapsulation assembly includes: An optical die includes an optical coupler adjacent to a first sidewall of the optical die, the first sidewall of the optical die and a first sidewall of the encapsulation assembly being located in the opening of the heat sink, a first end of an optical fiber facing the mirror, the optical fiber being configured such that an optical data path extends from the first end of the optical fiber through the mirror and the lens adapter to the optical coupler of the optical die.

14. The package according to claim 13, further comprising: A support structure is located on the encapsulation substrate in the opening of the heat sink, and the lens adapter is attached to the support structure.

15. The package according to claim 14, wherein, The optical die includes a first lens located on the back side of the optical die, the back side of the optical die being opposite to the packaging substrate, the lens adapter includes a second lens located on the lower surface of the lens adapter, and the mirror includes a third lens, the optical data path passing through the first lens, the second lens, and the third lens.

16. The package according to claim 13, wherein, The optical data path is reflected in the mirror.

17. The package according to claim 13, wherein, The packaging component further includes: Intermediate layer, to which the optical die is bonded; The logic die is bonded to the interposer layer; The memory die is bonded to the interposer layer; A first bottom filler is located between the optical die, the logic die, the memory die, and the interposer layer; and A sealant is used to seal the optical die, the logic die, the memory die, and the first underfill, and the lens adapter is attached to the sealant.

18. A method of forming a package, comprising: Forming a package component, wherein forming the package component includes: The optical die is bonded to the interlayer, the optical die including an optical coupler near a first sidewall of the optical die; Connect the logic die to the interposer layer; Depositing a first underfill material between the optical die, the logic die, and the interposer; and A sealant is formed on the optical die, the logic die, and the first bottom filler; The packaging component is bonded to the packaging substrate; A heat sink is attached to the packaging substrate and the packaging assembly, the heat sink including an opening, a portion of the packaging assembly being located in the opening of the heat sink; A support structure is attached to the packaging substrate through the opening in the heat sink cover; The lens adapter is attached to the portion of the encapsulation assembly located in the opening and the support structure in the opening; Attach the reflector to the lens adapter; and An optical fiber is attached to the reflector, the optical fiber being located on the lens adapter, and the optical fiber being configured such that an optical data path extends from a first end of the optical fiber through the reflector and the lens adapter to the optical coupler of the optical die.

19. The method according to claim 18, wherein, The optical die includes a first lens located on the back side of the optical die, the back side of the optical die being opposite to the packaging substrate, the lens adapter includes a second lens located on the lower surface of the lens adapter, and the mirror includes a third lens, the optical data path passing through the first lens, the second lens, and the third lens.

20. The method according to claim 18, wherein, The lens adapter extends across the opening in the heat sink and is attached to an external portion of the heat sink.

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