Clock switching device

Abstract

The present application provides a clock switching device, comprising a first latch circuit, a second latch circuit and a switching circuit. The first latch circuit latches a first selection signal based on a trigger of a first clock signal. The second latch circuit latches a second selection signal based on a trigger of a second clock signal. A reset terminal of the second latch circuit is coupled to the first latch circuit. The second latch circuit is selectively reset based on an output of the first latch circuit. The switching circuit is coupled to an output terminal of the first latch circuit and an output terminal of the second latch circuit. The switching circuit selects one of the clock signals as an output clock signal of the clock switching device based on the selection signals.

Description

Technical Field

[0001] This invention relates to an electronic circuit, and more particularly to a clock switching device. Background Technology

[0002] Electronic circuits require clock signals to operate. Generally, electronic circuits may require multiple clock signals. For example, a computer system may include a core clock signal (used by the central processing unit), a system bus clock signal, and peripheral clock signals. These clock signals can have different speeds / frequencies. The same functional circuit may require different clock signals at different times. For instance, the central processing unit requires a high-frequency clock signal in high-performance mode, but a low-frequency clock signal in power-saving mode. A clock switching device can select one of multiple clock signals and then transmit the selected clock signal to the functional circuit. How to implement a clock switching device is one of the many technical challenges in this field.

[0003] It should be noted that the content of the "Background Art" paragraph is used to help understand the present invention. Some (or all) of the content described in the "Background Art" paragraph may not be known to those skilled in the art. The content described in the "Background Art" paragraph does not imply that the content was known to those skilled in the art prior to this application. Summary of the Invention

[0004] The present invention provides a clock switching device for selecting one of a plurality of clock signals for a functional circuit based on a selection signal.

[0005] In one embodiment of the present invention, the clock switching device includes a first latching circuit, a second latching circuit, and a switching circuit. The first latching circuit latches a first selection signal among a plurality of selection signals based on the triggering of a first clock signal among a plurality of clock signals. The second latching circuit latches a second selection signal among the selection signals based on the triggering of a second clock signal among the clock signals. The reset terminal of the second latching circuit is coupled to the first latching circuit. The second latching circuit is selectively reset based on the output of the first latching circuit. The switching circuit is coupled to the output terminals of the first and second latching circuits. The switching circuit selects one of the clock signals as the output clock signal of the clock switching device based on the selection signals.

[0006] Based on the above, the clock switching device described in the embodiments of the present invention includes multiple latching circuits for latching different selection signals. Based on the latching content (selection signals) of these latching circuits, the switching circuit can select a corresponding clock signal from multiple clock signals for the functional circuit. When the second clock signal is lost and cannot trigger the second latching circuit, the output of the first latching circuit can reset the second latching circuit in real time, so that the switching circuit can at least select the first clock signal for the functional circuit. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a circuit block for an embodiment of a glitch-free clock switch.

[0008] Figure 2 This explains the situation when the clock signal is lost (missing). Figure 1 The waveform diagram of the output clock signal of the circuit shown is as follows.

[0009] Figure 3 This is a circuit block diagram of a clock switching device according to an embodiment of the present invention.

[0010] Figure 4 This is a circuit block diagram of a latching circuit and a switching circuit, drawn according to an embodiment of the present invention.

[0011] Figure 5 This is a circuit block diagram of a latching circuit and a switching circuit, drawn according to another embodiment of the present invention.

[0012] Figure 6 This is a circuit block diagram of the latching circuit and the switching circuit, drawn according to another embodiment of the present invention.

[0013] Figure 7 This is illustrated according to an embodiment of the present invention. Figure 6 The waveform diagram of the output clock signal of the circuit shown is as follows.

[0014] Figure 8 This explains what happens when the clock signal is lost. Figure 6 The waveform diagram of the output clock signal of the circuit shown is as follows.

[0015] Figure 9 This is a circuit block diagram of the latching circuit and the switching circuit, drawn according to a further embodiment of the present invention.

[0016] Figure 10 This is a circuit block diagram of the latching circuit and the switching circuit, drawn according to another embodiment of the present invention.

[0017] Figure 11 This is a circuit block diagram of a latching circuit and a switching circuit, drawn according to another embodiment of the present invention.

[0018] Figure label:

[0019] 30: Functional Circuit

[0020] 100: No False Signal Clock Switch

[0021] 105, 120, 130, 145, AND61, AND62, AND91, AND92, AND93, AND101, AND102, AND113: AND gates

[0022] 110, 115, 135, 140, FF41, FF42, FF53, FF61, FF62, FF63, FF64, FF95, FF96, FF101, FF102, FF103, FF104, FF115, FF116: Triggers

[0023] 125: NOT gate

[0024] 150, OR41, OR51, OR61, OR91: OR gate

[0025] 300: Clock switching device

[0026] 310_1, 310_2, 310_3, 310_n: Latch circuits

[0027] 320: Switching circuit

[0028] CGC41, CGC42, CGC51, CGC52, CGC53: Clock Gating Unit

[0029] CLK0, CLK1, CLK31, CLK_1, CLK_2, CLK_3, CLK_n: Clock signals

[0030] CLKout1, CLK32: Output clock signals

[0031] D: Input terminal

[0032] MUX101, MUX111: Multitasking

[0033] Q, QB, QN: Output terminals

[0034] R: Reset End

[0035] SEL3, SEL10, SEL11, SEL12, SEL_1, SEL_1', SEL_2, SEL_2', SEL_3, SEL_3', SEL_n: selection signal

[0036] t21, t22, t71, t81, t82: Time Detailed Implementation

[0037] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component symbols are used in the drawings and description to denote the same or similar parts.

[0038] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout this specification (including the claims) are used to name components or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of components, nor to limit the order of components. Furthermore, wherever possible, components / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Components / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0039] Figure 1 This is a schematic circuit block diagram of an embodiment of a glitch-free clock switch 100. The glitch-free clock switch 100 includes an AND gate 105, flip-flops 110 and 115, an AND gate 120, an NOT gate 125, an AND gate 130, a flip-flop 135, a flip-flop 140, an AND gate 145, and an OR gate 150. The first input of AND gate 105 receives a selection signal SEL11. The input of flip-flop 110 is coupled to the output of AND gate 105. The trigger terminal of flip-flop 110 receives a clock signal CLK1. The input of flip-flop 115 is coupled to its output Q. The trigger terminal of flip-flop 115 receives the clock signal CLK1. The first input of AND gate 120 is coupled to the first output Q of flip-flop 115 to receive the selection signal SEL11. The second input of AND gate 120 receives the clock signal CLK1.

[0040] The input of NOT gate 125 receives the selection signal SEL11. The first input of AND gate 130 is coupled to the output of NOT gate 125 to receive the selection signal SEL12 (the inverted signal of selection signal SEL11). The second input of AND gate 130 is coupled to the second output QN of flip-flop 115. The input of flip-flop 135 is coupled to the output of AND gate 130. The trigger terminal of flip-flop 135 receives the clock signal CLK0. The input of flip-flop 140 is coupled to the output Q of flip-flop 135. The trigger terminal of flip-flop 140 receives the clock signal CLK0. The second output QN of flip-flop 140 is coupled to the second input of AND gate 105. The first input of AND gate 145 is coupled to the first output Q of flip-flop 140 to receive the selection signal SEL12. The second input of AND gate 145 receives the clock signal CLK0. The first and second inputs of OR gate 150 are coupled to the outputs of AND gate 120 and AND gate 145, respectively. The output of OR gate 150 outputs the output clock signal CLKout1 of the spurious-signal-free clock switch 100.

[0041] When the selection signal SEL11 is at a low logic level, the selection signal SEL12 is at a high logic level. Based on clock signals CLK1 and CLK0, flip-flops 110 and 115 can latch the selection signal SEL11 and transmit it to AND gate 120, while flip-flops 135 and 140 can latch the selection signal SEL12 and transmit it to AND gate 145. Based on the selection signals SEL11 and SEL12, AND gate 120 can block clock signal CLK1, while AND gate 145 can transmit clock signal CLK0 to OR gate 150. Therefore, OR gate 150 can output clock signal CLK0 as the output clock signal CLKout1. Similarly, when the selection signal SEL11 is at a high logic level (and the selection signal SEL12 is at a low logic level), AND gate 145 can block clock signal CLK0, while AND gate 120 can transmit clock signal CLK1 to OR gate 150. Therefore, OR gate 150 can output clock signal CLK1 as output clock signal CLKout1.

[0042] Figure 2 This indicates that the clock signal CLK0 is missing. Figure 1 The waveform diagram of the output clock signal CLKout1 of the circuit shown is as follows. Figure 2 The horizontal axis represents time. Please also refer to... Figure 1 and Figure 2After time t21, the clock signal CLK0 is lost. At time t22, the selection signal SEL11 transitions from a low logic level to a high logic level, thus the voltage level at the output of AND gate 130 transitions from a high logic level to a low logic level. However, because the clock signal CLK0 is lost, the low logic level of the selection signal SEL12 cannot be updated to the first output Q of flip-flop 140, causing the first output Q of flip-flop 140 to remain at the old (incorrect) high logic level, while the second output QN of flip-flop 140 remains at the old (incorrect) low logic level. The incorrect level of the second output QN of flip-flop 140 causes AND gate 105 to erroneously block the transmission of the selection signal SEL11, causing AND gate 120 to block the clock signal CLK1, while AND gate 145 continues to transmit the lost clock signal CLK0 to OR gate 150. Therefore, the output clock signal CLKout1 is also lost, causing the entire system to malfunction (or operate incorrectly).

[0043] Figure 3 This is a circuit block diagram of a clock switching device 300 according to an embodiment of the present invention. It is assumed that the clock signal CLK31 includes n clock signals CLK_1, ..., CLK_n, where n is any integer (n greater than 1) determined according to the actual design. The clock switching device 300 can select a corresponding clock signal from the plurality of clock signals CLK_1 to CLK_n as the output clock signal CLK32 to the functional circuit 30 under the control of the selection signal SEL3. When the selection signal SEL3 changes from clock signal CLK_n to clock signal CLK_1 but clock signal CLK_n is missing, the clock switching device 300 can at least automatically select clock signal CLK_1 to the functional circuit 30 without being affected by the loss of clock signal CLK_n, thus maintaining the normal operation of the functional circuit 30.

[0044] exist Figure 3 In the illustrated embodiment, the clock switching device 300 includes multiple latching circuits, such as latching circuits 310_1, ..., 310_n. It is assumed here that the selection signal SEL3 includes n selection signals SEL_1, ..., SEL_n. Latching circuit 310_1 latches the selection signal SEL_1 in selection signal SEL3 based on the triggering of clock signal CLK_1 in clock signal CLK31. Latching circuit 310_n latches the selection signal SEL_n in selection signal SEL3 based on the triggering of clock signal CLK_n in clock signal CLK31. The reset terminal of latching circuit 310_n is coupled to latching circuit 310_1. Latching circuit 310_n is selectively reset based on the output of latching circuit 310_1. (Not shown in the diagram) Figure 3Other latching circuits can be referred to the relevant description of latching circuit 310_n and deduced by analogy, so they will not be described in detail here.

[0045] exist Figure 3 In the illustrated embodiment, the clock switching device 300 further includes a switching circuit 320. The switching circuit 320 is coupled to the output of each of the latching circuits 310_1 to 310_n. Based on the selection signals SEL_1 to SEL_n, the switching circuit 320 selects one of the clock signals CLK_1 to CLK_n as the output clock signal CLK32 of the clock switching device 300. Based on the latching contents (selection signals SEL_1 to SEL_n) of the latching circuits 310_1 to 310_n, the switching circuit 320 can select a corresponding clock signal (as the output clock signal CLK32) from the plurality of clock signals CLK_1 to CLK_n and supply it to the functional circuit 30. When the selection signal SEL3 changes from the clock signal CLK_n to the clock signal CLK_1, but the clock signal CLK_n is lost and cannot trigger the latch circuit 310_n, the output of the latch circuit 310_1 can reset the latch circuit 310_n in real time to eliminate the effect of the lost clock signal CLK_n, so that the switching circuit 320 can at least select the clock signal CLK_1 for the functional circuit 30.

[0046] This embodiment does not limit the implementation of the latching circuits 310_1 to 310_n and the switching circuit 320. For example, according to actual design, Figure 3 The latching circuit 310_1 shown can be referred to Figure 4 , Figure 5 , Figure 6 , Figure 9 , Figure 10 or Figure 11 The relevant description of the latch circuit 310_1 shown. Figure 3 Other latching circuits shown (e.g., latching circuit 310_n) can be referred to Figure 4 For related instructions on the latch circuit 310_2 shown, or refer to... Figure 5 For the relevant descriptions of the latch circuits 310_2 or 310_3 shown, or refer to... Figure 6 For related instructions on the latch circuit 310_2 shown, or refer to... Figure 9 For the relevant descriptions of the latch circuits 310_2 or 310_3 shown, or refer to... Figure 10 For related instructions on the latch circuit 310_2 shown, or refer to... Figure 11 The relevant descriptions of the latching circuits 310_2 or 310_3 shown are provided below. Figure 3 The switching circuit 320 shown can be referenced. Figure 4 , Figure 5 , Figure 6 , Figure 9 , Figure 10 or Figure 11 The relevant description of the switching circuit 320 shown.

[0047] Figure 4 This is a circuit block diagram illustrating the latching circuit and the switching circuit according to an embodiment of the present invention. Figure 4 In the illustrated embodiment, latching circuit 310_1 includes flip-flop FF41. The input D of flip-flop FF41 receives the selection signal SEL_1 from the selection signal SEL3. The output Q of flip-flop FF41 is coupled to the clock gating unit CGC41 of switching circuit 320 to provide the selection signal SEL_1'. The output QB of flip-flop FF41 is coupled to the reset terminal R of flip-flop FF42 of latching circuit 310_2 to reset latching circuit 310_2. The trigger terminal of flip-flop FF41 receives the clock signal CLK_1 from the clock signal CLK31. Figure 4 In the illustrated embodiment, the trigger terminal of trigger FF41 is a falling edge trigger terminal. In other embodiments, the trigger terminal of trigger FF41 can be a rising edge trigger terminal.

[0048] exist Figure 4 In the illustrated embodiment, the latching circuit 310_2 includes a flip-flop FF42. The input of flip-flop FF42 receives the selection signal SEL_2 from the selection signal SEL3. The output of flip-flop FF42 is coupled to the clock gating unit CGC42 of the switching circuit 320 to provide the selection signal SEL_2'. Figure 4 In the illustrated embodiment, the reset terminal R of flip-flop FF42 is an inverting input. The reset terminal R of flip-flop FF42 is coupled to the output QB of flip-flop FF41 in latch-up circuit 310_1. In other embodiments, when the reset terminal R of flip-flop FF42 is a non-inverting input, the reset terminal of flip-flop FF42 can be recoupled to the output Q of flip-flop FF41. The trigger terminal of flip-flop FF42 receives the clock signal CLK_2 from the clock signal CLK31. Figure 4 In the illustrated embodiment, the trigger terminal of trigger FF42 is a falling edge trigger terminal. In other embodiments, the trigger terminal of trigger FF42 can be a rising edge trigger terminal.

[0049] exist Figure 4 In the illustrated embodiment, the switching circuit 320 includes a clock gating cell CGC41, a clock gating cell CGC42, and an OR gate OR41. According to the actual design, Figure 4The clock gating unit shown can be a known clock gating unit or another clock gating unit. The control terminal of clock gating unit CGC41 is coupled to latch circuit 310_1 to receive selection signal SEL_1'. The input terminal of clock gating unit CGC41 receives clock signal CLK_1. The control terminal of clock gating unit CGC42 is coupled to latch circuit 310_2 to receive selection signal SEL_2'. The input terminal of clock gating unit CGC42 receives clock signal CLK_2. The first and second input terminals of OR gate OR41 are respectively coupled to the output terminal of clock gating unit CGC41, i.e., the output terminal of clock gating unit CGC42. The output terminal of OR gate OR41 outputs the output clock signal CLK32 of clock switching device 300. Based on the latching contents (selection signals SEL_1' and SEL_2') of latching circuits 310_1 and 310_2, switching circuit 320 can select a corresponding clock signal from multiple clock signals CLK_1 and CLK_2 as the output clock signal CLK32.

[0050] When the reset input R of flip-flop FF42 is not coupled to latch circuit 310_1, after the clock signal CLK_2 is lost, although the selection signal SEL_2 transitions from a high logic level to a low logic level (i.e., the selection signal SEL_1 transitions from a low logic level to a high logic level), the selection signal SEL_2' remains at an incorrect high logic level because latch circuit 310_2 is not triggered. When the reset input R of flip-flop FF42 is coupled to latch circuit 310_1, even if the clock signal CLK_2 is lost and latch circuit 310_2 is not triggered, the output of latch circuit 310_1 can reset latch circuit 310_2 in real time (i.e., the selection signal SEL_2' transitions from a high logic level to a low logic level in real time) to eliminate the effect of the lost clock signal CLK_n. Therefore, the clock gating unit CGC42 can block the clock signal CLK_2, while the clock gating unit CGC41 can transmit the clock signal CLK_1 to the OR gate OR41, so that the OR gate OR41 can output the clock signal CLK_1 as the output clock signal CLK32.

[0051] Figure 5 This is a circuit block diagram of a latching circuit and a switching circuit, drawn according to another embodiment of the present invention. Figure 5 The latching circuits 310_1 and 310_2 shown can be referenced. Figure 4 The related descriptions of latch circuits 310_1 and 310_2 shown are omitted here. Compared to Figure 4 The illustrated embodiment, in Figure 5In the illustrated embodiment, the clock switching device 300 further includes a latching circuit 310_3. The latching circuit 310_3 latches the selection signal SEL_3 in the selection signal SEL3 based on the triggering of the clock signal CLK_3 in the clock signal CLK31. The output of the latching circuit 310_3 is coupled to the switching circuit 320. The reset terminal of the latching circuit 310_3 is coupled to the latching circuit 310_1. The latching circuit 310_3 is selectively reset based on the output of the latching circuit 310_1. Figure 5 The latching circuit 310_3 shown can be referred to Figure 4 The relevant descriptions of the latch circuit 310_2 shown are provided and can be extrapolated from there.

[0052] exist Figure 5 In the illustrated embodiment, the latching circuit 310_3 includes a flip-flop FF53. The input D of the flip-flop FF53 receives a selection signal SEL_3. The output Q of the flip-flop FF53 is coupled to the switching circuit 320 to provide a selection signal SEL_3'. The reset terminal R of the flip-flop FF53 is coupled to the latching circuit 310_1. The trigger terminal of the flip-flop FF53 receives a clock signal CLK_3. Figure 5 The trigger FF53 shown can be referenced. Figure 4 The relevant explanations of the FF42 trigger shown are provided and can be extrapolated from here, so they will not be repeated here.

[0053] exist Figure 5 In the illustrated embodiment, the switching circuit 320 includes a clock gating unit CGC51, a clock gating unit CGC52, a clock gating unit CGC53, and an OR gate OR51. The control terminal of clock gating unit CGC51 is coupled to latch circuit 310_1 to receive a selection signal SEL_1'. The input terminal of clock gating unit CGC51 receives a clock signal CLK_1. The control terminal of clock gating unit CGC52 is coupled to latch circuit 310_2 to receive a selection signal SEL_2'. The input terminal of clock gating unit CGC52 receives a clock signal CLK_2. The control terminal of clock gating unit CGC53 is coupled to latch circuit 310_3 to receive a selection signal SEL_3'. The input terminal of clock gating unit CGC53 receives a clock signal CLK_3. The first, second, and third input terminals of OR gate OR51 are respectively coupled to the output terminals of clock gating units CGC51, CGC52, and CGC53. The output of OR gate OR51 outputs the clock signal CLK32 of clock switching device 300. Figure 5 The clock gating units CGC51, CGC52, and CGC53 shown can be referenced. Figure 4 The following is a description of the clock gating units CGC41 and CGC42 shown. Figure 5 The OR gate OR51 shown can be referenced. Figure 4The relevant explanations for the OR41 gate are shown below, so they will not be repeated here.

[0054] Figure 6 This is a circuit block diagram of the latching circuit and the switching circuit, drawn according to another embodiment of the present invention. Figure 6 In the illustrated embodiment, latching circuit 310_1 includes flip-flops FF61 and FF62, latching circuit 310_2 includes flip-flops FF63 and FF64, and switching circuit 320 includes AND gates AND61, AND gates AND62, and OR gates OR61. The input D of flip-flop FF61 receives the selection signal SEL_1 from the selection signal SEL3. The trigger terminal of flip-flop FF61 receives the clock signal CLK_1 from the clock signal CLK31. The input D of flip-flop FF62 is coupled to the output Q of flip-flop FF61. The trigger terminal of flip-flop FF62 receives the clock signal CLK_1. The output Q of flip-flop FF62 is coupled to the AND gate AND61 of switching circuit 320 to provide the selection signal SEL_1'.

[0055] The output terminal QB of flip-flop FF62 is coupled to one of the output terminals Q to the reset terminals R of flip-flop FF63 and FF64 in the latch circuit 310_2, so as to reset the second latch circuit 310_2. Figure 6 The reset terminals R of the flip-flops FF63 and FF64 shown are inverting inputs; therefore, the output QB of flip-flop FF62 is coupled to the reset terminals R of flip-flops FF63 and FF64. In other embodiments, when the reset terminals R of flip-flops FF63 and FF64 are non-inverting inputs, the output Q of flip-flop FF62 is instead coupled to the reset terminals R of flip-flops FF63 and FF64.

[0056] exist Figure 6 In the illustrated embodiment, the trigger terminal of trigger FF61 is a rising-edge trigger terminal, while the trigger terminal of trigger FF62 is a falling-edge trigger terminal. In other embodiments, the trigger terminal of trigger FF61 can be a falling-edge trigger terminal, while the trigger terminal of trigger FF62 can be a rising-edge trigger terminal. In still other embodiments, both the trigger terminals of trigger FF61 and trigger FF62 are rising-edge trigger terminals. In still more embodiments, both the trigger terminals of trigger FF61 and trigger FF62 are falling-edge trigger terminals.

[0057] The input D of flip-flop FF63 receives the selection signal SEL_2 from the selection signal SEL3. The trigger terminal of flip-flop FF63 receives the clock signal CLK_2 from the clock signal CLK31. The reset terminal R of flip-flop FF63 is coupled to latch circuit 310_1. The input D of flip-flop FF64 is coupled to the output Q of flip-flop FF63. The output Q of flip-flop FF64 is coupled to AND gate AND62 of switching circuit 320 to provide the selection signal SEL_2'. The reset terminal R of flip-flop FF64 is coupled to latch circuit 310_1. The trigger terminal of flip-flop FF64 receives the clock signal CLK_2.

[0058] exist Figure 6 In the illustrated embodiment, the trigger terminal of trigger FF63 is a rising-edge trigger terminal, while the trigger terminal of trigger FF64 is a falling-edge trigger terminal. In other embodiments, the trigger terminal of trigger FF63 may be a falling-edge trigger terminal, while the trigger terminal of trigger FF64 may be a rising-edge trigger terminal. In still other embodiments, both the trigger terminals of trigger FF63 and trigger FF64 are rising-edge trigger terminals. In even more embodiments, both the trigger terminals of trigger FF63 and trigger FF64 are falling-edge trigger terminals.

[0059] The first input of AND gate AND61 is coupled to latch circuit 310_1 to receive selection signal SEL_1'. The second input of AND gate AND61 receives clock signal CLK_1. The first input of AND gate AND62 is coupled to latch circuit 310_2 to receive selection signal SEL_2'. The second input of AND gate AND62 receives clock signal CLK_2. The first and second inputs of OR gate OR61 are coupled to the outputs of AND gate AND61 and AND gate AND62, respectively. The output of OR gate OR61 outputs the clock signal CLK32 of clock switching device 300. Based on the latching contents (selection signals SEL_1' and SEL_2') of latch circuits 310_1 and 310_2, switching circuit 320 can select a corresponding clock signal from multiple clock signals CLK_1 and CLK_2 as the output clock signal CLK32.

[0060] Figure 7 This is illustrated according to an embodiment of the present invention. Figure 6 The waveform diagram of the output clock signal CLK32 of the circuit shown is illustrated. Figure 7 The horizontal axis represents time. Please also refer to... Figure 6 and Figure 7Before time t71, the selection signal SEL_2 is at a high logic level (i.e., the selection signal SEL_1 is at a low logic level). Flip-flops FF61 and FF62 latch the selection signal SEL_1 based on the clock signal CLK_1, thus outputting a selection signal SEL_1' with a low logic level. Flip-flops FF63 and FF64 latch the selection signal SEL_2 based on the clock signal CLK_2, thus outputting a selection signal SEL_2' with a high logic level. AND gate AND61 can block the clock signal CLK_1 based on the selection signal SEL_1', while AND gate AND62 can transmit the clock signal CLK_2 to OR gate OR61 based on the selection signal SEL_2'. Therefore, OR gate OR61 can output the clock signal CLK_2 as the output clock signal CLK32.

[0061] After time t71, the selection signal SEL_2 transitions from a high logic level to a low logic level (that is, the selection signal SEL_1 transitions from a low logic level to a high logic level). Flip-flops FF61 and FF62 latch the selection signal SEL_1 based on the clock signal CLK_1, thus outputting a selection signal SEL_1' with a high logic level. Flip-flops FF63 and FF64 latch the selection signal SEL_2 based on the clock signal CLK_2, thus outputting a selection signal SEL_2' with a low logic level. AND gate AND62 can block the clock signal CLK_2 based on the selection signal SEL_2', while AND gate AND61 can transmit the clock signal CLK_1 to OR gate OR61 based on the selection signal SEL_1'. Therefore, after time t71, the output clock signal CLK32 output by OR gate OR61 can switch from clock signal CLK_2 to clock signal CLK_1.

[0062] Figure 8 This explains the situation when the clock signal CLK_2 is lost. Figure 6 The waveform diagram of the output clock signal CLK32 of the circuit shown is illustrated. Figure 8 The horizontal axis represents time. Please also refer to... Figure 6 and Figure 8 Before time t82, the selection signal SEL_2 is at a high logic level (i.e., the selection signal SEL_1 is at a low logic level), therefore OR gate OR61 can output clock signal CLK_2 as the output clock signal CLK32 (see details regarding...). Figure 7 (Relevant explanations before time t71 shown). Different from... Figure 7 The example of the scenario shown is that, in Figure 8 As shown, the clock signal CLK_2 is lost after time t81.

[0063] exist Figure 8After time t82, the selection signal SEL_2 transitions from a high logic level to a low logic level (i.e., the selection signal SEL_1 transitions from a low logic level to a high logic level). Because the clock signal CLK_2 is lost, flip-flops FF63 and FF64 cannot update their latch contents. Flip-flops FF61 and FF62 can latch the selection signal SEL_1 based on the triggering of the clock signal CLK_1, thereby outputting a selection signal SEL_1' with a high logic level. Simultaneously, the output QB of flip-flop FF62 can output a low logic level to the reset input R of flip-flops FF63 and FF64 to reset the latch circuit 310_2 in real time, thus causing the selection signal SEL_2' to transition from a high logic level to a low logic level in real time. AND gate AND62 can block the lost clock signal CLK_2 based on the low logic level selection signal SEL_2', while AND gate AND61 can transmit the clock signal CLK_1 to OR gate OR61 based on the high logic level selection signal SEL_1'. Therefore, OR gate OR61 can output clock signal CLK_1 as output clock signal CLK32.

[0064] Figure 9 This is a circuit block diagram of the latching circuit and the switching circuit, drawn according to a further embodiment of the present invention. Figure 9 The latching circuits 310_1 and 310_2 shown can be referenced. Figure 6 The related descriptions of latch circuits 310_1 and 310_2 shown are omitted here. Compared to Figure 6 The illustrated embodiment, in Figure 9 In the illustrated embodiment, the clock switching device 300 further includes a latching circuit 310_3. The latching circuit 310_3 latches the selection signal SEL_3 in the selection signal SEL3 based on the triggering of the clock signal CLK_3 in the clock signal CLK31. The output of the latching circuit 310_3 is coupled to the switching circuit 320. The reset terminal of the latching circuit 310_3 is coupled to the latching circuit 310_1. The latching circuit 310_3 is selectively reset based on the output of the latching circuit 310_1. Figure 9 The latching circuit 310_3 shown can be referred to Figure 6 The relevant descriptions of the latch circuit 310_2 shown are provided and can be extrapolated from there.

[0065] exist Figure 9In the illustrated embodiment, the latching circuit 310_3 includes flip-flops FF95 and FF96. The input of flip-flop FF95 receives a selection signal SEL_3. The trigger terminal of flip-flop FF95 receives a clock signal CLK_3. The reset terminal R of flip-flop FF95 is coupled to the latching circuit 310_1. The input of flip-flop FF96 is coupled to the output Q of flip-flop FF95. The output Q of flip-flop FF96 is coupled to the switching circuit 320 to provide a selection signal SEL_3'. The reset terminal R of flip-flop FF96 is coupled to the latching circuit 310_1. The trigger terminal of flip-flop FF96 receives the clock signal CLK_3. Figure 9 The triggers FF95 and FF96 shown can be referenced. Figure 6 The relevant explanations of the triggers FF63 and FF64 shown are provided and can be extrapolated from here on out, so they will not be repeated here.

[0066] exist Figure 9 In the illustrated embodiment, the switching circuit 320 includes AND gates AND91, AND92, AND93, and OR gate OR91. The first input of AND gate AND91 is coupled to latching circuit 310_1 to receive the selection signal SEL_1'. The second input of AND gate AND91 receives the clock signal CLK_1. The first input of AND gate AND92 is coupled to latching circuit 310_2 to receive the selection signal SEL_2'. The second input of AND gate AND92 receives the clock signal CLK_2. The first input of AND gate AND93 is coupled to latching circuit 310_3 to receive the selection signal SEL_3'. The second input of AND gate AND93 receives the clock signal CLK_3. The first, second, and third inputs of OR gate OR91 are coupled to the outputs of AND gates AND91, AND92, and AND93, respectively. The output of OR gate OR91 outputs the clock signal CLK32 of the clock switching device 300. Figure 9 The AND gates AND91, AND92, and AND93 shown can be referenced. Figure 6 The following is a description of AND gates AND612 and AND62. Figure 9 The OR gate OR91 shown can be referenced. Figure 6 The relevant explanations for the OR61 gate are shown below, so they will not be repeated here.

[0067] Figure 10 This is a circuit block diagram of the latching circuit and the switching circuit, drawn according to another embodiment of the present invention. Figure 10In the illustrated embodiment, latching circuit 310_1 includes flip-flops FF101 and FF102 and AND gate AND101, latching circuit 310_2 includes flip-flops FF103 and FF104 and AND gate AND102, and switching circuit 320 includes a multiplexer MUX101. The first input of AND gate AND101 receives clock signal CLK_1 from clock signal CLK31.

[0068] The input D of flip-flop FF101 receives the selection signal SEL_1 from the selection signal SEL3. The trigger terminal of flip-flop FF101 receives the clock signal CLK_1. The input D of flip-flop FF102 is coupled to the output Q of flip-flop FF101. The trigger terminal of flip-flop FF102 receives the clock signal CLK_1. The output Q of flip-flop FF102 is coupled to the second input of AND gate AND101 to provide the latch content (selection signal SEL_1'). The output of AND gate AND101 is coupled to the multiplexer MUX101 of switching circuit 320.

[0069] The output terminal QB and output terminal Q of flip-flop FF102 are coupled to the reset terminal R of flip-flop FF103 and the reset terminal R of flip-flop FF104 in latch circuit 310_2 to reset latch circuit 310_2. Figure 10 The reset terminals R of the flip-flops FF103 and FF104 shown are inverting inputs; therefore, the output QB of flip-flop FF102 is coupled to the reset terminals R of flip-flops FF103 and FF104. In other embodiments, when the reset terminals R of flip-flops FF103 and FF104 are non-inverting inputs, the output Q of flip-flop FF102 is instead coupled to the reset terminals R of flip-flops FF103 and FF104.

[0070] exist Figure 10 In the illustrated embodiment, the trigger terminal of trigger FF101 is a rising-edge trigger terminal, while the trigger terminal of trigger FF102 is a falling-edge trigger terminal. In other embodiments, the trigger terminal of trigger FF101 can be a falling-edge trigger terminal, while the trigger terminal of trigger FF102 can be a rising-edge trigger terminal. In still other embodiments, both the trigger terminals of trigger FF101 and trigger FF102 are rising-edge trigger terminals. In even more embodiments, both the trigger terminals of trigger FF101 and trigger FF102 are falling-edge trigger terminals.

[0071] The first input of AND gate AND102 receives clock signal CLK_2 from clock signal CLK31. The input D of flip-flop FF103 receives selection signal SEL_2 from selection signal SEL3. The trigger terminal of flip-flop FF103 receives clock signal CLK_2. The reset terminal R of flip-flop FF103 is coupled to latch circuit 310_1. The input D of flip-flop FF104 is coupled to the output Q of flip-flop FF103. The reset terminal R of flip-flop FF104 is coupled to latch circuit 310_1. The trigger terminal of flip-flop FF104 receives clock signal CLK_2. The output Q of flip-flop FF104 is coupled to the second input of AND gate AND102 to provide selection signal SEL_2'. The output of AND gate AND102 is coupled to the multiplexer MUX101 of switching circuit 320.

[0072] exist Figure 10 In the illustrated embodiment, the trigger terminal of trigger FF103 is a rising-edge trigger terminal, while the trigger terminal of trigger FF104 is a falling-edge trigger terminal. In other embodiments, the trigger terminal of trigger FF103 may be a falling-edge trigger terminal, while the trigger terminal of trigger FF104 may be a rising-edge trigger terminal. In still other embodiments, both the trigger terminals of trigger FF103 and trigger FF104 are rising-edge trigger terminals. In even more embodiments, both the trigger terminals of trigger FF103 and trigger FF104 are falling-edge trigger terminals.

[0073] The first input of the multiplexer MUX101 is coupled to the output of the AND gate AND101 of the latch circuit 310_1. The second input of the multiplexer MUX101 is coupled to the output of the AND gate AND102 of the latch circuit 310_2. The output of the multiplexer MUX101 outputs the output clock signal CLK32 of the clock switching device 300. The multiplexer MUX101 is controlled by the selection signal SEL10. In some embodiments, the selection signal SEL10 includes the selection signal SEL_1' provided by the flip-flop FF102 and the selection signal SEL_2' provided by the flip-flop FF104. In other embodiments, the selection signal SEL10 may be the selection signal SEL3. When the selection signal SEL10 selects the clock signal CLK_1, that is, when the selection signal SEL_2 is low and the selection signal SEL_1 is high, the multiplexer MUX101 selects the output of one of the AND gates AND101 and AND102 as the output clock signal CLK32.

[0074] Figure 11 This is a circuit block diagram of a latching circuit and a switching circuit, drawn according to another embodiment of the present invention. Figure 11 The latching circuits 310_1 and 310_2 shown can be referenced. Figure 10 The related descriptions of latch circuits 310_1 and 310_2 shown are omitted here. Compared to Figure 10 The illustrated embodiment, in Figure 11 In the illustrated embodiment, the clock switching device 300 further includes a latching circuit 310_3. The latching circuit 310_3 latches the selection signal SEL_3 in the selection signal SEL3 based on the triggering of the clock signal CLK_3 in the clock signal CLK31. The output of the latching circuit 310_3 is coupled to the switching circuit 320. The reset terminal of the latching circuit 310_3 is coupled to the latching circuit 310_1. The latching circuit 310_3 is selectively reset based on the output of the latching circuit 310_1. Figure 11 The latching circuit 310_3 shown can be referred to Figure 10 The relevant descriptions of the latch circuit 310_2 shown are provided and can be extrapolated from there.

[0075] exist Figure 11 In the illustrated embodiment, the latching circuit 310_3 includes flip-flops FF115 and FF116, and an AND gate AND113. The first input of the AND gate AND113 receives a clock signal CLK_3. The input of flip-flop FF115 receives a selection signal SEL_3. The trigger terminal of flip-flop FF115 receives the clock signal CLK_3. The reset terminal R of flip-flop FF115 is coupled to the latching circuit 310_1. The input of flip-flop FF116 is coupled to the output Q of flip-flop FF115. The output Q of flip-flop FF116 is coupled to the second input of the AND gate AND113 to provide the selection signal SEL_3'. The reset terminal R of flip-flop FF116 is coupled to the latching circuit 310_1. The trigger terminal of flip-flop FF116 receives the clock signal CLK_3. The output of the AND gate AND113 is coupled to the switching circuit 320. Figure 11 The flip-flop FF115, flip-flop FF116, and AND gate AND113 shown can be referenced. Figure 10 The descriptions of the triggers FF103, FF104, and AND gate AND102 are shown and can be extrapolated from there, so they will not be repeated here.

[0076] exist Figure 11In the illustrated embodiment, the switching circuit 320 includes a multiplexer MUX111. A first input of the multiplexer MUX111 is coupled to the output of latching circuit 310_1. A second input of the multiplexer MUX111 is coupled to the output of latching circuit 310_2. A third input of the multiplexer MUX111 is coupled to the output of latching circuit 310_3. The output of the multiplexer MUX111 outputs the output clock signal CLK32 of the clock switching device 300. The multiplexer MUX111 is controlled by a selection signal SEL10. In some embodiments, the selection signal SEL10 includes selection signals SEL_1', SEL_2', and SEL_3'. In other embodiments, the selection signal SEL10 may be the selection signal SEL3. Figure 11 The multitasking device MUX111 shown can be referenced. Figure 10 The relevant descriptions of the MUX101 multitasking unit shown are provided below, so they will not be repeated here.

[0077] In summary, the clock switching device 300 described in the above embodiments includes multiple latching circuits 310_1 to 310_n for latching different selection signals SEL_1 to SEL_n. Based on the latching content (selection signals SEL_1 to SEL_n) of these latching circuits 310_1 to 310_n, the switching circuit 320 can select a corresponding clock signal (as the output clock signal CLK32) from the multiple clock signals CLK_1 to CLK_n and send it to the functional circuit 30. When one of the clock signals (e.g., clock signal CLK_n) is lost and cannot trigger one of the latching circuits (e.g., latching circuit 310_n), the output of latching circuit 310_1 can reset the other latching circuits in real time, so that the switching circuit 320 can at least select clock signal CLK_1 to send to the functional circuit 30.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A clock switching apparatus, characterized by comprising: The clock switching device includes: A first latching circuit is used to latch a first selection signal among a plurality of selection signals based on the triggering of a first clock signal among a plurality of clock signals; A second latching circuit is configured to latch a second selection signal among the plurality of selection signals based on the triggering of a second clock signal among the plurality of clock signals, wherein the reset terminal of the second latching circuit is coupled to the first latching circuit, and the second latching circuit is selectively reset based on the output of the first latching circuit; and A switching circuit is coupled to the output of the first latching circuit and the output of the second latching circuit, wherein the switching circuit selects one of the plurality of clock signals as the output clock signal of the clock switching device based on the plurality of selection signals; The first latching circuit includes: A trigger has an input for receiving the first selection signal, wherein a first output of the trigger is coupled to the switching circuit to provide the first selection signal, a second output of the trigger is coupled to the reset terminal of the second latching circuit to reset the second latching circuit, and the trigger terminal of the trigger receives the first clock signal.

2. The clock switching device as described in claim 1, characterized in that, The first latching circuit includes: A first flip-flop has an input terminal for receiving the first selection signal, wherein the trigger terminal of the first flip-flop receives the first clock signal; An AND gate having an output coupled to the switching circuit, wherein a first input of the AND gate receives the first clock signal; and The second flip-flop has an input terminal coupled to the output terminal of the first flip-flop, wherein the first output terminal of the second flip-flop is coupled to the second input terminal of the AND gate to provide the first selection signal, the second output terminal of the second flip-flop and one of the first output terminals are coupled to the reset terminal of the second latch circuit to reset the second latch circuit, and the trigger terminal of the second flip-flop receives the first clock signal.

3. The clock switching device as described in claim 2, characterized in that, One of the trigger terminals of the first trigger and the second trigger is a rising edge trigger terminal, and the other of the trigger terminals of the first trigger and the second trigger is a falling edge trigger terminal.

4. The clock switching device as described in claim 2, characterized in that, Both the trigger terminals of the first trigger and the second trigger are either rising edge trigger terminals or falling edge trigger terminals.

5. The clock switching device as described in claim 1, characterized in that, The second latching circuit includes: A trigger has an input for receiving the second selection signal, wherein the output of the trigger is coupled to the switching circuit to provide the second selection signal, the reset terminal of the trigger is coupled to the first latching circuit, and the trigger terminal of the trigger receives the second clock signal.

6. The clock switching device as described in claim 1, characterized in that, The second latching circuit includes: A first flip-flop has an input terminal for receiving a second selection signal, wherein the trigger terminal of the first flip-flop receives a second clock signal, and the reset terminal of the first flip-flop is coupled to the first latching circuit; and The second flip-flop has an input terminal coupled to the output terminal of the first flip-flop, wherein the output terminal of the second flip-flop is coupled to the switching circuit to provide the second selection signal, the reset terminal of the second flip-flop is coupled to the first latching circuit, and the trigger terminal of the second flip-flop receives the second clock signal.

7. The clock switching device as described in claim 1, characterized in that, The second latching circuit includes: A first flip-flop has an input terminal for receiving a second selection signal, wherein the trigger terminal of the first flip-flop receives a second clock signal, and the reset terminal of the first flip-flop is coupled to the first latching circuit; and An AND gate having an output coupled to the switching circuit, wherein a first input of the AND gate receives the second clock signal; and The second flip-flop has an input terminal coupled to the output terminal of the first flip-flop, wherein the output terminal of the second flip-flop is coupled to the second input terminal of the AND gate to provide the second selection signal, the reset terminal of the second flip-flop is coupled to the first latch circuit, and the trigger terminal of the second flip-flop receives the second clock signal.

8. The clock switching device as described in claim 6 or 7, characterized in that, One of the trigger terminals of the first trigger and the second trigger is a rising edge trigger terminal, and the other of the trigger terminals of the first trigger and the second trigger is a falling edge trigger terminal.

9. The clock switching device as described in claim 6 or 7, characterized in that, Both the trigger terminals of the first trigger and the second trigger are either rising edge trigger terminals or falling edge trigger terminals.

10. The clock switching device as claimed in claim 1, characterized in that, The switching circuit includes: A first clock gating unit has a control terminal coupled to the first latching circuit to receive the first selection signal, wherein the input terminal of the first clock gating unit receives the first clock signal; A second clock gating unit has a control terminal coupled to the second latching circuit to receive the second selection signal, wherein the input terminal of the second clock gating unit receives the second clock signal; and An OR gate has a first input terminal and a second input terminal respectively coupled to the output terminal of the first clock gating unit and the output terminal of the second clock gating unit, wherein the output terminal of the OR gate outputs the output clock signal of the clock switching device.

11. The clock switching device as claimed in claim 1, characterized in that, The switching circuit includes: A multiplexer has a first input terminal coupled to the output terminal of the first latching circuit, wherein a second input terminal of the multiplexer is coupled to the output terminal of the second latching circuit, and the output terminal of the multiplexer outputs the output clock signal of the clock switching device.

12. The clock switching device as claimed in claim 1, characterized in that, The clock switching device further includes: A third latching circuit is configured to latch a third selection signal among the plurality of selection signals based on the triggering of a third clock signal among the plurality of clock signals, wherein the output of the third latching circuit is coupled to the switching circuit, the reset terminal of the third latching circuit is coupled to the first latching circuit, and the third latching circuit is selectively reset based on the output of the first latching circuit.

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