Fast block interleaving or deinterleaving method and apparatus implemented using a single memory

Abstract

The present disclosure provides a fast block interleaving or deinterleaving method implemented by using a single memory, which can be applied to the field of communication technology. The method comprises: writing initial data stored in a buffer to an external memory in response to a plurality of internal memories being in a data read state; in the case that a data read request returned by a target internal memory of the plurality of internal memories is received, determining a first unit offset and a second unit offset related to the external memory based on a preset interleaving depth, a data read-write performance parameter of the external memory and a first data bit width of the external memory; and writing the initial data to the target internal memory by interleaving based on the first unit offset and the second unit offset, and using a first row counter and a first column counter related to the initial data. The present disclosure also provides a fast block interleaving or deinterleaving device and an electronic equipment implemented by using a single memory.

Description

Technical Field

[0001] This disclosure relates to the field of communication technology, specifically to the field of free-space laser communication system technology, and more specifically to a fast block interleaving or deinterleaving method, apparatus, and electronic device implemented using a single-chip memory. Background Technology

[0002] Free-space optical communication transmits laser signals directly through space to achieve information communication goals. It boasts advantages such as high bandwidth, high security, and unrestricted frequency, leading to its rapid development in recent years. However, in free-space optical channels, if the transmission path passes through the atmosphere, additive noise and burst errors caused by atmospheric turbulence and dust particles can severely degrade the optical signal quality, even leading to complete signal loss. In space-to-ground laser communication systems, transmission path obstruction and fading caused by atmospheric turbulence can result in a series of burst errors in the data. Conventional channel error correction coding can only correct a limited number of random errors; for a large number of burst errors, this exceeds the error correction capability of channel error correction coding. Therefore, a combination of channel error correction coding and interleaving coding is used to correct a large number of burst errors. In interleaving coding, a greater interleaving depth and greater dispersion result in better error correction capability. Therefore, to improve error correction capability and meet the requirements of higher interleaving depth, the interleaver needs to provide a larger storage capacity. When using a Field Programmable Gate Array (FPGA) chip as an interleaver, the FPGA chip has limited storage capacity, which is difficult to meet the storage capacity requirements for higher interleaving depths. Therefore, an external high-speed memory is generally used to complete the interleaving and uninterleaving process.

[0003] Due to the characteristics of block interleaving, rows must be written before columns are read, resulting in non-contiguous addresses and preventing sequential read operations; only random reads are possible, reducing the memory read rate. Related technologies employ multiple external memory chips to meet the storage capacity and speed requirements for higher interleaving depths. However, using multiple external memory chips increases costs, and using a single external memory chip for interleaving and deinterleaving is affected by the interleaving strategy, leading to a lower read rate and failing to meet the demands of high-speed interleaving and deinterleaving. Summary of the Invention

[0004] In view of the above problems, this disclosure provides a method, apparatus and electronic device for fast block interleaving or deinterleaving implemented using a single-chip memory.

[0005] According to a first aspect of this disclosure, a fast block interleaving or deinterleaving method using a single-chip memory is provided, comprising: in response to multiple internal memories being in a data read state, writing initial data stored in a buffer into an external memory; upon receiving a data read request returned by a target internal memory among the multiple internal memories, determining a first unit offset and a second unit offset associated with the external memory based on a preset interleaving depth, data read / write performance parameters of the external memory, and a first data bit width of the external memory; and interleaving the initial data into the target internal memory based on the first unit offset and the second unit offset, using a first row counter and a first column counter associated with the initial data.

[0006] According to embodiments of this disclosure, the process of interleaving the initial data into the target internal memory based on the first unit offset and the second unit offset, using a first row counter and a first column counter associated with the initial data, includes: determining the storage address of the initial sub-data to be processed in the initial data based on the count value of the first row counter, the count value of the first column counter, the first unit offset, and the second unit offset; writing the initial sub-data into the target internal memory based on the storage address of the initial sub-data; and updating the count values ​​of the first row counter and the first column counter, respectively.

[0007] According to embodiments of this disclosure, determining the storage address of the initial sub-data based on the count value of the first row counter, the count value of the first column counter, the first unit offset, and the second unit offset includes: determining a row address offset based on the first unit offset and the count value of the first row counter; determining a column address offset based on the second unit offset and the count value of the first column counter; and determining the storage address of the initial sub-data based on the initial storage address of the initial data, the row address offset of the initial sub-data, and the column address offset of the initial sub-data.

[0008] According to embodiments of this disclosure, updating the count values ​​of the first row counter and the first column counter includes: updating the count value of the first row counter based on a first preset step size; and updating the count value of the first column counter based on a second preset step size when it is determined that the count value of the first row counter is equal to the preset interleaving depth.

[0009] According to an embodiment of this disclosure, the method further includes: resetting the count value of the first row counter to an initial value when it is determined that the count value of the first row counter is equal to the preset interleaving depth; and resetting the count value of the first column counter to an initial value when it is determined that the count value of the first column counter is equal to a pre-designed value, wherein the pre-designed value is related to the data read / write performance parameters of the external memory and the first data bit width of the external memory.

[0010] According to an embodiment of this disclosure, writing the initial sub-data into the target internal memory based on the storage address of the initial sub-data includes: dividing the initial sub-data into multiple data blocks based on the data read / write performance parameters of the external memory; determining the storage address of each of the multiple data blocks based on the storage address of the initial sub-data; and sequentially writing the multiple data blocks into the target internal memory based on the storage address of each of the multiple data blocks.

[0011] According to embodiments of this disclosure, determining the first unit offset and the second unit offset related to the external memory based on the preset interleaving depth, the data read / write performance parameters of the external memory, and the first data bit width of the external memory includes: determining the first unit offset based on the data volume of the initial data, the preset interleaving depth, and the first data bit width of the external memory; and determining the second unit offset based on the data read / write performance parameters of the external memory and the first data bit width of the external memory.

[0012] According to an embodiment of this disclosure, the method further includes: determining the number of rows and the number of columns associated with the internal memory based on the second bit width of the internal memory; and reading out the interleaved target data in the internal memory based on the number of rows and the number of columns using a second row counter and a second column counter.

[0013] A second aspect of this disclosure provides a fast block interleaving or deinterleaving apparatus implemented using a single-chip memory, comprising: an external memory write module for writing initial data stored in a buffer to an external memory in response to multiple internal memories being in a data read state; an offset determination module for determining a first unit offset and a second unit offset associated with the external memory based on a preset interleaving depth, data read / write performance parameters of the external memory, and a first data bit width of the external memory upon receiving a data read request returned by a target internal memory among the multiple internal memories; and a memory write module for interleaving the initial data into the target internal memory based on the first unit offset and the second unit offset, using a first row counter and a first column counter associated with the initial data.

[0014] A third aspect of this disclosure provides an electronic device comprising: one or more processors; and a memory for storing one or more programs, wherein, when the one or more programs are executed by the one or more processors, the one or more processors perform the fast block interleaving or deinterleaving method implemented using a single-chip memory described above.

[0015] By responding to multiple internal memories being in a data read state, the initial data stored in the buffer is written to the external memory. This allows the external memory to perform write operations when it is in an idle state where no read operation is required, saving the time needed for data read and write operations and thus improving the interleaving rate. Simultaneously, using external memory for interleaving increases the interleaver's storage capacity, meeting the requirements for higher interleaving depths. By determining the target internal memory among multiple internal memories, the internal memory not in a read state is identified as the target internal memory, ensuring that readable data is available in all internal memories. By determining the first unit offset and the second unit offset, address control is implemented based on the first unit offset and the second unit offset when reading the initial data stored in the external memory, thereby achieving high-speed interleaving. Attached Figure Description

[0016] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0017] Figure 1 This illustration schematically depicts an application scenario of a fast block interleaving or deinterleaving method, apparatus, and device implemented using a single-chip memory according to embodiments of the present disclosure.

[0018] Figure 2 A flowchart illustrating a fast block interleaving or deinterleaving method implemented using a single-chip memory according to an embodiment of the present disclosure is shown schematically.

[0019] Figure 3 A flowchart illustrating the writing of data to a target internal memory according to an embodiment of the present disclosure is shown schematically.

[0020] Figure 4 A flowchart illustrating the determination of the initial sub-data storage address according to an embodiment of the present disclosure is shown schematically;

[0021] Figure 5 A flowchart illustrating the writing of initial sub-data into the target internal memory according to an embodiment of the present disclosure is shown schematically;

[0022] Figure 6 This schematically illustrates a storage structure diagram of initial data in an external memory according to an embodiment of the present disclosure;

[0023] Figure 7 This schematically illustrates a structure for reading initial data from an external memory according to an embodiment of the present disclosure.

[0024] Figure 8 A flowchart illustrating the reading of target data according to an embodiment of the present disclosure is shown schematically;

[0025] Figure 9 This schematic diagram illustrates the storage structure of target data in the internal memory according to an embodiment of the present disclosure;

[0026] Figure 10 A schematic block diagram illustrating a fast block interleaving or deinterleaving apparatus implemented using a single-chip memory according to embodiments of the present disclosure is shown; and

[0027] Figure 11 A block diagram schematically illustrates an electronic device suitable for implementing a fast block interleaving or deinterleaving method using a single-chip memory, according to embodiments of the present disclosure. Detailed Implementation

[0028] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0030] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0031] When using expressions such as "at least one of A, B, and C", they should generally be interpreted in accordance with the meaning that is commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B, and C, etc.).

[0032] In related technologies, interleaving technology utilizes FPGA chips to achieve data interleaving and deinterleaving. However, due to the limited storage capacity of FPGA chips, it cannot meet the requirements for higher interleaving depths. For example, when the continuous bit error length is on the order of MBytes, if the error correction capability can meet the correction requirements at a bit error rate of 2%, interleaving requires approximately 128MB of storage space. Such a large-scale storage unit is difficult to integrate into a traditional FPGA chip, meaning that the storage capacity of the FPGA chip cannot meet the storage capacity requirements for interleaving and deinterleaving.

[0033] Embodiments of this disclosure provide a fast block interleaving or deinterleaving method implemented using a single-chip memory. The method includes: in response to multiple internal memories being in a data read state, writing initial data stored in a buffer into an external memory; upon receiving a data read request returned by a target internal memory among the multiple internal memories, determining a first unit offset and a second unit offset associated with the external memory based on a preset interleaving depth, data read / write performance parameters of the external memory, and a first data bit width of the external memory; and based on the first unit offset and the second unit offset, interleaving the initial data into the target internal memory using a first row counter and a first column counter associated with the initial data.

[0034] Figure 1 The illustration shows an application scenario of a fast block interleaving or deinterleaving method implemented using a single-chip memory according to an embodiment of the present disclosure.

[0035] like Figure 1 As shown, application scenario 100 according to this embodiment may include an FPGA chip 110 and an external memory 120. The FPGA chip 110 includes three parts: a buffer, internal memory, and a read / write control component. The external memory 120 is used to store data read from the buffer by the read / write control component.

[0036] The buffer performs bit-width conversion and buffering on data before it is written to external memory 120. The internal memory stores data read from external memory 120 by the read / write control component. The read / write control component writes data stored in the buffer to external memory 120 and writes data stored in external memory 120 to internal memory.

[0037] It should be noted that the fast block interleaving or deinterleaving method implemented using a single-chip memory provided in the embodiments of this disclosure can generally be executed by the read / write control component. Correspondingly, the fast block interleaving or deinterleaving device implemented using a single-chip memory provided in the embodiments of this disclosure can generally be disposed within the read / write control component. The fast block interleaving or deinterleaving method implemented using a single-chip memory provided in the embodiments of this disclosure can also be executed by a component or component cluster that is different from the read / write control component and can communicate with the cache, internal memory, external memory 120, and / or the read / write control component. Correspondingly, the fast block interleaving or deinterleaving device implemented using a single-chip memory provided in the embodiments of this disclosure can also be disposed within a component or component cluster that is different from the read / write control component and can communicate with the cache, internal memory, external memory 120, and / or the read / write control component.

[0038] It should be understood that Figure 1 The number of registers, internal memory, external memory, and read / write control components shown is merely illustrative. Depending on implementation requirements, any number of registers, internal memory, external memory, and read / write control components can be included.

[0039] The following will be based on Figure 1 The described scene, through Figures 2-9 The fast block interleaving or deinterleaving method implemented using a single-chip memory according to the disclosed embodiments is described in detail.

[0040] Figure 2 A flowchart illustrating a fast block interleaving or deinterleaving method implemented using a single-chip memory according to an embodiment of the present disclosure is shown.

[0041] like Figure 2 As shown, the fast block interleaving or deinterleaving method 200 implemented using a single-chip memory in this embodiment includes operations S210 to S230.

[0042] In operation S210, in response to multiple internal memories being in a data read state, the initial data stored in the buffer is written to the external memory.

[0043] According to embodiments of this disclosure, the number of internal memories is at least two, which may include simple dual-port random access memory (RAM) or similar memory, located inside the FPGA chip. The buffer may include first-in-first-out (FIFO) memory, located inside the FPGA chip. Initial data is stored in the buffer. External memories are located outside the FPGA chip and may include third-generation double-data-rate synchronous dynamic random-access memory (DDR3).

[0044] According to the embodiments of this disclosure, since external memory cannot perform read and write operations simultaneously, in order to prioritize ensuring that there is readable data in multiple internal memories, when multiple internal memories are in the data read state, it is not necessary to read the data in the external memory and write the data to the internal memory. The initial data in the buffer can be written to the external memory during the idle time of the external memory, saving time and improving efficiency.

[0045] According to embodiments of this disclosure, when an FPGA chip receives externally input data to be interleaved or deinterleaved, it stores the data in a buffer. This allows for bit-width conversion of the data before it is written to external memory, thus serving as a buffer.

[0046] For example, the external memory can be DDR3 with a storage bus width of 16 bits, and the data volume for one read / write operation is 128 bits. Therefore, the cache can be set to process 128 bits of data in one read operation, and the data volume processed in one write operation can be adjusted according to the needs of the external front-end components.

[0047] In operation S220, when a data read request is received from a target internal memory in multiple internal memories, a first unit offset and a second unit offset related to the external memory are determined based on a preset interleaving depth, the data read / write performance parameters of the external memory, and the first data bit width of the external memory.

[0048] According to embodiments of this disclosure, the target internal memory is an internal memory that is not in a read state among multiple internal memories. A data read request is a request returned by the target internal memory that requires reading data from the external memory and writing the data back to the target internal memory. The interleaving depth is the minimum distance between adjacent data before interleaving and after interleaving; the preset interleaving depth is a preset value for the interleaving depth and can be adjusted as needed. The data read / write performance parameters of the external memory are used to characterize the amount of data processed in a single read or write operation and are related to the read / write performance of the external memory. The first data bit width is used to characterize the number of data bits at each address in the external memory and is related to the storage performance of the external memory. The first unit offset and the second unit offset are used to characterize the unit distance between the actual storage address of the data in the external memory and the base address of the external memory.

[0049] According to the embodiments of this disclosure, an internal memory that is not in a read state among multiple internal memories is identified as the target internal memory. At this time, the target internal memory is in an idle state, and the target internal memory returns a data read request, ensuring that there is readable data in multiple internal memories.

[0050] In operation S230, based on the first unit offset and the second unit offset, the initial data is interleaved and written into the target internal memory using the first row counter and the first column counter associated with the initial data.

[0051] According to embodiments of this disclosure, a first row counter and a first column counter are used to determine the storage address when reading initial data from external memory.

[0052] According to embodiments of this disclosure, based on a first unit offset and a second unit offset, a first row counter and a first column counter can be used to determine a portion of initial data to be read and write it into the target internal memory.

[0053] According to the disclosed embodiments, in response to multiple internal memories being in a data read state, the initial data stored in the buffer is written to the external memory. This allows the external memory to perform write operations when it is in an idle state where no read operation is required, saving the time required for data read and write operations and thus improving the interleaving rate. Simultaneously, using the external memory for interleaving increases the interleaver's storage capacity, meeting the requirements for higher interleaving depths. By determining the target internal memory among the multiple internal memories, the internal memory not in a read state is identified as the target internal memory, ensuring that readable data exists in all internal memories. By determining a first unit offset and a second unit offset, address control is implemented based on the first unit offset and the second unit offset when reading the initial data stored in the external memory, thereby achieving high-speed interleaving.

[0054] Figure 3 A flowchart illustrating the writing of data to a target internal memory according to an embodiment of the present disclosure is shown.

[0055] like Figure 3 As shown, the method includes operations S310 to S330.

[0056] In operation S310, the storage address of the initial sub-data to be processed in the initial data is determined based on the count value of the first row counter, the count value of the first column counter, the first unit offset, and the second unit offset.

[0057] According to embodiments of this disclosure, the initial sub-data is a portion of the initial data to be processed, and the data elements within the initial sub-data are read out in a sequential manner.

[0058] According to embodiments of this disclosure, the count value of the first row counter is used to characterize the number of unit distances the storage address of the initial sub-data is offset from the initial data base address in the row direction. The first column counter is used to characterize the number of unit distances the storage address of the initial sub-data is offset from the initial data base address in the column direction.

[0059] According to the embodiments of this disclosure, since the initial data is interleaved by reading and writing the initial data in the external memory, when the initial data is written sequentially to the external memory, it is necessary to determine the storage address of the initial sub-data based on the count value of the first row counter, the count value of the first column counter, the first unit offset, and the second unit offset, and to use address control to achieve random reading.

[0060] During operation S320, the initial sub-data is written to the target internal memory based on the storage address of the initial sub-data.

[0061] According to embodiments of this disclosure, based on the storage address of the initial sub-data, the initial sub-data to be processed is determined, the initial sub-data to be processed in the external memory is read out and sequentially written into the target internal memory, thus completing the interleaving of the initial data.

[0062] In operation S330, update the count values ​​of the first row counter and the first column counter.

[0063] According to embodiments of this disclosure, the address of the initial sub-data to be processed in the initial data is determined by continuously updating the count values ​​of the first row counter and the first column counter.

[0064] According to embodiments of this disclosure, when interleaving initial data through read and write operations in external memory, if the initial data is written to external memory sequentially, then the initial data must be read from external memory randomly. First, the storage address of the first initial sub-data is determined based on the current count values ​​of the first row counter and the first column counter. Then, the storage address of the second initial sub-data to be processed is determined by the change in the count values ​​of the first row counter and the first column counter.

[0065] According to embodiments of this disclosure, the storage address of the initial sub-data to be processed is determined by using the continuously updated count values ​​of the first row counter and the first column counter based on the first unit offset and the second unit offset. The initial data is randomly read through address control, thereby achieving the interleaving of the initial data.

[0066] Figure 4 A flowchart illustrating the determination of the initial sub-data storage address according to an embodiment of the present disclosure is shown schematically.

[0067] like Figure 4 As shown, the method includes operations S410 to S430.

[0068] In operation S410, the row address offset is determined based on the first unit offset and the count value of the first row counter.

[0069] According to embodiments of this disclosure, the row address offset is the product of a first unit offset and the count value of a first row counter, used to characterize the address offset of the initial sub-data to be processed in the row direction.

[0070] For example, if the first unit offset is 8192 and the first row counter count is 1, then the row address offset is 1 * 8192 = 8192.

[0071] In operation S420, the column address offset is determined based on the second unit offset and the count value of the first column counter.

[0072] According to embodiments of this disclosure, the column address offset is the product of a second unit offset and the count value of a first column counter, used to characterize the address offset of the initial sub-data to be processed in the column direction.

[0073] For example, if the second unit offset is 32 and the second row counter count is 3, then the column address offset is 3*32=96.

[0074] In operation S430, the storage address of the initial sub-data is determined based on the initial storage address of the initial data, the row address offset of the initial sub-data, and the column address offset of the initial sub-data.

[0075] According to embodiments of this disclosure, the storage address of the initial sub-data is the sum of the initial storage address of the initial data, the row address offset, and the column address offset, which is used to characterize the actual storage address of the initial sub-data.

[0076] For example, if the initial storage address of the initial data is 0, the row address offset is 8192, and the column address offset is 96, then the storage address of the initial sub-data is 0 + 8192 + 96 = 8288.

[0077] According to embodiments of this disclosure, the actual storage address of the initial sub-data is determined by calculating the row address offset and column address offset, and the interleaving of the initial data is achieved through address control.

[0078] According to embodiments of this disclosure, updating the count values ​​of the first row counter and the first column counter includes: updating the count value of the first row counter based on a first preset step size; and updating the count value of the first column counter based on a second preset step size when it is determined that the count value of the first row counter is equal to a preset interleaving depth.

[0079] According to an embodiment of this disclosure, the first preset step size is a preset step size value for the first row counter to increment automatically.

[0080] According to an embodiment of this disclosure, after an initial sub-data is completely written into the target internal memory, the first row counter is incremented based on a first preset step size.

[0081] For example, the first preset step size is 1, the count value of the first row counter is 1, and after an initial sub-data is completely written into the target internal memory, the count value of the first row counter is incremented by 1, at which point the count value of the first row counter is 2.

[0082] According to an embodiment of this disclosure, the second preset step size is a preset step size value for the first column counter to increment automatically.

[0083] According to an embodiment of this disclosure, when the count value of the first row counter is equal to the preset interleaving depth, it indicates that a column of initial sub-data has been completely written into the target internal memory. At this time, it is necessary to determine the next column of multiple initial sub-data to be processed, and perform an auto-increment operation on the first column counter based on the second preset step size.

[0084] For example, if the second preset step size is 1, the count value of the first column counter is 1. When the count value of the first row counter is equal to the preset interleaving depth, the count value of the first column counter increments by 1, and the count value of the first column counter is 2.

[0085] According to embodiments of this disclosure, by updating the count values ​​of the first row counter and the first column counter based on certain conditions and a preset step size, the storage address of the initial sub-data can be accurately determined.

[0086] According to embodiments of this disclosure, when it is determined that the count value of the first row counter is equal to a preset interleaving depth, the count value of the first row counter is reset to an initial value; when it is determined that the count value of the first column counter is equal to a pre-designed value, the count value of the first column counter is reset to an initial value, wherein the pre-designed value is related to the data read / write performance parameters of the external memory and the first data bit width of the external memory.

[0087] According to an embodiment of this disclosure, when the count value of the first row counter is equal to the preset interleaving depth, it indicates that a column of initial sub-data has been completely written into the internal memory. At this time, it is necessary to determine the first initial sub-data to be processed among the multiple initial sub-data to be processed in the next column. Therefore, it is necessary to reset the count value of the first row counter to the initial value and determine the storage address of the first initial sub-data to be processed among the multiple initial sub-data to be processed in the next column.

[0088] According to an embodiment of this disclosure, the pre-designed value is obtained by performing a division operation between the data read / write performance parameters of the external memory and the first data bit width of the external memory.

[0089] According to the embodiments of this disclosure, when the count value of the first column counter is equal to the pre-designed value, it indicates that the first initial data has been completely written into the internal memory. At this time, the second initial data needs to be processed to reset the count value of the first column counter to the initial value, and the initial storage address of the second initial data can be determined.

[0090] According to embodiments of this disclosure, the first row counter and the first column counter are reset, and the initial data stored in the external memory is continuously written to the internal memory through address control, thereby improving data processing efficiency.

[0091] Figure 5 A flowchart illustrating the writing of initial sub-data into a target internal memory according to an embodiment of the present disclosure is shown.

[0092] like Figure 5 As shown, the method includes operations S510 to S530.

[0093] When operating the S510, the initial sub-data is divided into multiple data blocks based on the data read / write performance parameters of the external memory.

[0094] According to embodiments of this disclosure, a data block is data processed by an external memory in a single read or write operation.

[0095] For example, if the initial sub-data size is 512 bits and the external memory processes 128 bits of data in one read or write operation, then each initial sub-data is divided into 4 data blocks.

[0096] In operation S520, based on the storage address of the initial sub-data, the storage addresses of multiple data blocks are determined respectively.

[0097] According to the embodiments of this disclosure, since the initial sub-data is a segment of data with consecutive storage addresses and the storage addresses of multiple data blocks are adjacent, the storage addresses of multiple data blocks can be determined based on the storage location of the initial sub-data.

[0098] During operation of S530, multiple data blocks are sequentially written to the target internal memory based on their respective storage addresses.

[0099] According to embodiments of this disclosure, data blocks are read from external memory and sequentially written into target internal memory based on the storage address of the data blocks.

[0100] According to embodiments of this disclosure, by sequentially reading multiple data blocks within the initial sub-data, the reading speed of the initial data is improved, and the speed of interleaving the initial data is further improved.

[0101] According to embodiments of this disclosure, determining a first unit offset and a second unit offset related to the external memory based on a preset interleaving depth, data read / write performance parameters of the external memory, and a first data bit width of the external memory includes: determining a first unit offset based on the amount of initial data, the preset interleaving depth, and the first data bit width of the external memory; and determining a second unit offset based on the data read / write performance parameters of the external memory and the first data bit width of the external memory.

[0102] According to embodiments of this disclosure, the initial data stored in the external memory can be considered as a first matrix, the number of rows in the first matrix being equal to a preset interleaving depth. Dividing the initial data volume by the preset interleaving depth yields the data volume that each row of the matrix can hold. Dividing the data volume that each row of the matrix can hold by the first data bit width of the external memory yields a first unit offset. Multiplying the data volume processed in one read or write operation of the external memory by the number of sequential reads yields the continuously read data volume. Dividing the continuously read data volume by the first bit width of the external memory yields a second unit offset.

[0103] According to embodiments of this disclosure, the initial data is divided into units by determining a first unit offset and a second unit offset, which facilitates the interleaving of the initial data.

[0104] According to embodiments of this disclosure, taking DDR3 with a data width of 16 bits and a data processing volume of 128 bits per read or write operation as external memory, the initial data size is 1 Gbit, and the preset interleaving depth is 8192 as an example, but not limited to this, the storage structure of the initial data in the external memory can refer to Figure 6 .

[0105] Figure 6 A schematic diagram illustrating the storage structure of initial data in an external memory according to an embodiment of the present disclosure is shown.

[0106] like Figure 6 As shown, the first matrix has 8192 rows, which is equal to the preset interleaving depth. Therefore, the amount of data that each row can hold is 1 Gbit ÷ 8192 = 2. 17 Since the first bit width of external memory is 16 bits, meaning each address in external memory stores 16 bits of data, the size of each first unit of data is 16 bits, and the number of columns in the first matrix is ​​2. 17 bit ÷ 16bit = 8192, meaning that each row of the first matrix can hold 8192 units of data.

[0107] According to embodiments of this disclosure, since the amount of data read or written by the external memory at one time is 128 bits, and when writing initial data to the target internal memory, the initial data is read out randomly as initial sub-data, and the initial sub-data is read out sequentially as data blocks. The structure for reading initial data from the external memory can be referred to... Figure 7 The structure shown.

[0108] Figure 7 A schematic diagram illustrating the structure for reading initial data from an external memory according to an embodiment of the present disclosure is shown.

[0109] like Figure 7 As shown, when reading the initial data stored in the external memory, the size of the data read continuously is 512 bits, that is, the size of the initial sub-data is 512 bits. Each row of the first matrix contains 256 initial sub-data, the size of the data block is 128 bits, and each initial sub-data contains 4 data blocks.

[0110] According to embodiments of this disclosure, reading the initial data from the external memory does not change the storage method of the initial data in the external memory; the size of each first unit of data remains 16 bits. The number of first units of data contained in each row of the initial data is the first unit offset, and the number of first units of data contained in each initial sub-data is the second unit offset. Therefore, the storage address of the initial sub-data to be processed can be determined by the first unit offset and the second unit offset.

[0111] According to an embodiment of this disclosure, the first unit offset is 8192, and the second unit offset is 512bit ÷ 16bit = 32. The first preset step size and the second preset step size are both 1, the initial address of the initial data is 0, and the initial values ​​of the first row counter and the first column counter are both 0.

[0112] According to an embodiment of this disclosure, the row address offset is 0 and the column address offset is 0. The initial sub-data of the first row and first column is read. After reading, the count value of the first row counter is incremented by 1. The initial sub-data to be processed, stored at address 1×8192+0=8192, is then read, which is the initial sub-data of the second row and first column. After all the initial sub-data of the first column has been read using this method, the count value of the first column counter is incremented by 1, and the count value of the first row counter is reset to its initial value of 0. The storage address of the initial sub-data to be processed is determined to be 0+1×32=32, which is the initial sub-data of the first row and second column. After all 256 columns of initial sub-data have been read using this method, both the first row counter and the first column counter are reset to their initial values ​​of 0.

[0113] Figure 8 A flowchart illustrating the reading of target data according to an embodiment of the present disclosure is shown schematically.

[0114] like Figure 8 As shown, the method includes operations S810 to S820.

[0115] In operation S810, the number of rows and columns associated with the internal memory are determined based on the second bit width of the internal memory.

[0116] According to embodiments of this disclosure, the second bit width of the internal memory is the number of data bits stored at each memory address in the internal memory, and is related to the storage performance of the internal memory. The second bit width characterizes the data size of each second unit of data in the target data.

[0117] According to embodiments of this disclosure, the storage structure of the target data in the internal memory can be regarded as a second matrix. The number of rows in the second matrix is ​​equal to the preset interleaving depth, and the data size of each row of the second matrix is ​​equal to the data size of an initial sub-data. The number of columns in the second matrix is ​​obtained by dividing the data size of each row of the second matrix by the second bit width.

[0118] For example, if the second bit width of the internal memory is 8 bits, and the amount of data stored at each memory address in the internal memory is 8 bits, then the amount of data in each second unit of data in the internal memory is 8 bits. If the initial sub-data size is 512 bits, then the number of columns in the second matrix is ​​512 bits ÷ 8 bits = 64.

[0119] During operation of S820, based on the row number value and column number value, the second row counter and the second column counter are used to read the interleaved target data from the internal memory.

[0120] According to embodiments of this disclosure, a second row counter is used to characterize the number of times the storage address of the second unit of data to be read is offset in the row direction relative to the base address of the target data. A second column counter is used to characterize the number of times the storage address of the second unit of data to be read is offset in the column direction relative to the base address of the target data. The row address of the second unit of data is obtained by multiplying the count value of the second row counter by the number of rows, and the column address of the second unit of data is obtained by multiplying the count value of the second column counter by the number of rows. The storage address of the second unit of data to be read is obtained by adding the base address of the target data, the row address of the second unit of data, and the column address of the second unit of data.

[0121] For example, the second matrix has 8192 rows and 64 columns. The base address of the target data is 0, the count value of the second row counter is 2, and the count value of the second column counter is 1. At this time, the storage address of the second unit of data to be read is 0 + 2 × 64 + 1 × 8192 = 8320.

[0122] According to embodiments of this disclosure, the amount of data processed by the internal memory in a single read operation can be set to be equal to the second bit width, so that the internal memory processes only one piece of data in a single read operation.

[0123] According to embodiments of this disclosure, the count value of the second row counter increments by 1 each time a second unit of data is read. When the count value of the second row counter equals the number of rows, the count value of the second row counter is reset to 0, and the count value of the second column counter increments by 1. When the count value of the second column counter equals the number of columns, the count value of the second column counter is reset to 0.

[0124] According to embodiments of this disclosure, since the target data is written to the internal memory sequentially, random reads are required to achieve interleaving of the target data in the internal memory. The location of the second data to be read is determined by a second row counter, a second column counter, a row number value, and a column number value, and random reads are achieved through address control.

[0125] According to embodiments of this disclosure, by randomly reading the target data stored in the internal memory and interleaving it again, the interleaving of the data is made more thorough, thereby improving the error correction performance.

[0126] According to embodiments of this disclosure, an 8-bit RAM with a single read operation processing 8 bits of data is used as the internal memory. The size of the target data is equal to the size of a column of initial sub-data in the initial data, but is not limited thereto. The storage structure of the target data in the internal memory can be referenced. Figure 9 .

[0127] Figure 9 A schematic diagram illustrating the storage structure of target data in the internal memory according to an embodiment of the present disclosure is shown.

[0128] like Figure 9 As shown, the second matrix has 8192 rows, which is equal to the preset interleaving depth. Each row holds 512 bits of data, the size of one initial sub-data unit. Since the second bit width of the internal memory is 8 bits, meaning that each address in the internal memory stores 8 bits of data, the size of each second unit data is 8 bits. Therefore, the number of columns in the second matrix is ​​512 bits ÷ 8 bits = 64, meaning that each row of the second matrix holds 64 second unit data units.

[0129] According to an embodiment of this disclosure, the amount of data processed in a single read operation of the internal memory is set to be equal to the second bit width, and the amount of data processed in a single read operation of the internal memory is 8 bits.

[0130] According to an embodiment of this disclosure, the initial values ​​of the second row counter and the second column counter are both 0, and the base address of the target data in the internal memory is 0. At this time, the second unit data at storage address 0 is read out, which is the second unit data in the first row and first column of the second matrix. After reading out, the count value of the second row counter increments by 1, determining the storage address of the second unit data to be read as 0 + 1 × 64 + 0 = 64. After completely reading out one column of the second unit data from the target data using this method, the second column counter increments by 1, and the second row counter is reset to 0, determining the storage address of the second unit data to be processed as 0 + 0 + 1 × 8192 = 8192, which is the second unit data in the first row and second column. After reading out all 64 columns of the second unit data using this method, the count values ​​of both the second row counter and the second column counter are reset to 0.

[0131] Based on the above-described fast block interleaving or deinterleaving method implemented using a single-chip memory, this disclosure also provides a fast block interleaving or deinterleaving apparatus implemented using a single-chip memory. The following will be combined with... Figure 10 The device is described in detail.

[0132] Figure 10 The diagram illustrates a structural block diagram of a fast block interleaving or deinterleaving apparatus implemented using a single-chip memory according to an embodiment of the present disclosure.

[0133] like Figure 10 As shown, the fast block interleaving or deinterleaving device 1000 implemented using a single-chip memory in this embodiment includes an external memory writing module 1010, an offset determination module 1020, and a memory writing module 1030.

[0134] The external memory write module 1010 is used to write initial data stored in the buffer to external memory in response to multiple internal memories being in a data read state. In one embodiment, the external memory write module 1010 can be used to perform the operation S210 described above, which will not be repeated here.

[0135] The offset determination module 1020, upon receiving a data read request from a target internal memory among the plurality of internal memories, determines a first unit offset and a second unit offset related to the external memory based on a preset interleaving depth, the data read / write performance parameters of the external memory, and the first data bit width of the external memory. In one embodiment, the offset determination module 1020 may be used to perform the operation S220 described above, which will not be repeated here.

[0136] The memory write module 1030 is used to interleave the initial data into the target internal memory based on the first unit offset and the second unit offset, using a first row counter and a first column counter associated with the initial data. In one embodiment, the memory write module 1030 can be used to perform the operation S230 described above, which will not be repeated here.

[0137] According to embodiments of this disclosure, the memory writing module further includes an address determination submodule, a data writing submodule, and a count value update submodule.

[0138] The address determination submodule is used to determine the storage address of the initial sub-data to be processed in the initial data based on the count value of the first row counter, the count value of the first column counter, the first unit offset, and the second unit offset.

[0139] The data writing submodule is used to write the initial subdata into the target internal memory based on the storage address of the initial subdata.

[0140] The count value update submodule is used to update the count values ​​of the first row counter and the first column counter.

[0141] According to embodiments of this disclosure, the address determination submodule further includes a first determination unit, a second determination unit, and an address determination unit.

[0142] The first determining unit is used to determine the row address offset based on the first unit offset and the count value of the first row counter.

[0143] The second determining unit is used to determine the column address offset based on the second unit offset and the count value of the first column counter.

[0144] The address determination unit is used to determine the storage address of the initial sub-data based on the initial storage address of the initial data, the row address offset of the initial sub-data, and the column address offset of the initial sub-data.

[0145] According to embodiments of this disclosure, the count update submodule further includes a row update unit and a column update unit.

[0146] The row update unit is used to update the count value of the first row counter based on a first preset step size.

[0147] The column update unit is used to update the count value of the first column counter based on a second preset step size when it is determined that the count value of the first row counter is equal to the preset interleaving depth.

[0148] According to embodiments of this disclosure, the count update submodule further includes a row reset unit and a column reset unit.

[0149] The row reset unit is used to reset the count value of the first row counter to the initial value when it is determined that the count value of the first row counter is equal to the preset interleaving depth.

[0150] The column reset unit is used to reset the count value of the first column counter to an initial value when it is determined that the count value of the first column counter is equal to a pre-designed value, wherein the pre-designed value is related to the data read / write performance parameters of the external memory and the first data bit width of the external memory.

[0151] According to embodiments of this disclosure, the data writing submodule further includes a data block segmentation unit, a data block determination unit, and a data block writing unit.

[0152] The data block segmentation unit is used to segment the initial sub-data into multiple data blocks based on the data read / write performance parameters of the external memory.

[0153] The data block determination unit is used to determine the storage address of each of the plurality of data blocks based on the storage address of the initial sub-data.

[0154] The data block writing unit is used to write the multiple data blocks sequentially into the target internal memory based on their respective storage addresses.

[0155] According to embodiments of this disclosure, the offset determination module 1020 further includes a first determination submodule and a second determination submodule.

[0156] The first determining submodule is used to determine the first unit offset based on the data volume of the initial data, the preset interleaving depth, and the first data bit width of the external memory.

[0157] The second determining submodule is used to determine the second unit offset based on the data read / write performance parameters of the external memory and the first data bit width of the external memory.

[0158] According to embodiments of this disclosure, the fast block interleaving or deinterleaving device 1000 implemented using a single-chip memory further includes a row and column number determination module and a memory readout module.

[0159] The row and column number determination module is used to determine the number of rows and columns associated with the internal memory based on the second bit width of the internal memory.

[0160] The memory read module is used to read the interleaved target data in the internal memory based on the number of rows and the number of columns, using a second row counter and a second column counter.

[0161] According to embodiments of this disclosure, any plurality of modules among the external storage write module 1010, offset determination module 1020, and memory write module 1030 can be combined into one module, or any one of these modules can be split into multiple modules. Alternatively, at least part of the functionality of one or more of these modules can be combined with at least part of the functionality of other modules and implemented in one module. According to embodiments of this disclosure, at least one of the external storage write module 1010, offset determination module 1020, and memory write module 1030 can be at least partially implemented as hardware circuitry, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or implemented in hardware or firmware by any other reasonable means of integrating or packaging the circuitry, or implemented in any one of software, hardware, and firmware methods, or in a suitable combination of any of these methods. Alternatively, at least one of the external storage write module 1010, the offset determination module 1020, and the memory write module 1030 may be implemented at least partially as a computer program module, which can perform corresponding functions when the computer program module is run.

[0162] Figure 11 A block diagram schematically illustrates an electronic device suitable for implementing a fast block interleaving or deinterleaving method using a single-chip memory, according to embodiments of the present disclosure.

[0163] like Figure 11As shown, an electronic device 1100 according to an embodiment of the present disclosure includes a processor 1101, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1102 or a program loaded from a storage portion 1108 into a random access memory (RAM) 1103. The processor 1101 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 1101 may also include onboard memory for caching purposes. The processor 1101 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present disclosure.

[0164] RAM 1103 stores various programs and data required for the operation of electronic device 1100. Processor 1101, ROM 1102, and RAM 1103 are interconnected via bus 1104. Processor 1101 performs various operations of the method flow according to embodiments of the present disclosure by executing programs in ROM 1102 and / or RAM 1103. It should be noted that the programs may also be stored in one or more memories other than ROM 1102 and RAM 1103. Processor 1101 may also perform various operations of the method flow according to embodiments of the present disclosure by executing programs stored in said one or more memories.

[0165] According to embodiments of this disclosure, the electronic device 1100 may further include an input / output (I / O) interface 1105, which is also connected to a bus 1104. The electronic device 1100 may also include one or more of the following components connected to the I / O interface 1105: an input section 1106 including a keyboard, mouse, etc.; an output section 1107 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1108 including a hard disk, etc.; and a communication section 1109 including a network interface card such as a LAN card, modem, etc. The communication section 1109 performs communication processing via a network such as the Internet. A drive 1110 is also connected to the I / O interface 1105 as needed. A removable medium 1111, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 1110 as needed so that computer programs read from it can be installed into the storage section 1108 as needed.

[0166] This disclosure also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs that, when executed, implement the method according to the embodiments of this disclosure.

[0167] According to embodiments of this disclosure, the computer-readable storage medium may be a non-volatile computer-readable storage medium, such as including, but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this disclosure, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of this disclosure, the computer-readable storage medium may include ROM 1102 and / or RAM 1103 and / or one or more memories other than ROM 1102 and RAM 1103 described above.

[0168] Embodiments of this disclosure also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code is used to cause the computer system to implement the item recommendation method provided in the embodiments of this disclosure.

[0169] When the computer program is executed by the processor 1101, it performs the functions defined in the system / apparatus of this disclosure embodiments. According to embodiments of this disclosure, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0170] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and may be downloaded and installed via the communication section 1109, and / or installed from the removable medium 1111. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0171] In such an embodiment, the computer program can be downloaded and installed from a network via communication section 1109, and / or installed from removable medium 1111. When the computer program is executed by processor 1101, it performs the functions defined in the system of this disclosure embodiment. According to embodiments of this disclosure, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0172] According to embodiments of this disclosure, program code for executing the computer programs provided in embodiments of this disclosure can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can execute entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0173] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0174] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0175] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A fast block interleaving or deinterleaving method implemented using a single-chip memory, comprising: In response to multiple internal memories being in a data read state, the initial data stored in the buffer is written to the external memory; Upon receiving a data read request returned by a target internal memory among the plurality of internal memories, a first unit offset and a second unit offset related to the external memory are determined based on a preset interleaving depth, the data read / write performance parameters of the external memory, and the first data bit width of the external memory. as well as Based on the first unit offset and the second unit offset, the initial data is interleaved and written into the target internal memory using the first row counter and the first column counter associated with the initial data; The step of interleaving the initial data into the target internal memory based on the first unit offset and the second unit offset, using a first row counter and a first column counter associated with the initial data, includes: Based on the count value of the first row counter, the count value of the first column counter, the first unit offset, and the second unit offset, the storage address of the initial sub-data to be processed in the initial data is determined; Based on the storage address of the initial sub-data, the initial sub-data is written into the target internal memory; and Update the count values ​​of the first row counter and the first column counter; The step of determining the storage address of the initial sub-data based on the count value of the first row counter, the count value of the first column counter, the first unit offset, and the second unit offset includes: The row address offset is determined based on the first unit offset and the count value of the first row counter; Based on the second unit offset and the count value of the first column counter, the column address offset is determined; and The storage address of the initial sub-data is determined based on the initial storage address of the initial data, the row address offset of the initial sub-data, and the column address offset of the initial sub-data. The step of determining the first unit offset and the second unit offset related to the external memory based on the preset interleaving depth, the data read / write performance parameters of the external memory, and the first data bit width of the external memory includes: Based on the amount of initial data, the preset interleaving depth, and the first data bit width of the external memory, the first unit offset is determined; and The second unit offset is determined based on the data read / write performance parameters of the external memory and the first data bit width of the external memory.

2. The method according to claim 1, wherein, Updating the count values ​​of the first row counter and the first column counter includes: Based on the first preset step size, update the count value of the first row counter; and If the count value of the first row counter is determined to be equal to the preset interleaving depth, the count value of the first column counter is updated based on the second preset step size.

3. The method according to claim 2, further comprising: If it is determined that the count value of the first row counter is equal to the preset interleaving depth, the count value of the first row counter is reset to the initial value; as well as If the count value of the first column counter is determined to be equal to the pre-designed value, the count value of the first column counter is reset to the initial value, wherein the pre-designed value is related to the data read / write performance parameters of the external memory and the first data bit width of the external memory.

4. The method according to claim 1, wherein, The step of writing the initial sub-data into the target internal memory based on the storage address of the initial sub-data includes: Based on the data read / write performance parameters of the external memory, the initial sub-data is divided into multiple data blocks; Based on the storage address of the initial sub-data, the storage address of each of the plurality of data blocks is determined; and Based on the respective storage addresses of the multiple data blocks, the multiple data blocks are sequentially written into the target internal memory.

5. The method according to claim 1, further comprising: Based on the second bit width of the internal memory, determine the number of rows and columns associated with the internal memory; as well as Based on the number of rows and the number of columns, the interleaved target data in the internal memory is read out using the second row counter and the second column counter.

6. A fast block interleaving or deinterleaving device implemented using a single-chip memory, comprising: The external memory write module is used to write the initial data stored in the buffer to the external memory in response to multiple internal memory devices being in the data read state. The offset determination module is used to determine, upon receiving a data read request returned by a target internal memory among the plurality of internal memories, a first unit offset and a second unit offset related to the external memory based on a preset interleaving depth, the data read / write performance parameters of the external memory, and the first data bit width of the external memory. as well as A memory writing module is used to interleave the initial data into the target internal memory based on the first unit offset and the second unit offset, using a first row counter and a first column counter associated with the initial data. The memory writing module includes: an address determination submodule, used to determine the storage address of the initial sub-data to be processed in the initial data based on the count value of the first row counter, the count value of the first column counter, the first unit offset, and the second unit offset; a data writing submodule, used to write the initial sub-data into the target internal memory based on the storage address of the initial sub-data; and a count value update submodule, used to update the count values ​​of the first row counter and the first column counter respectively. The address determination submodule includes: a first determination unit, configured to determine a row address offset based on the first unit offset and the count value of the first row counter; a second determination unit, configured to determine a column address offset based on the second unit offset and the count value of the first column counter; and an address determination unit, configured to determine the storage address of the initial sub-data based on the initial storage address of the initial data, the row address offset of the initial sub-data, and the column address offset. The offset determination module includes: a first determination submodule, used to determine the first unit offset based on the data volume of the initial data, the preset interleaving depth and the first data bit width of the external memory; and a second determination submodule, used to determine the second unit offset based on the data read / write performance parameters of the external memory and the first data bit width of the external memory.

7. An electronic device, comprising: One or more processors; Storage device for storing one or more programs. Wherein, when the one or more programs are executed by the one or more processors, the one or more processors perform the method according to any one of claims 1 to 5.

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