Semiconductor structure and method of forming the same

Abstract

The present disclosure provides a semiconductor structure and a forming method thereof, and relates to the technical field of semiconductor. The forming method of the semiconductor structure comprises the following steps: providing a substrate; forming a plurality of multilayer stacked distributed capacitor structures on the surface of the substrate, each of the capacitor structures comprises a plurality of spaced distributed sub-capacitors, and the sub-capacitors in two adjacent capacitor structures correspond to each other one by one in a direction perpendicular to the substrate. Through the method, the capacitance storage capacity of the semiconductor structure can be improved, and the yield of the product can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for forming the same. Background Technology

[0002] Memory, due to its small size, high integration, and high transmission speed, has been widely used in smart devices such as mobile phones and tablets. Capacitors, as storage units in memory, are used to store electrical charge. Capacitors are one of the core structures of memory, and their size affects the memory's data storage capacity.

[0003] Currently, due to limitations in manufacturing processes, existing memory chips have relatively small capacitance, which in turn affects the functionality of semiconductor devices and results in low device yield.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a semiconductor structure and a method for forming the same, which can improve the storage capacity of capacitors in semiconductor devices, thereby improving the function of the devices and increasing the yield of products.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0007] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided, the method comprising:

[0008] Provide substrate;

[0009] A multilayer stacked capacitor structure is formed on the surface of the substrate. Each capacitor structure includes multiple spaced sub-capacitors. The sub-capacitors in two adjacent capacitor structures are connected to each other in a direction perpendicular to the substrate.

[0010] Within two adjacent capacitor structures, the orthographic projection of the lower electrode layer of the sub-capacitor located in the upper layer onto the substrate lies within the orthographic projection of the lower electrode layer of the sub-capacitor located in the lower layer onto the substrate.

[0011] Alternatively, within two adjacent capacitor structures, the orthographic projection of the upper electrode layer of the sub-capacitor located in the upper layer onto the substrate lies within the orthographic projection of the upper electrode layer of the sub-capacitor located in the lower layer onto the substrate.

[0012] In some embodiments of this disclosure, based on the foregoing scheme, within two adjacent capacitor structures, the thickness of the lower electrode layer of the sub-capacitor located in the upper layer is greater than or equal to one-third of the thickness of the lower electrode layer of the sub-capacitor located in the lower layer, and the thickness of the lower electrode layer of the sub-capacitor located in the upper layer is less than the thickness of the lower electrode layer of the sub-capacitor located in the lower layer.

[0013] In some embodiments of this disclosure, based on the foregoing scheme, within two adjacent capacitor structures, the thickness of the upper electrode layer of the sub-capacitor located in the upper layer is greater than or equal to one-third of the thickness of the upper electrode layer of the sub-capacitor located in the lower layer, and the thickness of the upper electrode layer of the sub-capacitor located in the upper layer is less than the thickness of the upper electrode layer of the sub-capacitor located in the lower layer.

[0014] In some embodiments of this disclosure, based on the foregoing scheme, a multilayer stacked capacitor structure is formed on the surface of the substrate, including:

[0015] The height of the multilayer capacitor structure decreases sequentially in the direction away from the substrate.

[0016] In some embodiments of this disclosure, based on the foregoing scheme, the capacitor structure includes a first capacitor structure and a second capacitor structure, forming a multilayer stacked capacitor structure on the surface of the substrate. Each capacitor structure includes multiple spaced sub-capacitors, and the sub-capacitors in adjacent capacitor structures are connected to each other in a direction perpendicular to the substrate, including:

[0017] The first capacitor structure is formed on the surface of the substrate, and a plurality of first sub-capacitors are formed in the first capacitor structure at intervals. The first sub-capacitors include a first lower electrode layer, a first dielectric layer and a first upper electrode layer.

[0018] The second capacitor structure is formed on the first capacitor structure, and second sub-capacitors are formed in the second capacitor structure at intervals. The second sub-capacitors include a second lower electrode layer, a second dielectric layer and a second upper electrode layer.

[0019] The first lower electrode layer and the second lower electrode layer are connected to each other, and the first upper electrode layer and the second upper electrode layer are connected to each other.

[0020] In some embodiments of this disclosure, based on the foregoing scheme, the method further includes:

[0021] A first semiconductor layer is formed to cover the first sub-capacitor structure, and the first semiconductor layer fills the gaps in the first sub-capacitor and the gaps between the plurality of first sub-capacitors.

[0022] Remove a portion of the first semiconductor layer to expose the ends of the first lower electrode layer, the first dielectric layer, and the first upper electrode layer;

[0023] A cutoff layer is formed on the surface where the ends of the first lower electrode layer, the first upper electrode layer and the first dielectric layer are located, and a second stacked layer is formed on the cutoff layer;

[0024] A plurality of spaced second capacitor holes are formed in the second stacked layer, and the orthographic projection of the second capacitor holes on the substrate overlaps with the orthographic projection of the first capacitor holes on the substrate.

[0025] Remove the cut-off layer located at the bottom of the second capacitor hole;

[0026] A second sub-capacitor is formed within the second capacitor hole.

[0027] According to another aspect of this disclosure, a semiconductor structure is provided, the semiconductor structure comprising:

[0028] Substrate;

[0029] A capacitor structure, wherein multiple layers of the capacitor structure are stacked on the surface of the substrate, each capacitor structure includes multiple spaced sub-capacitors, and the sub-capacitors in two adjacent capacitor structures are connected to each other in a direction perpendicular to the substrate.

[0030] Within two adjacent capacitor structures, the orthographic projection of the lower electrode layer of the sub-capacitor located in the upper layer onto the substrate lies within the orthographic projection of the lower electrode layer of the sub-capacitor located in the lower layer onto the substrate.

[0031] Alternatively, within two adjacent capacitor structures, the orthographic projection of the upper electrode layer of the sub-capacitor located in the upper layer onto the substrate lies within the orthographic projection of the upper electrode layer of the sub-capacitor located in the lower layer onto the substrate.

[0032] In some embodiments of this disclosure, based on the foregoing scheme, within two adjacent capacitor structures, the thickness of the lower electrode layer of the sub-capacitor located in the upper layer is greater than or equal to one-third of the thickness of the lower electrode layer of the sub-capacitor located in the lower layer, and the thickness of the lower electrode layer of the sub-capacitor located in the upper layer is less than the thickness of the lower electrode layer of the sub-capacitor located in the lower layer.

[0033] In some embodiments of this disclosure, based on the foregoing scheme, within two adjacent capacitor structures, the thickness of the upper electrode layer of the sub-capacitor located in the upper layer is greater than or equal to one-third of the thickness of the upper electrode layer of the sub-capacitor located in the lower layer, and the thickness of the upper electrode layer of the sub-capacitor located in the upper layer is less than the thickness of the upper electrode layer of the sub-capacitor located in the lower layer.

[0034] In some embodiments of this disclosure, based on the foregoing scheme, the height of the multilayer capacitor structure decreases sequentially along the direction away from the substrate.

[0035] The semiconductor structure formation method disclosed herein forms multiple sub-capacitors within a multilayer capacitor structure, with the sub-capacitors in adjacent capacitor structures connected one-to-one. During the fabrication process, while increasing the aspect ratio of the capacitor structure, it avoids the problem of the capacitor structure collapsing or failing due to being suspended because of the aspect ratio, reduces the fabrication difficulty of capacitors with large aspect ratios, further improves the yield of semiconductor devices, and increases the storage capacity of capacitors in semiconductor devices, thereby improving the functionality of the devices.

[0036] Another aspect of this disclosure provides a semiconductor structure having a multilayer stacked capacitor structure, wherein sub-capacitors in adjacent capacitor structures are connected to each other in a direction perpendicular to the substrate, and the semiconductor structure has a large storage capacity capacitor structure. The semiconductor structure has good performance and a stable capacitor storage structure.

[0037] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0038] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0039] Figure 1 This is a flowchart of a method for forming a semiconductor structure according to an exemplary embodiment of the present disclosure.

[0040] Figure 2 This is a schematic diagram of the structure of a substrate according to an exemplary embodiment of the present disclosure.

[0041] Figure 3 This is a flowchart illustrating a method for connecting a first capacitor structure and a second capacitor structure in an exemplary embodiment of this disclosure.

[0042] Figure 4 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment of the present disclosure.

[0043] Figure 5 This is a flowchart of a method for forming a first capacitor structure according to an exemplary embodiment of the present disclosure.

[0044] Figure 6This is a schematic diagram of the semiconductor structure corresponding to step S211 in an exemplary embodiment of this disclosure.

[0045] Figure 7 This is a schematic diagram of the semiconductor structure corresponding to step S212 in an exemplary embodiment of this disclosure.

[0046] Figure 8 This is a flowchart of a method for forming a first sub-capacitor in an exemplary embodiment of the present disclosure.

[0047] Figure 9 This is a schematic diagram of the semiconductor structure corresponding to step S2121 in an exemplary embodiment of this disclosure.

[0048] Figure 10 This is a schematic diagram of a first capacitor structure in an exemplary embodiment of the present disclosure.

[0049] Figure 11 This is a schematic diagram of another first capacitor structure in an exemplary embodiment of the present disclosure.

[0050] Figure 12 This is a flowchart of a method for forming a second capacitor structure according to an exemplary embodiment of the present disclosure.

[0051] Figure 13 This is a schematic diagram of the semiconductor structure corresponding to step S221 in an exemplary embodiment of this disclosure.

[0052] Figure 14 This is a schematic diagram of the semiconductor structure corresponding to step S222 in an exemplary embodiment of this disclosure.

[0053] Figure 15 This is a flowchart illustrating a method for forming a second sub-capacitor according to an exemplary embodiment of the present disclosure.

[0054] Figure 16 This is a schematic diagram of a second capacitor structure in an exemplary embodiment of the present disclosure.

[0055] Figures 17-20 In exemplary embodiments of this disclosure Figure 4 A magnified view of a portion of point A in the middle.

[0056] Figure 21 In exemplary embodiments of this disclosure Figure 4 A cross-sectional view of BB.

[0057] The reference numerals in the attached figures are explained as follows:

[0058] 10. Substrate; 101. Conductive contact plug; 20. First capacitor structure; 200. First stacked layer; 211. First support layer; 212. Second support layer; 213. Third support layer; 221. First sacrificial layer; 222. Second sacrificial layer; 210. First capacitor aperture; 220. First sub-capacitor; 201. First lower electrode layer; 202. First dielectric layer; 203. First upper electrode layer; 230. First semiconductor layer; 240. Cut-off layer; 30. Second capacitor structure; 300. Second stacked layer; 321. Third sacrificial layer; 311. Fourth support layer; 310. Second capacitor aperture; 320. Second sub-capacitor; 301. Second lower electrode layer; 302. Second dielectric layer; 303. Second upper electrode layer; 330. Second semiconductor layer. Detailed Implementation

[0059] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0060] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0061] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0062] With the development of semiconductor technology, higher demands are being placed on the size of memory. Capacitors, as one of the core components of memory, are mainly used to store electrical charge. For increasingly miniaturized memory, achieving capacitors of the same or even larger capacity becomes extremely difficult.

[0063] According to the capacitance calculation formula C = εS / d, where S is the area of ​​the two opposing electrode plates, ε is the dielectric constant of the dielectric, and d is the distance between the two electrode plates, increasing capacitance is usually achieved through three methods: increasing the size of the capacitor structure, i.e., increasing the distance between the two electrode plates; using a dielectric material with a high dielectric constant; and increasing the aspect ratio of the capacitor structure, i.e., increasing the area of ​​the two opposing electrode plates. However, excessively large capacitor structures can lead to a decrease in the distance between different capacitor structures, causing short circuits. Due to material limitations, high dielectric constant dielectric materials are still under further investigation. Increasing the aspect ratio of the capacitor structure is also problematic because, due to limitations in the fabrication process, the etching depth of the film layer varies in different etching areas during the formation of capacitor holes, causing some capacitor structures to collapse due to suspension, and making it difficult to form some capacitors.

[0064] Therefore, this disclosure provides a semiconductor structure and a method for forming the same, which solves the problem that the capacitor structure is difficult to form due to limitations in the fabrication process when increasing the aspect ratio to increase the capacitance.

[0065] This disclosure provides a method for forming a semiconductor structure, such as... Figure 1 As shown, the method includes:

[0066] Step S100: Provide a substrate;

[0067] Step S200: A multilayer stacked capacitor structure is formed on the surface of the substrate. Each capacitor structure includes multiple spaced sub-capacitors. The sub-capacitors in two adjacent capacitor structures are connected to each other in a one-to-one manner along the direction perpendicular to the substrate.

[0068] In this method, within two adjacent capacitor structures, the orthographic projection of the lower electrode layer of the sub-capacitor in the upper layer onto the substrate falls within the orthographic projection of the lower electrode layer of the sub-capacitor in the lower layer onto the substrate; or, within two adjacent capacitor structures, the orthographic projection of the upper electrode layer of the sub-capacitor in the upper layer onto the substrate falls within the orthographic projection of the upper electrode layer of the sub-capacitor in the lower layer onto the substrate. The semiconductor structure formation method provided in this disclosure forms a multilayer capacitor structure on a substrate, with multiple spaced sub-capacitors formed within each capacitor. By connecting the sub-capacitors in adjacent capacitor structures one-to-one, a capacitor structure with multiple connected sub-capacitors is formed in a direction perpendicular to the substrate, increasing the aspect ratio of the capacitor structure and thus increasing its capacitance. Furthermore, this method solves the problem of inconsistent etching depth caused by the increased aspect ratio during capacitor structure formation, which leads to suspended capacitor structures, resulting in capacitor structure collapse or failure, thereby improving product yield.

[0069] The steps of the method for forming a semiconductor structure according to the present disclosure will be described in detail below with reference to the accompanying drawings:

[0070] In step S100, a substrate 10 is provided. Figure 2 As shown in the embodiments provided in this disclosure, the substrate 10 of the semiconductor structure can be a flat plate structure, and may further include multiple structures required for forming semiconductor devices. For example, conductive contact plugs 101 may be included within the substrate 10. The conductive contact plugs 101 can be used to connect the substrate 10 and the capacitor structure. The conductive contact plugs 101 can be formed by pre-defining a capacitor contact hole formation area on the substrate 10. The capacitor contact hole formation area can be used to form the conductive contact plugs 101. Bit line structures may also be included within the substrate 10. A bit line structure formation area is pre-defined on the substrate 10. The bit line structure formation area can be used to form the bit line structure. The specific formation methods and structures of the conductive contact plugs 101 and the bit line structures can be fabricated according to actual manufacturing needs. Here, no specific limitations are made on the specific formation methods and structures of the conductive contact plugs 101 and the bit line structures.

[0071] The substrate 10 may also include an insulating layer, in which multiple spaced-apart capacitor contact holes can be formed. Conductive contact plugs 101 are formed within the capacitor contact holes, and the insulating layer separates the multiple conductive contact plugs 101 to prevent coupling or short circuits between them. Of course, before forming the capacitor contact holes in the insulating layer, a bit line structure can be formed on the substrate 10. The fabrication process and flow here can be adapted to meet actual needs.

[0072] The conductive contact plugs 101 can be vertically arrayed along a direction perpendicular to the substrate 10. The direction perpendicular to the substrate 10 provided in this disclosure can be absolutely perpendicular or approximately perpendicular. Due to limitations in the manufacturing process, the vertical angle will not be strictly 90°, and there will be a certain range of deviation. For example, the deviation range of the vertical angle is 10°, that is, the direction perpendicular to the substrate 10 can be within the range of 80° to 100° with respect to the substrate 10. It should be noted that the direction perpendicular to the substrate 10 mentioned below in this disclosure is also within the above range, and will not be repeated hereafter.

[0073] The conductive contact plug 101 provided in this embodiment can be made of a conductor or semiconductor material. For example, the material used to make the conductive contact plug 101 can be polycrystalline silicon, copper, or tungsten. The conductive contact plug 101 can be formed by one or more methods such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, magnetron sputtering, or vacuum evaporation. The methods for forming the conductive contact plug 101 include, but are not limited to, the methods described above.

[0074] In addition to the conductive contact plug 101 and bit line structure, the substrate 10 also includes other structures that form semiconductor devices, which will not be listed here.

[0075] In step S200, a multi-layer stacked capacitor structure is formed on the surface of the substrate 10. Each capacitor structure includes multiple spaced sub-capacitors, and the sub-capacitors in two adjacent capacitor structures are connected to each other in a direction perpendicular to the substrate 10.

[0076] like Figure 4 As shown in the embodiments provided in this disclosure, there are multiple capacitor structures formed on the substrate 10, and the multiple capacitor structures are stacked in a direction perpendicular to the substrate 10. The number of capacitor structures can be one, two, three, four or more, and the number of capacitor structures can be adaptively adjusted according to the required capacitance of the semiconductor structure.

[0077] Each capacitor structure can be formed by one or more methods such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, magnetron sputtering or vacuum evaporation, or other methods can be used to form the capacitor structure. This disclosure does not specifically limit the method of forming the capacitor structure.

[0078] Combination Figure 4 and Figure 21 As shown, each capacitor structure formed on the substrate 10 may include multiple sub-capacitors, which may be spaced apart and arranged in an array within the capacitor structure. The number of sub-capacitors in each capacitor structure may be multiple, for example, 2, 4, 6, 8, 10 or more.

[0079] Within each capacitor structure, the aspect ratio of the sub-capacitors formed should not be too large or too small to ensure good performance. Due to limitations in the manufacturing process, an excessively large aspect ratio can lead to structural collapse or failure of the sub-capacitor, while an excessively small aspect ratio will result in insufficient capacitance for each sub-capacitor. To increase the capacitance of the semiconductor structure, the formation process would need to be repeated multiple times, increasing the complexity of the manufacturing process and reducing manufacturing efficiency. Therefore, sub-capacitors with suitable aspect ratios can be selected so that the formation method provided in this disclosure has both good capacitance performance and simplified manufacturing steps. Of course, parameters such as the aspect ratio of the sub-capacitors can also be adaptively adjusted according to actual needs, and corresponding changes can be made to the manufacturing process.

[0080] The cross-section of each sub-capacitor can be circular, triangular, or rectangular, etc. The cross-sectional shape of the sub-capacitors in each layer can be the same or different. The cross-sectional shape of the sub-capacitors in different capacitor structures can be the same or different. However, in order to simplify the manufacturing process and facilitate the arrangement of sub-capacitors in the capacitor structure, the sub-capacitors in the same capacitor structure and in different capacitor structures usually adopt the same cross-sectional shape.

[0081] In one embodiment of this disclosure, a multilayer stacked capacitor structure is formed on the surface of a substrate 10. Each capacitor structure includes multiple spaced sub-capacitors, and the sub-capacitors in adjacent capacitor structures are connected to each other in a direction perpendicular to the substrate 10. By connecting the sub-capacitors in adjacent capacitor structures one by one to form an integral capacitor structure, the aspect ratio of the capacitor structure is increased, thereby improving the capacitance of the semiconductor structure. Since the integral capacitor is formed by multiple sub-capacitors arranged and connected, each sub-capacitor is fabricated separately during the manufacturing process. That is, after forming the sub-capacitors in the lower capacitor structure, the upper capacitor structure is formed on the lower capacitor structure, and each sub-capacitor in the lower layer corresponds to a sub-capacitor in the upper layer. This capacitor formation method avoids the collapse problem caused by insufficient etching due to excessive aspect ratio of the capacitor structure, thereby improving both capacitance and device yield.

[0082] like Figures 17 to 20 As shown, in the first embodiment provided in this disclosure, in two adjacent capacitor structures, the orthographic projection of the lower electrode layer (second lower electrode layer 301) of the sub-capacitor located in the upper layer onto the substrate 10 is within the orthographic projection of the lower electrode layer (first lower electrode layer 201) of the sub-capacitor located in the lower layer onto the substrate 10. In a first specific embodiment, within two adjacent capacitor structures, the thickness of the lower electrode layer (second lower electrode layer 301) of the sub-capacitor in the upper layer can be equal to the thickness of the lower electrode layer (first lower electrode layer 201) of the sub-capacitor in the lower layer, that is, the orthographic projections of the lower electrode layer in the upper layer and the lower electrode layer in the lower layer on the substrate 10 completely coincide. In a second specific embodiment, within two adjacent capacitor structures, the thickness of the lower electrode layer (second lower electrode layer 301) of the sub-capacitor in the upper layer is greater than one-third of the thickness of the lower electrode layer (first lower electrode layer 201) of the sub-capacitor in the lower layer, and the thickness of the lower electrode layer (second lower electrode layer 301) of the sub-capacitor in the upper layer is less than the thickness of the lower electrode layer (first lower electrode layer 201) of the sub-capacitor in the lower layer, that is, the orthographic projection of the lower electrode layer (first lower electrode layer 201) in the lower layer on the substrate 10 includes the orthographic projection of the lower electrode layer (second lower electrode layer 301) in the upper layer on the substrate 10.

[0083] Continue to refer to Figures 17 to 20In the second embodiment provided in this disclosure, in two adjacent capacitor structures, the orthographic projection of the upper electrode layer (second upper electrode layer 303) of the sub-capacitor located in the upper layer onto the substrate 10 is within the orthographic projection of the upper electrode layer (first upper electrode layer 203) of the sub-capacitor located in the lower layer onto the substrate 10. In a third specific embodiment, within two adjacent capacitor structures, the thickness of the upper electrode layer (second upper electrode layer 303) of the sub-capacitor in the upper layer can be equal to the thickness of the upper electrode layer (first upper electrode layer 203) of the sub-capacitor in the lower layer, that is, the orthographic projections of the upper electrode layer (second upper electrode layer 303) in the upper layer and the upper electrode layer (first upper electrode layer 203) in the lower layer on the substrate 10 completely coincide. In a fourth specific embodiment, within two adjacent capacitor structures, the thickness of the upper electrode layer (second upper electrode layer 303) of the sub-capacitor in the upper layer is greater than one-third of the thickness of the upper electrode layer (first upper electrode layer 203) of the sub-capacitor in the lower layer, and the thickness of the upper electrode layer (second upper electrode layer 303) of the sub-capacitor in the upper layer is less than the thickness of the upper electrode layer (first upper electrode layer 203) of the sub-capacitor in the lower layer, that is, the orthographic projection of the upper electrode layer (second upper electrode layer 303) in the lower layer on the substrate 10 includes the orthographic projection of the upper electrode layer (first upper electrode layer 203) in the upper layer on the substrate 10.

[0084] The above-described embodiments are connection methods for two adjacent capacitor structures. The first and second embodiments described above can be implemented separately to form a connection between the two capacitor structures. That is, the connection between the two capacitor structures can be achieved simply by aligning the lower electrode layer or the upper electrode layer of the two capacitor structures. Alternatively, the connection between two adjacent capacitor structures can be achieved by any combination of embodiments. For example, the connection can be achieved by combining the first and third embodiments, or by combining the first and fourth embodiments, or by combining the second and third embodiments, or by combining the second and fourth embodiments, etc. This disclosure does not impose any specific limitations.

[0085] Specifically, when forming two adjacent capacitor structures, an overlay process can be used to align the electrode layers of the upper and lower sub-capacitors. This improves the alignment accuracy of the two adjacent capacitor structures, preventing issues such as suspended or short-circuited structures due to low alignment, and further improving the yield of semiconductor structures. Of course, other process techniques can also be used for the connection alignment of adjacent capacitor structures.

[0086] In one embodiment of this disclosure, forming a multilayer stacked capacitor structure on the surface of substrate 10 further includes: the height of the multilayer capacitor structure decreasing sequentially along the direction away from substrate 10. During the fabrication process of the capacitor structure, an excessively large aspect ratio in each capacitor structure can lead to formation defects, such as capacitor short circuits or capacitor collapse. Therefore, to ensure the formation quality of each capacitor structure and avoid formation defects, in this disclosure, the height of the multilayer capacitor structure can decrease sequentially along the direction away from substrate 10. For example, the height distribution of the multilayer capacitor structure can follow an arithmetic or geometric decreasing pattern along the direction away from substrate 10. Of course, the height of the multilayer capacitor structure can also follow an alternating pattern. For example, five capacitor structures are formed along the direction away from substrate 10 with heights of H1, H2, H3, H4, and H5, and their order can be H1 > H3 > H2 > H5 > H4. The above embodiments are merely illustrative; semiconductor structures include, but are not limited to, five-layer capacitor structures, and the height distribution pattern of the multilayer capacitor structure can be the distribution pattern given in the above embodiments or a combination thereof. This disclosure does not impose specific limitations.

[0087] In one exemplary embodiment provided in this disclosure, there can be two capacitor structures, including a first capacitor structure 20 and a second capacitor structure 30. The connection method of the first capacitor structure 20 and the second capacitor structure 30 is as follows: Figure 3 As shown, combined with Figure 4 The method includes:

[0088] Step S210: A first capacitor structure 20 is formed on the surface of the substrate 10, and a plurality of first sub-capacitors 220 are formed in the first capacitor structure 20 at intervals. The first sub-capacitors 220 include a first lower electrode layer 201, a first dielectric layer 202 and a first upper electrode layer 203.

[0089] Step S220: A second capacitor structure 30 is formed on the first capacitor structure 20, and a second sub-capacitor 320 is formed in the second capacitor structure 30 at intervals. The second sub-capacitor 320 includes a second lower electrode layer 301, a second dielectric layer 302, and a second upper electrode layer 303.

[0090] Step S230: The first lower electrode layer 201 and the second lower electrode layer 301 are connected to each other, and the first upper electrode layer 203 and the second upper electrode layer 303 are connected to each other.

[0091] A first capacitor structure 20 is formed on the surface of the substrate 10, such as... Figure 5 As shown, combined with Figure 6 and Figure 7 The method includes:

[0092] Step S211: Form a first stacked layer 200 on the surface of the substrate 10;

[0093] Step S212: Form a plurality of spaced first capacitor holes 210 within the first stacked layer 200;

[0094] Step S213: Form the first sub-capacitor 220 within the first capacitor hole 210.

[0095] The first stacked layer 200 includes a first support layer 211, a first sacrificial layer 221, a second support layer 212, a second sacrificial layer 222, and a third support layer 213 stacked along a direction away from the substrate 10. A first sub-capacitor 220 is formed within the first capacitor hole 210. Figure 8 As shown, combined with Figure 9 and Figure 10 The method includes:

[0096] Step S2121: Form a first lower electrode layer 201 on the sidewall and bottom of the first sub-capacitor 220 hole;

[0097] Step S2122: Remove the first sacrificial layer 221 and the second sacrificial layer 222;

[0098] Step S2123: Form a first dielectric layer 202 on the surface of the first lower electrode layer 201;

[0099] Step S2124: Form a first upper electrode layer 203 on the surface of the first dielectric layer 202.

[0100] Reference Figure 4 and Figure 21 As shown, the first support layer 211, the second support layer 212, and the third support layer 213 can be sequentially formed on the substrate 10 by methods such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, or magnetron sputtering. Their thickness along the direction perpendicular to the substrate 10 can be selected according to the actual process requirements of the capacitor structure. Of course, the support layers can also be formed by other methods, which will not be listed here. The materials of the first support layer 211, the second support layer 212, and the third support layer 213 can be silicon nitride or silicon carbonitride, i.e., Si3N4 or SiCN, and their thickness can be 20nm to 200nm. The materials of the first support layer 211, the second support layer 212, and the third support layer 213 can be the same or different, and their thicknesses can also be the same or different, depending on the specific requirements.

[0101] The first sacrificial layer 221 and the second sacrificial layer 222 can be silicon-containing compound films formed between the support layers, such as SiO2 layers or BPSG layers, and their thickness can be 20nm to 200nm.

[0102] When forming the first capacitor hole 210, a mask layer can be formed on the side of the third support layer 213 facing away from the substrate 10, and the first capacitor hole 210 can be formed in the first stacked layer 200 by etching or other methods. Specifically, a photoresist layer can be formed on the side of the mask layer facing away from the substrate 10 by spin coating or other methods. The material of the photoresist layer can be positive photoresist or negative photoresist. The shape of the surface of the photoresist layer away from the mask layer can be the same as the shape of the mask layer surface. A mask can be used to expose the photoresist layer, and the pattern of the mask can match the pattern required for the first capacitor hole 210. Then, the exposed photoresist layer can be developed to form a developing area. The developing area can expose the mask layer, and the pattern of the developing area can be the same as the pattern required for the first capacitor hole 210. The size of the developing area can be the same as the size of the required first capacitor hole 210. The first stacked layer 200 is then dry etched in the developing area to form the first capacitor hole 210. In this disclosure, the width and depth of the first capacitor hole 210 can be selected according to the number and volume of the first sub-capacitors 220, and the number of the first capacitor holes 210 can be the same as the number of the first sub-capacitors 220.

[0103] After forming the first capacitor hole 210, the aforementioned mask layer can be removed, and then step S2121 can be performed to form a first lower electrode layer 201 on the sidewall and bottom of the first sub-capacitor 220 hole. Specifically, a first lower electrode layer 201 can be formed within the first capacitor hole 210, conforming to the bottom and sidewall surfaces of the first capacitor hole 210. For process convenience, after simultaneously forming the first lower electrode layer 201 on the inner wall and top surface of the first capacitor hole 210, the first lower electrode layer 201 on the top surface can be removed, leaving the first lower electrode layer 201 attached to the bottom and sidewall of the first capacitor hole 210. Specifically, the first lower electrode layer 201 can be formed in the first capacitor hole 210 by methods such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation or magnetron sputtering. The first lower electrode layer 201 can be made of conductive materials, such as tungsten, titanium or titanium nitride. Of course, it can also be other materials that can be used as electrode layers, which are not specifically limited here.

[0104] Furthermore, if the first sub-capacitor 220 is formed directly on the substrate 10, then the first lower electrode layer 201 of the first sub-capacitor 220 is connected to the conductive contact plug 101 disposed on the substrate 10, so that the charge stored in the first lower electrode layer 201 of the first sub-capacitor 220 can be input to the conductive contact plug 101, thereby realizing the charge storage of the capacitor in the semiconductor structure.

[0105] After the first lower electrode layer 201 is formed, step S2122 is performed to remove the first sacrificial layer 221 and the second sacrificial layer 222, and retain the first support layer 211, the second support layer 212 and the third support layer 213. The three support layers cover the outside of the first lower electrode layer 201 and support the first lower electrode layer 201 to prevent the first lower electrode layer 201 from deforming and reduce the short circuit risk of the capacitor structure.

[0106] like Figure 10 As shown, the removal of the first sacrificial layer 221 and the second sacrificial layer 222 can be achieved by a wet etching process. For example, an acidic solution can be used for wet etching to remove the sacrificial layers. The acidic solution can contain hydrofluoric acid, and more specifically, it can be a hydrofluoric acid solution with a concentration of 40% to 55%. Of course, the acidic solution can also include other acidic reagents, such as nitric acid, to achieve the same effect as hydrofluoric acid in removing the first sacrificial layer 221 and the second sacrificial layer 222.

[0107] In step S2123, a first dielectric layer 202 is formed on the surface of the first lower electrode layer 201. The first dielectric layer 202 can be a thin film formed on the first lower electrode layer 201, and can be formed by methods such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, or magnetron sputtering. The first dielectric layer 202 can be a single-layer film or a mixed multilayer film composed of various different materials. For example, the first dielectric layer 202 can be a film including a material with a high dielectric constant, which may include alumina, hafnium oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, silicon nitride, and mixtures of the above materials.

[0108] In step S2124, a first upper electrode layer 203 is formed on the surface of the first dielectric layer 202. The first upper electrode layer 203 is an electrode layer formed on the first dielectric layer 202, and can be formed by methods such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, or magnetron sputtering. The first upper electrode layer 203 can be made of a conductive material, such as tungsten, titanium, or titanium nitride, or other materials that can be used as electrode layers; no specific limitation is made here.

[0109] After forming the first upper electrode layer 203, a first semiconductor layer 230 is formed covering the first capacitor structure 20. The first semiconductor layer 230 fills the gaps within the first sub-capacitor 220 and the gaps between the multiple first sub-capacitors 220 to ensure the structural stability of the first capacitor structure 20 and avoid instability caused by the gaps within the first sub-capacitors 220 and between the multiple first sub-capacitors 220. The first semiconductor layer 230 fills the interior of the first capacitor structure 20 and covers the top surface of the first capacitor structure 20. The first semiconductor layer 230 can be a film layer made of polycrystalline silicon or other materials.

[0110] like Figure 11 As shown, since the first semiconductor film layer covers the top surface of the first capacitor structure 20, in order to connect the first capacitor structure 20 with the second capacitor structure 30, it is necessary to expose the conductive part of the first capacitor structure 20, that is, to remove part of the first semiconductor layer 230 to expose the ends of the first lower electrode layer 201, the first dielectric layer 202 and the first upper electrode layer 203.

[0111] A second capacitor structure 30 is formed on the first capacitor structure 20, such as Figure 12 As shown, combined with Figure 13 and Figure 14 The method includes:

[0112] Step S221: A cutoff layer 240 is formed at the end of the first lower electrode layer 201, the first upper electrode layer 203 and the first dielectric layer 202, and a second stacked layer 300 is formed on the cutoff layer 240.

[0113] Step S222: A plurality of spaced second capacitor holes 310 are formed in the second stacked layer 300, and the orthographic projection of the second capacitor holes 310 on the substrate 10 overlaps with the orthographic projection of the first capacitor holes 210 on the substrate 10.

[0114] Step S223: Remove the cut-off layer 240 located at the bottom of the second capacitor hole 310;

[0115] Step S224: Form a second sub-capacitor 320 within the second capacitor hole 310.

[0116] In step S221, to prevent damage to the integrity of the first capacitor structure 20 during the formation of the second capacitor structure 30, a stop layer 240 can be formed on the top surface of the first capacitor structure 20 as an etching stop layer for the second capacitor structure 30. Specifically, the stop layer 240 is formed on the surface where the end faces of the first lower electrode layer 201, the first dielectric layer 202, and the first upper electrode layer 203 are located. The stop layer 240 can be formed by methods such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, or magnetron sputtering. The material of the stop layer 240 can be the same as that of the third support layer 213, for example, it can be a silicon nitride or silicon carbonitride film. Its thickness can be selected according to actual process requirements, typically from 20nm to 200nm. The stop layer 240 serves as both an etching stop layer and a support layer for the second capacitor structure 30, providing support for the second capacitor structure 30.

[0117] After the cutoff layer 240 is formed on the top surface of the first capacitor structure 20, the cutoff layer 240 can be planarized to provide a flat film layer for the formation of the second capacitor structure 30. For example, the cutoff layer 240 can be partially removed by chemical mechanical polishing or other methods to ensure the flatness of the side of the cutoff layer 240 facing away from the substrate 10.

[0118] The orthographic projection of the second capacitor hole 310 on the substrate 10 overlaps with the orthographic projection of the first capacitor hole 210 on the substrate 10. That is, the orthographic projection of the first capacitor hole 210 on the substrate 10 includes the orthographic projection of the second capacitor hole 310 on the substrate 10, or the orthographic projection of the second capacitor hole 310 on the substrate 10 overlaps with the orthographic projection of the first capacitor hole 210 on the substrate 10.

[0119] After the second capacitor hole 310 is formed, the cut-off layer 240 at the bottom of the second capacitor hole 310 is exposed. In order to connect the first capacitor structure 20 and the second capacitor structure 30, the cut-off layer 240 at the bottom of the second capacitor hole 310 needs to be removed, and then a second sub-capacitor 320 is formed in the second capacitor hole 310.

[0120] The second stacked layer 300 includes a third sacrificial layer 321 and a fourth support layer 311. The third sacrificial layer 321 is formed on the side of the fourth support layer 311 facing away from the substrate 10. A second sub-capacitor 320 is formed within the second capacitor hole 310, as shown below. Figure 15 As shown, combined with Figure 16 The method includes:

[0121] Step S2221: Form a second lower electrode layer 301 on the sidewall and bottom of the second capacitor hole 310;

[0122] Step S2222: Remove the third sacrificial layer 321;

[0123] Step S2223: Form a second dielectric layer 302 on the surface of the second lower electrode layer 301;

[0124] Step S2224: Form a second upper electrode layer 303 on the surface of the second dielectric layer 302.

[0125] In steps S2221 to S2224, the second lower electrode layer 301 is made of the same material and formed by the first lower electrode layer 201; the second dielectric layer 302 is made of the same material and formed by the first dielectric layer 202; the second upper electrode layer 303 is made of the same material and formed by the first upper electrode layer 203; and the removal method of the third sacrificial layer 321 is the same as the removal method of the first sacrificial layer 221. These details will not be repeated here.

[0126] In the above steps, the end of the second lower electrode layer 301 near the substrate 10 is connected to the end of the first lower electrode layer 201 away from the substrate 10, and the end of the second upper electrode layer 303 near the substrate 10 is connected to the end of the first upper electrode layer 203 away from the substrate 10, thereby realizing the connection between the first capacitor structure 20 and the second capacitor structure 30. The structural relationship between the upper and lower electrode layers in the two capacitor structures has been described above and will not be repeated here.

[0127] After forming the second sub-capacitor 320, a second semiconductor layer 330 can be formed covering the second capacitor structure 30. The second semiconductor layer 330 fills the gaps within the second sub-capacitor 320 and the gaps between the multiple second sub-capacitors 320. This ensures the structural stability of the second capacitor structure 30 and avoids instability caused by gaps within the second sub-capacitor 320 and between the multiple second sub-capacitors 320. The second semiconductor layer 330 fills the interior of the second capacitor structure 30 and covers the top surface of the second capacitor structure 30. The second semiconductor layer 330 can be a film layer made of polycrystalline silicon or other materials.

[0128] The above embodiments of this disclosure illustrate the method for forming a semiconductor structure provided in this disclosure using a two-layer capacitor structure. However, in this disclosure, the capacitor structure includes a multi-layer capacitor structure formed on the substrate 10, and the formation method of the multi-layer capacitor structure is the same as that of the two-layer capacitor structure. The multi-layer here includes, but is not limited to, two layers. For example, it can be two layers, three layers, four layers, five layers, etc., which will not be elaborated here.

[0129] The semiconductor structure formation method disclosed herein forms a multilayer capacitor structure on a substrate 10, in which multiple spaced sub-capacitors are formed within each capacitor. By connecting the sub-capacitors in adjacent capacitor structures one-to-one, a capacitor structure with multiple sub-capacitors connected in a direction perpendicular to the substrate 10 is formed, increasing the aspect ratio of the capacitor structure and thus increasing the capacitance of the capacitor structure. In addition, this formation method solves the problem of inconsistent etching depth caused by increasing the aspect ratio during capacitor structure formation, which leads to the capacitor structure being suspended, resulting in capacitor structure collapse or failure, and improves the product yield.

[0130] It should be noted that although the steps of the semiconductor structure formation method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0131] This disclosure also provides a semiconductor structure, such as Figure 4 As shown, the semiconductor structure includes a substrate 10 and a capacitor structure; multiple capacitor layers are stacked on the surface of the substrate 10, each capacitor layer including multiple spaced sub-capacitors, and the sub-capacitors in adjacent capacitor layers are connected to each other in a direction perpendicular to the substrate 10. Specifically, in two adjacent capacitor structures, the orthographic projection of the lower electrode layer of the sub-capacitor in the upper layer onto the substrate lies within the orthographic projection of the lower electrode layer of the sub-capacitor in the lower layer onto the substrate; or, in two adjacent capacitor structures, the orthographic projection of the upper electrode layer of the sub-capacitor in the upper layer onto the substrate lies within the orthographic projection of the upper electrode layer of the sub-capacitor in the lower layer onto the substrate. The semiconductor structure disclosed herein forms a multilayer capacitor structure on a substrate 10. Each capacitor contains multiple spaced sub-capacitors. By connecting the sub-capacitors in adjacent capacitor structures one-to-one, a capacitor structure with multiple connected sub-capacitors is formed in a direction perpendicular to the substrate 10, increasing the aspect ratio of the capacitor structure and thus increasing the capacitance of the capacitor structure. In addition, this formation method solves the problem that inconsistent etching depth caused by increasing the aspect ratio during capacitor structure formation can lead to capacitor structure suspension, resulting in capacitor structure collapse or failure, thereby improving product yield.

[0132] The semiconductor structure provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings:

[0133] like Figure 4 and Figure 21As shown in the embodiments provided in this disclosure, the substrate 10 of the semiconductor structure can be a flat plate structure, and may further include multiple structures required for forming semiconductor devices. For example, conductive contact plugs 101 may be included within the substrate 10. The conductive contact plugs 101 can be used to connect the substrate 10 and the capacitor structure. The conductive contact plugs 101 can be formed by pre-defining a capacitor contact hole formation area on the substrate 10. The capacitor contact hole formation area can be used to form the conductive contact plugs 101. Bit line structures may also be included within the substrate 10. A bit line structure formation area is pre-defined on the substrate 10. The bit line structure formation area can be used to form the bit line structure. The specific formation methods and structures of the conductive contact plugs 101 and the bit line structures can be fabricated according to actual manufacturing needs. Here, no specific limitations are made on the specific formation methods and structures of the conductive contact plugs 101 and the bit line structures.

[0134] The substrate 10 may also include an insulating layer, in which multiple spaced-apart capacitor contact holes can be formed. Conductive contact plugs 101 are formed within the capacitor contact holes, and the insulating layer separates the multiple conductive contact plugs 101 to prevent coupling or short circuits between them. Of course, before forming the capacitor contact holes in the insulating layer, a bit line structure can be formed on the substrate 10. The fabrication process and flow here can be adapted to meet actual needs.

[0135] The conductive contact plugs 101 can be vertically arrayed along a direction perpendicular to the substrate 10. The direction perpendicular to the substrate 10 provided in this disclosure can be absolutely perpendicular or approximately perpendicular. Due to limitations in the manufacturing process, the vertical angle will not be strictly 90°, and there will be a certain range of deviation. For example, the deviation range of the vertical angle is 10°, that is, the direction perpendicular to the substrate 10 can be within the range of 80° to 100° with respect to the substrate 10. It should be noted that the direction perpendicular to the substrate 10 mentioned below in this disclosure is also within the above range, and will not be repeated hereafter.

[0136] The conductive contact plug 101 provided in this embodiment may be made of a conductor or semiconductor material. For example, the material used to make the conductive contact plug 101 may be polycrystalline silicon, copper, or tungsten. The conductive contact plug 101 may be formed by one or more methods such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, magnetron sputtering, or vacuum evaporation. The methods for forming the conductive contact plug 101 include, but are not limited to, the methods described above.

[0137] In addition to the conductive contact plug 101 and bit line structure, the substrate 10 also includes other structures that form semiconductor devices, which will not be listed here.

[0138] In the embodiments provided in this disclosure, there are multiple capacitor structures formed on the substrate 10, and the multiple capacitor structures are stacked in a direction perpendicular to the substrate 10. The number of capacitor structures can be one, two, three, four or more, and the number of capacitor structures can be adaptively adjusted according to the required capacitance of the semiconductor structure.

[0139] Each capacitor structure can be formed by one or more methods such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, magnetron sputtering or vacuum evaporation, or other methods can be used to form the capacitor structure. This disclosure does not specifically limit the method of forming the capacitor structure.

[0140] Each capacitor structure formed on the substrate 10 may include multiple sub-capacitors, which may be spaced apart and arranged in an array within the capacitor structure. The number of sub-capacitors in each capacitor structure may be multiple, for example, 2, 4, 6, 8, 10 or more.

[0141] Within each capacitor structure, the aspect ratio of the sub-capacitors formed should not be too large or too small to ensure good performance. Due to limitations in the manufacturing process, an excessively large aspect ratio can lead to structural collapse or failure of the sub-capacitor, while an excessively small aspect ratio will result in insufficient capacitance for each sub-capacitor. To increase the capacitance of the semiconductor structure, the formation process would need to be repeated multiple times, increasing the complexity of the manufacturing process and reducing manufacturing efficiency. Therefore, sub-capacitors with suitable aspect ratios can be selected so that the formation method provided in this disclosure has both good capacitance performance and simplified manufacturing steps. Of course, parameters such as the aspect ratio of the sub-capacitors can also be adaptively adjusted according to actual needs, and corresponding changes can be made to the manufacturing process.

[0142] The cross-section of each sub-capacitor can be circular, triangular, or rectangular, etc. The cross-sectional shape of the sub-capacitors in each layer can be the same or different. The cross-sectional shape of the sub-capacitors in different capacitor structures can be the same or different. However, in order to simplify the manufacturing process and facilitate the arrangement of sub-capacitors in the capacitor structure, the sub-capacitors in the same capacitor structure and in different capacitor structures usually adopt the same cross-sectional shape.

[0143] In one embodiment of this disclosure, a multilayer capacitor structure is formed on a substrate 10. Each capacitor structure includes multiple spaced sub-capacitors, and the sub-capacitors in adjacent capacitor structures are connected by a one-to-one docking manner along a direction perpendicular to the substrate 10. By docking the sub-capacitors in adjacent capacitor structures one-to-one, a whole capacitor structure is formed, which increases the aspect ratio of the capacitor structure and thus improves the capacitance of the semiconductor structure.

[0144] Specifically, within two adjacent capacitor structures, the orthographic projection of the lower electrode layer of the sub-capacitor located in the upper layer onto the substrate 10 lies within the orthographic projection of the lower electrode layer of the sub-capacitor located in the lower layer onto the substrate 10. Furthermore, within two adjacent capacitor structures, the thickness of the lower electrode layer of the sub-capacitor located in the upper layer is greater than or equal to one-third of the thickness of the lower electrode layer of the sub-capacitor located in the lower layer, and the thickness of the lower electrode layer of the sub-capacitor located in the upper layer is less than the thickness of the lower electrode layer of the sub-capacitor located in the lower layer.

[0145] And / or, within two adjacent capacitor structures, the orthographic projection of the upper electrode layer of the sub-capacitor located in the upper layer onto the substrate 10 lies within the orthographic projection of the upper electrode layer of the sub-capacitor located in the lower layer onto the substrate 10. Further, within two adjacent capacitor structures, the thickness of the upper electrode layer of the sub-capacitor located in the upper layer is greater than or equal to one-third of the thickness of the upper electrode layer of the sub-capacitor located in the lower layer, and the thickness of the upper electrode layer of the sub-capacitor located in the upper layer is less than the thickness of the upper electrode layer of the sub-capacitor located in the lower layer.

[0146] Furthermore, the height of the multilayer capacitor structure can decrease sequentially along the direction away from the substrate 10. The height relationship of the multilayer capacitor structure in the semiconductor structure has been described above and will not be repeated here.

[0147] In an exemplary embodiment provided in this disclosure, the capacitor structure can be two-layered, namely a first capacitor structure 20 and a second capacitor structure 30. The semiconductor structure includes the first capacitor structure 20 and the second capacitor structure 30. The first capacitor structure 20 includes a plurality of spaced-apart first sub-capacitors 220, each sub-capacitor 220 including a first lower electrode layer 201, a first dielectric layer 202, and a first upper electrode layer 203. The second capacitor structure 30 includes a plurality of spaced-apart second sub-capacitors 320, each sub-capacitor 320 including a second lower electrode layer 301, a second dielectric layer 302, and a second upper electrode layer 303. The second lower electrode layers 301 are connected one-to-one with the first lower electrode layers 201, and the second upper electrode layers 303 are connected one-to-one with the first upper electrode layers 203, so that the first capacitors and the second capacitor structure 30 are connected to form a semiconductor structure.

[0148] The first capacitor structure 20 further includes a first support layer 211, which supports different parts of the first sub-capacitor 220; the second capacitor structure 30 includes a second support layer 212, which supports the formation of the second sub-capacitor 320. In this disclosure, at least one first support layer 211 and a second support layer 212 are used. The specific number of the first support layer 211 and the second support layer 212 can be determined based on the height of the first capacitor structure 20 and the second capacitor structure 30, so that the first support layer 211 and the second support layer 212 provide support for the first capacitor structure 20 and the second capacitor structure 30, preventing deformation of the electrode layers in the capacitor structure, which could lead to capacitor collapse or short circuit. The first support layer 211 and the second support layer 212 can be silicon nitride or silicon carbonitride films, and their thickness can be selected according to actual process requirements, typically ranging from 20 nm to 200 nm.

[0149] The above embodiment uses a semiconductor structure including a two-layer capacitor structure as an example for illustration. In actual structures, the semiconductor structure may include multiple capacitor structures stacked on the substrate 10, such as two, three, four, five, or six layers. The number of capacitor layers can be selected according to the capacitance requirements of the semiconductor structure, and no specific limitation is made here. By connecting the upper and lower electrode layers in the multilayer capacitor structure, the multilayer capacitor structure is connected into a whole, thereby increasing the aspect ratio of the capacitor structure in the semiconductor structure and achieving the purpose of increasing capacitance.

[0150] The semiconductor structure also includes multiple semiconductor layers. The number of semiconductor layers can be the same as the number of capacitor structures. Each semiconductor layer covers its corresponding capacitor structure and fills the gaps within the sub-capacitors and between multiple sub-capacitors in its corresponding capacitor structure to improve the stability of the capacitor structure. The semiconductor layers can be films such as polycrystalline silicon layers.

[0151] The semiconductor structure disclosed herein has a multilayer stacked capacitor structure, and the sub-capacitors in adjacent capacitor structures are connected to each other in a direction perpendicular to the substrate 10. The semiconductor structure has a large storage capacity and good performance, and it has a stable capacitor storage structure.

[0152] The semiconductor structure provided in this disclosure can be applied to memory. The specific structure, formation process and beneficial effects of the semiconductor have been described in detail in the corresponding semiconductor structure formation method and semiconductor structure, and will not be repeated here.

[0153] In the embodiments provided in this disclosure, the memory may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. Of course, other storage devices may also be used, which will not be listed here.

[0154] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A multilayer stacked capacitor structure is formed on the surface of the substrate. Each capacitor structure includes multiple spaced sub-capacitors. The sub-capacitors in two adjacent capacitor structures are connected to each other in a direction perpendicular to the substrate. Within two adjacent capacitor structures, the orthographic projection of the lower electrode layer of the sub-capacitor located in the upper layer onto the substrate lies within the orthographic projection of the lower electrode layer of the sub-capacitor located in the lower layer onto the substrate. Alternatively, within two adjacent capacitor structures, the orthographic projection of the upper electrode layer of the sub-capacitor located in the upper layer onto the substrate lies within the orthographic projection of the upper electrode layer of the sub-capacitor located in the lower layer onto the substrate. The capacitor structure includes a first capacitor structure and a second capacitor structure, forming a multi-layered stacked capacitor structure on the surface of the substrate. Each capacitor structure includes multiple spaced sub-capacitors, and the sub-capacitors in adjacent capacitor structures are connected to each other in a one-to-one correspondence along a direction perpendicular to the substrate. The first capacitor structure is formed on the surface of the substrate, and a plurality of first sub-capacitors are formed in the first capacitor structure at intervals. The first sub-capacitors include a first lower electrode layer, a first dielectric layer and a first upper electrode layer. The second capacitor structure is formed on the first capacitor structure, and second sub-capacitors are formed in the second capacitor structure at intervals. The second sub-capacitors include a second lower electrode layer, a second dielectric layer and a second upper electrode layer. The first lower electrode layer and the second lower electrode layer are connected to each other, and the first upper electrode layer and the second upper electrode layer are connected to each other.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, Within two adjacent capacitor structures, the thickness of the lower electrode layer of the sub-capacitor located in the upper layer is greater than or equal to one-third of the thickness of the lower electrode layer of the sub-capacitor located in the lower layer, and the thickness of the lower electrode layer of the sub-capacitor located in the upper layer is less than the thickness of the lower electrode layer of the sub-capacitor located in the lower layer.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, Within two adjacent capacitor structures, the thickness of the upper electrode layer of the sub-capacitor located in the upper layer is greater than or equal to one-third of the thickness of the upper electrode layer of the sub-capacitor located in the lower layer, and the thickness of the upper electrode layer of the sub-capacitor located in the upper layer is less than the thickness of the upper electrode layer of the sub-capacitor located in the lower layer.

4. The method for forming a semiconductor structure according to claim 1, characterized in that, A multilayer stacked capacitor structure is formed on the surface of the substrate, including: The height of the multilayer capacitor structure decreases sequentially in the direction away from the substrate.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, The method further includes: A first stacked layer is formed on the surface of the substrate; Multiple spaced-out first capacitor holes are formed within the first stacked layer; A first semiconductor layer is formed to cover the first sub-capacitor structure, and the first semiconductor layer fills the gaps in the first sub-capacitor and the gaps between the plurality of first sub-capacitors. Remove a portion of the first semiconductor layer to expose the ends of the first lower electrode layer, the first dielectric layer, and the first upper electrode layer; A cutoff layer is formed on the surface where the ends of the first lower electrode layer, the first upper electrode layer and the first dielectric layer are located, and a second stacked layer is formed on the cutoff layer; A plurality of spaced second capacitor holes are formed in the second stacked layer, and the orthographic projection of the second capacitor holes on the substrate overlaps with the orthographic projection of the first capacitor holes on the substrate. Remove the cut-off layer located at the bottom of the second capacitor hole; A second sub-capacitor is formed within the second capacitor hole.

6. A semiconductor structure formed by the method according to any one of claims 1-5, characterized in that, include: Substrate; A capacitor structure, wherein multiple layers of the capacitor structure are stacked on the surface of the substrate, each capacitor structure includes multiple spaced sub-capacitors, and the sub-capacitors in two adjacent capacitor structures are connected to each other in a direction perpendicular to the substrate. Within two adjacent capacitor structures, the orthographic projection of the lower electrode layer of the sub-capacitor located in the upper layer onto the substrate lies within the orthographic projection of the lower electrode layer of the sub-capacitor located in the lower layer onto the substrate. Alternatively, within two adjacent capacitor structures, the orthographic projection of the upper electrode layer of the sub-capacitor located in the upper layer onto the substrate lies within the orthographic projection of the upper electrode layer of the sub-capacitor located in the lower layer onto the substrate.

7. The semiconductor structure according to claim 6, characterized in that, Within two adjacent capacitor structures, the thickness of the lower electrode layer of the sub-capacitor located in the upper layer is greater than or equal to one-third of the thickness of the lower electrode layer of the sub-capacitor located in the lower layer, and the thickness of the lower electrode layer of the sub-capacitor located in the upper layer is less than the thickness of the lower electrode layer of the sub-capacitor located in the lower layer.

8. The semiconductor structure according to claim 6, characterized in that, Within two adjacent capacitor structures, the thickness of the upper electrode layer of the sub-capacitor located in the upper layer is greater than or equal to one-third of the thickness of the upper electrode layer of the sub-capacitor located in the lower layer, and the thickness of the upper electrode layer of the sub-capacitor located in the upper layer is less than the thickness of the upper electrode layer of the sub-capacitor located in the lower layer.

9. The semiconductor structure according to claim 6, characterized in that, The height of the multilayer capacitor structure decreases sequentially along the direction away from the substrate.

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