Quantum circuit processing method, device and electronic equipment

Abstract

The present disclosure provides a quantum circuit processing method, device and electronic device, which relates to the field of quantum computing technology, and specifically to the field of quantum circuit technology. The specific implementation scheme is: obtain a first instruction list for a first quantum circuit, the first quantum circuit includes L strong entanglement layers, in which the quantum bit of quantum bit j and the quantum bit of quantum bit j+1 are entangled in turn through the first double quantum bit gate, and the quantum bit of quantum bit N-1 and the quantum bit of quantum bit 0 are entangled through the second double quantum bit gate; when N is greater than or equal to 4 and L is equal to 1, based on the first instruction list, the first quantum circuit is equivalently compiled to obtain the second instruction list of the second quantum circuit; the equivalent compilation includes: adding a first reset operation instruction after the first measurement operation instruction in the first instruction list; mapping the target operation instruction acting on quantum bit i+2 in the first instruction list to the quantum bit of quantum bit i.

Description

Technical Field

[0001] The present disclosure relates to the field of quantum computing technology, in particular to the field of quantum circuit technology, and specifically to a quantum circuit processing method, device and electronic device. Background Art

[0002] Quantum computing uses the unique operating rules of the quantum world to provide a new and very promising way of information processing. In many specific problems, quantum algorithms can bring advantages over classical algorithms. For example, using Shor's algorithm, large integers can be efficiently decomposed, and using Grover's algorithm, data searches can be performed faster. With the development of quantum theory, new quantum algorithms are constantly being proposed. How to efficiently simulate these algorithms or run them on real quantum hardware has always been an important issue.

[0003] The classical simulation or real machine operation of quantum algorithms is mainly limited by the number of quantum bits. In classical simulation, the length of the column vector describing the quantum state grows exponentially with the number of corresponding bits (for example, the length of the column vector of an n-bit quantum state is 2 n ), it is difficult for classical computers to simulate large-scale quantum algorithms. Limited by computer memory and processor capabilities, existing quantum circuit simulation methods can only support the simulation of algorithms with dozens of quantum bits at most.

[0004] At present, heuristic algorithms are usually used to compile quantum circuits to obtain dynamic quantum circuits equivalent to quantum circuits. Summary of the invention

[0005] The present disclosure provides a quantum circuit processing method, device and electronic device.

[0006] According to a first aspect of the present disclosure, a quantum circuit processing method is provided, comprising:

[0007] Obtain a first instruction list of a first quantum circuit including N quantum bits, wherein the first quantum circuit is a quantum circuit of a strongly entangled structure, and the first quantum circuit includes L strongly entangled layers, wherein the N quantum bits in the first quantum circuit are sequentially arranged from the quantum bit of quantum bit 0 to the quantum bit of quantum bit N-1, and in the strongly entangled layer, the quantum bit of quantum bit j and the quantum bit of quantum bit j+1 are sequentially entangled through a first double quantum bit gate in order of j from small to large, and the quantum bit of quantum bit N-1 and the quantum bit of quantum bit 0 are entangled through a second double quantum bit gate, and the second double quantum bit gate is located at the end of the quantum state time evolution direction in the strongly entangled layer, and the value range of j is [0, N-2], N is an integer greater than 2, and L is a positive integer;

[0008] When N is greater than or equal to 4 and L is equal to 1, based on the first instruction list, equivalently compile the first quantum circuit to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit;

[0009] Among them, the number of quantum bits of the second quantum circuit is less than the number of quantum bits of the first quantum circuit, and the equivalent compilation includes: adding a first reset operation instruction after the first measurement operation instruction in the first instruction list; and remapping each target operation instruction in the first instruction list to the quantum bit of quantum bit i, the first measurement operation instruction and the first reset operation instruction both act on quantum bit i, and the target operation instruction acts on quantum bit i+2, and the value range of i is [1, N-3].

[0010] According to a second aspect of the present disclosure, there is provided a quantum circuit processing device, comprising:

[0011] An acquisition module is used to acquire a first instruction list of a first quantum circuit including N quantum bits, wherein the first quantum circuit is a quantum circuit of a strongly entangled structure, and the first quantum circuit includes L strongly entangled layers, wherein the N quantum bits in the first quantum circuit are sequentially arranged from the quantum bit of quantum bit 0 to the quantum bit of quantum bit N-1, and in the strongly entangled layer, the quantum bit of quantum bit j and the quantum bit of quantum bit j+1 are sequentially entangled through a first double quantum bit gate in order of j from small to large, and the quantum bit of quantum bit N-1 and the quantum bit of quantum bit 0 are entangled through a second double quantum bit gate, and the second double quantum bit gate is located at the end of the quantum state time evolution direction in the strongly entangled layer, and the value range of j is [0, N-2], N is an integer greater than 2, and L is a positive integer;

[0012] an equivalent compiling module, configured to perform equivalent compiling on the first quantum circuit based on the first instruction list to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit when N is greater than or equal to 4 and L is equal to 1;

[0013] Among them, the number of quantum bits of the second quantum circuit is less than the number of quantum bits of the first quantum circuit, and the equivalent compilation includes: adding a first reset operation instruction after the first measurement operation instruction in the first instruction list; and remapping each target operation instruction in the first instruction list to the quantum bit of quantum bit i, the first measurement operation instruction and the first reset operation instruction both act on quantum bit i, and the target operation instruction acts on quantum bit i+2, and the value range of i is [1, N-3].

[0014] According to a third aspect of the present disclosure, there is provided an electronic device, including:

[0015] at least one processor; and

[0016] a memory communicatively connected to at least one processor; wherein,

[0017] The memory stores instructions that can be executed by at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform any method in the first aspect.

[0018] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause a computer to execute any one of the methods in the first aspect.

[0019] According to a fifth aspect of the present disclosure, a computer program product is provided, comprising a computer program, which implements any one of the methods in the first aspect when executed by a processor.

[0020] The technology disclosed in the present invention solves the problem in the related art that classical simulation and real-machine operation of cyclic entangled quantum circuits, i.e., strongly entangled quantum circuits, are relatively difficult, and can achieve optimal compilation of cyclic entangled quantum circuits so that the width of the compiled quantum circuit can be minimized, that is, a cyclic entangled quantum circuit can be compiled into an equivalent dynamic quantum circuit with the least number of required quantum bits, thereby simplifying the classical simulation and real-machine operation of cyclic entangled quantum circuits.

[0021] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0023] Figure 1 is a flowchart of a quantum circuit processing method according to the first embodiment of the present disclosure;

[0024] Figure 2 This is a schematic diagram of the structure of an example static quantum circuit;

[0025] Figure 3 is a schematic diagram of the structure of a static quantum circuit of another example;

[0026] Figure 4 yes Figure 3 A schematic diagram of the structure of a dynamic quantum circuit compiled from the quantum circuit shown;

[0027] Figure 5 This is a schematic diagram of the structure of an example of a circular entangled quantum circuit;

[0028] Figure 6 is a schematic diagram of the structure of another example of a circular entangled quantum circuit;

[0029] Figure 7 yes Figure 6 A schematic diagram of the structure of a dynamic quantum circuit compiled from the quantum circuit shown;

[0030] Figure 8 is a schematic structural diagram of a quantum circuit processing device according to a second embodiment of the present disclosure;

[0031] Fig. 9 is a schematic block diagram of an example electronic device for implementing an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0033] First embodiment

[0034] like Figure 1 As shown, the present disclosure provides a quantum circuit processing method, comprising the following steps:

[0035] Step S101: obtaining a first instruction list of a first quantum circuit including N quantum bits, wherein the first quantum circuit is a quantum circuit of a strongly entangled structure, and the first quantum circuit includes L strongly entangled layers, wherein the N quantum bits in the first quantum circuit are sequentially arranged from the quantum bit of quantum bit 0 to the quantum bit of quantum bit N-1, and in the strongly entangled layer, the quantum bit of quantum bit j and the quantum bit of quantum bit j+1 are sequentially entangled through a first two-qubit gate in order of j from small to large, and the quantum bit of quantum bit N-1 is entangled with the quantum bit of quantum bit 0 through a second two-qubit gate, and the second two-qubit gate is located at the end of the quantum state time evolution direction in the strongly entangled layer, and the value range of j is [0, N-2], N is an integer greater than 2, and L is a positive integer.

[0036] In this embodiment, the quantum circuit processing method relates to the field of quantum computing technology, and in particular to the field of quantum circuit technology, which can be widely used in classical simulation and real machine operation scenarios of quantum circuits. The quantum circuit processing method of the disclosed embodiment can be executed by the quantum circuit processing device of the disclosed embodiment. The quantum circuit processing device of the disclosed embodiment can be configured in any electronic device to execute the quantum circuit processing method of the disclosed embodiment.

[0037] At present, the mainstream quantum computing implementation method is based on the quantum circuit model, that is, the evolution of quantum states is completed by acting on a series of quantum gates on quantum bits, and quantum measurements are performed at the end of the circuit to obtain the calculation results. The quantum circuit commonly used in the industry is a static quantum circuit, that is, a quantum circuit that only contains measurement operations at the end of the circuit.

[0038] With the recent rapid development of hardware (mainly the significant improvement of quantum bit coherence time, and the realization of high-fidelity intermediate state measurement and reset operations), dynamic quantum circuits that include intermediate measurements and reset operations of quantum circuits have received increasing attention from the industry. Due to the introduction of intermediate measurements of circuits, dynamic quantum circuits can effectively combine quantum computing with real-time classical computing and communication within the coherence time of quantum bits. This feature greatly increases the diversity of computing tasks that can be achieved through quantum circuit models. For example, using intermediate measurements of dynamic quantum circuits, it is possible to implement forward feedback operations during circuit operation, that is, to determine which quantum gate to act on next based on the results obtained from the intermediate measurements, or to discard the current calculation results and restart the calculation task. Such functions are very important in quantum error correction and fault-tolerant quantum computing. Therefore, it is foreseeable that dynamic quantum circuits will become an important part of various quantum algorithms and quantum applications in the future.

[0039] Since the qubits in a dynamic quantum circuit can be reset and continue to be used in subsequent calculations, compared with a static quantum circuit, when running the same quantum algorithm, a dynamic quantum circuit can effectively reduce the number of qubits required for a computing task, and in theory, computing power is not affected in any way. For example, the Bernstein-Vazirani algorithm, which requires n qubits in a static circuit, can be implemented with only 2 qubits in a dynamic quantum circuit.

[0040] Limited by computer memory and processor capabilities, existing quantum circuit simulation methods can only support algorithms that simulate dozens of qubits at most. For example, a laptop can simulate about 20-30 qubits, and a large supercomputer and cluster can simulate up to 30-40 qubits. In real machine operation, the scalability problem of current quantum chips has not yet been solved, resulting in a very limited number of qubits that a quantum computer can provide. Therefore, quantum circuit optimization is a fundamental issue in the field of quantum computing.

[0041] Quantum circuit optimization is a process that uses certain technical means to compile a given quantum circuit into a dynamic quantum circuit to reduce the number of quantum bits. This can lower the requirements for classical simulation and real machine operation, and accelerate the research of quantum algorithms and the implementation of quantum computing in practical scenarios.

[0042] In this embodiment, by compiling the cyclic entangled quantum circuit, i.e., the strongly entangled quantum circuit, the original quantum circuit can be greatly simplified in terms of the number of quantum bits. On the one hand, it can further improve the scale of classical simulation of quantum algorithms and enhance the verification capability of classical computers for quantum algorithms. On the other hand, it can also reduce the bit number requirements for quantum algorithms running on real machines, making up for the current lack of scalability issues in quantum chips. Circular entangled quantum circuits are very important in the use scenarios of quantum machine learning.

[0043] The quantum circuit model is introduced in detail below.

[0044] At present, quantum computing can be implemented based on the quantum circuit model, that is, a series of quantum gates are applied to the quantum bits to complete the evolution of the quantum state, and quantum measurements are performed at the end of the circuit to obtain the calculation results. The quantum circuit diagram can represent the entire process of quantum circuit model calculation.

[0045] Figure 2 This is a schematic diagram of the structure of an example quantum circuit. Figure 2 As shown, a quantum bit system can be represented by a horizontal line, and the quantum bits of the quantum bits are numbered from top to bottom, where the quantum bit numbers often start from zero.

[0046] The direction of time evolution in the quantum circuit diagram is from left to right. The leftmost end is the initial quantum state, where each quantum bit is usually initialized to the zero state, and then different quantum gate operations are applied to the initial state in sequence to complete the evolution of the quantum state. At the same time, quantum measurements can be performed on certain quantum bits to obtain measurement results.

[0047] If a quantum circuit does not contain operations such as reset and intermediate quantum measurement, and all measurement operations are located at the very end of the quantum circuit, then such a quantum circuit is called a static quantum circuit, such as Figure 2The quantum circuit shown is a static quantum circuit.

[0048] The operations in a quantum circuit diagram can usually be represented by an ordered instruction list in the order of action, where each element in the instruction list represents an operation instruction.

[0049] Each quantum state preparation (or initialization) operation is represented by a four-element instruction [Reset, qubit, None, None]. For example, [Reset, 2, None, None] means initializing the quantum bit of qubit 2 to the zero state.

[0050] Each single-bit quantum gate (such as H, X, Y, Z, S, T, Rx, Ry, Rz, etc.) is represented by an operation instruction containing four elements [name, qubit, parameter, condition], where name is the name of the quantum gate, qubit is the quantum bit acted on by the quantum gate, parameter is the parameter of the quantum gate (if there is no parameter, the default is None), and condition indicates which quantum bit measurement result controls the quantum gate operation (the default parameter in the standard quantum circuit is None). For example, [Rx, 2, pi, None] means to act on the quantum bit on quantum bit 2 with an Rx rotation gate, and the rotation angle is pi.

[0051] Each two-bit quantum gate (such as controlled NOT gate CNOT, SWAP gate) is represented by an instruction containing four elements [name, qubit, parameter, condition]. Among them, name is the name of the quantum gate, qubit is a list of control bits and controlled bits, parameter is the parameter of the quantum gate (if there is no parameter, the default is None), and the condition parameter in the standard quantum circuit defaults to None. For example, [SWAP, [1,2], None, None] means to apply a SWAP gate between qubits 1 and 2; [CNOT, [1,3], None, None] means to apply a controlled NOT gate to qubits 1 and 3, where qubit 1 is the control bit and qubit 3 is the controlled bit.

[0052] More generally, each multi-qubit gate (such as a CCX gate) is represented by an instruction containing four elements: [name, qubit, parameter, condition]. Name is the name of the quantum gate, qubit is a list of qubits that the multi-qubit gate acts on, parameter is the parameter of the quantum gate (if there is no parameter, the default is None), and condition indicates which qubit measurement result controls the quantum gate operation (if there is no parameter, the default is None).

[0053] Each computational basis measurement is represented by a four-element instruction [measure, qubit, None, None]. For example, [measure, 2, None, None] represents a computational basis measurement on qubit 2.

[0054] According to the above instruction expression rules, Figure 2 The static quantum circuit in can be represented as the following ordered list of instructions: static_circuit = [[Reset,0,None,None],[Reset,1,None,None],[Reset,2,None,None],[H,0,None,None],[H,1,None,None],[H,2,None,None],[CNOT,[0,1],None,None],[SWAP,[1,2],None,None],[Rx,0,α,None],[Ry,1,β,None],[Rz,2,γ,None],[Measure,0,None,None],[Measure,1,None,None],[Measure,2,None,None]].

[0055] In some application scenarios, it is possible to measure some qubits in the middle of a quantum circuit, and reset them to the |0> state after the measurement results are obtained for subsequent calculations. A quantum circuit that includes measurements and reset operations in the middle of the circuit is called a dynamic quantum circuit.

[0056] The static quantum circuit can be compiled into a dynamic quantum circuit through quantum circuit optimization, for example Figure 3 The static quantum circuit shown is equivalent to compiling to Figure 4 As shown in the dynamic quantum circuit, it can be seen that the number of quantum bits in the dynamic quantum circuit is reduced by one compared to the original static quantum circuit, but the operating effects of the two quantum circuits are equivalent.

[0057] The instruction list of the original static quantum circuit is: static_circuit = [[Reset,0,None,None],[Reset,1,None,None],[Reset,2,None,None],[H,0,None,None],[H,1,None,None],[H,2,None,None],[CNOT,[0,1],None,None],[CNOT,[1,2],None,None],[Measure,0,None,None],[Measure,1,None,None],[Measure,2,None,None]]. The instruction list of the compiled dynamic quantum circuit is: dynamic_circuit = [[Reset,0,None,None],[Reset,1,None,None],[H,0,None,None],[H,1,None,None],[CNOT,[0,1],None,None],[Measure,0,None,None],[Reset,0,None,None],[H,0,None,None],[CNOT,[1,0],None,None],[Measure,0,None,None],[Measure,1,None,None]].

[0058] The purpose of this embodiment is to compile a given static quantum circuit into its equivalent dynamic quantum circuit, and minimize the number of quantum bits required for the compiled quantum circuit.

[0059] In step S101, the first quantum circuit may be a static quantum circuit, and the first quantum circuit is a quantum circuit of a strongly entangled structure, which is called a strongly entangled quantum circuit, or a cyclic entangled quantum circuit. A cyclic entangled quantum circuit is a quantum circuit widely used in quantum machine learning, and the first quantum circuit may include L strongly entangled layers (also referred to as cyclic entangled layers), and the strongly entangled structure of each strongly entangled layer is the same, that is, in the strongly entangled layer, the quantum bit of quantum bit j and the quantum bit of quantum bit j+1 are entangled in sequence through the first double quantum bit gate in the order of j from small to large, and the quantum bit of quantum bit N-1 and the quantum bit of quantum bit 0 are entangled through the second double quantum bit gate, and the second double quantum bit gate is located at the end of the quantum state time evolution direction in the strongly entangled layer, and the value range of j is [0, N-2].

[0060] For example, for a cyclic entangled quantum circuit containing N qubits and L layers of circuits, for each layer of subcircuit, the structure is that starting from the qubit of qubit 0, the first two-qubit gate is applied to the qubit of qubit j and the qubit of qubit j+1 in sequence; then, the second two-qubit gate is applied to the qubit of qubit N-1 and the qubit of qubit 0. The first two-qubit gate and the second two-qubit gate can be CNOT gates, SWAP gates, or other two-qubit gates.

[0061] Figure 5 This is a schematic diagram of the structure of an example of a circular entangled quantum circuit. Figure 5 As shown, the cyclic entangled quantum circuit contains 4 quantum bits and two strongly entangled layers. Each line in the dotted box is a strongly entangled layer, and the entire quantum circuit needs to be repeated twice according to the strongly entangled structure in the dotted box.

[0062] The first instruction list for the first quantum circuit may be obtained by pre-stored means, or by user input means, or by the first instruction list for the first quantum circuit based on an instruction list of a third quantum circuit equivalent to the first quantum circuit, without specific limitation here.

[0063] Step S102: when N is greater than or equal to 4 and L is equal to 1, based on the first instruction list, the first quantum circuit is equivalently compiled to obtain a second instruction list for a second quantum circuit equivalent to the first quantum circuit; wherein the number of quantum bits of the second quantum circuit is less than the number of quantum bits of the first quantum circuit, and the equivalent compilation includes: adding a first reset operation instruction after the first measurement operation instruction in the first instruction list; and remapping each target operation instruction in the first instruction list to the quantum bit of quantum bit i, the first measurement operation instruction and the first reset operation instruction both act on quantum bit i, and the target operation instruction acts on quantum bit i+2, and the value range of i is [1, N-3].

[0064] In this step, the second quantum circuit may be a dynamic quantum circuit.

[0065] When performing equivalent compilation, the first measurement operation instructions in the first instruction list can be obtained in sequence, and for each first measurement operation instruction, based on the qubit i acted on by the first measurement operation instruction, the first reset operation instruction on the qubit i is added after the first measurement operation instruction, and each target operation instruction in the first instruction list is remapped to the qubit of qubit i. The first measurement operation instructions are measurement operation instructions acting on qubit 1, qubit 2..., qubit N-3.

[0066] If N is 4 and L is 1, the first measurement operation instruction is a measurement operation instruction acting on qubit 1. That is, during equivalent compilation, a reset operation instruction on qubit 1 is added after the measurement operation instruction on qubit 1, and the target operation instruction acting on qubit 3 in the first instruction list is remapped to the qubit of qubit 1, thereby obtaining a second instruction list of a second quantum circuit equivalent to the first quantum circuit.

[0067] If N is 5 and L is 1, the first measurement operation instruction is a measurement operation instruction acting on qubit 1 and qubit 2, respectively. That is, during equivalent compilation, first for the measurement operation instruction on qubit 1, add a reset operation instruction on qubit 1 after the measurement operation instruction on qubit 1, and remap the target operation instruction acting on qubit 3 in the first instruction list to the qubit of qubit 1. Then for the measurement operation instruction on qubit 2, add a reset operation instruction on qubit 2 after the measurement operation instruction on qubit 2, and remap the target operation instruction acting on qubit 4 in the first instruction list to the qubit of qubit 2, so that the second instruction list of the second quantum circuit equivalent to the first quantum circuit can be obtained.

[0068] In this way, after the operation instructions of the quantum measurement operation are equivalently compiled, the operation instructions of the reset operation can be added after the operation instructions of the quantum measurement operation. Through the reset operation instructions, the register unit allocated to quantum bit i can be recycled for continued use by the quantum bit of quantum bit i+2, so as to reduce the number of quantum bits of the compiled second quantum circuit.

[0069] In an optional implementation, the equivalent compilation of the first quantum circuit can be directly performed based on the first instruction list, that is, by traversing the first instruction list, the first measurement operation instruction and the target operation instruction are respectively obtained, and the equivalent compilation of the first quantum circuit is performed. In another optional implementation, a directed acyclic graph can be constructed based on the first instruction list, and the equivalent compilation of the first quantum circuit is performed based on the directed acyclic graph.

[0070] In the related art, heuristic algorithms are usually used for quantum circuit compilation, which cannot guarantee the optimality of circuit compilation. If the optimal compilation scheme is given through mathematical modeling of circuit compilation, the algorithm complexity increases exponentially with the number of quantum bits, and the efficiency of large-scale circuit compilation is very low. In this embodiment, in view of the structural particularity of the cyclic entangled quantum circuit, when the number of layers L of the strong entanglement layer is 1 and the circuit width N≥4, the quantum bit of quantum bit i can be reset after measurement, and all operation instructions acting on the quantum bit of quantum bit i+2 can be remapped to the quantum bit of quantum bit i for execution. This rule is obtained by theoretical proof based on circuit structure.

[0071] In terms of time complexity, since this embodiment does not need to build a complex mathematical model, the compilation process is simple, and the running time can grow linearly with N and L, and the compilation is very efficient. In terms of compilation effect, if a cyclic entangled quantum circuit can be compiled, the compiled dynamic quantum circuit will only need 3 quantum bits. It can be theoretically proved that the compilation scheme in this embodiment is the optimal compilation scheme, that is, it is impossible to have a compilation scheme that makes the compiled circuit width less than 3. In this way, this embodiment provides an optimal compilation method for cyclic entangled quantum circuits, which can be directly applied to corresponding scenarios without complex calculations and optimizations.

[0072] Moreover, quantum computers based on different architecture designs can provide different numbers of quantum bits and the ability to implement various operations. Through equivalent compilation, the operation scheme of quantum circuits on real quantum computers can be made more flexible, and dynamic quantum circuits and static quantum circuits can be flexibly selected according to actual hardware conditions. For example, for superconducting quantum computers with short coherence time but easy to expand the number of quantum bits, it is more suitable to run static quantum circuits with larger width and smaller depth; while for quantum computers based on ion trap architecture with longer coherence time but relatively poor scalability, it is more suitable to run dynamic quantum circuits with smaller width and larger depth.

[0073] Optionally, the method further includes:

[0074] When N is less than or equal to 3, or L is greater than or equal to 2, target information is output, where the target information indicates that the first quantum circuit cannot be equivalently compiled into the second quantum circuit.

[0075] The equivalent compilation of a quantum circuit essentially resets the measured qubits for subsequent quantum instruction operations. Based on the structure of a cyclic entangled quantum circuit, when N≤3 or L≥2, the quantum circuit cannot be further compiled into a dynamic quantum circuit with fewer qubits. At this point, the instruction list of the original quantum circuit can be output. In this way, the compilability of a cyclic entangled quantum circuit can be efficiently determined.

[0076] Optionally, the first quantum circuit further includes at least one single-qubit gate, and the single-qubit gate is located at any position of the first quantum circuit.

[0077] The equivalent compilation process in this embodiment is independent of information such as the number, type, and specific execution location of single-qubit gates. Therefore, the first quantum circuit in this embodiment can also include single-qubit gates while ensuring that it is a strongly entangled structure.

[0078] Figure 6is a schematic diagram of the structure of another example of a loop entangled quantum circuit, such as Figure 6 As shown, it can be Figure 5 Add a single-qubit gate to any position of the quantum circuit shown, or replace the CNOT gate with other two-qubit gates. As long as the two-qubit gates of the quantum circuit satisfy the strong entanglement structure, the quantum circuit is a cyclic entangled quantum circuit.

[0079] for Figure 6 The circuit instruction list of the cyclic entangled quantum circuit shown is static_circuit = [[Reset,0,None,None],[Reset,1,None,None],[Reset,2,None,None],[Reset,3,None,None],[H,0,None,None],[S,1,None,None],[T,2,None,None],[H,3,None,None],[CNOT,[1,0],None,None],[CNOT,[1, 2],None,None],[CNOT,[2,3],None,None],[Rz,2,0.1,None],[Rx,3,0.5,None],[CNOT,[3,0],None,None],[H,0,None,None ],[H,1,None,None],[Measure,0,None,None],[Measure,1,None,None],[Measure,2,None,None],[Measure,3,None,None]].

[0080] In this way, the application scope of the original quantum circuit processed by the quantum circuit can be expanded.

[0081] Optionally, the step S102 specifically includes:

[0082] Based on the first instruction list, determining a first directed acyclic graph, wherein the first directed acyclic graph includes nodes corresponding to the operation instructions in the first instruction list and first directed edges, wherein the first directed edges are used to represent a timing relationship between different operation instructions in the first instruction list;

[0083] Adding a second directed edge to the first directed acyclic graph to obtain a directed edge list consisting of the second directed acyclic graph and the second directed edge, wherein the second directed edge includes a directed edge from an output node corresponding to the first measurement operation instruction to an input node corresponding to a second reset operation instruction, and the second reset operation instruction is a reset operation instruction acting on quantum bit i+2;

[0084] Based on the second directed acyclic graph and the directed edge list, the first quantum circuit is equivalently compiled to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit.

[0085] In an optional implementation, the first instruction list may be traversed in the order of instruction arrangement from left to right, and a first directed acyclic graph may be constructed by searching for nearest neighbor operation instructions whose acted qubits intersect with the qubits acted upon by the currently traversed operation instruction.

[0086] In another optional implementation, optionally, determining a first directed acyclic graph based on the first instruction list includes:

[0087] Traversing the first instruction list according to the arrangement order of the operation instructions;

[0088] Take the currently traversed operation instruction as a node, and if the target list is not an empty list, add the node corresponding to the operation instruction at the end of the target list to the first directed edge of the node corresponding to the currently traversed operation instruction; the target list is a list corresponding to the qubits acted upon by the currently traversed operation instruction;

[0089] The currently traversed operation instruction is added to the end of the target list, and the first directed acyclic graph is obtained when the traversal of the first instruction list is completed.

[0090] That is, by constructing N target lists corresponding to N quantum bits one by one, the preceding operation instructions of the currently traversed operation instructions are stored. Based on the quantum bit acted upon by the currently traversed operation instruction, the target list corresponding to the quantum bit is obtained, and the quantum bits acted upon by the operation instructions in the target list all have intersections with the quantum bits acted upon by the currently traversed operation instruction. The operation instruction with the nearest neighbor, that is, the operation instruction at the end of the target list, is selected to construct the first directed edge. In this way, the construction process of the first directed acyclic graph can be simplified, and the efficient construction of the first directed acyclic graph can be achieved.

[0091] Further, a second directed edge is added to the first directed acyclic graph to obtain a directed edge list consisting of the second directed acyclic graph and the second directed edge, wherein the second directed edge includes a directed edge from the output node corresponding to the first measurement operation instruction to the input node corresponding to the second reset operation instruction, and the second reset operation instruction is a reset operation instruction acting on quantum bit i+2. For example, if N is 4 and L is 1, the second directed edge is a directed edge from the node corresponding to the measurement operation instruction acting on quantum bit 1 to the node corresponding to the reset operation instruction acting on quantum bit 3. For another example, if N is 5 and L is 1, the second directed edge includes: a directed edge from the node corresponding to the measurement operation instruction acting on quantum bit 1 to the node corresponding to the reset operation instruction acting on quantum bit 3, and a directed edge from the node corresponding to the measurement operation instruction acting on quantum bit 2 to the node corresponding to the reset operation instruction acting on quantum bit 4.

[0092] Then, based on the second directed acyclic graph and the directed edge list, the first quantum circuit is equivalently compiled to obtain a second instruction list of the second quantum circuit equivalent to the first quantum circuit. Optionally, based on the second directed acyclic graph and the directed edge list, the first quantum circuit is equivalently compiled to obtain a second instruction list of the second quantum circuit equivalent to the first quantum circuit, including:

[0093] Obtaining a topological sort of operation instructions corresponding to the second directed acyclic graph to obtain a third instruction list;

[0094] For each of the second directed edges in the directed edge list, each target operation instruction corresponding to the quantum bit acted upon by the input node of the second directed edge in the third instruction list is remapped to the quantum bit acted upon by the output node of the second directed edge to obtain the second instruction list.

[0095] The optimal compilation process of the cyclic entangled quantum circuit is as follows:

[0096] Input: the first instruction list of the cyclic entangled quantum circuit circuit_list, circuit width N ≥ 2, number of strong entanglement layers L ≥ 1;

[0097] Output: The second instruction list of the compiled dynamic quantum circuit.

[0098] Step 1: If N≤3 or L≥2, return the original circuit instruction list circuit_list as output;

[0099] Step 2: Initialize an empty directed acyclic graph digraph;

[0100] Step 3: Initialize a target list causal_lists of length N, where each element is an empty list;

[0101] Step 4: Loop through circuit_list, setting the currently looped element to instruction:

[0102] Step 4.1: Take out the qubit value in the instruction and loop it. Let the looped element be q. Add instruction as a node to the directed acyclic graph digraph. Find the last element of the target list causal_lists[q] and record it as preinstruction. If preinstruction is not an empty element, add the first directed edge from preinstruction to instruction to the directed acyclic graph digraph. Add instruction to the end of the list causal_lists[q].

[0103] Step 5: Initialize an empty list added_edges (i.e. directed edge list);

[0104] Step 6: Loop over the variable i∈{1,···,N-3}:

[0105] Step 6.1: Add a second directed edge to the directed acyclic graph digraph, from the measure operation on qubit i to the reset operation on qubit i+2, and add the directed edge to the added_edges list;

[0106] Step 7: Obtain the topological sorting of all circuit instructions according to the directed acyclic graph digraph and record them in circuit_list;

[0107] Step 8: Loop through the added_edges list and set the variable of the current loop to edge:

[0108] Step 8.1: Let preinstruction and postinstruction represent the output node and input node of the directed edge edge respectively;

[0109] Step 8.2: Note that the qubits acted on by the two operation instructions preinstruction and postinstruction are prequbit and postqubit respectively; loop through the circuit_list list and update all target operation instructions acting on the qubit postqubit to act on the qubit prequbit;

[0110] Step 9: Return circuit_list as output.

[0111] In this way, the equivalent compilation of cyclic entangled quantum circuits can be achieved with the help of directed acyclic graphs, and the implementation process is very simple.

[0112] for Figure 6 The quantum circuit in the example is compiled by the scheme in this embodiment to obtain the dynamic quantum circuit: Figure 7 As shown, the corresponding circuit instruction list is: dynamic_circuit = [[Reset,0,None,None],[Reset,1,None,None],[Reset,2,None,None],[H,0,None,None],[S,1,None,None],[T,2,None,None],[CNOT,[1,0],None,None],[CNOT,[1,2],None,None],[H,1,None,None],[Measure, 1,None,None],[Reset,1,None,None],[H,1,None,None],[CNOT,[2,1],None,None],[Rx,1,0.5,None],[Rz,2,0.1,None],[CNOT,[1,0],None,None],[H,0,None,None],[Measure,0,None,None],[Measure,1,None,None],[Measure,2,None,None]]. The number of quantum bits of its dynamic quantum circuit is 3, which is the optimal compilation scheme.

[0113] Optionally, the step S101 specifically includes:

[0114] adding a reset operation instruction for each quantum bit in the first quantum circuit to a circuit list;

[0115] For each strongly entangled layer in the first quantum circuit, add the operation instructions of each first two-qubit gate between the qubit of qubit j and the qubit of qubit j+1 in the strongly entangled layer to the circuit list in order from small to large j; and when the operation instructions of the first two-qubit gate in the strongly entangled layer are added, add the operation instructions of the second two-qubit gate between the qubit of qubit N-1 and the qubit of qubit 0 in the strongly entangled layer to the circuit list;

[0116] Add the quantum measurement operation instruction of each quantum bit in the first quantum circuit to the circuit list to obtain the first instruction list.

[0117] The specific process of obtaining the circuit instruction list of a cyclic entangled quantum circuit containing N quantum bits and L layers of circuits is as follows:

[0118] Input: quantum circuit width N, number of strongly entangled layers L;

[0119] Output: Instruction list of the cyclic entangled quantum circuit.

[0120] Step 1: Initialize an empty list circuit_list;

[0121] Step 2: Loop over the variable i∈{0,1,···,N-1}:

[0122] Step 2.1: Add the reset operation instruction [Reset,i,None,None] to the end of the list circuit_list;

[0123] Step 3: Loop over the variable k∈{0,1,···,L-1}:

[0124] Step 3.1: Loop over the variable i∈{0,1,···,N-2}; add the operation instruction of the first two-qubit gate, such as [CNOT,[i,i+1],None,None], to the end of the list circuit_list;

[0125] Step 3.2: Add the operation instructions of the second two-qubit gate, such as [CNOT, [N-1, 0], None, None], to the end of the list circuit_list;

[0126] Step 4: Loop over the variable i∈{0,1,···,N-1}:

[0127] Step 4.1: Add the circuit instruction [Measure,i,None,None] to the end of the list circuit_list;

[0128] Step 5: Return circuit_list as output.

[0129] In this way, the first instruction list of the cyclic entangled quantum circuit can be obtained by inputting the structural information of the cyclic entangled quantum circuit, and the process is simple. By inputting the circuit width N as 4 and the number of layers L of the strong entanglement layer as 2, the following can be generated: Figure 5The first instruction list of the cyclic entangled quantum circuit shown is static_circuit=[[Reset,0,None,None],[Reset,1,None,None],[Reset,2,None,None],[Reset,3,None,None],[CNOT,[0,1],None,None],[CNOT,[1,2],None,None],[CNOT,[2,3],None,None],[CNOT,[3,0],None,None],[CNOT,[0,1],None,None],[CNOT,[1,2],None,None],[CNOT,[2,3],None,None],[CNOT,[3,0],None,None],[Measure,0,None,None],[Measure,1,None,None],[Measure,2,None,None]].

[0130] Optionally, before step S101, the method further includes:

[0131] Performing a permutation mapping on a third quantum circuit including N quantum bits to sequentially arrange the N quantum bits in the third quantum circuit from the quantum bit of quantum bit 0 to the quantum bit of quantum bit N-1;

[0132] When the third quantum circuit after permutation mapping is a quantum circuit of a strongly entangled structure, it is determined that the third quantum circuit is equivalent to the first quantum circuit.

[0133] The third quantum circuit that is not a standard quantum circuit can be converted into a standard quantum circuit. If the standard quantum circuit obtained after the conversion is a quantum circuit with a strongly entangled structure, it indicates that the third quantum circuit is equivalent to the first quantum circuit. In the standard quantum circuit, the N quantum bits are arranged in order from the quantum bit of quantum bit 0 to the quantum bit of quantum bit N-1.

[0134] In this way, the application scope of the original quantum circuit processed by the quantum circuit can be expanded.

[0135] Optionally, when the third quantum circuit after permutation mapping is a quantum circuit of a strongly entangled structure, step S101 specifically includes:

[0136] Obtaining a fourth instruction list of the third quantum circuit;

[0137] Permuting the first number list of N quantum bits in the third quantum circuit to obtain a second number list, wherein the second number list is sequentially arranged from the quantum bit of quantum bit 0 to the quantum bit of quantum bit N-1;

[0138] Based on the mapping relationship between the first number list and the second number list, the qubits acted upon by the operation instructions in the fourth instruction list are transformed to obtain the first instruction list.

[0139] Among them, the first number list of N quantum bits in the third quantum circuit can be permuted based on a permutation matrix to obtain a second number list, and the permutation matrix can be input or preset by a user. Afterwards, based on the mapping relationship between the first number list and the second number list, for example, quantum bit 2 in the third quantum circuit is mapped to quantum bit 0 in the first quantum circuit, the quantum bits acted on by the operation instructions in the fourth instruction list can be transformed, such as remapping the operation instructions acting on quantum bit 2 in the fourth instruction list to quantum bit 0, so as to obtain the first instruction list of the first quantum circuit.

[0140] In this way, the instruction list of the first quantum circuit can be acquired based on the instruction list of the third quantum circuit equivalent to the first quantum circuit.

[0141] Second embodiment

[0142] like Figure 8 As shown, the present disclosure provides a quantum circuit processing device 800, comprising:

[0143] An acquisition module 801 is used to acquire a first instruction list of a first quantum circuit including N quantum bits, wherein the first quantum circuit is a quantum circuit of a strongly entangled structure, and the first quantum circuit includes L strongly entangled layers, wherein the N quantum bits in the first quantum circuit are sequentially arranged from the quantum bit of quantum bit 0 to the quantum bit of quantum bit N-1, and in the strongly entangled layer, the quantum bit of quantum bit j and the quantum bit of quantum bit j+1 are sequentially entangled through a first double quantum bit gate in order of j from small to large, and the quantum bit of quantum bit N-1 and the quantum bit of quantum bit 0 are entangled through a second double quantum bit gate, and the second double quantum bit gate is located at the end of the quantum state time evolution direction in the strongly entangled layer, and the value range of j is [0, N-2], N is an integer greater than 2, and L is a positive integer;

[0144] an equivalent compiling module 802, configured to perform equivalent compiling on the first quantum circuit based on the first instruction list to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit when N is greater than or equal to 4 and L is equal to 1;

[0145] Among them, the number of quantum bits of the second quantum circuit is less than the number of quantum bits of the first quantum circuit, and the equivalent compilation includes: adding a first reset operation instruction after the first measurement operation instruction in the first instruction list; and remapping each target operation instruction in the first instruction list to the quantum bit of quantum bit i, the first measurement operation instruction and the first reset operation instruction both act on quantum bit i, and the target operation instruction acts on quantum bit i+2, and the value range of i is [1, N-3].

[0146] Optionally, the equivalent compilation module 802 includes:

[0147] A determining unit, configured to determine a first directed acyclic graph based on the first instruction list, wherein the first directed acyclic graph includes nodes corresponding to the operation instructions in the first instruction list and first directed edges, wherein the first directed edges are used to represent a timing relationship between different operation instructions in the first instruction list;

[0148] an adding unit, configured to add a second directed edge to the first directed acyclic graph, to obtain a directed edge list consisting of the second directed acyclic graph and the second directed edge, wherein the second directed edge includes a directed edge from an output node corresponding to the first measurement operation instruction to an input node corresponding to a second reset operation instruction, and the second reset operation instruction is a reset operation instruction acting on quantum bit i+2;

[0149] An equivalent compilation unit is used to perform equivalent compilation on the first quantum circuit based on the second directed acyclic graph and the directed edge list to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit.

[0150] Optionally, the determining unit is specifically configured to:

[0151] Traversing the first instruction list according to the arrangement order of the operation instructions;

[0152] Take the currently traversed operation instruction as a node, and if the target list is not an empty list, add the node corresponding to the operation instruction at the end of the target list to the first directed edge of the node corresponding to the currently traversed operation instruction; the target list is a list corresponding to the qubits acted upon by the currently traversed operation instruction;

[0153] The currently traversed operation instruction is added to the end of the target list, and the first directed acyclic graph is obtained when the traversal of the first instruction list is completed.

[0154] Optionally, the equivalent compilation unit is specifically used for:

[0155] Obtaining a topological sort of operation instructions corresponding to the second directed acyclic graph to obtain a third instruction list;

[0156] For each of the second directed edges in the directed edge list, each target operation instruction corresponding to the quantum bit acted upon by the input node of the second directed edge in the third instruction list is remapped to the quantum bit acted upon by the output node of the second directed edge to obtain the second instruction list.

[0157] Optionally, the acquisition module 801 is specifically used to:

[0158] adding a reset operation instruction for each quantum bit in the first quantum circuit to a circuit list;

[0159] For each strongly entangled layer in the first quantum circuit, add the operation instructions of each first two-qubit gate between the qubit of qubit j and the qubit of qubit j+1 in the strongly entangled layer to the circuit list in order from small to large j; and when the operation instructions of the first two-qubit gate in the strongly entangled layer are added, add the operation instructions of the second two-qubit gate between the qubit of qubit N-1 and the qubit of qubit 0 in the strongly entangled layer to the circuit list;

[0160] Add the quantum measurement operation instruction of each quantum bit in the first quantum circuit to the circuit list to obtain the first instruction list.

[0161] Optionally, the device further comprises:

[0162] A permutation mapping module, used to perform permutation mapping on a third quantum circuit including N quantum bits, so as to arrange the N quantum bits in the third quantum circuit in order from the quantum bit of quantum bit 0 to the quantum bit of quantum bit N-1;

[0163] A determination module is used to determine that the third quantum circuit is equivalent to the first quantum circuit when the third quantum circuit after permutation mapping is a quantum circuit of a strongly entangled structure.

[0164] Optionally, the acquisition module 801 is specifically used to:

[0165] When the third quantum circuit after permutation mapping is a quantum circuit of a strongly entangled structure, obtaining a fourth instruction list of the third quantum circuit;

[0166] Permuting the first number list of N quantum bits in the third quantum circuit to obtain a second number list, wherein the second number list is sequentially arranged from the quantum bit of quantum bit 0 to the quantum bit of quantum bit N-1;

[0167] Based on the mapping relationship between the first number list and the second number list, the qubits acted upon by the operation instructions in the fourth instruction list are transformed to obtain the first instruction list.

[0168] Optionally, the first quantum circuit further includes at least one single-qubit gate, and the single-qubit gate is located at any position of the first quantum circuit.

[0169] Optionally, the device further comprises:

[0170] An output module is used to output target information when N is less than or equal to 3, or when L is greater than or equal to 2, wherein the target information indicates that the first quantum circuit cannot be equivalently compiled into the second quantum circuit.

[0171] The quantum circuit processing device 800 provided in the present disclosure can implement each process implemented in the quantum circuit processing method embodiment and can achieve the same beneficial effects. To avoid repetition, it will not be described here.

[0172] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0173] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

[0174] Fig. 9 A schematic block diagram of an example electronic device that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0175] like Fig. 9As shown, the device 900 includes a computing unit 901, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 902 or a computer program loaded from a storage unit 908 into a random access memory (RAM) 903. In the RAM 903, various programs and data required for the operation of the device 900 can also be stored. The computing unit 901, the ROM 902, and the RAM 903 are connected to each other via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0176] A number of components in the device 900 are connected to the I / O interface 905, including: an input unit 906, such as a keyboard, a mouse, etc.; an output unit 907, such as various types of displays, speakers, etc.; a storage unit 908, such as a disk, an optical disk, etc.; and a communication unit 909, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 909 allows the device 900 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0177] The computing unit 901 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 901 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 901 performs the various methods and processes described above, such as the quantum circuit processing method. For example, in some embodiments, the quantum circuit processing method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 908. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 900 via the ROM 902 and / or the communication unit 909. When the computer program is loaded into the RAM 903 and executed by the computing unit 901, one or more steps of the quantum circuit processing method described above may be performed. Alternatively, in other embodiments, the computing unit 901 may be configured to perform the quantum circuit processing method in any other appropriate manner (e.g., by means of firmware).

[0178] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0179] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0180] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0181] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0182] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0183] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0184] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0185] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A quantum circuit processing method, comprising: Obtain a first instruction list of a first quantum circuit including N quantum bits, wherein the first quantum circuit is a quantum circuit of a strongly entangled structure, and the first quantum circuit includes L strongly entangled layers, wherein the N quantum bits in the first quantum circuit are sequentially arranged from the quantum bit of quantum bit 0 to the quantum bit of quantum bit N-1, and in the strongly entangled layer, the quantum bit of quantum bit j and the quantum bit of quantum bit j+1 are sequentially entangled through a first double quantum bit gate in order of j from small to large, and the quantum bit of quantum bit N-1 and the quantum bit of quantum bit 0 are entangled through a second double quantum bit gate, and the second double quantum bit gate is located at the end of the quantum state time evolution direction in the strongly entangled layer, and the value range of j is [0, N-2], N is an integer greater than 2, and L is a positive integer; When N is greater than or equal to 4 and L is equal to 1, based on the first instruction list, equivalently compile the first quantum circuit to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit; Among them, the number of quantum bits of the second quantum circuit is less than the number of quantum bits of the first quantum circuit, and the equivalent compilation includes: adding a first reset operation instruction after the first measurement operation instruction in the first instruction list; and remapping each target operation instruction in the first instruction list to the quantum bit of quantum bit i, the first measurement operation instruction and the first reset operation instruction both act on quantum bit i, and the target operation instruction acts on quantum bit i+2, and the value range of i is [1, N-3].

2. The method according to claim 1, wherein: The step of performing equivalent compilation on the first quantum circuit based on the first instruction list to obtain a second instruction list for a second quantum circuit equivalent to the first quantum circuit includes: Based on the first instruction list, determining a first directed acyclic graph, wherein the first directed acyclic graph includes nodes corresponding to the operation instructions in the first instruction list and first directed edges, wherein the first directed edges are used to represent a timing relationship between different operation instructions in the first instruction list; Adding a second directed edge to the first directed acyclic graph to obtain a directed edge list consisting of the second directed acyclic graph and the second directed edge, wherein the second directed edge includes a directed edge from an output node corresponding to the first measurement operation instruction to an input node corresponding to a second reset operation instruction, and the second reset operation instruction is a reset operation instruction acting on quantum bit i+2; Based on the second directed acyclic graph and the directed edge list, the first quantum circuit is equivalently compiled to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit.

3. The method according to claim 2, wherein: Determining a first directed acyclic graph based on the first instruction list includes: Traversing the first instruction list according to the arrangement order of the operation instructions; Take the currently traversed operation instruction as a node, and if the target list is not an empty list, add the node corresponding to the operation instruction at the end of the target list to the first directed edge of the node corresponding to the currently traversed operation instruction; the target list is a list corresponding to the qubits acted upon by the currently traversed operation instruction; The currently traversed operation instruction is added to the end of the target list, and the first directed acyclic graph is obtained when the traversal of the first instruction list is completed.

4. The method according to claim 2, wherein: The equivalent compilation of the first quantum circuit based on the second directed acyclic graph and the directed edge list to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit includes: Obtaining a topological sort of operation instructions corresponding to the second directed acyclic graph to obtain a third instruction list; For each of the second directed edges in the directed edge list, each target operation instruction corresponding to the quantum bit acted upon by the input node of the second directed edge in the third instruction list is remapped to the quantum bit acted upon by the output node of the second directed edge to obtain the second instruction list.

5. The method according to claim 1, wherein: The obtaining of a first instruction list of a first quantum circuit including N quantum bits comprises: adding a reset operation instruction for each quantum bit in the first quantum circuit to an instruction list of the first quantum circuit; the instruction list of the first quantum circuit is used to add an operation instruction for the quantum bit in the first quantum circuit; For each strongly entangled layer in the first quantum circuit, add the operation instructions of each first two-qubit gate between the qubit of qubit j and the qubit of qubit j+1 in the strongly entangled layer to the instruction list of the first quantum circuit in order of j from small to large; and when the operation instructions of the first two-qubit gate in the strongly entangled layer are added, add the operation instructions of the second two-qubit gate between the qubit of qubit N-1 and the qubit of qubit 0 in the strongly entangled layer to the instruction list of the first quantum circuit; Adding the quantum measurement operation instruction of each quantum bit in the first quantum circuit to the instruction list of the first quantum circuit to obtain the first instruction list.

6. The method according to claim 1, before obtaining the first instruction list of the first quantum circuit including N quantum bits, further comprising: Performing a permutation mapping on a third quantum circuit including N quantum bits to sequentially arrange the N quantum bits in the third quantum circuit from the quantum bit of quantum bit 0 to the quantum bit of quantum bit N-1; When the third quantum circuit after permutation mapping is a quantum circuit of a strongly entangled structure, it is determined that the third quantum circuit is equivalent to the first quantum circuit.

7. The method according to claim 6, wherein: In the case where the third quantum circuit after permutation mapping is a quantum circuit of a strongly entangled structure, the step of obtaining a first instruction list of a first quantum circuit including N quantum bits includes: Obtaining a fourth instruction list of the third quantum circuit; The first number list of N quantum bits in the third quantum circuit is permuted to obtain a second number list, wherein the second number list is sequentially arranged from the quantum bit of quantum bit 0 to the quantum bit of quantum bit N-1; the first number list represents the arrangement order of the quantum bits of the N quantum bits in the third quantum circuit; Based on the mapping relationship between the first number list and the second number list, the qubits acted upon by the operation instructions in the fourth instruction list are transformed to obtain the first instruction list.

8. The method according to claim 1, wherein: The first quantum circuit also includes at least one single-qubit gate, and the single-qubit gate is located at any position of the first quantum circuit.

9. The method according to claim 1, further comprising: When N is less than or equal to 3, or L is greater than or equal to 2, target information is output, where the target information indicates that the first quantum circuit cannot be equivalently compiled into the second quantum circuit.

10. A quantum circuit processing device, comprising: An acquisition module is used to acquire a first instruction list of a first quantum circuit including N quantum bits, wherein the first quantum circuit is a quantum circuit of a strongly entangled structure, and the first quantum circuit includes L strongly entangled layers, wherein the N quantum bits in the first quantum circuit are sequentially arranged from the quantum bit of quantum bit 0 to the quantum bit of quantum bit N-1, and in the strongly entangled layer, the quantum bit of quantum bit j and the quantum bit of quantum bit j+1 are sequentially entangled through a first double quantum bit gate in order of j from small to large, and the quantum bit of quantum bit N-1 and the quantum bit of quantum bit 0 are entangled through a second double quantum bit gate, and the second double quantum bit gate is located at the end of the quantum state time evolution direction in the strongly entangled layer, and the value range of j is [0, N-2], N is an integer greater than 2, and L is a positive integer; an equivalent compiling module, configured to perform equivalent compiling on the first quantum circuit based on the first instruction list to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit when N is greater than or equal to 4 and L is equal to 1; Among them, the number of quantum bits of the second quantum circuit is less than the number of quantum bits of the first quantum circuit, and the equivalent compilation includes: adding a first reset operation instruction after the first measurement operation instruction in the first instruction list; and remapping each target operation instruction in the first instruction list to the quantum bit of quantum bit i, the first measurement operation instruction and the first reset operation instruction both act on quantum bit i, and the target operation instruction acts on quantum bit i+2, and the value range of i is [1, N-3].

11. The device according to claim 10, wherein: The equivalent compilation module includes: A determining unit, configured to determine a first directed acyclic graph based on the first instruction list, wherein the first directed acyclic graph includes nodes corresponding to the operation instructions in the first instruction list and first directed edges, wherein the first directed edges are used to represent a timing relationship between different operation instructions in the first instruction list; an adding unit, configured to add a second directed edge to the first directed acyclic graph, to obtain a directed edge list consisting of the second directed acyclic graph and the second directed edge, wherein the second directed edge includes a directed edge from an output node corresponding to the first measurement operation instruction to an input node corresponding to a second reset operation instruction, and the second reset operation instruction is a reset operation instruction acting on quantum bit i+2; An equivalent compilation unit is used to perform equivalent compilation on the first quantum circuit based on the second directed acyclic graph and the directed edge list to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit.

12. The device according to claim 11, wherein The determining unit is specifically configured to: Traversing the first instruction list according to the arrangement order of the operation instructions; Take the currently traversed operation instruction as a node, and if the target list is not an empty list, add the node corresponding to the operation instruction at the end of the target list to the first directed edge of the node corresponding to the currently traversed operation instruction; the target list is a list corresponding to the qubits acted upon by the currently traversed operation instruction; The currently traversed operation instruction is added to the end of the target list, and the first directed acyclic graph is obtained when the traversal of the first instruction list is completed.

13. The device according to claim 11, wherein: The equivalent compilation unit is specifically used for: Obtaining a topological sort of operation instructions corresponding to the second directed acyclic graph to obtain a third instruction list; For each of the second directed edges in the directed edge list, each target operation instruction corresponding to the quantum bit acted upon by the input node of the second directed edge in the third instruction list is remapped to the quantum bit acted upon by the output node of the second directed edge to obtain the second instruction list.

14. The device according to claim 10, wherein: The acquisition module is specifically used for: adding a reset operation instruction for each quantum bit in the first quantum circuit to an instruction list of the first quantum circuit; the instruction list of the first quantum circuit is used to add an operation instruction for the quantum bit in the first quantum circuit; For each strongly entangled layer in the first quantum circuit, add the operation instructions of each first two-qubit gate between the qubit of qubit j and the qubit of qubit j+1 in the strongly entangled layer to the instruction list of the first quantum circuit in order of j from small to large; and when the operation instructions of the first two-qubit gate in the strongly entangled layer are added, add the operation instructions of the second two-qubit gate between the qubit of qubit N-1 and the qubit of qubit 0 in the strongly entangled layer to the instruction list of the first quantum circuit; Adding the quantum measurement operation instruction of each quantum bit in the first quantum circuit to the instruction list of the first quantum circuit to obtain the first instruction list.

15. The apparatus according to claim 10, further comprising: A permutation mapping module, used to perform permutation mapping on a third quantum circuit including N quantum bits, so as to arrange the N quantum bits in the third quantum circuit in order from the quantum bit of quantum bit 0 to the quantum bit of quantum bit N-1; A determination module is used to determine that the third quantum circuit is equivalent to the first quantum circuit when the third quantum circuit after permutation mapping is a quantum circuit of a strongly entangled structure.

16. The device according to claim 15, wherein: The acquisition module is specifically used for: When the third quantum circuit after permutation mapping is a quantum circuit of a strongly entangled structure, obtaining a fourth instruction list of the third quantum circuit; The first number list of N quantum bits in the third quantum circuit is permuted to obtain a second number list, wherein the second number list is sequentially arranged from the quantum bit of quantum bit 0 to the quantum bit of quantum bit N-1; the first number list represents the arrangement order of the quantum bits of the N quantum bits in the third quantum circuit; Based on the mapping relationship between the first number list and the second number list, the qubits acted upon by the operation instructions in the fourth instruction list are transformed to obtain the first instruction list.

17. The device according to claim 10, wherein: The first quantum circuit also includes at least one single-qubit gate, and the single-qubit gate is located at any position of the first quantum circuit.

18. The apparatus according to claim 10, further comprising: An output module is used to output target information when N is less than or equal to 3, or when L is greater than or equal to 2, wherein the target information indicates that the first quantum circuit cannot be equivalently compiled into the second quantum circuit.

19. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 9.

20. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-9.

21. A computer program product comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 9.

Images