Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the semiconductor structure comprising: a substrate; a channel structure layer suspended above the substrate, the channel structure layer comprising one or more channel layers arranged in sequence and spaced apart in a direction perpendicular to a surface of the substrate; a gate structure located above the substrate, the gate structure crossing the channel structure layer and surrounding the channel layers, portions of the gate structure located between the substrate and adjacent channel layers and between adjacent channel layers serving as first portions, and the remaining portions serving as second portions; a gate inner sidewall located on sidewalls of the second portions, an end surface of the gate inner sidewall being vertically coplanar with the channel structure layer, and an inner sidewall of the gate inner sidewall having an arc-shaped corner at a junction of the gate inner sidewall and a top of the channel structure layer and a sidewall thereof; and a gate oxide layer located between the gate inner sidewall and the channel structure layer, and a thickness of the gate oxide layer between the gate inner sidewall and the channel structure layer being equal to that of the gate inner sidewall. Embodiments of the present application are beneficial to improving the performance of semiconductor devices.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration, and semiconductor process nodes are continuously shrinking in accordance with Moore's Law. Transistors, as the most basic semiconductor devices, are currently widely used. Therefore, as the component density and integration of semiconductor devices increase, the channel length of transistors must be continuously shortened to adapt to the shrinking process nodes.

[0003] To better adapt to the requirement of proportionally shrinking device dimensions, semiconductor technology has gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors. In a GAA transistor, the gate surrounds the channel area from all sides. Compared to planar transistors, GAA transistors have stronger control over the channel and can better suppress short-channel effects.

[0004] However, the performance of fully enclosed gate transistors still needs to be improved. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; a channel structure layer suspended above the substrate along a direction perpendicular to the surface of the substrate, the channel structure layer comprising one or more channel layers spaced apart sequentially; a gate structure located above the substrate, the gate structure spanning the channel structure layer and surrounding the channel layer, wherein portions of the gate structure located between the substrate and adjacent channel layers, and between adjacent channel layers, constitute a first portion, and the remaining portion constitutes a second portion; and an inner sidewall of the gate located on the sidewall of the second portion. The inner sidewall end face is vertically coplanar with the channel structure layer end face. At the junction of the inner sidewall of the gate and the top and sidewall of the channel structure layer, the inner sidewall of the gate has an arc-shaped corner. A gate oxide layer is located between the inner sidewall of the gate and the channel structure layer, and the thickness of the gate oxide layer between the inner sidewall of the gate and the channel structure layer is less than the vertical distance from the arc-shaped corner of the inner sidewall of the gate to the channel structure layer. Source and drain doped regions are located in the channel structure layer on both sides of the gate structure. The end face of the inner sidewall of the gate, the end face of the channel structure layer, and the end face of the source and drain doped regions are vertically coplanar.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a stacked structure is formed on the substrate, the stacked structure including one or more stacked channel layers, the channel layer including a sacrificial layer and a channel layer located on the sacrificial layer, a gate oxide layer being formed on the top and sidewalls of the channel layer, and a dummy gate structure being formed on the substrate spanning the stacked structure and covering a portion of the gate oxide layer; thinning the gate oxide layers on both sides of the dummy gate structure; and after the thinning process, forming a dummy gate structure at the dummy gate junction. A gate inner sidewall is formed on the sidewall of the structure; after forming the gate inner sidewall, a source / drain doped region is formed in the stacked structure on both sides of the dummy gate structure; after forming the source / drain doped region, the dummy gate structure and the gate oxide layer at the bottom of the dummy gate structure are removed, and a gate opening is formed between the gate inner sidewalls; the sacrificial layer is removed through the gate opening to form a through trench, which is surrounded by adjacent channel layers, or by adjacent channel layers and a substrate; a gate structure is formed in the gate opening and the through trench, and the gate structure surrounds the channel layer.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] The semiconductor structure provided in this embodiment of the invention has a gate oxide layer located between the gate inner wall and the channel structure layer. The thickness of the gate oxide layer between the gate inner wall and the channel structure layer is less than the vertical distance from the arc-shaped corner of the gate inner wall to the channel structure layer. During the formation of the semiconductor structure, a sacrificial layer is pre-formed at the position of the first part of the gate structure. After removing the sacrificial layer, the gate structure is formed. Since the thickness of the gate oxide layer between the gate inner wall and the channel structure layer is less than the vertical distance from the arc-shaped corner of the gate inner wall to the channel structure layer, the distance between the gate inner wall and the channel stack is reduced. This means that the space between the gate inner wall and the channel stack is smaller, which helps to reduce the probability that the source and drain doped regions are exposed through the space between the gate inner wall and the channel stack. Correspondingly, it reduces the probability that the process of removing the sacrificial layer will damage the source and drain doped regions through the space between the gate inner wall and the channel stack, thereby improving the performance of the semiconductor device.

[0010] In the semiconductor structure formation method provided by the present invention, after thinning the gate oxide layers on both sides of the dummy gate structure, an inner gate wall is formed on the sidewall of the dummy gate structure. Therefore, compared with the scheme without thinning, the distance between the inner gate wall and the channel stack is reduced, which means that the space between the inner gate wall and the channel stack is smaller. This helps to reduce the probability of the source and drain doped regions being exposed through the space between the inner gate wall and the channel stack when removing the gate oxide layer at the location of the dummy gate structure, thereby increasing the process window for forming the gate opening. At the same time, it also helps to reduce the probability of damage to the source and drain doped regions caused by the subsequent sacrificial layer removal process, thereby improving the performance of the semiconductor device. Attached Figure Description

[0011] Figures 1 to 7 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] Figure 8 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0013] Figures 9 to 15 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0014] As the background technology shows, the performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using a semiconductor structure formation method as an example. Figures 1 to 7 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0015] refer to Figures 1 to 6 This is a sectional view along the extension direction of the laminated structure and at the top of the laminated structure, with reference to... Figure 1 A substrate (not shown) is provided on which a stacked structure (not shown) is formed, the stacked structure including one or more stacked channel stacks 180, the channel stack 180 including a sacrificial layer 181 and a channel layer 182 located on the sacrificial layer 181, a gate oxide layer 131 being formed on the top and sidewalls of the channel stack 180, and a pseudo-gate structure 132 being formed on the substrate that spans the stacked structure and covers a portion of the gate oxide layer 131.

[0016] refer to Figure 2 A gate inner sidewall 133 is formed on the top of the exposed stacked structure and on the sidewall of the pseudo-gate structure 132.

[0017] refer to Figure 3Remove the inner gate walls 133 and the stacked structure on both sides of the pseudo gate structure 132, and form a groove 140 through the stacked structure on both sides of the pseudo gate structure 132.

[0018] Continue to refer to Figure 3 After the groove 140 is formed, a portion of the sacrificial layer 181 exposed along the extension direction of the groove layer 182 is removed to form an inner groove (not shown), and an inner sidewall 138 is formed in the inner groove.

[0019] refer to Figure 4 After the inner sidewall 138 is formed, a source / drain doped region 139 is formed in the groove 140.

[0020] refer to Figure 5 After the source / drain doped region 139 is formed, an interlayer dielectric layer 160 is formed on the substrate on the side of the pseudo-gate structure 132, and the interlayer dielectric layer 160 covers the source / drain doped region 139.

[0021] Continue to refer to Figure 5 After forming the interlayer dielectric layer 160, the dummy gate structure 132 and the gate oxide layer 131 at the bottom of the dummy gate structure 132 are removed, and a gate opening 155 is formed between the inner sidewalls of the gate 133.

[0022] Reference Figure 6 and Figure 7 , Figure 6 It is a top view. Figure 7 for Figure 6 In a partial cross-sectional view at the top of the channel layer 182, the sacrificial layer 181 is removed through the gate opening 155 to form a through trench (not shown). The through trench is surrounded by adjacent channel layers 182, or by adjacent channel layers 182 and the substrate. A gate structure 190 is formed in the gate opening 155 and the through trench, and the gate structure 190 surrounds the channel layer 182.

[0023] During the formation of the pseudo-gate structure 132, due to the process of forming the pseudo-gate structure 132, a foot 199 (see reference) is formed at the junction of the pseudo-gate structure 132 with the top and sidewalls of the channel structure layer. Figure 1 and Figure 7That is, the junction of the dummy gate structure 132 with the top and sidewalls of the channel structure layer has an arc-shaped corner. This correspondingly results in the inner sidewall of the gate inner wall 133 also having an arc-shaped corner at the junction of the gate inner wall 133 with the top and sidewalls of the channel structure layer. After removing the dummy gate structure 132, the exposed gate oxide layer 131 is removed. The gate oxide layer 131 is not only located on the exposed channel stack 180, but also between the gate inner wall 133 and the channel stack 180. Therefore, when removing the exposed gate oxide layer 131, it is easy to remove the gate inner wall 133 and the channel stack 180. The gate oxide layer 131 between the channel stack 180 is exposed more due to the arc shape of the foot 199. This increases the length of the gate oxide layer 131 between the gate inner sidewall 133 and the channel stack 180 to be removed, thereby increasing the probability that the source / drain doped region 139 is exposed through the space between the gate inner sidewall 133 and the channel stack 180. This further increases the probability that the subsequent process of removing the sacrificial layer 181 will damage the source / drain doped region 139, and consequently reduces the performance of the semiconductor device.

[0024] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a stacked structure is formed on the substrate, the stacked structure including one or more stacked channel layers, the channel layers including a sacrificial layer and a channel layer located on the sacrificial layer, a gate oxide layer being formed on the top and sidewalls of the channel layers, and a dummy gate structure being formed on the substrate spanning the stacked structure and covering a portion of the gate oxide layer; thinning the gate oxide layers on both sides of the dummy gate structure; and after the thinning process, [further details about the method]. A gate inner sidewall is formed on the sidewall of the dummy gate structure; after forming the gate inner sidewall, a source / drain doped region is formed in the stacked structure on both sides of the dummy gate structure; after forming the source / drain doped region, the dummy gate structure and the gate oxide layer at the bottom of the dummy gate structure are removed, and a gate opening is formed between the gate inner sidewalls; through the gate opening, the sacrificial layer is removed to form a through trench, which is surrounded by adjacent channel layers, or by adjacent channel layers and a substrate; a gate structure is formed in the gate opening and the through trench, and the gate structure surrounds the channel layer.

[0025] In the semiconductor structure formation method provided by the present invention, after thinning the gate oxide layers on both sides of the dummy gate structure, an inner gate wall is formed on the sidewall of the dummy gate structure. Therefore, compared with the scheme without thinning, the distance between the inner gate wall and the channel stack is reduced, which means that the space between the inner gate wall and the channel stack is smaller. This helps to reduce the probability of the source and drain doped regions being exposed through the space between the inner gate wall and the channel stack when removing the gate oxide layer at the location of the dummy gate structure, thereby increasing the process window for forming the gate opening. At the same time, it also helps to reduce the probability of damage to the source and drain doped regions caused by the subsequent sacrificial layer removal process, thereby improving the performance of the semiconductor device.

[0026] To make the above-mentioned objects, features, and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. (Reference) Figure 8 The diagram shows a schematic representation of an embodiment of the semiconductor structure of the present invention.

[0027] like Figure 8 The diagram shows a cross-sectional view along the extension direction of the channel structure layer and at the top of the channel structure layer. In this embodiment, the semiconductor structure includes: a substrate (not shown); a channel structure layer (not shown) suspended above the substrate in a direction perpendicular to the surface of the substrate, the channel structure layer including one or more channel layers 682 arranged sequentially at intervals; a gate structure 680 located above the substrate, the gate structure 680 spanning the channel structure layer and surrounding the channel layer 682, the portion of the gate structure 680 located between the substrate and adjacent channel layers 682, and the portion located between adjacent channel layers 682, serving as a first portion 666, and the remaining portion serving as a second portion 667; and a gate inner wall 633 located in the second portion. The gate inner sidewall 633 has an end face that is vertically coplanar with the end face of the channel structure layer. At the junction of the gate inner sidewall 633 and the top and sidewalls of the channel structure layer, the inner sidewall of the gate inner sidewall 633 has an arc-shaped corner 688. The gate oxide layer 631 is located between the gate inner sidewall 633 and the channel structure layer, and the thickness of the gate oxide layer 631 between the gate inner sidewall 633 and the channel structure layer is less than the vertical distance A from the arc-shaped corner 688 of the gate inner sidewall 633 to the channel structure layer. The source / drain doped regions 639 are located in the channel structure layer on both sides of the gate structure 680, and the end faces of the gate inner sidewall 633, the channel structure layer, and the source / drain doped regions 639 are vertically coplanar.

[0028] In this embodiment, a gate-all-around (GAA) transistor is used as an example of the semiconductor structure. In other embodiments, the semiconductor structure may also be other types of transistors such as forksheet transistors.

[0029] In this embodiment, the substrate includes a substrate (not shown) and a fin (not shown) located on the substrate, and the channel layer 682 is suspended on top of the fin.

[0030] The substrate serves as a process platform for the formation of semiconductor structures. In this embodiment, the substrate is a silicon substrate, meaning the substrate material is single-crystal silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium dihydrogen nitride. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0031] The fins serve to provide support for the channel structure layer. In this embodiment, the fins and substrate are an integral structure, and the material of the fins is the same as that of the substrate, which is silicon. In other embodiments, the material of the fins may be different from that of the substrate. The material of the fins may be other suitable materials, such as one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0032] It should be noted that the substrate also includes an isolation layer (not shown) located on the substrate on the side of the fin, the isolation layer surrounding the sidewall covering the fin. The isolation layer serves to isolate adjacent devices. As an example, the material of the isolation layer is silicon oxide. In other embodiments, the material of the isolation layer may also be other insulating materials, such as silicon oxynitride.

[0033] The channel layer 682 provides a conductive channel for the transistor. In this embodiment, the channel layer 682 is made of Si, which is beneficial for improving the performance of the NMOS transistor. In other embodiments, when the semiconductor structure is a PMOS transistor, SiGe channel technology can be used to improve the performance of the PMOS transistor, and the channel layer 682 is made of SiGe. In other embodiments, the channel layer material can also be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0034] As an example, in the channel structure layer, the number of channel layers 682 is three. In other embodiments, the number of channel layers may also be other.

[0035] When the device is in operation, the gate structure 680 is used to control the opening and closing of the conductive channel.

[0036] In this embodiment, the gate structure 680 is a metal gate structure, which includes a gate dielectric layer (not shown) surrounding the channel layer 682 and a gate electrode layer (not shown) covering the gate dielectric layer.

[0037] The gate electrode layer is used as an external electrode for electrical connection between the gate structure 680 and external circuitry.

[0038] The material of the gate electrode layer includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN), and titanium aluminum carbide (TiAlC).

[0039] In this embodiment, the gate electrode layer includes one or both of a work function layer and an electrode layer.

[0040] In this embodiment, the work function layer is used to adjust the threshold voltage of the transistor. For example, when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of titanium aluminide and titanium aluminum carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of titanium nitride, tantalum nitride, and titanium silicon nitride.

[0041] The electrode layer is used for electrical connection with an external circuit. The electrode layer is made of a conductive material, including one or more of tungsten and aluminum. In this embodiment, the electrode layer is made of tungsten.

[0042] The gate dielectric layer is used to achieve electrical isolation between the gate electrode layer and the conductive channel.

[0043] In this embodiment, the material of the gate dielectric layer includes one or more of the following: hafnium oxide (HfO2), zirconium oxide (ZrO2), silicon hafnium oxide (HfSiO), silicon oxynitride hafnium (HfSiON), tantalum hafnium oxide (HfTaO), titanium hafnium oxide (HfTiO), zirconium hafnium oxide (HfZrO), aluminum oxide (Al2O3), silicon oxide (SiO2), and lanthanum oxide (La2O3).

[0044] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from zirconium oxide (ZrO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), or aluminum oxide (Al2O3). In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer may only include a gate oxide layer.

[0045] The inner wall 633 of the gate is used to protect the gate structure 680.

[0046] During the formation of the pseudo-gate structure, due to the process of forming the pseudo-gate structure, a foot is formed at the junction of the pseudo-gate structure with the top and sidewalls of the channel structure layer. That is, the junction of the pseudo-gate structure with the top and sidewalls of the channel structure layer has an arc-shaped corner, thereby forming an arc-shaped corner 688 on the inner sidewall of the gate inner sidewall 633, and the arc-shaped corner 688 faces the gate structure 680. The inner sidewall is the sidewall of the gate inner sidewall 633 that is close to the pseudo-gate structure.

[0047] The end face of the gate inner wall 633 is vertically coplanar with the end face of the channel structure layer, which facilitates the channel layer 682 to wrap the gate structure 680 located between adjacent gate inner walls 633, thereby improving the turn-on and turn-off capability of the semiconductor device.

[0048] In this embodiment, the material of the gate inner sidewall 633 includes one or more of silicon nitride and low-k dielectric materials. Here, a low-k dielectric material refers to a material with a dielectric constant k less than 3.9. The low-k dielectric material includes: silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the gate inner sidewall 633 is silicon nitride.

[0049] In the process of forming a semiconductor structure, a dummy gate structure is usually formed first to occupy the position of the gate structure 680. The gate oxide layer 631 is used to protect the channel layer 682 during the process of removing the dummy gate structure.

[0050] In this embodiment, the thickness of the gate oxide layer 631 between the gate inner wall 633 and the channel structure layer is less than the vertical distance A from the arc-shaped corner 688 of the gate inner wall 633 to the channel structure layer. Therefore, during the formation of the semiconductor structure, a sacrificial layer is pre-formed at the position of the first part 666 of the gate structure 680. After removing the sacrificial layer, the gate structure 680 is formed. Since the thickness of the gate oxide layer 631 between the gate inner wall 633 and the channel structure layer is less than the vertical distance A from the arc-shaped corner of the gate inner wall 633 to the channel structure layer, the distance between the gate inner wall 633 and the channel stack is reduced. This means that the space between the gate inner wall 633 and the channel stack is smaller, which helps to reduce the probability that the source and drain doped regions are exposed through the space between the gate inner wall 633 and the channel stack. Correspondingly, it reduces the probability that the process of removing the sacrificial layer will damage the source and drain doped regions through the space between the gate inner wall 633 and the channel stack, thereby improving the performance of the semiconductor device.

[0051] In this embodiment, the thickness of the gate oxide layer 631 between the gate inner wall 633 and the channel structure layer should not be too large. If the thickness of the gate oxide layer 631 between the gate inner wall 633 and the channel structure layer is too large, it will easily increase the space between the gate inner wall 633 and the channel stack, thereby increasing the risk that the source and drain doped regions will be easily exposed through the space between the gate inner wall 633 and the channel stack. Therefore, in this embodiment, the thickness of the gate oxide layer 631 between the gate inner wall 633 and the channel structure layer is less than or equal to 3 nm.

[0052] In this embodiment, the gate oxide layer 631 is made of silicon oxide. In other embodiments, the gate oxide layer may also be made of silicon oxynitride.

[0053] The source / drain doped region 639 is used as the source or drain of the field-effect transistor. When the field-effect transistor is working, the source / drain doped region 639 is used to provide a source of charge carriers.

[0054] The end face of the gate inner sidewall 633, the end face of the channel structure layer, and the end face of the source / drain doped region 639 are vertically coplanar, which facilitates the contact between the source / drain doped region 639 and the end face of the channel structure layer, thereby improving the formation quality of the source / drain doped region 639.

[0055] In this embodiment, the source / drain doped region 639 includes an ion-doped stress layer. This stress layer provides stress to the channel region, thereby improving carrier mobility. Specifically, when forming an NMOS transistor, the source / drain doped region 639 includes an N-type ion-doped stress layer, and the stress layer material is Si or SiC; when forming a PMOS transistor, the source / drain doped region 639 includes a P-type ion-doped stress layer, and the stress layer material is Si or SiGe.

[0056] In this embodiment, the semiconductor structure further includes an inner sidewall 638, located between the sidewall of the first portion 666 and the source / drain doped region 639.

[0057] The inner wall 638 is used to support the channel layer 682 and realizes the isolation between the source / drain doped region 639 and the gate structure 680, thereby increasing the distance between the gate structure 680 and the source / drain doped region 639, which is beneficial to reduce the parasitic capacitance between the gate structure 680 and the source / drain doped region 639.

[0058] In this embodiment, the material of the inner wall 638 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate or silicon oxycarbonitride, boron nitride and boron carbonitride; as an example, the material of the inner wall 638 is silicon nitride.

[0059] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 660, which is located on the substrate on the side of the gate structure 680 and covers the source / drain doped region 639.

[0060] Interlayer dielectric layer 660 is used to isolate adjacent devices.

[0061] In this embodiment, the material of the interlayer dielectric layer 660 is silicon oxide. The material of the interlayer dielectric layer 660 can also be other insulating materials.

[0062] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 9 to 15 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0063] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

[0064] refer to Figures 9 to 15 All views are sectional views taken along the extension direction of the stacked structure and at the top of the stacked structure, for reference. Figure 9 A substrate (not shown) is provided on which a stacked structure (not shown) is formed, the stacked structure including one or more stacked channel stacks 880, the channel stack 880 including a sacrificial layer 881 and a channel layer 882 located on the sacrificial layer 881, a gate oxide layer 831 being formed on the top and sidewalls of the channel stack 880, and a pseudo-gate structure 832 being formed on the substrate that spans the stacked structure and covers a portion of the gate oxide layer 831.

[0065] In this embodiment, a gate-all-around (GAA) transistor is used as an example of the semiconductor structure. In other embodiments, the semiconductor structure may also be other types of transistors such as forksheet transistors.

[0066] In this embodiment, in the step of providing a substrate, the substrate includes a substrate (not shown) and a fin (not shown) located on the substrate, and the stacked structure is located on top of the fin.

[0067] The substrate serves as a process platform for the formation of semiconductor structures. In this embodiment, the substrate is a silicon substrate, meaning the substrate material is single-crystal silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium dihydrogen nitride. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0068] The fins serve to provide support for the stacked structure. In this embodiment, the fins and the substrate are an integral structure, and the material of the fins is the same as that of the substrate, which is silicon. In other embodiments, the material of the fins may be different from that of the substrate. The material of the fins may be other suitable materials, such as one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0069] It should be noted that the substrate also includes an isolation layer (not shown) located on the substrate on the side of the fin, the isolation layer surrounding the sidewall covering the fin. The isolation layer serves to isolate adjacent devices. As an example, the material of the isolation layer is silicon oxide. In other embodiments, the material of the isolation layer may also be other insulating materials, such as silicon oxynitride.

[0070] The channel stack 880 provides a process basis for the subsequent formation of the channel layer 882 and the gate structure enclosing the channel layer 882. In this embodiment, the number of channel stacks 880 is 3; in other embodiments, the number of channel stacks may be other numbers.

[0071] The channel layer 882 is used to provide a conductive channel for the transistor. The sacrificial layer 881 is used to support the channel layer 882, thereby providing a process basis for the subsequent implementation of the spaced floating arrangement of the sacrificial layer 881. The sacrificial layer 881 is also used to occupy space for the subsequent formation of the gate structure that encloses the channel layer 882.

[0072] In this embodiment, an NMOS transistor is formed, with the channel layer 882 made of Si and the sacrificial layer 881 made of SiGe. During the subsequent removal of the sacrificial layer 881, the etching selectivity for SiGe and Si is relatively high. By setting the material of the sacrificial layer 881 to SiGe and the material of the channel layer 882 to Si, the impact of the sacrificial layer 881 removal process on the channel layer 882 can be effectively reduced, thereby improving the quality of the channel layer 882 and ultimately contributing to improved device performance.

[0073] The gate oxide layer 831 is used to protect the channel layer 882 during the subsequent removal of the dummy gate structure.

[0074] In this embodiment, the gate oxide layer 831 is made of silicon oxide. In other embodiments, the gate oxide layer may also be made of silicon oxynitride.

[0075] The pseudo-gate structure 832 is used to pre-reserve space for the subsequent formation of the gate structure.

[0076] Specifically, the pseudo-gate structure 832 is a polycrystalline silicon gate structure or an amorphous silicon gate structure, that is, the material of the pseudo-gate structure 832 can be polycrystalline silicon or amorphous silicon.

[0077] In this embodiment, the dummy gate structure 832 spans the stacked structure and covers part of the gate oxide layer 831, so that in the subsequent step of forming the gate opening, it is necessary to remove the dummy gate structure 832 and the exposed gate oxide layer 831.

[0078] refer to Figure 10 The gate oxide layer 831 on both sides of the pseudo-gate structure 832 is thinned.

[0079] After thinning the gate oxide layer 831 on both sides of the dummy gate structure 832, it is beneficial to form the gate inner sidewall on the sidewall of the dummy gate structure 832. Compared with the solution without thinning, the distance between the gate inner sidewall and the channel stack 880 is reduced, which means that the space between the gate inner sidewall and the channel stack 880 is smaller. Therefore, when removing the gate oxide layer 831 at the location of the dummy gate structure 832, it is beneficial to reduce the probability that the source and drain doped regions formed later will be exposed through the space between the gate inner sidewall and the channel stack 880, thereby increasing the process window for forming the gate opening. At the same time, it is also beneficial to reduce the probability of damage to the source and drain doped regions caused by the subsequent removal of the sacrificial layer 881, thereby improving the performance of the semiconductor device.

[0080] In this embodiment, during the thinning process, a portion or all of the gate oxide layer 831 on both sides of the dummy gate structure 832 is removed, thereby reducing the distance between the inner gate wall and the channel stack 880, and consequently reducing the probability of the source / drain doped regions being exposed through the space between the inner gate wall and the channel stack 880. It should be noted that the greater the thickness of the removed gate oxide layer 831, the more beneficial it is to reducing the distance between the inner gate wall and the channel stack 880, and thus the more beneficial it is to reducing the probability of the source / drain doped regions being exposed.

[0081] In this embodiment, the thickness removal amount during the thinning process should not be too small a proportion of the initial thickness of the gate oxide layer 831. If the removal amount is too small a proportion of the initial thickness of the gate oxide layer 831, it will be detrimental to reducing the distance between the subsequently formed gate inner sidewall and the channel stack 880, and consequently, it will be detrimental to reducing the probability of the source / drain doped regions being exposed through the space between the gate inner sidewall and the channel stack 880. Therefore, in this embodiment, the removal amount is between 1% and 100% of the initial thickness of the gate oxide layer 831. For example, the removal amount is 5%, 20%, or 50% of the initial thickness of the gate oxide layer 831.

[0082] In this embodiment, during the thinning process, the etching selectivity ratio between the gate oxide layer 831 and the gate inner wall should not be too small. If the etching selectivity ratio is too small, the gate inner wall may be damaged while removing the gate oxide layer 831. Therefore, in this embodiment, the etching selectivity ratio between the gate oxide layer 831 and the gate inner wall is greater than 5:1.

[0083] In this embodiment, the thinning process is a wet etching process. The wet etching process has high selectivity, which is beneficial for the targeted removal of the gate oxide layer 831.

[0084] In this embodiment, the etching solution used in the wet etching process includes a hydrofluoric acid solution. The mass fraction of hydrofluoric acid in the hydrofluoric acid solution should not be too low or too high. If the mass fraction of hydrofluoric acid is too low, it will not be conducive to sufficient reaction with the gate oxide layer 831 of the required thickness, thus hindering the removal of the gate oxide layer 831. If the mass fraction of hydrofluoric acid is too high, it will be difficult to control the reaction stop time, and since an isolation layer (not shown) is formed around the fin on the substrate, if the mass fraction of hydrofluoric acid is too high, it will easily damage the isolation layer. Therefore, in this embodiment, the mass fraction of hydrofluoric acid in the hydrofluoric acid solution is 0.12% to 0.98%.

[0085] In this embodiment, the process time of the wet etching process should not be too short or too long. If the process time is too short, it will not be conducive to sufficient reaction with the gate oxide layer 831 to remove the gate oxide layer 831 of the required thickness; if the process time is too long, it will increase the process time and increase the process cost. Therefore, in this embodiment, the process time is 5 seconds to 180 seconds.

[0086] In other embodiments, the thinning process can also be a vapor phase etching process. The vapor phase etching process includes the Certas etching process, which has high selectivity and is also beneficial for targeted removal of the gate oxide layer 831.

[0087] The Certas etching process uses a mixture of hydrogen fluoride and ammonia as the etching gas. Hydrogen fluoride is a commonly used gas in the semiconductor field for etching silicon oxide materials. Ammonia acts as a catalyst to increase the etching rate.

[0088] refer to Figure 11 After the thinning process, an inner gate wall 833 is formed on the sidewall of the pseudo-gate structure 832.

[0089] The inner sidewall 833 of the gate is used to support the dummy gate structure 832, thereby providing a process basis for the subsequent removal of the dummy gate structure 832 and the formation of the gate opening.

[0090] In this embodiment, after thinning the gate oxide layer 831 on both sides of the dummy gate structure 832, an inner gate wall 833 is formed on the sidewall of the dummy gate structure 832. Compared with the scheme without thinning, the distance between the inner gate wall 833 and the channel stack 880 is reduced, which means that the space between the inner gate wall 833 and the channel stack 880 is smaller. Therefore, when the gate oxide layer 831 at the location of the dummy gate structure 832 is removed, it is beneficial to reduce the probability that the source and drain doped regions formed later will be exposed through the space between the inner gate wall 833 and the channel stack 880.

[0091] It should be noted that the inner wall 833 of the gate also covers the top of the exposed stacked structure and the top of the pseudo-gate structure 832.

[0092] refer to Figure 12 After the inner sidewall 833 of the gate is formed and before the source and drain doped regions are formed, grooves 840 that penetrate the stacked structure are formed on both sides of the pseudo gate structure 832.

[0093] Groove 840 is used to provide space for the subsequent formation of source / drain doped regions.

[0094] Specifically, in this embodiment, an anisotropic etching process (e.g., anisotropic dry etching process) is used to etch the stacked structure on both sides of the pseudo gate structure 832, which is beneficial to improve the cross-sectional morphology quality of the groove 840, thereby facilitating precise control of the sidewall morphology of the groove 840.

[0095] It should be noted that before etching the stacked structures on both sides of the dummy gate structure 832, the process also includes etching away the top of the dummy gate structure 832 and the gate inner wall 833 on the stacked structure.

[0096] Correspondingly, using the inner sidewall 833 of the gate on the sidewall of the pseudo gate structure 832 as a mask, the stacked structure on both sides of the pseudo gate structure 832 is etched to form a groove 840.

[0097] Continue to refer to Figure 12 After the groove 840 is formed, a portion of the sacrificial layer 881 exposed on the sidewall of the groove 840 is removed along the extension direction of the channel layer 882 to form an inner groove (not shown), and an inner sidewall 838 is formed in the inner groove.

[0098] The inner groove 838 provides space for the subsequent formation of the inner sidewall.

[0099] In this embodiment, a vapor etching process is used to etch a portion of the sacrificial layer 881 exposed on the sidewall of the groove 840 along the extension direction of the channel layer 882. Vapor etching is an isotropic etching process that can etch the sacrificial layer 881 along the extension direction of the channel layer 882. Furthermore, vapor etching easily achieves a large etching selectivity, which helps reduce the difficulty of etching the sacrificial layer 881 and reduces the probability of damage to other film structures (e.g., the channel layer).

[0100] In this embodiment, the sacrificial layer 881 is made of SiGe, and the channel layer 882 is made of Si. The sacrificial layer 881 on the sidewall of the groove 840 is etched by HCl vapor. The etching rate of HCl vapor on SiGe material is much greater than that on Si material, which can effectively reduce the probability of damage to the channel layer 882.

[0101] The inner wall 838 is used to support the channel layer 882, which facilitates the subsequent replacement of the pseudo gate structure 832 with the gate structure. In addition, the inner wall 838 is used to achieve the isolation between the subsequently formed source / drain doped regions and the gate structure, thereby increasing the distance between the gate structure and the source / drain doped regions, which helps to reduce the parasitic capacitance between the gate structure and the source / drain doped regions.

[0102] In this embodiment, the step of forming the inner sidewall 838 includes: forming an inner sidewall material layer on the sidewall of the pseudo-grid structure 832 and the sidewall of the groove 840, wherein the inner sidewall material layer is also filled in the inner groove, removing the inner sidewall material layer located outside the inner groove, and retaining the remaining inner sidewall material layer in the inner groove as the inner sidewall 838.

[0103] In this embodiment, the material of the inner wall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate or silicon oxycarbonitride, boron nitride and boron carbonitride; as an example, the material of the inner wall is silicon nitride.

[0104] refer to Figure 13 After forming the inner sidewall 833 of the gate, source and drain doped regions 839 are formed in the stacked structure on both sides of the pseudo gate structure 832.

[0105] Specifically, source / drain doped regions 839 are formed within the groove 840.

[0106] The source / drain doped region 839 is used as the source or drain of the field-effect transistor. When the field-effect transistor is working, the source / drain doped region 839 is used to provide a source of charge carriers.

[0107] In this embodiment, the source / drain doped region 839 includes an ion-doped stress layer. This stress layer provides stress to the channel region, thereby improving carrier mobility. Specifically, when forming an NMOS transistor, the source / drain doped region 839 includes an N-type ion-doped stress layer, and the stress layer material is Si or SiC; when forming a PMOS transistor, the source / drain doped region 839 includes a P-type ion-doped stress layer, and the stress layer material is Si or SiGe.

[0108] In this embodiment, an epitaxial process is used to form a stress layer, and ions are self-doped in situ during the formation of the stress layer. The stress layer doped with ions is used as the source / drain doping region 839.

[0109] refer to Figure 14 After forming the source / drain doped region 839 and before removing the pseudo-gate structure 832, the method further includes: forming an interlayer dielectric layer 860 on the substrate on the side of the pseudo-gate structure 832, wherein the interlayer dielectric layer 860 covers the source / drain doped region 839.

[0110] The interlayer dielectric layer 860 is used to isolate adjacent devices and also to support the gate inner wall 833 and the fin during the subsequent removal of the dummy gate structure 832.

[0111] In this embodiment, the interlayer dielectric layer 860 is made of silicon oxide. In other embodiments, the interlayer dielectric layer may be made of other insulating materials.

[0112] Continue to refer to Figure 14 After forming the source / drain doped region 839, the dummy gate structure 832 and the gate oxide layer 831 at the bottom of the dummy gate structure 832 are removed, and a gate opening 855 is formed between the inner sidewalls of the gate 833.

[0113] The gate opening 855 is used to provide space for forming the gate structure.

[0114] The gate oxide layer 831 at the location of the dummy gate structure 832 is removed to meet the device performance requirements (e.g., operating voltage), and the sacrificial layer 881 is exposed so that it can be subsequently removed through the gate opening 855.

[0115] In this embodiment, the process of removing the gate oxide layer 831 at the location of the dummy gate structure 832 includes a dry etching process. The process of removing the gate oxide layer 831 at the location of the dummy gate structure 832 is the same as the process of removing the dummy gate structure 832, which helps to improve process compatibility and reduce process cost. In other embodiments, the process of removing the gate oxide layer at the location of the dummy gate structure also includes a wet etching process.

[0116] refer to Figure 15The sacrificial layer 881 is removed through the gate opening 855 to form a through trench (not shown), which is surrounded by adjacent channel layers 882, or by adjacent channel layers 882 and the substrate.

[0117] In this embodiment, the gate opening 855 spans the stacked structure.

[0118] The through-slot and the gate opening 855 together provide space for forming the gate structure. The through-slot is connected to the gate opening 855.

[0119] In this embodiment, a vapor etching process is used to remove the sacrificial layer 881. Specifically, the channel layer 882 is made of Si, and the sacrificial layer 881 is made of SiGe. Therefore, the sacrificial layer 881 exposed by the gate opening 855 is removed by HCl vapor. HCl vapor has a high etching selectivity between SiGe and Si, which is beneficial to improving the removal efficiency of the sacrificial layer 881 and reducing the probability of damage to the channel layer 882.

[0120] Continue to refer to Figure 14 A gate structure 890 is formed in the gate opening 855 and the through slot, and the gate structure 890 surrounds the channel layer 882.

[0121] During device operation, the gate structure 890 is used to control the opening and closing of the conductive channel. In this embodiment, the gate structure 890 is a metal gate structure, which includes a gate dielectric layer (not shown) surrounding the channel layer 882 and a gate electrode layer (not shown) covering the gate dielectric layer.

[0122] The gate electrode layer is used as an external electrode for electrical connection between the gate structure 890 and external circuitry.

[0123] The gate electrode layer material includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN), and titanium aluminum carbide (TiAlC).

[0124] In this embodiment, the gate electrode layer includes one or both of the work function layer and the electrode layer.

[0125] In this embodiment, the work function layer is used to adjust the threshold voltage of the transistor. For example, when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of titanium aluminide and titanium aluminum carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of titanium nitride, tantalum nitride, and titanium silicon nitride.

[0126] The electrode layer is used for electrical connection to an external circuit. The electrode layer is made of a conductive material, including one or more of tungsten and aluminum. In this embodiment, the electrode layer is made of tungsten.

[0127] The gate dielectric layer is used to achieve electrical isolation between the gate electrode layer and the conductive channel.

[0128] In this embodiment, the material of the gate dielectric layer includes one or more of the following: hafnium oxide (HfO2), zirconium oxide (ZrO2), silicon hafnium oxide (HfSiO), silicon oxynitride hafnium (HfSiON), tantalum hafnium oxide (HfTaO), titanium hafnium oxide (HfTiO), zirconium hafnium oxide (HfZrO), aluminum oxide (Al2O3), silicon oxide (SiO2), and lanthanum oxide (La2O3).

[0129] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from zirconium oxide (ZrO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), or aluminum oxide (Al2O3). In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer may only include a gate oxide layer.

[0130] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A channel structure layer, suspended above the substrate, along a direction perpendicular to the surface of the substrate, the channel structure layer comprising one or more channel layers arranged at intervals in sequence; A gate structure is located above the substrate, the gate structure spans the channel structure layer and surrounds the channel layer, the portion of the gate structure located between the substrate and the adjacent channel layer, and the portion located between the adjacent channel layers, is designated as a first portion, and the remaining portion is designated as a second portion; The gate inner wall is located in the second part of the sidewall. The end face of the gate inner wall is vertically coplanar with the end face of the channel structure layer. At the junction of the gate inner wall and the top and sidewall of the channel structure layer, the inner wall of the gate inner wall has an arc-shaped corner. A gate oxide layer is located between the inner wall of the gate and the channel structure layer, and the thickness of the gate oxide layer between the inner wall of the gate and the channel structure layer is less than the vertical distance from the arc-shaped corner of the inner wall of the gate to the channel structure layer. The source and drain doped regions are located within the channel structure layers on both sides of the gate structure, and the end faces of the inner sidewalls of the gate, the channel structure layers, and the source and drain doped regions are vertically coplanar.

2. The semiconductor structure as described in claim 1, characterized in that, The thickness of the gate oxide layer between the inner gate wall and the channel structure layer is less than or equal to 3 nm.

3. The semiconductor structure as described in claim 1, characterized in that, The material of the inner sidewall of the gate includes one or more of silicon nitride and low-k dielectric materials.

4. The semiconductor structure as described in claim 1, characterized in that, The gate structure is a metal gate structure.

5. The semiconductor structure as described in claim 1, characterized in that, The gate structure includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer; The material of the gate dielectric layer includes one or more of the following: hafnium oxide, zirconium oxide, silicon hafnium oxide, silicon oxynitride hafnium oxide, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, aluminum oxide, silicon oxide, and lanthanum oxide. The material of the gate electrode layer includes one or more of titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, titanium silicon nitride, and titanium aluminum carbide.

6. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure includes an interlayer dielectric layer located on a substrate on the side of the gate structure, and the interlayer dielectric layer covering the source and drain doped regions.

7. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which a stacked structure is formed, the stacked structure including one or more stacked channel stacks, the channel stacks including a sacrificial layer and a channel layer located on the sacrificial layer, a gate oxide layer being formed on the top and sidewalls of the channel stacks, and a pseudo-gate structure being formed on the substrate that spans the stacked structure and covers a portion of the gate oxide layer; The gate oxide layers on both sides of the pseudo-gate structure are thinned. After the thinning process, an inner gate wall is formed on the sidewall of the pseudo-gate structure; After the inner sidewall of the gate is formed, source and drain doped regions are formed in the stacked structure on both sides of the pseudo gate structure. After forming the source and drain doped regions, the dummy gate structure and the gate oxide layer at the bottom of the dummy gate structure are removed, and a gate opening is formed between the inner sidewalls of the gate. The sacrificial layer is removed through the gate opening to form a through-slot, which is surrounded by adjacent channel layers, or by adjacent channel layers and a substrate; A gate structure is formed within the gate opening and the through-slot, the gate structure surrounding the channel layer.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, In the thinning process, a portion or all of the gate oxide layer on both sides of the pseudo-gate structure is removed.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, The thickness removal amount of the thinning process is 1% to 100% of the initial thickness of the gate oxide layer.

10. The method for forming a semiconductor structure as described in claim 7, characterized in that, In the thinning process, the etching selectivity ratio of the gate oxide layer to the gate inner sidewall is greater than 5:

1.

11. The method for forming a semiconductor structure as described in claim 7, characterized in that, The thinning process includes wet etching or vapor phase etching.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The etching solution used in the wet etching process includes hydrofluoric acid solution.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The parameters of the wet etching process include: the mass fraction of hydrofluoric acid in the hydrofluoric acid solution is 0.12% to 0.98%, and the process time is 5 seconds to 180 seconds.

14. The method for forming a semiconductor structure as described in claim 11, characterized in that, The vapor phase etching process includes the Certas etching process, and the etching gas used in the Certas etching process includes a mixture of hydrogen fluoride gas and ammonia gas.

15. The method for forming a semiconductor structure as described in claim 7, characterized in that, After forming the source / drain doped regions and before removing the dummy gate structure, the method further includes: forming an interlayer dielectric layer on the substrate on the side of the dummy gate structure, wherein the interlayer dielectric layer covers the source / drain doped regions.

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