Data receiving circuit, data receiving system and storage device

Abstract

This disclosure provides a data receiving circuit, a data receiving system, and a storage device. The data receiving circuit includes: a first amplification module configured to receive a data signal, a first reference signal, and a second reference signal; perform a first comparison on the data signal and the first reference signal and output a first signal pair; and perform a second comparison on the data signal and the second reference signal and output a second signal pair; wherein the voltage levels of the first reference signal and the second reference signal are different; and a second amplification module configured to select either the first signal pair or the second signal pair as an input signal pair based on a feedback signal; amplify the voltage difference between the input signal pairs; and output a first output signal and a second output signal, wherein the feedback signal is obtained based on previously received data. This disclosure at least improves the receiving performance of the data receiving circuit.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a data receiving circuit, a data receiving system, and a storage device. Background Technology

[0002] In memory applications, as signal transmission rates increase, channel loss has a greater impact on signal quality, easily leading to inter-symbol interference (ISI). Furthermore, the difference in level between the data signal received by the memory's data receiving circuit and the reference signal can affect the data receiving circuit's judgment of the data signal, thus impacting the accuracy of the output signal. Currently, equalization circuits are commonly used to compensate for channel loss. The equalization circuit can be either a CTLE (Continuous Time Linear Equalizer) or a DFE (Decision Feedback Equalizer).

[0003] However, the current equalization circuits have limited ability to adjust data signals, and the accuracy of the signals output by the data receiving circuits needs to be improved. Therefore, the receiving performance of the data receiving circuits needs to be improved. Summary of the Invention

[0004] This disclosure provides a data receiving circuit, a data receiving system, and a storage device, which at least helps to improve the receiving performance of the data receiving circuit.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a data receiving circuit, including: a first amplification module configured to receive a data signal, a first reference signal, and a second reference signal; perform a first comparison on the data signal and the first reference signal and output a first signal pair as the result of the first comparison; perform a second comparison on the data signal and the second reference signal and output a second signal pair as the result of the second comparison; wherein the level value of the first reference signal is different from the level value of the second reference signal, the first signal pair includes a first signal and a second signal, and the second signal pair includes a third signal and a fourth signal; a second amplification module configured to select receiving either the first signal pair or the second signal pair as an input signal pair based on a feedback signal; amplify the voltage difference of the input signal pair; and output a first output signal and a second output signal as the result of the amplification process; wherein the feedback signal is obtained based on previously received data.

[0006] In some embodiments, the first amplification module includes: a first comparison circuit having a first node and a second node, configured to receive the data signal and the first reference signal and perform the first comparison, and output the first signal and the second signal through the first node and the second node respectively; and a second comparison circuit having a third node and a fourth node, configured to receive the data signal and the second reference signal and perform the second comparison, and output the third signal and the fourth signal through the third node and the fourth node respectively.

[0007] In some embodiments, the first comparison circuit includes: a first current source configured to be connected between a power supply node and a fifth node, providing current to the fifth node in response to a sampling clock signal; a first comparison unit connected to the first node, the second node, and the fifth node, configured to receive the data signal and the first reference signal, perform the first comparison when the first current source provides current to the fifth node, and output the first signal and the second signal; the second comparison circuit includes: a second current source configured to be connected between a power supply node and a sixth node, providing current to the sixth node in response to the sampling clock signal; a second comparison unit connected to the third node, the fourth node, and the sixth node, configured to receive the data signal and the second reference signal, perform the second comparison when the second current source provides current to the sixth node, and output the third signal and the fourth signal.

[0008] In some embodiments, the circuit structure of the first current source is the same as that of the second current source; the circuit structure of the first comparison unit is the same as that of the second comparison unit.

[0009] In some embodiments, the first current source includes: a first PMOS transistor connected between the power supply node and the fifth node, wherein the gate of the first PMOS transistor receives the sampling clock signal; the second current source includes: a second PMOS transistor connected between the power supply node and the sixth node, wherein the gate of the second PMOS transistor receives the sampling clock signal.

[0010] In some embodiments, the first comparison unit includes: a third PMOS transistor connected between the first node and the fifth node, the gate of the third PMOS transistor receiving the data signal; and a fourth PMOS transistor connected between the second node and the fifth node, the gate of the fourth PMOS transistor receiving the first reference signal; the second comparison unit includes: a fifth PMOS transistor connected between the third node and the sixth node, the gate of the fifth PMOS transistor receiving the data signal; and a sixth PMOS transistor connected between the fourth node and the sixth node, the gate of the sixth PMOS transistor receiving the second reference signal.

[0011] In some embodiments, the first amplification module further includes: a first reset unit connected to the first node and the second node, configured to reset the first node and the second node; and a second reset unit connected to the third node and the fourth node, configured to reset the third node and the fourth node.

[0012] In some embodiments, the first reset unit includes: a first NMOS transistor connected between the first node and ground, the gate of the first NMOS transistor receiving a first reset signal; a second NMOS transistor connected between the second node and ground, the gate of the second NMOS transistor receiving the first reset signal; the second reset unit includes: a third NMOS transistor connected between the third node and ground, the gate of the third NMOS transistor receiving the first reset signal; and a fourth NMOS transistor connected between the fourth node and ground, the gate of the fourth NMOS transistor receiving the first reset signal.

[0013] In some embodiments, the second amplification module includes: a first input unit connected to the seventh node and the eighth node, configured to receive and compare the first signal pair in response to the feedback signal being turned on, and provide signals to the seventh node and the eighth node respectively; a second input unit connected to the seventh node and the eighth node, configured to receive and compare the second signal pair in response to the feedback signal being turned on, and provide signals to the seventh node and the eighth node respectively; wherein the first input unit and the second input unit are selectively turned on based on the feedback signal; and a latching unit connected to the seventh node and the eighth node, configured to amplify and latch the signals of the seventh node and the eighth node, and output the first output signal and the second output signal through the first output node and the second output node respectively.

[0014] In some embodiments, the feedback signal includes a differential first feedback signal and a second feedback signal; the first input unit is turned on in response to the first feedback signal, and the second input unit is turned on in response to the second feedback signal.

[0015] In some embodiments, the first input unit includes: a fifth NMOS transistor and a sixth NMOS transistor, wherein the drain of the fifth NMOS transistor is connected to the seventh node, the source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor, and the source of the sixth NMOS transistor is connected to ground; wherein the gate of the fifth NMOS transistor receives either the first signal or the first feedback signal, and the gate of the sixth NMOS transistor receives the other of the first signal or the first feedback signal; a seventh NMOS transistor and an eighth NMOS transistor, wherein the drain of the seventh NMOS transistor is connected to the eighth node, the source of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor, and the source of the eighth NMOS transistor is connected to ground; wherein the gate of the seventh NMOS transistor receives either the second signal or the first feedback signal, and the gate of the eighth NMOS transistor receives the other of the second signal or the first feedback signal.

[0016] In some embodiments, the second input unit includes: a ninth NMOS transistor and a tenth NMOS transistor, wherein the drain of the ninth NMOS transistor is connected to the seventh node, the source of the ninth NMOS transistor is connected to the drain of the tenth NMOS transistor, and the source of the tenth NMOS transistor is connected to ground; wherein the gate of the ninth NMOS transistor receives one of the third signal or the second feedback signal, and the gate of the tenth NMOS transistor receives the other of the third signal or the second feedback signal; and an eleventh NMOS transistor and a twelfth NMOS transistor, wherein the drain of the eleventh NMOS transistor is connected to the eighth node, the source of the eleventh NMOS transistor is connected to the drain of the twelfth NMOS transistor, and the source of the twelfth NMOS transistor is connected to ground; wherein the gate of the eleventh NMOS transistor receives one of the fourth signal or the second feedback signal, and the gate of the twelfth NMOS transistor receives the other of the fourth signal or the second feedback signal.

[0017] In some embodiments, the latching unit includes: a thirteenth NMOS transistor and a seventh PMOS transistor, wherein the gates of the thirteenth NMOS transistor and the seventh PMOS transistor are both connected to the second output node, the source of the thirteenth NMOS transistor is connected to the seventh node, the drains of the thirteenth NMOS transistor and the seventh PMOS transistor are both connected to the first output node, and the source of the seventh PMOS transistor is connected to a power supply node; a fourteenth NMOS transistor and an eighth PMOS transistor, wherein the gates of the fourteenth NMOS transistor and the eighth PMOS transistor are both connected to the first output node, the source of the fourteenth NMOS transistor is connected to the eighth node, the drains of the fourteenth NMOS transistor and the eighth PMOS transistor are both connected to the second output node, and the source of the eighth PMOS transistor is connected to the power supply node.

[0018] In some embodiments, the second amplification module further includes: a third reset unit connected between the power supply node and the output terminal of the latch unit, configured to reset the output terminal of the latch unit.

[0019] In some embodiments, the output terminal of the latch unit includes a first output node and a second output node; the third reset unit includes: a ninth PMOS transistor connected between the first output node and the power supply node, the gate of the ninth PMOS transistor receiving a second reset signal; and a tenth PMOS transistor connected between the second output node and the power supply node, the gate of the tenth PMOS transistor receiving the second reset signal.

[0020] According to some embodiments of this disclosure, another aspect of this disclosure also provides a data receiving system, including: a plurality of cascaded data transmission circuits, each of the data transmission circuits including a data receiving circuit as described in any of the preceding claims and a latching circuit connected to the data receiving circuit; the output signal of the previous stage data transmission circuit serving as the feedback signal of the next stage data transmission circuit; and the output signal of the last stage data transmission circuit serving as the feedback signal of the first stage data transmission circuit.

[0021] In some embodiments, the data receiving circuit receives data in response to a sampling clock signal; and the data receiving system includes four cascaded data receiving circuits, with a 90° phase difference between the sampling clock signals of adjacent data receiving circuits.

[0022] In some embodiments, the feedback signal of the next-level data transmission circuit is the output signal of the previous-level data receiving circuit or the output signal of the previous-level latch circuit; the feedback signal of the first-level data transmission circuit is the output signal of the last-level data receiving circuit or the output signal of the last-level latch circuit.

[0023] According to some embodiments of the present disclosure, another aspect of the present disclosure also provides a storage device, including: a plurality of data ports; a plurality of data receiving systems as described in any of the preceding claims, each of the data receiving systems corresponding to one of the data ports.

[0024] The technical solutions provided in this disclosure have at least the following advantages:

[0025] The first amplification module uses the first reference signal and the second reference signal to perform a first comparison and a second comparison on the data signal, respectively, to obtain a first signal pair and a second signal pair. The level value of the first reference signal is different from the level value of the second reference signal. For data signals with different level values, it can be ensured that the level value difference between the data signal and either the first reference signal or the second reference signal is large. This is beneficial to ensure that the level value difference between at least one of the first signal pair and the second signal pair is large. Thus, when there is inter-symbol interference in the data signal received by the data receiving circuit, it is beneficial for the subsequent second amplification module to receive the one with the larger level value difference between the first signal pair and the second signal pair based on the feedback signal. Understandably, based on the differences in level values ​​between the data signal and the first reference signal, and between the data signal and the second reference signal, the second amplification module can select the signal with the larger level difference between the first and second signal pairs based on the feedback signal. This ensures that the second amplification module receives a pair of differential signals with a larger level difference, thereby improving the accuracy of the first and second output signals from the second amplification module. In other words, the first and second reference signals are used to improve the data receiving circuit's ability to adjust the received data signal and reduce the impact of inter-symbol interference of the received data signal on the data receiving circuit. Attached Figure Description

[0026] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A functional block diagram of a data receiving circuit provided in an embodiment of this disclosure;

[0028] Figure 2 A functional block diagram of a data receiving system provided in another embodiment of this disclosure;

[0029] Figures 3 to 4 Two other functional block diagrams of a data receiving circuit provided in one embodiment of this disclosure;

[0030] Figure 5 This is a schematic diagram of a circuit structure of a first amplification module in a data receiving circuit provided in an embodiment of the present disclosure;

[0031] Figure 6 This is a schematic diagram of a circuit structure of a second amplification module in a data receiving circuit provided in an embodiment of the present disclosure. Detailed Implementation

[0032] As can be seen from the background technology, the signal adjustment capability of equalization circuits needs to be improved.

[0033] Analysis revealed that when the difference between the level of the data signal received by the data receiving circuit and the level of the reference signal is small, the data receiving circuit is prone to errors in judging the data signal. For example, it may judge a data signal that should be high as low, causing the output signal of the data receiving circuit to be incorrect.

[0034] This disclosure provides a data receiving circuit, a data receiving system, and a storage device. In the data receiving circuit, a first reference signal and a second reference signal are used to perform a first comparison and a second comparison on a data signal, respectively, to obtain a first signal pair and a second signal pair. The level values ​​of the first and second reference signals are different. For data signals with different level values, the data signal can be significantly different from either the first or second reference signal. Therefore, when inter-symbol interference (ISI) exists in the data signal received by the data receiving circuit, it is beneficial for the subsequent second amplification module to receive the signal with the larger level difference between the first and second signal pairs based on the feedback signal. This achieves the purpose of improving the data receiving circuit's adjustment capability for the received data signal using the first and second reference signals, and reducing the impact of ISI on the data receiving circuit. The subsequent second amplification module selects to receive the signal with the larger level difference between the first and second signal pairs based on the feedback signal, which helps ensure that the second amplification module receives a pair of differential signals with a significant level difference, thereby improving the accuracy of the first and second output signals from the second amplification module. Therefore, the cooperation between the first and second amplification modules is beneficial to improving the receiving performance of the data receiving circuit.

[0035] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0036] This disclosure provides a data receiving circuit according to an embodiment. The data receiving circuit provided by this disclosure will be described in detail below with reference to the accompanying drawings. Figure 1 A functional block diagram of a data receiving circuit provided in an embodiment of this disclosure; Figures 3 to 4 Two other functional block diagrams of a data receiving circuit provided in one embodiment of this disclosure; Figure 5 This is a schematic diagram of a circuit structure of a first amplification module in a data receiving circuit provided in an embodiment of the present disclosure; Figure 6 This is a schematic diagram of a circuit structure of a second amplification module in a data receiving circuit provided in an embodiment of the present disclosure.

[0037] refer to Figure 1 and Figure 3The data receiving circuit 100 includes: a first amplification module 101, configured to receive a data signal DQ, a first reference signal VR+, and a second reference signal VR-; perform a first comparison on the data signal DQ and the first reference signal VR+, and output a first signal pair as the result of the first comparison; perform a second comparison on the data signal DQ and the second reference signal VR-, and output a second signal pair as the result of the second comparison; wherein the level value of the first reference signal VR+ is different from the level value of the second reference signal VR-; the first signal pair includes a first signal Sn+ and a second signal Sp+; and the second signal pair includes a third signal Sn- and a fourth signal Sp-; and a second amplification module 102, configured to select either the first signal pair or the second signal pair as the input signal pair based on a feedback signal Fb; amplify the voltage difference of the input signal pairs; and output a first output signal Vout and a second output signal VoutN as the result of the amplification; wherein the feedback signal Fb is obtained based on previously received data.

[0038] It is understandable that the level value of the first reference signal VR+ is different from the level value of the second reference signal VR-. Therefore, for data signals DQ with different level values, the level value difference between the data signal DQ and either the first reference signal VR+ or the second reference signal VR- can be large. This is beneficial for the first amplification module 101 to amplify the level value difference, so that the level value difference between at least one of the first signal pair and the second signal pair output by the first amplification module 101 is large. Therefore, when there is inter-symbol interference in the data signal DQ received by the data receiving circuit 100, it is beneficial for the subsequent second amplification module 102 to receive the pair of signals with large level value difference between the first signal pair and the second signal pair based on the feedback signal Fb. Understandably, the data receiving circuit 100 utilizes the first reference signal VR+ and the second reference signal VR- to improve its ability to adjust the received data signal DQ. That is, when inter-symbol interference exists in the data signal DQ received by the data receiving circuit 100, the second amplification module 102 receives the pair of signals from the first amplification module 101 that process the data signal DQ better based on the feedback signal Fb. The pair of signals that process the data signal DQ better is the pair of signals with a large difference in level value between the first signal pair and the second signal pair, thereby achieving the purpose of reducing the impact of inter-symbol interference of the received data signal DQ on the data receiving circuit 100.

[0039] Furthermore, the second amplification module 102 selects to receive the signal with the larger level difference between the first signal pair and the second signal pair based on the feedback signal Fb. This helps ensure that the second amplification module 102 receives a pair of differential signals with a large difference in signal level, thereby improving the accuracy of the first output signal Vout and the second output signal VoutN output by the second amplification module 102. Therefore, the cooperation between the first amplification module 101 and the second amplification module 102 helps improve the receiving performance of the data receiving circuit 100.

[0040] In some embodiments, the level of the first reference signal VR+ is higher than the level of the second reference signal VR-. If the data signal DQ is low and inter-symbol interference exists in the data signal DQ received by the data receiving circuit 100, the second amplification module 102 receives the first signal pair based on the feedback signal Fb. At this time, the level difference between the data signal DQ and the first reference signal VR+ is greater than the level difference between the data signal DQ and the second reference signal VR-. That is, the level difference of the signals in the first signal pair is greater than the level difference of the signals in the second signal pair. Therefore, the second amplification module 102 receiving the first signal pair is beneficial to outputting the first output signal Vout and the second output signal VoutN that meet the requirements, that is, ensuring the accuracy of the first output signal Vout and the second output signal VoutN, thereby helping to reduce the impact of inter-symbol interference of the received data signal DQ on the data receiving circuit 100.

[0041] Furthermore, if the data signal DQ is high and inter-symbol interference exists in the data signal DQ received by the data receiving circuit 100, the second amplification module 102 receives the second signal pair based on the feedback signal Fb. At this time, the level difference between the data signal DQ and the first reference signal VR+ is less than the level difference between the data signal DQ and the second reference signal VR-. That is, the level difference of the signals in the first signal pair is less than the level difference of the signals in the second signal pair. Therefore, the second amplification module 102 receiving the second signal pair is beneficial to outputting the first output signal Vout and the second output signal VoutN that meet the requirements, that is, ensuring the accuracy of the first output signal Vout and the second output signal VoutN, thereby helping to reduce the impact of inter-symbol interference of the received data signal DQ on the data receiving circuit 100.

[0042] As can be seen, through the cooperation of the first amplification module 101 and the second amplification module 102, when there is inter-symbol interference in the data signal DQ received by the data receiving circuit 100, the second amplification module 102 can receive a pair of signals from the first amplification module 101 that have better processed the data signal DQ based on the feedback signal Fb, so as to improve the accuracy of the first output signal Vout and the second output signal VoutN output by the second amplification module 102, thereby reducing the impact of inter-symbol interference of the received data signal DQ on the data receiving circuit 100.

[0043] The following combination Figures 3 to 6 The first amplification module 101 and the second amplification module 102 are described in detail.

[0044] In some embodiments, reference Figure 3 and Figure 4 The first amplification module 101 includes: a first comparison circuit 111 having a first node net1 and a second node net2, configured to receive a data signal DQ and a first reference signal VR+ and perform a first comparison, and output a first signal Sn+ and a second signal Sp+ through the first node net1 and the second node net2 respectively; and a second comparison circuit 121 having a third node net3 and a fourth node net4, configured to receive a data signal DQ and a second reference signal VR- and perform a second comparison, and output a third signal Sn- and a fourth signal Sp- through the third node net3 and the fourth node net4 respectively.

[0045] Specifically, the first comparator circuit 111 amplifies the voltage difference between the data signal DQ and the first reference signal VR+ to output a first signal Sn+ and a second signal Sp+, meaning that the first and second signals Sn+ and Sp+ are influenced by the data signal DQ and the first reference signal VR+. The second comparator circuit 121 amplifies the voltage difference between the data signal DQ and the second reference signal VR- to output a third signal Sn- and a fourth signal Sp-, meaning that the third and fourth signals Sn- and Sp- are influenced by the data signal DQ and the second reference signal VR-. Therefore, when the second amplification module 102 receives the first signal pair based on the feedback signal Fb and outputs the first output signal Vout and the second output signal VoutN, the first and second output signals VoutN are influenced by the first signal Sn+ and the second signal Sp+; when the second amplification module 102 receives the second signal pair based on the feedback signal Fb and outputs the first and second output signals VoutN, the first and second output signals VoutN are influenced by the third signal Sn- and the fourth signal Sp-.

[0046] It is evident that regardless of whether the data signal DQ received by the first amplification module 101 is high or low, the difference in level between the first signal Sn+ and the second signal Sp+ will be greater than the difference in level between the third signal Sn- and the fourth signal Sp-. Based on the feedback signal Fb, the second amplification module 102 can selectively select the signal with the greater voltage difference between the first signal pair and the second signal pair. That is, the data receiving circuit 100 uses the first reference signal VR+ and the second reference signal VR- to improve the adjustment capability of the data receiving circuit 100 on the received data signal DQ. In other words, when there is inter-symbol interference in the data signal DQ received by the data receiving circuit 100, the second amplification module 102 receives the pair of signals from the first amplification module 101 that processes the data signal DQ better based on the feedback signal Fb, so as to further adjust the first output signal Vout and the second output signal VoutN affected by the signal pair.

[0047] In some embodiments, continue to refer to Figure 3 and Figure 4 The first comparator circuit 111 may include: a first current source 1111, configured to be connected to the power supply node Vcc (reference). Figure 5 Between the first current source 1111 and the fifth node net5, current is supplied to the fifth node net5 in response to the sampling clock signal clkN; the first comparison unit 1112, connected to the first node net1, the second node net2 and the fifth node net5, is configured to receive the data signal DQ and the first reference signal VR+, perform a first comparison when the first current source 1111 supplies current to the fifth node net5, and output the first signal Sn+ and the second signal Sp+; the second comparison circuit 121 may include: a second current source 1211, configured to be connected between the power supply node Vcc and the sixth node net6, supplying current to the sixth node net6 in response to the sampling clock signal clkN; the second comparison unit 1212, connected to the third node net3, the fourth node net4 and the sixth node net6, is configured to receive the data signal DQ and the second reference signal VR-, perform a second comparison when the second current source 1211 supplies current to the sixth node net6, and output the third signal Sn- and the fourth signal Sp-.

[0048] Understandably, the first comparison unit 1112 can control the difference between the current supplied to the first node net1 and the current supplied to the second node net2 based on the voltage difference between the data signal DQ and the first reference signal VR+, so as to output the first signal Sn+ and the second signal Sp+; the second comparison unit 1212 can control the difference between the current supplied to the third node net3 and the current supplied to the fourth node net4 based on the voltage difference between the data signal DQ and the second reference signal VR-, so as to output the third signal Sn- and the fourth signal Sp-.

[0049] In some embodiments, the circuit structure of the first current source 1111 is the same as that of the second current source 1211; the circuit structure of the first comparison unit 1112 is the same as that of the second comparison unit 1212. This is advantageous because the difference between the first signal pair output by the first comparison circuit 111 and the second signal pair output by the second comparison circuit 121 is mainly affected by the first reference signal VR+ and the second reference signal VR-. Furthermore, this is advantageous because the data receiving circuit 100 reduces the impact of inter-symbol interference of the received data signal DQ on the data receiving circuit 100 based on the first reference signal VR+ and the second reference signal VR-, thereby further improving the accuracy of the first output signal Vout and the second output signal VoutN output by the second amplification module 102.

[0050] In some embodiments, reference Figure 5 The first current source 1111 may include: a first PMOS transistor MP1, connected between power node Vcc and fifth node net5, the gate of the first PMOS transistor MP1 receiving the sampling clock signal clkN; the second current source 1211 includes: a second PMOS transistor MP2, connected between power node Vcc and sixth node net6, the gate of the second PMOS transistor MP2 receiving the sampling clock signal clkN. When the sampling clock signal clkN is low, the gate of the first PMOS transistor MP1 receives the sampling clock signal clkN and is turned on, providing current to the fifth node net5, so that the first comparison unit 1112 is in working state, performing a first comparison on the received data signal DQ and the first reference signal VR+; the gate of the second PMOS transistor MP2 receives the sampling clock signal clkN and is turned on, providing current to the sixth node net6, so that the second comparison unit 1212 is in working state, performing a second comparison on the received data signal DQ and the second reference signal VR+.

[0051] In some embodiments, continue to refer to Figure 5 The first comparison unit 1112 may include: a third PMOS transistor MP3, connected between the first node net1 and the fifth node net5, the gate of the third PMOS transistor MP3 receiving the data signal DQ; and a fourth PMOS transistor MP4, connected between the second node net2 and the fifth node net5, the gate of the fourth PMOS transistor MP4 receiving the first reference signal VR+; the second comparison unit 1212 may include: a fifth PMOS transistor MP5, connected between the third node net3 and the sixth node net6, the gate of the fifth PMOS transistor MP5 receiving the data signal DQ; and a sixth PMOS transistor MP6, connected between the fourth node net4 and the sixth node net6, the gate of the sixth PMOS transistor MP6 receiving the second reference signal VR-.

[0052] It should be noted that, for the first comparison unit 1112, the level changes of the data signal DQ and the first reference signal VR+ are asynchronous. This causes the turn-on time of the third PMOS transistor MP3, which receives the data signal DQ, to differ from the turn-on time of the fourth PMOS transistor MP4, which receives the first reference signal VR+. Furthermore, at the same time, the conduction degree of the third PMOS transistor MP3 differs from that of the fourth PMOS transistor MP4. Understandably, because the conduction degree of the third PMOS transistor MP3 differs from that of the fourth PMOS transistor MP4, the current shunting capabilities of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 at the fifth node net5 are also different. This results in a difference between the voltage at the first node net1 and the voltage at the second node net2, which is beneficial for outputting the first signal Sn+ and the second signal Sp+ as a first signal pair with a significant difference in signal level.

[0053] For the second comparison unit 1212, the level changes of the data signal DQ and the second reference signal VR- are asynchronous. This causes the turn-on time of the fifth PMOS transistor MP5, which receives the data signal DQ, to differ from the turn-on time of the sixth PMOS transistor MP6, which receives the second reference signal VR-. Furthermore, at the same time, the conduction degree of the fifth PMOS transistor MP5 differs from that of the sixth PMOS transistor MP6. It is understandable that, based on the difference in conduction degree between the fifth and sixth PMOS transistors MP5 and MP6, their current shunting capabilities at the sixth node net6 also differ. This results in a difference between the voltage at the third node net3 and the voltage at the fourth node net4, which is beneficial for outputting the third signal Sn- and the fourth signal Sp- as a second signal pair with a significant difference in signal level.

[0054] In one example, when the level of the data signal DQ is lower than the level of the first reference signal VR+, the conduction degree of the third PMOS transistor MP3 is greater than that of the fourth PMOS transistor MP4. This causes more current to flow into the path of the third PMOS transistor MP3 at the fifth node net5, making the current at the first node net1 greater than the current at the second node net2. Consequently, the level of the first signal Sn+ output by the first node net1 is higher, and the level of the second signal Sp+ output by the second node net2 is lower. When the level of the data signal DQ is lower than the level of the second reference signal VR-, the conduction degree of the fifth PMOS transistor MP5 is greater than that of the sixth PMOS transistor MP6. This causes more current to flow into the path of the fifth PMOS transistor MP5 at the sixth node net6, making the current at the third node net3 greater than the current at the fourth node net4. Consequently, the level of the third signal Sn- output by the third node net3 is higher, and the level of the fourth signal Sp- output by the fourth node net4 is lower.

[0055] Similarly, when the level of the data signal DQ is higher than the level of the first reference signal VR+, the conduction degree of the third PMOS transistor MP3 is less than that of the fourth PMOS transistor MP4, the level of the first signal Sn+ output by the first node net1 is low, and the level of the second signal Sp+ output by the second node net2 is high; when the level of the data signal DQ is higher than the level of the second reference signal VR-, the conduction degree of the fifth PMOS transistor MP5 is less than that of the sixth PMOS transistor MP6, the level of the third signal Sn- output by the third node net3 is low, and the level of the fourth signal Sp- output by the fourth node net4 is high.

[0056] In some embodiments, reference Figure 3 and Figure 4 The first amplification module 101 may further include: a first reset unit 131, connected to the first node net1 and the second node net2, configured to reset the first node net1 and the second node net2; and a second reset unit 141, connected to the third node net3 and the fourth node net4, configured to reset the third node net3 and the fourth node net4. Thus, after the data receiving circuit 100 completes the reception of a data signal DQ, a first reference signal VR+, and a second reference signal VR-, and the output of a first output signal Vout and a second output signal VoutN, the first reset unit 131 can restore the level values ​​at the first node net1 and the second node net2 to their initial values, and the second reset unit 141 can restore the level values ​​at the third node net3 and the fourth node net4 to their initial values, so that the subsequent data receiving circuit 100 can perform the next data reception and processing.

[0057] In some embodiments, reference Figure 5 The first reset unit 131 may include: a first NMOS transistor MN1, connected between the first node net1 and ground, the gate of the first NMOS transistor MN1 receiving the first reset signal WckN; a second NMOS transistor MN2, connected between the second node net2 and ground, the gate of the second NMOS transistor MN2 receiving the first reset signal WckN; the second reset unit 141 may include: a third NMOS transistor MN3, connected between the third node net3 and ground, the gate of the third NMOS transistor MN3 receiving the first reset signal WckN; and a fourth NMOS transistor MN4, connected between the fourth node net4 and ground, the gate of the fourth NMOS transistor MN4 receiving the first reset signal WckN.

[0058] In one example, when the sampling clock signal clkN is low, both the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on. At this time, the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are all turned off to ensure the normal operation of the data receiving circuit 100. Simultaneously, the first NMOS transistor MN1 and the second NMOS transistor MN2 can serve as loads for the first comparator unit 1112 to increase its amplification gain. The third NMOS transistor MN3 and the fourth NMOS transistor MN4 can serve as loads for the second comparator unit 1212 to increase its amplification gain. The amplification gain is 12. When the sampling clock signal clkN is high, the first PMOS transistor MP1 and the second PMOS transistor MP2 are both turned off, and no current flows through the first comparator unit 1112 and the second comparator unit 1212. At this time, the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are all turned on. The voltage at the first node net1, the second node net2, the third node net3 and the fourth node net4 are pulled down to reset the first node net1, the second node net2, the third node net3 and the fourth node net4.

[0059] It should be noted that the first reset signal WckN and the sampling clock signal clkN can be the same clock signal, or they can be different clock signals with the same phase but different amplitudes.

[0060] In some embodiments, reference Figure 6 The second amplification module 102 may include: a first input unit 112, connected to the seventh node net7 and the eighth node net8, configured to respond to the feedback signal Fb (reference). Figure 1The first input unit 112 and the second input unit 122 are configured to receive and compare the first signal pair in response to the feedback signal Fb, and provide signals to the seventh node net7 and the eighth node net8 respectively; wherein, the first input unit 112 and the second input unit 122 are selectively turned on based on the feedback signal Fb; the latching unit 132 is configured to amplify and latch the signals of the seventh node net7 and the eighth node net8, and output the first output signal Vout and the second output signal VoutN through the first output node net9 and the second output node net10 respectively.

[0061] The first input unit 112 is used to compare the first signal Sn+ and the second signal Sp+ to provide signals to the seventh node net7 and the eighth node net8; the second input unit 122 is used to compare the third signal Sn- and the fourth signal Sp- to provide signals to the seventh node net7 and the eighth node net8; the latch unit 132 is used to output a high-level signal to the first output node net9 and a low-level signal to the second output node net10 according to the signals of the seventh node net7 and the eighth node net8, or output a low-level signal to the first output node net9 and a high-level signal to the second output node net10.

[0062] In some embodiments, reference Figure 6 Feedback signal Fb (reference) Figure 1 It includes a differential first feedback signal Fb+ and a second feedback signal Fb-; the first input unit 112 turns on in response to the first feedback signal Fb+, and the second input unit 122 turns on in response to the second feedback signal Fb-.

[0063] In one example, when the first feedback signal Fb+ is high and the second feedback signal Fb- is low, the first input unit 112 turns on in response to the first feedback signal Fb+, and the second input unit 122 turns off in response to the second feedback signal Fb-. That is, the first output signal Vout and the second output signal VoutN are obtained based on the first signal Sn+ and the second signal Sp+ received by the first input unit 112. In another example, when the first feedback signal Fb+ is low and the second feedback signal Fb- is high, the first input unit 112 turns off in response to the first feedback signal Fb+, and the second input unit 122 turns on in response to the second feedback signal Fb-. That is, the first output signal Vout and the second output signal VoutN are obtained based on the third signal Sn- and the fourth signal Sp- received by the second input unit 122.

[0064] In some embodiments, continue to refer to Figure 6 The first input unit 112 may include: a fifth NMOS transistor MN5 and a sixth NMOS transistor MN6, wherein the drain of the fifth NMOS transistor MN5 is connected to the seventh node net7, the source of the fifth NMOS transistor MN5 is connected to the drain of the sixth NMOS transistor MN6, and the source of the sixth NMOS transistor MN6 is connected to ground. The gate of the fifth NMOS transistor MN5 receives either a first signal Sn+ or a first feedback signal Fb+, and the gate of the sixth NMOS transistor MN6 receives the other of the first signal Sn+ or the first feedback signal Fb+. The second input unit 112 may also include: a seventh NMOS transistor MN7 and an eighth NMOS transistor MN8, wherein the drain of the seventh NMOS transistor MN7 is connected to the eighth node net8, the source of the seventh NMOS transistor MN7 is connected to the drain of the eighth NMOS transistor MN8, and the source of the eighth NMOS transistor MN8 is connected to ground. The gate of the seventh NMOS transistor MN7 receives either a second signal Sp+ or the first feedback signal Fb+, and the gate of the eighth NMOS transistor MN8 receives the other of the second signal Sp+ or the first feedback signal Fb+.

[0065] It should be noted that, Figure 6 The example uses the gate of the fifth NMOS transistor MN5 receiving the first feedback signal Fb+, the gate of the sixth NMOS transistor MN6 receiving the first signal Sn+, the gate of the seventh NMOS transistor MN7 receiving the first feedback signal Fb+, and the gate of the eighth NMOS transistor MN8 receiving the second signal Sp+. In practical applications, it can also be the gate of the fifth NMOS transistor MN5 receiving the first signal Sn+, the gate of the sixth NMOS transistor MN6 receiving the first feedback signal Fb+, the gate of the seventh NMOS transistor MN7 receiving the second signal Sp+, and the gate of the eighth NMOS transistor MN8 receiving the first feedback signal Fb+.

[0066] In one example, when the level of the data signal DQ is higher than the level of the first reference signal VR+, the level of the first signal Sn+ is low, and the level of the second signal Sp+ is high. If the first input unit 112 is turned on in response to the first feedback signal Fb+, the gate of the sixth NMOS transistor MN6 receives the first signal Sn+, and the gate of the eighth NMOS transistor MN8 receives the second signal Sp+. Then, the conduction degree of the eighth NMOS transistor MN8 is greater than that of the sixth NMOS transistor MN6, making the voltage at the eighth node net8 less than the voltage at the seventh node net7. This makes the conduction degree of the fourteenth NMOS transistor MN14 greater than that of the thirteenth NMOS transistor MN13. The voltage at the second output node net10 is less than the voltage at the first output node net9. Therefore, the conduction degree of the eighth PMOS transistor MP8 is less than that of the seventh PMOS transistor MP7. The latch unit 132 forms positive feedback amplification, further making the first output signal Vout output by the first output node net9 high and the second output signal VoutN output by the second output node net10 low. Similarly, when the level of the data signal DQ is lower than the level of the first reference signal VR+, the level of the first signal Sn+ is high and the level of the second signal Sp+ is low. If the first input unit 112 is turned on in response to the first feedback signal Fb+, the first output signal Vout output by the first output node net9 is low and the second output signal VoutN output by the second output node net10 is high.

[0067] In some embodiments, the second input unit 122 may include: a ninth NMOS transistor MN9 and a tenth NMOS transistor MN10, wherein the drain of the ninth NMOS transistor MN9 is connected to the seventh node net7, the source of the ninth NMOS transistor MN9 is connected to the drain of the tenth NMOS transistor MN10, and the source of the tenth NMOS transistor MN10 is connected to ground; wherein the gate of the ninth NMOS transistor MN9 receives either a third signal Sn- or a second feedback signal Fb-, and the gate of the tenth NMOS transistor MN10 receives either the third signal Sn- or the second feedback signal Fb-. The other one consists of an eleventh NMOS transistor MN11 and a twelfth NMOS transistor MN12. The drain of the eleventh NMOS transistor MN11 is connected to the eighth node net8, and the source of the eleventh NMOS transistor MN11 is connected to the drain of the twelfth NMOS transistor MN12. The source of the twelfth NMOS transistor MN12 is connected to ground. The gate of the eleventh NMOS transistor MN11 receives either the fourth signal Sp- or the second feedback signal Fb-, and the gate of the twelfth NMOS transistor MN12 receives the other of the fourth signal Sp- or the second feedback signal Fb-.

[0068] It should be noted that, Figure 6In the example, the gate of the ninth NMOS transistor MN9 receives the second feedback signal Fb-, the gate of the tenth NMOS transistor MN10 receives the third signal Sn-, the gate of the eleventh NMOS transistor MN11 receives the second feedback signal Fb-, and the gate of the twelfth NMOS transistor MN12 receives the fourth signal Sp-. In practical applications, it can also be that the gate of the ninth NMOS transistor MN9 receives the third signal Sn-, the gate of the tenth NMOS transistor MN10 receives the second feedback signal Fb-, the gate of the eleventh NMOS transistor MN11 receives the fourth signal Sp-, and the gate of the twelfth NMOS transistor MN12 receives the second feedback signal Fb-.

[0069] In one example, when the level of the data signal DQ is higher than the level of the second reference signal VR-, the level of the third signal Sn- is low and the level of the fourth signal Sp- is high. If the second input unit 122 is turned on in response to the second feedback signal Fb-, the gate of the tenth NMOS transistor MN10 receives the third signal Sn-, and the gate of the twelfth NMOS transistor MN12 receives the fourth signal Sp-. Then, the conduction degree of the twelfth NMOS transistor MN12 is greater than that of the tenth NMOS transistor MN10, making the voltage at the eighth node net8 less than the voltage at the seventh node net7. As a result, the first output signal Vout output by the first output node net9 is high and the second output signal VoutN output by the second output node net10 is low. Similarly, when the level of the data signal DQ is lower than the level of the second reference signal VR-, the level of the third signal Sn- is high and the level of the fourth signal Sp- is low. If the second input unit 122 is turned on in response to the second feedback signal Fb-, the first output signal Vout output by the first output node net9 is low and the second output signal VoutN output by the second output node net10 is high.

[0070] It should be noted that when multiple data receiving circuits 100 are cascaded, the feedback signal Fb based on previously received data means that: the first output signal Vout and the second output signal VoutN output by the previous stage data receiving circuit 100 serve as the feedback signal Fb of the next stage data receiving circuit 100, and the first output signal Vout and the second output signal VoutN output by the last stage data receiving circuit 100 serve as the feedback signal Fb of the first stage data receiving circuit 100. Specifically, the first output signal Vout output by the first output node net9 of the previous stage data receiving circuit 100 serves as the first feedback signal Fb+ of the next stage data receiving circuit 100; the second output signal VoutN output by the second output node net10 of the previous stage data receiving circuit 100 serves as the second feedback signal Fb- of the next stage data receiving circuit 100; the first output signal Vout output by the first output node net9 of the last stage data receiving circuit 100 serves as the first feedback signal Fb+ of the first stage data receiving circuit 100; and the second output signal VoutN output by the second output node net10 of the last stage data receiving circuit 100 serves as the second feedback signal Fb- of the first stage data receiving circuit 100.

[0071] Understandably, when the first output signal Vout from the first output node net9 of the preceding data receiving circuit 100 is high and the second output signal VoutN from the second output node net10 is low, the first feedback signal Fb+ received by the next-stage data receiving circuit 100 is high and the second feedback signal Fb- is low. The first input unit 112 in the next-stage data receiving circuit 100 is turned on in response to the first feedback signal Fb+, and the second input unit 122 is turned off in response to the second feedback signal Fb-. Conversely, when the first output signal Vout from the first output node net9 of the preceding data receiving circuit 100 is low and the second output signal VoutN from the second output node net10 is high, the first feedback signal Fb+ received by the next-stage data receiving circuit 100 is low and the second feedback signal Fb- is high. The first input unit 112 in the next-stage data receiving circuit 100 is turned off in response to the first feedback signal Fb+, and the second input unit 122 is turned on in response to the second feedback signal Fb-.

[0072] In some embodiments, reference Figure 6The latch unit 132 may include: a thirteenth NMOS transistor MN13 and a seventh PMOS transistor MP7, the gates of the thirteenth NMOS transistor MN13 and the seventh PMOS transistor MP7 are both connected to the second output node net10, the source of the thirteenth NMOS transistor MN13 is connected to the seventh node net7, the drains of the thirteenth NMOS transistor MN13 and the seventh PMOS transistor MP7 are both connected to the first output node net9, and the source of the seventh PMOS transistor MP7 is connected to the power supply node Vcc; a fourteenth NMOS transistor MN14 and an eighth PMOS transistor MP8, the gates of the fourteenth NMOS transistor MN14 and the eighth PMOS transistor MP8 are both connected to the first output node net9, the source of the fourteenth NMOS transistor MN14 is connected to the eighth node net8, the drains of the fourteenth NMOS transistor MN14 and the eighth PMOS transistor MP8 are both connected to the second output node net10, and the source of the eighth PMOS transistor MP8 is connected to the power supply node Vcc.

[0073] In some embodiments, reference Figure 6 The second amplification module 102 may further include a third reset unit 142, connected between the power supply node Vcc and the output terminal of the latch unit 132, configured to reset the output terminal of the latch unit 132. Thus, after the data receiving circuit 100 completes the reception of a data signal DQ, a first reference signal VR+, and a second reference signal VR-, and the output of a first output signal Vout and a second output signal VoutN, the third reset unit 142 can restore the level values ​​at the first output node net9 and the second output node net10 to their initial values, so that the subsequent data receiving circuit 100 can perform the next data reception and processing.

[0074] In some embodiments, continue to refer to Figure 6 The output of latch unit 132 includes a first output node net9 and a second output node net10; the third reset unit 142 may include: a ninth PMOS transistor MP9, connected between the first output node net9 and the power supply node Vcc, the gate of the ninth PMOS transistor MP9 receiving the second reset signal clk; and a tenth PMOS transistor MP10, connected between the second output node net10 and the power supply node Vcc, the gate of the tenth PMOS transistor MP10 receiving the second reset signal clk.

[0075] In one example, the second reset signal clk samples the inverted signal of the clock signal clkN, combined with a reference. Figure 5 and Figure 6When the sampling clock signal clkN is low, both the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on, while the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are turned off. The second reset signal clk is high, and the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 are turned off to ensure the normal operation of the data receiving circuit 100. When the sampling clock signal clkN is high, both the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned off, while the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are turned on. The second reset signal clk is low, and the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 are also turned on. This pulls up the voltage at the first output node net9 and the second output node net10 to reset the first output node net9 and the second output node net10.

[0076] The following combination Figure 6 Table 1 provides a detailed description of the specific working principle of the data receiving circuit 100 improved according to an embodiment of the present disclosure.

[0077] In one example, when multiple data receiving circuits 100 are cascaded, the first output signal Vout output by the first output node net9 of the previous stage data receiving circuit 100 serves as the first feedback signal Fb+ of the next stage data receiving circuit 100, the second output signal VoutN output by the second output node net10 of the previous stage data receiving circuit 100 serves as the second feedback signal Fb- of the next stage data receiving circuit 100, the first output signal Vout output by the first output node net9 of the last stage data receiving circuit 100 serves as the first feedback signal Fb+ of the first stage data receiving circuit 100, and the second output signal VoutN output by the second output node net10 of the last stage data receiving circuit 100 serves as the second feedback signal Fb- of the first stage data receiving circuit 100.

[0078] The following explanation uses the example of the received first reference signal VR+ having a higher level than the second reference signal VR-. In one example, the level of the first reference signal VR+ can be 0.7V, the level of the second reference signal VR- can be 0.3V, and when the data signal DQ is at logic level 1, it indicates that the level of the data signal DQ is greater than the level of the first reference signal VR+; when the data signal DQ is at logic level 0, it indicates that the level of the data signal DQ is less than the level of the second reference signal VR-.

[0079] Referring to Table 1, if the data signal DQ1 received by the previous stage data receiving circuit 100 is at logic level 1, the first output signal Vout output by the previous stage data receiving circuit 100, i.e., the first feedback signal Fb+ of the next stage data receiving circuit 100, is at a high level (represented by logic level 1 in Table 1). The second output signal VoutN output by the previous stage data receiving circuit 100, i.e., the second feedback signal Fb- of the next stage data receiving circuit 100, is at a low level (represented by logic level 0 in Table 1). At this time, the gates of the fifth NMOS transistor MN5 and the seventh NMOS transistor MN7 receive the first feedback signal Fb+ to conduct, and the gates of the ninth NMOS transistor MN9 and the eleventh NMOS transistor MN11 receive the second feedback signal Fb- to disconnect. The first input unit 112 is used to compare the first signal Sn+ and the second signal Sp+ to provide signals to the seventh node net7 and the eighth node net8. No current flows through the second input unit 122.

[0080] When the data signal DQ1 received by the previous stage data receiving circuit 100 is at logic level 1, the data signal DQ2 received by the next stage data receiving circuit 100 will fall into the following two categories:

[0081] Scenario 1: Referring to Table 1, when the data signal DQ2 received by the next-stage data receiving circuit 100 is at logic level 0, the level difference between it and the data signal DQ1 received by the previous-stage data receiving circuit 100 is large, resulting in significant inter-symbol interference. At this time, the first input unit 112 in the next-stage data receiving circuit 100 is turned on, meaning that the second amplification module 102 in the next-stage data receiving circuit 100 receives the first signal Sn+ and the second signal Sp+. The first signal pair output by the first comparison circuit 111 in the next-stage data receiving circuit 100 is received by the second amplification module 102. At this time, in the next-stage data receiving circuit 100, the data signal DQ2 is at logic level 0. The voltage difference between the data signal DQ2 and the first reference signal VR+ is greater than the voltage difference between the data signal DQ2 and the second reference signal VR-. Therefore, the difference in the level values ​​of the first signal pair obtained after processing by the first comparison circuit 111 is even greater. At this time, the second amplification module 102 receiving the first signal pair is more conducive to outputting the first output signal Vout and the second output signal VoutN with higher accuracy, so as to reduce the impact of inter-symbol interference of the received data signal DQ on the data receiving circuit 100.

[0082] Scenario 2: Referring to Table 1, when the data signal DQ2 received by the next-stage data receiving circuit 100 is at logic level 1, the difference in level between it and the data signal DQ1 received by the previous-stage data receiving circuit 100 is small, and there is little or no inter-symbol interference. At this time, the first input unit 112 in the next-stage data receiving circuit 100 is turned on, and the first signal output by the first comparison circuit 111 in the next-stage data receiving circuit 100 is received by the second amplification module 102.

[0083] Referring to Table 1, if the data signal DQ1 received by the previous stage data receiving circuit 100 is at logic level 0, the first output signal Vout of the previous stage data receiving circuit 100, i.e. the first feedback signal Fb+ of the next stage data receiving circuit 100, is at a low level, represented by logic level 0 in Table 1. The second output signal VoutN of the previous stage data receiving circuit 100, i.e. the second feedback signal Fb- of the next stage data receiving circuit 100, is at a high level, represented by logic level 1 in Table 1. At this time, the gates of the fifth NMOS transistor MN5 and the seventh NMOS transistor MN7 receive the first feedback signal Fb+ to disconnect, and the gates of the ninth NMOS transistor MN9 and the eleventh NMOS transistor MN11 receive the second feedback signal Fb- to conduct. The second input unit 122 is used to compare the third signal Sn- and the fourth signal Sp- to provide signals to the seventh node net7 and the eighth node net8. No current flows through the first input unit 112.

[0084] When the data signal DQ1 received by the previous stage data receiving circuit 100 is at logic level 0, the data signal DQ2 received by the next stage data receiving circuit 100 will fall into the following two categories:

[0085] Scenario 3: Referring to Table 1, when the data signal DQ2 received by the next-stage data receiving circuit 100 is at logic level 0, the difference in level between it and the data signal DQ1 received by the previous-stage data receiving circuit 100 is small, and there is little or no inter-symbol interference. At this time, the second input unit 122 in the next-stage data receiving circuit 100 is turned on, and the second signal output by the second comparison circuit 121 in the next-stage data receiving circuit 100 is received by the second amplification module 102.

[0086] Scenario 4: Referring to Table 1, when the data signal DQ2 received by the next-stage data receiving circuit 100 is at logic level 1, the level difference between it and the data signal DQ1 received by the previous-stage data receiving circuit 100 is large, resulting in significant inter-symbol interference. At this time, the second input unit 122 in the next-stage data receiving circuit 100 is turned on, meaning that the second amplification module 102 in the next-stage data receiving circuit 100 receives the third signal Sn- and the fourth signal Sp-. The second signal pair output by the second comparison circuit 121 in the next-stage data receiving circuit 100 is received by the second amplification module 102. At this time, in the next-stage data receiving circuit 100, the data signal DQ2 is at logic level 1. The voltage difference between the data signal DQ2 and the second reference signal VR- is greater than the voltage difference between the data signal DQ2 and the first reference signal VR+. Therefore, the difference in the level values ​​of the second signal pair obtained after processing by the second comparison circuit 121 is even greater. At this time, the second amplification module 102 receiving the second signal pair is more conducive to outputting the first output signal Vout and the second output signal VoutN with higher accuracy, so as to reduce the impact of inter-symbol interference of the received data signal DQ on the data receiving circuit 100.

[0087] Table 1

[0088]

[0089] It should be noted that in the above descriptions of high and low voltage levels, a high voltage level can be a voltage value greater than or equal to the power supply voltage, and a low voltage level can be a voltage value less than or equal to the ground voltage. Furthermore, high and low voltage levels are relative, and the specific range of voltage values ​​included in high and low voltage levels can be determined according to the specific device. For example, for an NMOS transistor, a high voltage level refers to the range of gate voltage values ​​that enable the NMOS transistor to conduct, and a low voltage level refers to the range of gate voltage values ​​that enable the NMOS transistor to turn off; for a PMOS transistor, a low voltage level refers to the range of gate voltage values ​​that enable the PMOS transistor to conduct, and a high voltage level refers to the range of gate voltage values ​​that enable the PMOS transistor to turn off.

[0090] In summary, by using the first reference signal VR+ and the second reference signal VR- to perform a first comparison and a second comparison on the data signal DQ, respectively, a first signal pair and a second signal pair are obtained. Since the level values ​​of the first reference signal VR+ and the second reference signal VR- are different, for data signals DQ with different level values, it is possible to satisfy the condition that the level difference between the data signal DQ and either the first reference signal VR+ or the second reference signal VR- is significant. Therefore, when inter-symbol interference exists in the data signal DQ received by the data receiving circuit 100, it is beneficial for the subsequent second amplification module 102 to receive the first signal pair and the second signal pair based on the feedback signal Fb. The first reference signal VR+ and the second reference signal VR- are used to improve the adjustment capability of the data receiving circuit 100 on the received data signal DQ, thereby reducing the impact of inter-symbol interference of the received data signal DQ on the data receiving circuit 100. Subsequently, the second amplification module 102 selects to receive the signal with the larger level difference between the first signal pair and the second signal pair based on the feedback signal Fb. This helps ensure that the second amplification module 102 receives a pair of differential signals with a large difference in signal level, thereby improving the accuracy of the first output signal Vout and the second output signal VoutN output by the second amplification module 102. Therefore, the cooperation between the first amplification module 101 and the second amplification module 102 helps improve the receiving performance of the data receiving circuit 100.

[0091] Another embodiment of this disclosure also provides a data receiving system, which will be described in detail below with reference to the accompanying drawings. Figure 2 A functional block diagram of a data receiving system provided in another embodiment of this disclosure.

[0092] refer to Figure 2 The data receiving system includes: multiple cascaded data transmission circuits 120, each data transmission circuit 120 including a data receiving circuit 100 as described in one embodiment of the present disclosure and a latching circuit 110 connected to the data receiving circuit 100; the output signal of the previous level data transmission circuit 120 serves as the feedback signal Fb of the next level data transmission circuit 120; the output signal of the last level data transmission circuit 120 serves as the feedback signal Fb of the first level data transmission circuit 120.

[0093] The latch circuit 110 is configured to correspond one-to-one with the data receiving circuit 100. The latch circuit 110 is used to latch and output the signal output by the data receiving circuit 100 corresponding to the latch circuit 110.

[0094] In some embodiments, the data receiving circuit 100 responds to the sampling clock signal clkN (reference). Figure 3The system receives data; and the data receiving system includes four cascaded data receiving circuits 100, with a 90° phase difference between the sampling clock signals clkN of adjacent data receiving circuits 100. Thus, the period of the sampling clock signal clkN is twice the period of the data signal DQ received by the data port, which is beneficial for clock routing and saves power consumption.

[0095] It should be noted that, Figure 1 The Sino-Israeli data receiving system includes four cascaded data receiving circuits 100. Taking the phase difference of the sampling clock signals of adjacent data receiving circuits 100 as an example, the number of cascaded data receiving circuits 100 included in the data receiving system is not limited in practical applications. The phase difference of the sampling clock signals of adjacent data receiving circuits 100 can be reasonably set based on the number of cascaded data receiving circuits 100.

[0096] In some embodiments, the feedback signal Fb of the next-level data transmission circuit 120 is the output signal of the previous-level data receiving circuit 100 or the output signal of the previous-level latch circuit 110; the feedback signal Fb of the first-level data transmission circuit 120 is the output signal of the last-level data receiving circuit 100 or the output signal of the last-level latch circuit 110. That is, in one example, the feedback signal Fb of the next-level data transmission circuit 120 is the output signal of the previous-level data receiving circuit 100. In this way, the output of the data receiving circuit 100 is directly transmitted to the next-level data transmission circuit 120 without going through the latch circuit 110, which helps to reduce data transmission delay; in another example, the feedback signal Fb of the next-level data transmission circuit 120 is the output signal of the previous-level latch circuit 110.

[0097] In summary, the data receiving system provided in another embodiment of this disclosure can use the first reference signal VR+ and the second reference signal VR- to perform a first comparison and a second comparison on the data signal DQ, respectively, to obtain a first signal pair and a second signal pair. For data signals DQ with different level values, it can satisfy the requirement that the level value difference between the data signal DQ and one of the first reference signal VR+ or the second reference signal VR- is large. Therefore, when there is inter-symbol interference in the data signal DQ received by the data receiving circuit 100, it is beneficial for the subsequent second amplification module 102 to receive the one with a larger level value difference between the first signal pair and the second signal pair based on the feedback signal Fb, so as to reduce the impact of inter-symbol interference of the received data signal DQ on the data receiving circuit 100. Moreover, it is beneficial to ensure that the second amplification module 102 receives a pair of differential signals with a large difference in signal level value, thereby improving the accuracy of the first output signal Vout and the second output signal VoutN output by the second amplification module 102, and thus improving the receiving performance of the data receiving system.

[0098] Another embodiment of this disclosure also provides a storage device, including: a plurality of data ports; and a plurality of data receiving systems as provided in another embodiment of this disclosure, each data receiving system corresponding to a data port. Thus, each data port in the storage device can flexibly adjust the received data signal DQ through the data receiving system, and improve the adjustment capability of the first output signal Vout and the second output signal VoutN, thereby improving the receiving performance of the storage device.

[0099] In some embodiments, the storage device may be a DDR memory, such as a DDR4 memory, DDR5 memory, DDR6 memory, LPDDR4 memory, LPDDR5 memory, or LPDDR6 memory.

[0100] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A data receiving circuit, characterized in that, include: The first amplification module is configured to receive a data signal, a first reference signal, and a second reference signal; perform a first comparison on the data signal and the first reference signal and output a first signal pair as the result of the first comparison; perform a second comparison on the data signal and the second reference signal and output a second signal pair as the result of the second comparison. Wherein, the level value of the first reference signal is different from the level value of the second reference signal, the first signal pair includes a first signal and a second signal, and the second signal pair includes a third signal and a fourth signal; The second amplification module is configured to select either the first signal pair or the second signal pair as an input signal pair based on a feedback signal, amplify the voltage difference of the input signal pair, and output a first output signal and a second output signal as the result of the amplification process, wherein the feedback signal is obtained based on previously received data; The second amplification module includes: The first input unit, connecting the seventh node and the eighth node, is configured to receive the first signal pair and compare the first signal pair in response to the feedback signal being turned on, and to provide signals to the seventh node and the eighth node respectively; The second input unit, connecting the seventh node and the eighth node, is configured to receive the second signal pair and compare the second signal pair in response to the feedback signal being turned on, and to provide signals to the seventh node and the eighth node respectively; The first input unit and the second input unit are selectively turned on based on the feedback signal; The latching unit, connected to the seventh node and the eighth node, is configured to amplify and latch the signals of the seventh node and the eighth node, and output the first output signal and the second output signal through the first output node and the second output node, respectively.

2. The data receiving circuit as described in claim 1, characterized in that, The first amplification module includes: A first comparison circuit, having a first node and a second node, is configured to receive the data signal and the first reference signal and perform the first comparison, and output the first signal and the second signal through the first node and the second node respectively. The second comparison circuit, having a third node and a fourth node, is configured to receive the data signal and the second reference signal and perform the second comparison, and output the third signal and the fourth signal through the third node and the fourth node, respectively.

3. The data receiving circuit as described in claim 2, characterized in that, The first comparator circuit includes: A first current source is configured to be connected between the power supply node and the fifth node, and to provide current to the fifth node in response to a sampling clock signal; The first comparison unit, connected to the first node, the second node, and the fifth node, is configured to receive the data signal and the first reference signal, perform the first comparison when the first current source provides current to the fifth node, and output the first signal and the second signal. The second comparator circuit includes: A second current source is configured to be connected between the power supply node and the sixth node, and to provide current to the sixth node in response to the sampling clock signal; The second comparison unit, connected to the third node, the fourth node, and the sixth node, is configured to receive the data signal and the second reference signal, perform the second comparison when the second current source provides current to the sixth node, and output the third signal and the fourth signal.

4. The data receiving circuit as described in claim 3, characterized in that, The circuit structure of the first current source is the same as that of the second current source; the circuit structure of the first comparison unit is the same as that of the second comparison unit.

5. The data receiving circuit as described in claim 3, characterized in that, The first current source includes: A first PMOS transistor is connected between the power supply node and the fifth node, and the gate of the first PMOS transistor receives the sampling clock signal. The second current source includes: A second PMOS transistor is connected between the power supply node and the sixth node, and the gate of the second PMOS transistor receives the sampling clock signal.

6. The data receiving circuit as described in claim 3, characterized in that, The first comparison unit includes: A third PMOS transistor is connected between the first node and the fifth node, and the gate of the third PMOS transistor receives the data signal. A fourth PMOS transistor is connected between the second node and the fifth node, and the gate of the fourth PMOS transistor receives the first reference signal; The second comparison unit includes: A fifth PMOS transistor is connected between the third node and the sixth node, and the gate of the fifth PMOS transistor receives the data signal. A sixth PMOS transistor is connected between the fourth node and the sixth node, and the gate of the sixth PMOS transistor receives the second reference signal.

7. The data receiving circuit as described in claim 3, characterized in that, The first amplification module also includes: A first reset unit, connected to the first node and the second node, is configured to reset the first node and the second node; The second reset unit, connected to the third node and the fourth node, is configured to reset the third node and the fourth node.

8. The data receiving circuit as described in claim 7, characterized in that, The first reset unit includes: The first NMOS transistor is connected between the first node and the ground terminal, and the gate of the first NMOS transistor receives the first reset signal; A second NMOS transistor is connected between the second node and the ground terminal, and the gate of the second NMOS transistor receives the first reset signal; The second reset unit includes: A third NMOS transistor is connected between the third node and the ground terminal, and the gate of the third NMOS transistor receives the first reset signal; A fourth NMOS transistor is connected between the fourth node and the ground terminal, and the gate of the fourth NMOS transistor receives the first reset signal.

9. The data receiving circuit as described in claim 1, characterized in that, The feedback signal includes a differential first feedback signal and a second feedback signal; the first input unit is turned on in response to the first feedback signal, and the second input unit is turned on in response to the second feedback signal.

10. The data receiving circuit as described in claim 9, characterized in that, The first input unit includes: A fifth NMOS transistor and a sixth NMOS transistor, wherein the drain of the fifth NMOS transistor is connected to the seventh node, the source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor, and the source of the sixth NMOS transistor is connected to ground, wherein the gate of the fifth NMOS transistor receives one of the first signal or the first feedback signal, and the gate of the sixth NMOS transistor receives the other of the first signal or the first feedback signal; A seventh NMOS transistor and an eighth NMOS transistor are provided, wherein the drain of the seventh NMOS transistor is connected to the eighth node, the source of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor, and the source of the eighth NMOS transistor is connected to the ground terminal. The gate of the seventh NMOS transistor receives either the second signal or the first feedback signal, and the gate of the eighth NMOS transistor receives the other of the second signal or the first feedback signal.

11. The data receiving circuit as described in claim 9, characterized in that, The second input unit includes: The ninth NMOS transistor and the tenth NMOS transistor, wherein the drain of the ninth NMOS transistor is connected to the seventh node, the source of the ninth NMOS transistor is connected to the drain of the tenth NMOS transistor, and the source of the tenth NMOS transistor is connected to ground. The gate of the ninth NMOS transistor receives either the third signal or the second feedback signal, and the gate of the tenth NMOS transistor receives the other of the third signal or the second feedback signal. The eleventh NMOS transistor and the twelfth NMOS transistor, wherein the drain of the eleventh NMOS transistor is connected to the eighth node, the source of the eleventh NMOS transistor is connected to the drain of the twelfth NMOS transistor, and the source of the twelfth NMOS transistor is connected to the ground terminal; The gate of the eleventh NMOS transistor receives either the fourth signal or the second feedback signal, and the gate of the twelfth NMOS transistor receives the other of the fourth signal or the second feedback signal.

12. The data receiving circuit as described in claim 1, characterized in that, The latch unit includes: The thirteenth NMOS transistor and the seventh PMOS transistor are connected to the second output node. The source of the thirteenth NMOS transistor is connected to the seventh node. The drain of the thirteenth NMOS transistor and the drain of the seventh PMOS transistor are connected to the first output node. The source of the seventh PMOS transistor is connected to the power supply node. The fourteenth NMOS transistor and the eighth PMOS transistor are connected to the first output node, the source of the fourteenth NMOS transistor is connected to the eighth node, the drain of the fourteenth NMOS transistor and the drain of the eighth PMOS transistor are connected to the second output node, and the source of the eighth PMOS transistor is connected to the power supply node.

13. The data receiving circuit as described in claim 1, characterized in that, The second amplification module also includes: The third reset unit, connected between the power supply node and the output of the latch unit, is configured to reset the output of the latch unit.

14. The data receiving circuit as described in claim 13, characterized in that, The output of the latch unit includes a first output node and a second output node; the third reset unit includes: The ninth PMOS transistor is connected between the first output node and the power supply node, and the gate of the ninth PMOS transistor receives the second reset signal. The tenth PMOS transistor is connected between the second output node and the power supply node, and the gate of the tenth PMOS transistor receives the second reset signal.

15. A data receiving system, characterized in that, include: Multiple cascaded data transmission circuits, each of the data transmission circuits including a data receiving circuit as described in any one of claims 1-14 and a latching circuit connected to the data receiving circuit; The output signal of the data transmission circuit described in the previous stage serves as the feedback signal of the data transmission circuit described in the next stage. The output signal of the final stage data transmission circuit serves as the feedback signal of the first stage data transmission circuit.

16. The data receiving system as described in claim 15, characterized in that, The data receiving circuit receives data in response to a sampling clock signal; and the data receiving system includes four cascaded data receiving circuits, with a 90° phase difference between the sampling clock signals of adjacent data receiving circuits.

17. The data receiving system as described in claim 15, characterized in that, The feedback signal of the next-level data transmission circuit is the output signal of the previous-level data receiving circuit or the output signal of the previous-level latch circuit; the feedback signal of the first-level data transmission circuit is the output signal of the last-level data receiving circuit or the output signal of the last-level latch circuit.

18. A storage device, characterized in that, include: Multiple data ports; Multiple data receiving systems as described in any one of claims 15 to 17, each of the data receiving systems corresponding to one of the data ports.

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