Semiconductor structure and method of forming the same, layout structure

Abstract

The embodiment of the present disclosure provides a semiconductor structure and a forming method thereof and a layout structure, wherein the method comprises the following steps: providing a substrate; the substrate comprises a first region and a second region arranged in sequence along a second direction; the first region comprises active layers arranged at intervals along a third direction; an initial gate structure is formed on the surface of the active layer in the first region; the initial gate structure is etched to form a comb-shaped gate structure stacked along the third direction; wherein the comb-shaped gate structure comprises at least a first gate structure arranged at intervals in a first direction; the first direction, the second direction and the third direction are perpendicular to each other in pairs, and the first direction and the second direction are parallel to the surface of the substrate; a bit line structure extending along the third direction and a capacitor structure extending along the second direction are formed in the second region, and the bit line structure and the capacitor structure are connected with the first gate structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and its formation method and layout structure. Background Technology

[0002] Currently, 6F is widely used. 2 Dynamic Random Access Memory (DRAM) is fabricated using traditional layout methods and buried word line technology. However, miniaturization of DRAM becomes extremely difficult under this technology. There are also attempts to improve DRAM performance by using new materials, but this undoubtedly increases the process complexity and manufacturing cost of DRAM.

[0003] Based on this, in related technologies, 4F is fabricated using a full-ring gate or dual-gate process. 2 DRAM, 4F 2 DRAM requires the formation of bit line steps or word line steps. However, bit line steps have relatively large sensing noise in DRAM use, while word line steps have word line coupling and the interconnection of word lines on the same plane is difficult to achieve for multi-layer stacking. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, as well as a layout structure.

[0005] In a first aspect, embodiments of this disclosure provide a method for forming a semiconductor structure, the method comprising:

[0006] A substrate is provided; the substrate includes a first region and a second region arranged sequentially along a second direction; the first region includes active layers spaced apart along a third direction;

[0007] An initial gate structure is formed in the first region on the surface of the active layer;

[0008] The initial gate structure is etched to form a comb-shaped gate structure stacked along the third direction; wherein the comb-shaped gate structure includes at least a first gate structure spaced apart in a first direction; the first direction, the second direction, and the third direction are mutually perpendicular, and the first direction and the second direction are parallel to the substrate surface;

[0009] A bit line structure extending along the third direction and a capacitor structure extending along the second direction are formed in the second region, and both the bit line structure and the capacitor structure are connected to the first gate structure.

[0010] In some embodiments, the comb-shaped gate structure further includes a second gate structure that is connected to the first gate structure located in the same layer.

[0011] In some embodiments, the projection of the first gate structure onto the substrate surface is U-shaped.

[0012] In some embodiments, the active layer is formed by the following steps:

[0013] Provide semiconductor substrates;

[0014] A stacked structure located in the first region and the second region is formed on the surface of the semiconductor substrate; the stacked structure includes alternately stacked first semiconductor layers and second semiconductor layers;

[0015] Remove the first semiconductor layer in the first region to expose the second semiconductor layer in the first region;

[0016] The exposed second semiconductor layer is thinned to form an initial active layer;

[0017] The initial active layer is processed to form the active layer.

[0018] In some embodiments, processing the initial active layer to form the active layer includes:

[0019] A sacrificial layer and a first isolation layer are sequentially formed on the surface of the initial active layer; wherein the first isolation layer fills the spaces between the sacrificial layers;

[0020] Remove the initial active layer having a first length in the second direction to form a first space;

[0021] The sacrificial layer having a second length in the second direction is removed, exposing a portion of the initial active layer to form a second space; wherein the second space includes the first space and the second length is greater than the first length, and the exposed portion of the initial active layer constitutes the active layer.

[0022] In some embodiments, an initial gate structure is formed in the first region on the surface of the active layer, including:

[0023] A gate dielectric layer and a gate conductive layer are sequentially formed on the surface of the active layer; wherein the gate conductive layer fills the second space.

[0024] In some embodiments, after forming the comb-shaped gate structure, the method for forming the semiconductor structure further includes:

[0025] Forming a series of stacked word line steps along the third direction;

[0026] Each word line in the word line step is electrically connected to the second gate structure in the corresponding comb-shaped gate structure arranged along the first direction.

[0027] In some embodiments, the comb-shaped gate structure is formed by the following steps:

[0028] Simultaneously, a portion of the initial gate structure and a portion of the stacked structure in the second region are removed to form L-shaped grooves and isolation grooves that are alternately arranged along the first direction, and the remaining initial gate structure constitutes the comb-shaped gate structure.

[0029] Wherein, the size of the isolation groove in the second direction is larger than the size of the L-shaped groove in the second direction; the isolation groove divides the active layer into a plurality of active structures arranged in the first direction.

[0030] In some embodiments, the stacked structures located on both sides of the L-shaped groove in the first direction have different dimensions in the second direction; forming a bit line structure extending along the third direction and a capacitor structure extending along the second direction in the second region includes:

[0031] A second isolation layer is formed by filling the L-shaped groove and the isolation groove with an isolation material.

[0032] The second isolation layer and the first semiconductor layer located in the second region are removed, and the remaining second semiconductor layer forms a first active pillar and a second active pillar arranged alternately along the first direction; wherein, the first active pillar includes a first sub-pillar and a second sub-pillar;

[0033] The capacitor structure is formed on the surface of the second sub-pillar;

[0034] The bitline structure is formed on the surface of the second active post.

[0035] In some embodiments, prior to forming the capacitor structure, the method further includes:

[0036] A support layer is formed on the surface of the first sub-post; wherein the support layer fills the spaces between the first sub-posts.

[0037] In some embodiments, the capacitor structure is formed on the surface of the second sub-pillar, including:

[0038] A first electrode layer, a dielectric layer, and a second electrode layer are sequentially formed on the surface of the second sub-pillar to form the capacitor structure.

[0039] In a second aspect, embodiments of this disclosure provide a semiconductor structure, including:

[0040] A semiconductor substrate, the semiconductor substrate comprising a first region and a second region arranged sequentially along a second direction;

[0041] An active structure located on the surface of the semiconductor substrate; the active structure is arranged in an array along a first direction and a third direction;

[0042] A comb-shaped gate structure is located on the surface of the active structure in the first region, and the comb-shaped gate structure includes at least a first gate structure spaced apart in a first direction;

[0043] Bitline structure extending along the third direction;

[0044] A capacitor structure extending along a second direction; both the bit line structure and the capacitor structure are located on the second region and are connected to the first gate structure; the first direction, the second direction, and the third direction are mutually perpendicular, and the first direction and the second direction are parallel to the surface of the semiconductor substrate.

[0045] In some embodiments, the comb-shaped gate structure further includes a second gate structure that is connected to the first gate structure located in the same layer.

[0046] In some embodiments, the active structure includes a first active post and a second active post located on the second region and arranged along the first direction, and a channel post located on the first region;

[0047] Both the first active post and the second active post are connected to the channel post.

[0048] In some embodiments, the first gate structure covers the first and second surfaces of the channel pillars along the third direction;

[0049] The first gate structure includes a gate dielectric layer and a gate conductive layer stacked together.

[0050] In some embodiments, the projection of the channel pillar onto the semiconductor substrate is U-shaped.

[0051] In some embodiments, the capacitor structure is formed on the first active pillar; the bit line structure is formed on the second active pillar;

[0052] An L-shaped groove is provided between the first active post and the second active post of the same active structure.

[0053] In some embodiments, an isolation groove is provided between adjacent active structures along the first direction;

[0054] The dimension of the isolation groove in the second direction is greater than the dimension of the L-shaped groove in the second direction.

[0055] In some embodiments, the semiconductor structure further includes: word line steps;

[0056] The word line steps are stacked sequentially along the third direction, and each layer of word lines in the word line steps is connected to a plurality of second gate structures in the corresponding comb-shaped gate structure arranged along the first direction.

[0057] Thirdly, embodiments of this disclosure provide a layout structure, including: the aforementioned semiconductor structures arranged at intervals along a second direction;

[0058] The semiconductor structure includes memory cells arranged in an array along a first direction and a third direction; each memory cell includes a first gate structure and a capacitor structure.

[0059] Wherein, two adjacent memory cells in the second direction are centrally symmetrical, and the capacitor structures of two adjacent memory cells in the second direction at least partially overlap in the projection area in the first direction.

[0060] In some embodiments, two adjacent storage cells in the first direction have the same layout or are axially symmetrical.

[0061] In this embodiment of the disclosure, since a comb-shaped gate structure is formed and the gate metal layer on the outside of the comb-shaped gate structure can serve as a word line of the semiconductor structure, the comb-shaped gate structure can not only realize the interconnection of word lines on the same plane in the multi-layer stacked structure, but also realize the control of the size of the word lines, thereby reducing the coupling effect between word line steps. Attached Figure Description

[0062] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0063] Figure 1 A schematic flowchart illustrating a semiconductor structure formation method provided in an embodiment of this disclosure;

[0064] Figures 2a-2m , Figures 3a-3i This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this disclosure;

[0065] Figures 4a-4c This is a schematic diagram of the semiconductor structure provided in the embodiments of this disclosure;

[0066] Figure 5a and 5bThis is a schematic diagram of a planar structure of a semiconductor structure provided in an embodiment of the present disclosure;

[0067] Figure 6a and 6b A plan layout diagram of the layout structure provided in the embodiments of this disclosure;

[0068] The annotations in the attached figures are explained as follows:

[0069] 10—Semiconductor substrate; 11—Stacked structure; 11a—First stacked structure; 11b—Second stacked structure; 111—First semiconductor layer; 112—Second semiconductor layer; 12—Initial active layer; 121—Sacrificial layer; 122—First isolation layer; 13—Active layer; 130—Active structure; 14—Initial gate structure; 141—Gate dielectric layer; 142—Gate conductive layer; 15—L-shaped trench; 16—Isolation trench; 17—Comb gate structure; 171—First gate structure; 172—Second Gate structure; 18—Word line step; 19—Second isolation layer; 131—First active pillar; 1311—First sub-pillar; 1312—Second sub-pillar; 132—Second active pillar; 20—Second protective layer; 21—First protective layer; 221—Third semiconductor layer; 222—Bit line metal layer; 22—Bit line structure; 23—Support layer; 24—Capacitor structure; 241—First electrode layer; 242—Dielectric layer; 243—Second electrode layer; 25—Channel pillar; 100—Semiconductor structure; 200—Layout structure. Detailed Implementation

[0070] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0071] In the following description, numerous details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0072] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0073] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0074] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0075] Before introducing the embodiments of this disclosure, let's define three directions that may be used in the following embodiments to describe the three-dimensional structure. Taking a Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis, and Z-axis. The substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side. Ignoring the flatness of the top and bottom surfaces, the direction perpendicular to the top and bottom surfaces of the substrate is defined as the third direction. In the direction of the top and bottom surfaces of the substrate (i.e., the plane in which the substrate is located), two intersecting (e.g., perpendicular) directions are defined. For example, the direction of the extension of the letter lines can be defined as the first direction, and the direction of the extension of the capacitor structure can be defined as the second direction. The planar orientation of the substrate can be determined based on the first and second directions. Here, the first direction, the second direction, and the third direction are perpendicular to each other. In the embodiments of this disclosure, the first direction is defined as the X-axis, the second direction is defined as the Y-axis, and the third direction is defined as the Z-axis.

[0076] This disclosure provides a method for forming a semiconductor structure. Figure 1This is a schematic flowchart of a semiconductor structure formation method provided in an embodiment of the present disclosure, such as... Figure 1 As shown, the method for forming a semiconductor structure includes the following steps:

[0077] Step S101, providing a substrate; the substrate includes a first region and a second region arranged sequentially along a second direction; the first region includes active layers spaced apart along a third direction.

[0078] In this embodiment of the disclosure, the substrate includes at least a semiconductor substrate, which may be a silicon substrate, or may include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof.

[0079] In this embodiment of the disclosure, the first region and the second region can be used to form different functional structures, for example, the first region can be used to form a gate structure and a stepped word line structure, and the second region can be used to form a capacitor structure and a bit line structure.

[0080] Step S102: Form an initial gate structure located on the surface of the active layer in the first region.

[0081] In this embodiment of the disclosure, the initial gate structure includes a gate dielectric layer and a gate conductive layer located on the surface of the gate dielectric layer.

[0082] Step S103: Etch the initial gate structure to form a comb-shaped gate structure stacked along a third direction; wherein the comb-shaped gate structure includes at least a first gate structure spaced apart in a first direction.

[0083] In this embodiment, the first gate structure can be a dual-gate structure, and the first gate structure covers the first and second surfaces of the active layer along a third direction. The projection of the first gate structure onto the substrate surface can be U-shaped; in other embodiments, the projection of the first gate structure onto the substrate surface can also be rectangular.

[0084] In some embodiments, the comb-shaped gate structure further includes a second gate structure connected to the first gate structure located in the same layer. The second gate structure may be a three-sided ring gate structure, for example, the second gate structure covers a first surface and a second surface of the active layer along a third direction, and covers a surface of the active layer along a second direction.

[0085] In this embodiment of the present disclosure, the dimension of the first gate structure in the second direction can be 2 to 3 times the dimension of the second gate structure in the second direction.

[0086] In this embodiment of the present disclosure, multiple comb-shaped gate structures located on the same layer in the first direction are interconnected through a second gate structure. The gate metal layer of the comb-shaped gate structure can serve as a word line of the semiconductor structure. In this way, not only can the interconnection of word lines on the same plane in the multi-layer stacked structure be realized, but also the size of the word lines can be controlled, thereby reducing the coupling effect between word line steps.

[0087] Step S104: A bit line structure extending along a third direction and a capacitor structure extending along a second direction are formed in the second region. Both the bit line structure and the capacitor structure are connected to the first gate structure.

[0088] The capacitor structure formed in this embodiment extends along a second direction, meaning it is arranged horizontally. This horizontal arrangement reduces the likelihood of tipping or breaking, thus improving stability. Furthermore, multiple horizontal capacitor structures and comb-shaped gate structures can be stacked to form a three-dimensional semiconductor structure, thereby increasing integration and achieving miniaturization.

[0089] Figures 2a-2m , Figures 3a-3i This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this disclosure. The following is in conjunction with... Figures 2a-2m , Figures 3a-3i The formation process of the semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0090] First, you can refer to Figures 2a-2g Step S101 is executed: a substrate is provided; the substrate includes a first region A and a second region B arranged sequentially along a second direction; the first region A includes active layers 13 arranged at intervals along a third direction.

[0091] In some embodiments, the substrate may be formed by the following steps: providing a semiconductor substrate 10; forming a stacked structure 11 on the surface of the semiconductor substrate 10, located in a first region A and a second region B; the stacked structure 11 includes alternating stacked first semiconductor layers 111 and second semiconductor layers 112; removing the first semiconductor layer 111 in the first region A to expose the second semiconductor layer 112 in the first region A; thinning the exposed second semiconductor layer 112 to form an initial active layer 12; and processing the initial active layer 12 to form an active layer 13.

[0092] like Figure 2a and 2bAs shown, a stacked structure 11 located in a first region A and a second region B is formed on the surface of a semiconductor substrate 10; the stacked structure 11 includes an alternately stacked first semiconductor layer 111 and a second semiconductor layer 112.

[0093] In this embodiment of the disclosure, the material of the first semiconductor layer 111 may be germanium (Ge), silicon germanide (SiGe), or silicon carbide; it may also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI). The second semiconductor layer 112 may be a silicon layer, or may include other semiconductor elements, such as germanium, or include semiconductor compounds, such as silicon carbide, gallium arsenide, gallium indium phosphide, indium arsenide, or indium antimonide, or include other semiconductor alloys, such as silicon germanium, gallium arsenide phosphide, indium aluminum arsenide, gallium aluminum arsenide, indium gallium arsenide, indium gallium phosphide, and / or indium gallium arsenide phosphide or combinations thereof.

[0094] In this embodiment, the first semiconductor layer 111 and the second semiconductor layer 112 are made of different materials because the first semiconductor layer 111 needs to be removed later, while the second semiconductor layer 112 is retained. Therefore, the first semiconductor layer 111 has a larger selective etching ratio than the second semiconductor layer 112. For example, the selective etching ratio of the first semiconductor layer 111 to the second semiconductor layer 112 can be 5 to 15, so that the first semiconductor layer 111 is more easily etched away than the second semiconductor layer 112 during the etching process.

[0095] In this embodiment of the disclosure, the thickness of the first semiconductor layer 111 can be 5 to 50 nanometers (nm), for example, 8 nm or 45 nm; the thickness of the second semiconductor layer 112 can be 15 to 100 nm, for example, 20 nm or 75 nm. The number of the first semiconductor layer 111 and the second semiconductor layer 112 in the stacked structure 11 can be set according to the required capacitance density (or storage density). The more layers of the first semiconductor layer 111 and the second semiconductor layer 112, the higher the integration level and the greater the capacitance density of the formed semiconductor structure.

[0096] In this embodiment of the disclosure, the first semiconductor layer 111 and the second semiconductor layer 112 can be formed by any of the following deposition processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, coating process, or thin film process, etc.

[0097] like Figure 2cAs shown, the first semiconductor layer 111 in the first region A is removed to expose the second semiconductor layer 112 in the first region A.

[0098] In this embodiment of the present disclosure, the first semiconductor layer 111 in the stacked structure 11 can be removed by wet etching (e.g., etching with strong acids such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid) or dry etching techniques. Since the first semiconductor layer 111 has a high etching selectivity relative to the second semiconductor layer 112, the second semiconductor layer 112 can be removed without damaging it.

[0099] like Figure 2d As shown, the exposed second semiconductor layer 112 is thinned to form the initial active layer 12.

[0100] In this embodiment of the disclosure, the second semiconductor layer 112 can be thinned in the following two ways to form the initial active layer 12:

[0101] Method 1: Dry etching is performed directly on the second semiconductor layer 112 until the required thickness is formed, at which point the etching is stopped.

[0102] Method 2: In-situ oxidation of the second semiconductor layer 112, partially oxidizing the second semiconductor layer 112 into a silicon oxide layer, and removing the silicon oxide layer by wet etching or dry etching techniques.

[0103] In this embodiment, the second semiconductor layer 112 is thinned to 15-20 nm to form an initial active layer 12. For example, the thickness of the initial active layer 12 can be 18 nm. In this way, a channel region formed by the fully depleted semiconductor layer can be formed. At this time, holes are easily recombinated in the source region without accumulation, so the floating body effect can be improved. In addition, since the gap between two adjacent initial active layers 12 becomes larger, more space can be reserved for the formation of subsequent gate structure and word line structure, reducing word line coupling effect, as well as the fabrication process complexity and manufacturing cost of gate structure and word line structure.

[0104] It should be noted that in other embodiments, the second semiconductor layer 112 may not be thinned.

[0105] In some embodiments, processing the initial active layer 12 to form the active layer 13 may include the following steps: sequentially forming a sacrificial layer 121 and a first isolation layer 122 on the surface of the initial active layer 12; wherein the first isolation layer 122 fills the gaps between the sacrificial layers 121. The initial active layer 12 having a first length in a second direction is removed to form a first space; the sacrificial layers 121 having a second length in the second direction are removed to expose a portion of the initial active layer 12, forming a second space; wherein the second space includes the first space and the second length is greater than the first length, and the exposed portion of the initial active layer 12 constitutes the active layer 13.

[0106] like Figure 2e and 2f As shown, a sacrificial layer 121 and a first isolation layer 122 are sequentially formed on the surface of the initial active layer 12, and the initial active layer 12 with a first length L1 in the Y-axis direction is removed to form a first space C.

[0107] In this embodiment, the sacrificial layer 121 may be made of silicon oxide or other suitable materials. The first isolation layer 122 may be made of silicon nitride or other suitable materials. Here, the sacrificial layer 121 has a different etching selectivity relative to the first isolation layer 122; for example, the etching selectivity between the sacrificial layer 121 and the semiconductor substrate 10 is 5 to 10 times that between the first isolation layer 122 and the semiconductor substrate 10. Both the sacrificial layer 121 and the first isolation layer 122 can be formed by any suitable deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, coating process, or furnace tube process.

[0108] In this embodiment of the disclosure, the thickness of the sacrificial layer 121 can be 15-20 nm, for example 17 nm; the thickness of the first isolation layer 122 can be 10-20 nm, for example 15 nm.

[0109] In this embodiment, the first isolation layer 122 can isolate two adjacent comb-shaped gate structures on the one hand, and on the other hand, it can work together with the subsequently formed support layer as a support structure for the semiconductor structure, thereby improving the stability of the semiconductor structure.

[0110] In this embodiment of the present disclosure, the initial active layer 12 having a first length L1 can be removed by lateral etching using a wet etching process. The etching solution used in the wet etching can be a hydrofluoric acid solution or a mixed solution of diluted hydrofluoric acid and ammonia.

[0111] like Figure 2gAs shown, the sacrificial layer 121 with a second length L2 in the second direction is removed, exposing a portion of the initial active layer 12 to form a second space D; wherein, the second space D includes the first space C and the second length L2 is greater than the first length L1, and the exposed portion of the initial active layer 12 constitutes the active layer 13.

[0112] In this embodiment of the present disclosure, a wet etching process can be used to laterally etch away the sacrificial layer 121 having a second length L2 to form an active layer 13. The etching solution used in the wet etching process can be a mixed solution of diluted hydrofluoric acid and ammonia.

[0113] It should be noted that when the active layer 13 is formed, the sacrificial layer 121 is not completely removed. The remaining part of the sacrificial layer 121 is used to isolate the comb gate structure and bit line structure formed later, as well as the comb gate structure and capacitor structure, in order to reduce the generation of leakage current.

[0114] Next, you can refer to Figure 2h and 2l Step S102 is executed to form an initial gate structure 14 located on the surface of the active layer 13 in the first region A.

[0115] In some embodiments, the initial gate structure 14 can be formed by the following steps: a gate dielectric layer 141 and a gate conductive layer 142 are sequentially formed on the surface of the active layer 13, and the gate conductive layer 142 fills the second space D.

[0116] In this embodiment of the disclosure, the material used for the gate dielectric layer 141 may be silicon oxide or other suitable materials; the material used for the gate conductive layer 142 may include polysilicon, metals (e.g., tungsten, copper, aluminum, titanium, tantalum, ruthenium, etc.), metal alloys, metal silicides, titanium nitride, or any combination thereof.

[0117] In this embodiment, the gate dielectric layer 141 can be formed by in-situ steam generation (ISSG), and the thickness of the gate dielectric layer 141 can be 4.5 to 10 nm, for example, 5 nm or 9 nm. The gate conductive layer 142 can be formed by any suitable deposition process, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0118] Next, you can refer to Figure 2j and 2k Step S103 is executed, etching the initial gate structure 14 to form a comb-shaped gate structure 17 stacked along the third direction. Figure 2j This is a three-dimensional view of a portion of the comb-shaped gate structure. Figure 2k and 2l A cross-sectional view showing the formation of a comb-shaped gate structure.

[0119] In some embodiments, the comb-shaped gate structure 17 may include at least a first gate structure spaced apart in a first direction. In other embodiments, the comb-shaped gate structure 17 may also include a second gate structure 172 that is connected to the first gate structure 171 located in the same layer.

[0120] like Figure 2j As shown, the comb-shaped gate structure 17 includes a first gate structure 171 and a second gate structure 172, wherein the second gate structure 172 is connected to the first gate structure 171 located on the same layer.

[0121] In this embodiment of the disclosure, the projection of the first gate structure 171 on the substrate surface (i.e., semiconductor substrate 10) can be U-shaped; the first gate structure 171 can be a dual gate structure, for example, the first gate structure 171 covers the top and bottom surfaces of the active layer, and the size of the first gate structure 171 in the Y-axis direction can be 2 to 3 times the size of the second gate structure 172 in the Y-axis direction.

[0122] In other embodiments, the projection of the first gate structure 171 onto the substrate surface (i.e., the semiconductor substrate 10) may also be rectangular.

[0123] In some embodiments, such as Figure 2k and 2l As shown, the comb-shaped gate structure 17 can be formed by the following steps: simultaneously removing part of the initial gate structure and part of the stacked structure 11 in the second region B to form L-shaped grooves 15 and isolation grooves 16 arranged alternately along the X-axis direction, and the remaining initial gate structure constitutes the comb-shaped gate structure 17; wherein, the size L3 of the isolation groove 16 in the second direction is greater than the size L4 of the L-shaped groove 15 in the second direction.

[0124] In this embodiment of the disclosure, the isolation groove 16 divides the active layer into a plurality of active structures 130 arranged along the X-axis direction.

[0125] In this embodiment of the disclosure, the two stacked structures located on both sides of the L-shaped groove 15 along the X-axis direction have different dimensions in the second direction. For example, the first stacked structure 11a and the second stacked structure 11b are located on both sides of the L-shaped groove 15 along the X-axis direction, and the dimension L5 of the first stacked structure 11a in the Y-axis direction is greater than the dimension L6 of the second stacked structure 11b in the Y-axis direction.

[0126] In this embodiment, a dry etching process (e.g., plasma etching, reactive ion etching, or ion milling) or a wet etching process can be used to etch the initial gate structure and a portion of the stacked structure 11 in the second region B. The gas used in the dry etching process can be one or a combination of trifluoromethane (CHF3), carbon tetrafluoride (CF4), difluoromethane (CH2F2), hydrobromic acid (HBr), chlorine (Cl2), or sulfur hexafluoride (SF6).

[0127] In this embodiment of the disclosure, the formed comb-shaped gate structure 17 has a wider channel region, which can reduce the short-channel effect and thereby improve the performance of the formed semiconductor structure.

[0128] In some embodiments, such as Figure 2m As shown, after forming the comb-shaped gate structure 17, the method for forming the semiconductor structure further includes: forming word line steps 18 stacked sequentially along a third direction; wherein each word line in the word line steps 18 is electrically connected to a plurality of second gate structures 172 in the corresponding comb-shaped gate structure arranged along the first direction.

[0129] In this embodiment, firstly, a photoresist layer with a first opening is formed on the surface of a first region A; the first opening exposes one end of the first region A; the first region A is etched by the photoresist layer with the first opening to form a first stepped structure; secondly, a photoresist layer with a second opening is formed on the surface of the first stepped structure, the second opening exposing a portion of the first stepped structure, the first stepped structure is etched by the photoresist layer with the second opening to form a second stepped structure, wherein the size of the second opening in the first direction is larger than the size of the first opening; thirdly, a photoresist layer with a third opening is formed on the surface of the second stepped structure, the third opening exposing a portion of the second stepped structure, the second stepped structure is etched by the photoresist layer with the third opening to form a third stepped structure, wherein the size of the third opening in the first direction is larger than the size of the second opening; the above steps are repeated, and after multiple etching processes, a word line step 18 is finally formed, the word line step 18 having a progressively decreasing length from bottom to top along the Z-axis direction.

[0130] In other embodiments, the word line step 18 can also be formed by the following steps: First, a first word line of a first length is formed on the substrate surface of the first region A, wherein the first word line is electrically connected to the bottommost first layer comb gate structure 17 along the X-axis direction; Second, a first isolation unit of a second length is formed on the surface of the first word line; A second word line of a second length is formed on the surface of the first isolation unit, wherein the second word line is electrically connected to the bottommost second layer comb gate structure 17 along the first direction, wherein the first length is greater than the second length, and the first isolation unit is used to isolate adjacent first word lines and second word lines; Third, a second isolation unit of a third length is formed on the surface of the second word line; A third word line of a third length is formed on the surface of the second isolation unit, wherein the third word line is electrically connected to the bottommost third layer comb gate structure 17 along the X-axis direction, wherein the second length is greater than the third length, and the second isolation unit is used to isolate adjacent second word lines and third word lines; Repeating the above steps, after multiple formation processes, a word line step 18 composed of multiple word lines is formed.

[0131] In this embodiment of the disclosure, a comb-shaped gate structure 17 is formed and a word line side-connection method is adopted, which not only solves the problem that word line interconnection on the same plane is difficult to achieve for multi-layer stacking, but also controls word line coupling by controlling the size of the side-connected word lines.

[0132] Finally, you can refer to Figures 3a-3i In step S104, a bit line structure 22 extending along a third direction and a capacitor structure 24 extending along a second direction are formed in the second region B. Both the bit line structure 22 and the capacitor structure 24 are connected to the first gate structure 171.

[0133] In some embodiments, such as Figure 3a and 3b As shown, before forming the bit line structure 22 and the capacitor structure 24, the method for forming the semiconductor structure includes: filling the L-shaped groove 15 and the isolation groove 16 with an isolation material to form a second isolation layer 19.

[0134] In this embodiment, the insulating material can be silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials. The second insulating layer 19 can be formed by any deposition process.

[0135] like Figure 3c and 3dAs shown, the second isolation layer 19 and the first semiconductor layer 111 located in the second region B are removed, exposing the second semiconductor layer 112 in the stacked structures 11a and 11b. The exposed second semiconductor layer 112 forms first active pillars 131 and second active pillars 132 alternately arranged along the X-axis direction. The first active pillar 131 includes a first sub-pillar 1311 and a second sub-pillar 1312 arranged sequentially along the X-axis direction, and the second active pillar 132 is located within the projection area of ​​the first sub-pillar 1311 along the X-axis direction. In this embodiment, the second sub-pillar 1312 is used to form a capacitor structure; the second active pillar 132 is used to form a bit line structure.

[0136] In this embodiment of the disclosure, the second isolation layer 19 and the first semiconductor layer 111 located in the second region B can be removed by dry etching technology or wet etching technology.

[0137] In other embodiments, the first active column 131 and the second active column 132 may also be thinned. The thinning process includes the following two methods:

[0138] Method 1: Dry etching is performed directly on the first active pillar 131 and the second active pillar 132 until the required thickness is formed, at which point the etching is stopped.

[0139] Method 2: In-situ oxidation of the first active pillar 131 and the second active pillar 132, oxidizing part of the first active pillar 131 and part of the second active pillar 132 into a silicon oxide layer, and removing the silicon oxide layer by wet etching or dry etching techniques.

[0140] In this embodiment of the present disclosure, by thinning the first active pillar 131 and the second active pillar 132, the gap between adjacent first active pillars 131 and second active pillars 132 is increased. On the one hand, the effective area between the electrodes of the formed capacitor structure can be increased, thereby increasing the capacitance of the formed capacitor structure. On the other hand, the process complexity of the capacitor structure and bit line structure can be reduced, thereby reducing the manufacturing cost of the semiconductor structure.

[0141] In some embodiments, such as Figure 3e As shown, before forming the capacitor structure 24 and after forming the first active pillar 131, the method for forming the semiconductor structure further includes: forming a support layer 23 on the surface of the first sub-pillar 1311; the support layer 23 fills the spaces between the first sub-pillars 1311.

[0142] In this embodiment, the material of the support layer 23 can be silicon nitride or silicon carbonitride. The support layer 23 serves two purposes: firstly, it supports the subsequent formation of capacitor structures, preventing the collapse of capacitor structures and improving the stability of the formed semiconductor structure; secondly, it can isolate adjacent capacitor structures, as well as capacitor structures and bit line structures, reducing the generation of leakage current.

[0143] In this embodiment of the disclosure, such as Figure 3f As shown, before forming the capacitor structure, the method for forming the semiconductor structure further includes forming a first protective layer 21 on the surface of the first region A and the second active pillar 132. The first protective layer 21 is used to protect the comb-shaped gate structure 17 already formed in the first region A and the portion of the second active pillar 132 from damage during the formation of the capacitor structure 24. The material of the first protective layer 21 can be a low dielectric constant (Low K) material, for example, it can be doped silicon dioxide, organic polymer, or porous material.

[0144] In some embodiments, such as Figure 3g and 3h As shown, the capacitor structure 24 can be formed by the following steps: a first electrode layer 241, a dielectric layer 242, and a second electrode layer 243 are sequentially formed on the surface of the second sub-pillar 1312 to form the capacitor structure 24.

[0145] In this embodiment, the first electrode layer 241, the dielectric layer 242, and the second electrode layer 243 can be formed by any of the following deposition processes: selective atomic layer deposition (SALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and spin coating. The materials of the first electrode layer 241 and the second electrode layer 243 may include metals or metal nitrides, such as ruthenium (Ru) or titanium nitride. The material of the dielectric layer 242 may include a high-k dielectric material, such as one or any combination of lanthanum oxide (La₂O₃), aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), hafnium oxynitride (HfON), hafnium silicate (HfSiOx), or zirconium oxide (ZrO₂). In other embodiments, the materials of the first electrode layer and the second electrode layer may also be polycrystalline silicon.

[0146] In this embodiment, the capacitor structure 24 extends along the Y-axis, meaning that the capacitor structure 24 is horizontal. On the one hand, compared to a vertical capacitor structure with a high aspect ratio (i.e., the ratio of height to width or diameter), a horizontal capacitor structure can reduce the possibility of tipping over or breaking, thereby improving the stability of the capacitor structure. On the other hand, the stacked structure formed by stacking multiple capacitor structures in the vertical direction can form a three-dimensional semiconductor structure, thereby improving the integration of the semiconductor structure and achieving miniaturization.

[0147] In some embodiments, before forming the first electrode layer 241, the method for forming the semiconductor structure further includes forming a metal silicide on the surface of the second sub-pillar 1312. In practice, a metal material, such as any one of cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), platinum (Pt), and palladium (Pd), can be deposited on the surface of the second sub-pillar 1312; subsequently, a rapid thermal annealing process is performed to allow the metal material to react with the second sub-pillar 1312, thereby forming a metal silicide on the surface of the second sub-pillar 1312. Since the metal silicide has a low resistance, the contact resistance between the lower electrode and the second sub-pillar can be reduced, thereby reducing the power consumption of the semiconductor structure.

[0148] In some embodiments, after forming the capacitor structure 24, the method further includes removing the first protective layer 21. For example, a dry or wet etching process can be used to remove the first protective layer 21.

[0149] In some embodiments, the method for forming the semiconductor structure further includes: forming a conductive layer on the surface of the second electrode layer 243, wherein the conductive layer fills the spaces between adjacent second electrode layers 243. The material of the conductive layer may be polycrystalline silicon or any other suitable conductive material, such as doped polycrystalline silicon.

[0150] In this embodiment of the disclosure, such as Figure 3i As shown, before forming the bit line structure, the method for forming the semiconductor structure further includes forming a second protective layer 20 on the surface of the first region A, the support layer 23, and the capacitor structure 24. The second protective layer 20 is used to protect the already formed comb-shaped gate structure 17, the support layer 23, and the capacitor structure 24 from damage during the formation of the bit line structure 22. The material of the second protective layer 20 can be a low dielectric constant material, for example, it can be doped silicon dioxide, an organic polymer, or a porous material.

[0151] In some embodiments, please continue to see Figure 3i The bit line structure 22 can be formed by the following steps: a third semiconductor layer 221 and a bit line metal layer 222 are sequentially formed on the surface of the second active pillar 132.

[0152] The third semiconductor layer 221 can be made of metal silicide. Since metal silicide has a low resistance, it can reduce the contact resistance between the bit line metal layer 222 and the second active pillar 132, thereby further reducing the power consumption of the semiconductor structure. The bit line metal layer 222 can be made of any material with good conductivity, such as tungsten, cobalt, copper, aluminum, titanium nitride, titanium-containing metal layer, polysilicon, or any combination thereof.

[0153] In some embodiments, after forming the bit line structure 22, the method for forming the semiconductor structure further includes removing the second protective layer 20.

[0154] In this embodiment, a comb-shaped gate structure is formed, and a word line side-connection method is adopted. This not only solves the problem that interconnecting word lines on the same plane is difficult to achieve for multi-layer stacking, but also reduces the coupling effect of word lines by controlling the size of the side-connected word lines. In addition, since the capacitor structure in this embodiment extends along the second direction, that is, the capacitor structure in this embodiment is horizontal, compared with the vertical capacitor structure with a high aspect ratio, the horizontal capacitor structure can reduce the possibility of tipping or breaking, thereby improving the stability of the capacitor structure. Moreover, the stacked structure formed by stacking multiple capacitor structures in the third direction can form a three-dimensional semiconductor structure, thereby improving the integration of the semiconductor structure and realizing miniaturization.

[0155] This disclosure also provides a semiconductor structure. Figures 4a-4c This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure, wherein, Figure 4a This is a 3D view. For example... Figures 4a-4c As shown, the semiconductor structure 100 includes at least: a semiconductor substrate 10, the semiconductor substrate 10 including a first region A and a second region B arranged sequentially along a second direction (Y-axis direction); an active structure 130 located on the surface of the semiconductor substrate 10; the active structure 130 being arranged in an array along a first direction (X-axis direction) and a third direction (Z-axis direction); and a comb-shaped gate structure 17 located on the surface of the active structure in the first region A, and the comb-shaped gate structure 17 includes at least a first gate structure 171 spaced apart in the X-axis direction.

[0156] In some embodiments, please continue to see Figures 4a-4c The semiconductor structure 100 further includes a bit line structure 22 extending along the Z-axis and a capacitor structure 24 extending along the Y-axis; both the bit line structure 22 and the capacitor structure 24 are located on the second region B and are connected to the first gate structure 171.

[0157] In some embodiments, please continue to see Figure 4b and 4c The capacitor structure 24 includes a first electrode layer 241, a dielectric layer 242, and a second electrode layer 243. The bit line structure 22 includes a third semiconductor layer 221 and a bit line metal layer 222.

[0158] In some embodiments, please continue to see Figures 4a-4c The comb-shaped gate structure 17 further includes a second gate structure 172 that is connected to the first gate structure 171 located in the same layer.

[0159] In some embodiments, please continue to see Figure 4band 4c The active structure 130 includes a first active pillar 131 and a second active pillar 132 located on the second region B and arranged along the X-axis, and a channel pillar 25 located on the first region A; both the first active pillar 131 and the second active pillar 132 are connected to the channel pillar 25. The first gate structure 171 at least covers the first surface and the second surface of the channel pillar 25 along the Z-axis; wherein, the first gate structure 171 includes a gate dielectric layer 141 and a gate conductive layer 142 stacked together.

[0160] In some embodiments, the projection of the channel pillar 25 onto the semiconductor substrate 10 is U-shaped. In other embodiments, the projection of the channel pillar 25 onto the semiconductor substrate 10 may also be rectangular.

[0161] In some embodiments, please continue to see Figure 4b The first active pillar 131 includes a first sub-pillar (not shown) and a second sub-pillar 1312. A capacitor structure 24 is formed on the second sub-pillar 1312; a bit line structure 22 is formed on the second active pillar 132; an L-shaped groove 15 is provided between the first active pillar 131 and the second active pillar 132 of the same active structure 130. An isolation groove 16 is provided between adjacent active structures 130 along the X-axis direction; wherein, the dimension L3 of the isolation groove 16 in the Y-axis direction is greater than the dimension L4 of the L-shaped groove 15 in the Y-axis direction.

[0162] In some embodiments, please continue to see Figure 4b The semiconductor structure 100 further includes a support layer 23, which is located on the surface of the first sub-pillars and fills the spaces between the first sub-pillars. The support layer 23 is used to support a plurality of capacitor structures 24, a plurality of bit line structures 22, and a plurality of comb gate structures 17 stacked along the Z-axis direction.

[0163] In some embodiments, please continue to see Figure 4a The semiconductor structure 100 further includes: word line steps 18; the word line steps 18 are stacked sequentially along the Z-axis direction, and each layer of word lines in the word line steps is connected to a plurality of second gate structures 172 in the corresponding comb gate structures 17 arranged along the X-axis direction.

[0164] In this embodiment of the disclosure, the first gate structure may be a dual-gate structure, and the dimension of the first gate structure 171 in the Y-axis direction may be 2 to 3 times the dimension of the second gate structure 172 in the Y-axis direction.

[0165] In this embodiment of the disclosure, the formed comb-shaped gate structure has a wide channel region, which can reduce the short-channel effect. At the same time, the formed dual-gate structure can further improve the control capability of the gate, thereby improving the performance of the formed semiconductor structure.

[0166] The semiconductor structure provided in this disclosure is similar to the semiconductor structure formed by the above embodiments. For technical features not disclosed in detail in this disclosure, please refer to the above embodiments for understanding, and will not be repeated here.

[0167] The semiconductor structure provided in this disclosure embodiment forms a comb-shaped gate structure, and the word line structure is located outside the comb-shaped gate structure, which can realize the interconnection of word lines on the same plane in a multi-layer stacked structure. In addition, the capacitor structure in this disclosure embodiment is horizontal and arranged in an array along the first direction and the third direction. The horizontal capacitor structure can reduce the possibility of tipping or breaking. The stacked structure formed by stacking multiple capacitor structures in the third direction can form a three-dimensional semiconductor structure, thereby improving the integration of the semiconductor structure and realizing miniaturization.

[0168] Figure 5a and 5b This is a schematic diagram of a planar structure of a semiconductor structure provided in an embodiment of this disclosure, such as... Figure 5a and 5b As shown, the semiconductor structure 100 includes a first gate structure 171, a bit line structure 22, and a capacitor structure 24 arranged in an array along the X-axis and Z-axis directions; wherein the bit line structure 22 and the capacitor structure 24 are both connected to the comb-shaped gate structure 17.

[0169] In this embodiment of the disclosure, a first gate structure 171 and a capacitor structure 24 constitute a memory cell; adjacent memory cells along the X-axis direction have the same layout (e.g., ...). Figure 5a As shown), or, adjacent memory cells along the X-axis are axially symmetric (e.g. Figure 5b (As shown).

[0170] In some embodiments, see 5a and Figure 5b The semiconductor structure 100 includes a second gate structure 172 that is connected to the first gate structure 171 in the same layer. The first gate structure 171 and the second gate structure 172 arranged in the same layer along the X-axis direction constitute a comb-shaped gate structure 17.

[0171] In some embodiments, see 5a and Figure 5b The semiconductor structure 100 also includes word line steps 18 extending along the X-axis direction, wherein each word line in the word line steps 18 is electrically connected to a plurality of first gate structures 171 arranged along the X-axis direction.

[0172] In addition, this disclosure also provides a layout structure. Figure 6a and 6b This is a planar layout diagram of the layout structure provided in an embodiment of the present disclosure. The layout structure 200 includes the aforementioned semiconductor structures 100 arranged at intervals along the Y-axis direction.

[0173] like Figure 6a and 6b As shown, the semiconductor structure 100 includes a plurality of memory cells arranged in an array along the X-axis and Z-axis directions; each memory cell includes at least a first gate structure 171 and a capacitor structure 24; wherein, two adjacent memory cells in the Y-axis direction are centrally symmetrical; and the projection regions of the capacitor structures 24 of two adjacent memory cells in the Y-axis direction at least partially overlap in the X-axis direction.

[0174] In this embodiment of the present disclosure, the memory cell further includes a second gate structure 172, wherein the first gate structure 171 and the second gate structure 172 constitute a comb-shaped gate structure 17.

[0175] In some embodiments, please continue to see Figure 6a and 6b The semiconductor structure 100 also includes a bit line structure 22 and a word line step 18.

[0176] In some embodiments, please continue to see Figure 6a The layout of two adjacent storage cells in the X-axis direction is the same.

[0177] In some embodiments, please continue to see Figure 6b The layout of two adjacent storage cells along the X-axis is axially symmetrical.

[0178] The layout structure provided in this disclosure can effectively utilize the space in the semiconductor structure to achieve miniaturization of the semiconductor structure.

[0179] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed.

[0180] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0181] The above descriptions are merely some embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method includes: A substrate is provided; the substrate includes a first region and a second region arranged sequentially along a second direction; the first region includes active layers spaced apart along a third direction; An initial gate structure is formed in the first region on the surface of the active layer; The initial gate structure is etched to form a comb-shaped gate structure stacked along the third direction; wherein the comb-shaped gate structure includes at least a first gate structure spaced apart in a first direction; the first direction, the second direction, and the third direction are mutually perpendicular, and the first direction and the second direction are parallel to the substrate surface; A bit line structure extending along the third direction and a capacitor structure extending along the second direction are formed in the second region, and both the bit line structure and the capacitor structure are connected to the first gate structure.

2. The method according to claim 1, characterized in that, The comb-shaped gate structure further includes a second gate structure that is connected to the first gate structure located in the same layer.

3. The method according to claim 2, characterized in that, The projection of the first gate structure onto the substrate surface is U-shaped.

4. The method according to any one of claims 1 to 3, characterized in that, The active layer is formed through the following steps: Provide semiconductor substrates; A stacked structure located in the first region and the second region is formed on the surface of the semiconductor substrate; the stacked structure includes alternately stacked first semiconductor layers and second semiconductor layers; Remove the first semiconductor layer in the first region to expose the second semiconductor layer in the first region; The exposed second semiconductor layer is thinned to form an initial active layer; The initial active layer is processed to form the active layer.

5. The method according to claim 4, characterized in that, The process of processing the initial active layer to form the active layer includes: A sacrificial layer and a first isolation layer are sequentially formed on the surface of the initial active layer; wherein the first isolation layer fills the spaces between the sacrificial layers; Remove the initial active layer having a first length in the second direction to form a first space; The sacrificial layer having a second length in the second direction is removed, exposing a portion of the initial active layer to form a second space; wherein the second space includes the first space and the second length is greater than the first length, and the exposed portion of the initial active layer constitutes the active layer.

6. The method according to claim 5, characterized in that, Forming an initial gate structure located on the surface of the active layer in the first region includes: A gate dielectric layer and a gate conductive layer are sequentially formed on the surface of the active layer; wherein the gate conductive layer fills the second space.

7. The method according to claim 6, characterized in that, After forming the comb-shaped gate structure, the method for forming the semiconductor structure further includes: Forming a series of stacked word line steps along the third direction; Each word line in the word line step is electrically connected to the second gate structure in the corresponding comb-shaped gate structure arranged along the first direction.

8. The method according to claim 7, characterized in that, The comb-shaped gate structure is formed through the following steps: Simultaneously, a portion of the initial gate structure and a portion of the stacked structure in the second region are removed to form L-shaped grooves and isolation grooves that are alternately arranged along the first direction, and the remaining initial gate structure constitutes the comb-shaped gate structure. Wherein, the size of the isolation groove in the second direction is larger than the size of the L-shaped groove in the second direction; the isolation groove divides the active layer into a plurality of active structures arranged in the first direction.

9. The method according to claim 8, characterized in that, The stacked structures located on both sides of the L-shaped groove in the first direction have different dimensions in the second direction; Forming a bit line structure extending along the third direction and a capacitor structure extending along the second direction in the second region includes: A second isolation layer is formed by filling the L-shaped groove and the isolation groove with an isolation material. The second isolation layer and the first semiconductor layer located in the second region are removed, and the remaining second semiconductor layer forms a first active pillar and a second active pillar arranged alternately along the first direction; wherein, the first active pillar includes a first sub-pillar and a second sub-pillar; The capacitor structure is formed on the surface of the second sub-pillar; The bitline structure is formed on the surface of the second active post.

10. The method according to claim 9, characterized in that, Before forming the capacitor structure, the method further includes: A support layer is formed on the surface of the first sub-post; wherein the support layer fills the spaces between the first sub-posts.

11. The method according to claim 10, characterized in that, The capacitor structure is formed on the surface of the second sub-pillar, including: A first electrode layer, a dielectric layer, and a second electrode layer are sequentially formed on the surface of the second sub-pillar to form the capacitor structure.

12. A semiconductor structure, characterized in that, At least including: A semiconductor substrate, the semiconductor substrate comprising a first region and a second region arranged sequentially along a second direction; An active structure located on the surface of the semiconductor substrate; the active structure is arranged in an array along a first direction and a third direction; A comb-shaped gate structure is located on the surface of the active structure in the first region, and the comb-shaped gate structure includes at least a first gate structure spaced apart in a first direction; Bitline structure extending along the third direction; A capacitor structure extending along a second direction; both the bit line structure and the capacitor structure are located on the second region and are connected to the first gate structure; the first direction, the second direction, and the third direction are mutually perpendicular, and the first direction and the second direction are parallel to the surface of the semiconductor substrate.

13. The semiconductor structure according to claim 12, characterized in that, The comb-shaped gate structure further includes a second gate structure that is connected to the first gate structure located in the same layer.

14. The semiconductor structure according to claim 13, characterized in that, The active structure includes a first active post and a second active post located on the second region and arranged along the first direction, and a channel post located on the first region. Both the first active post and the second active post are connected to the channel post.

15. The semiconductor structure according to claim 14, characterized in that, The first gate structure covers the first and second surfaces of the channel pillars along the third direction; The first gate structure includes a gate dielectric layer and a gate conductive layer stacked together.

16. The semiconductor structure according to claim 15, characterized in that, The projection of the channel pillar onto the semiconductor substrate is U-shaped.

17. The semiconductor structure according to any one of claims 14 to 16, characterized in that, The capacitor structure is formed on the first active pillar; the bit line structure is formed on the second active pillar; An L-shaped groove is provided between the first active post and the second active post of the same active structure.

18. The semiconductor structure according to claim 17, characterized in that, The active structures adjacent to each other along the first direction have an isolation groove; The dimension of the isolation groove in the second direction is greater than the dimension of the L-shaped groove in the second direction.

19. The semiconductor structure according to claim 13, characterized in that, The semiconductor structure further includes: word line steps; The word line steps are stacked sequentially along the third direction, and each layer of word lines in the word line steps is connected to a plurality of second gate structures in the corresponding comb-shaped gate structure arranged along the first direction.

20. A layout structure, characterized in that, include: Semiconductor structures as described in any one of claims 12 to 19 are arranged sequentially at intervals along a second direction; The semiconductor structure includes memory cells arranged in an array along a first direction and a third direction; each memory cell includes a first gate structure and a capacitor structure. Wherein, two adjacent memory cells in the second direction are centrally symmetrical, and the capacitor structures of two adjacent memory cells in the second direction at least partially overlap in the projection area in the first direction.

21. The layout structure according to claim 20, characterized in that, The two adjacent storage cells in the first direction have the same layout or are axially symmetrical.

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