A double-sided passivated battery prepared based on a physical deposition technology and a preparation method thereof

Abstract

The application discloses a double-sided passivation battery prepared based on a physical deposition technology and a preparation method thereof. The double-sided passivation battery structure comprises a silicon substrate, and a P++ emitter, a local silicon oxide tunnel layer, a local boron-doped p+ poly layer, an aluminum oxide layer, a silicon nitride layer and a metal electrode are sequentially prepared from inside to outside on the front side of the silicon substrate; and a full silicon oxide tunnel layer, a full phosphorus-doped n+ poly layer, a silicon nitride layer and a metal electrode are sequentially prepared from inside to outside on the back side of the silicon substrate. The double-sided TOPcon battery prepared by the application is based on the PVD technology, compared with other preparation technologies disclosed in the prior art, a large number of mask preparation and cleaning steps are omitted, and only one process needs to be added in the current preparation process, so that the steps are simple and the cost is low; the application realizes a back full passivation and front local passivation contact structure, that is, the function of improving the passivation capability and increasing the battery efficiency is met, and optical loss caused by the parasitic absorption of the poly layer to light is effectively avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a double-sided passivation cell prepared based on a physical deposition technology and a preparation method thereof. Background Art

[0002] Crystalline silicon solar cells are microelectronic devices that directly convert light energy into electrical energy. To ensure sufficient conversion efficiency, it is necessary to ensure that the cell absorbs enough photons to generate photogenerated carriers and to maximize the lifetime of minority carriers (minority carriers), that is, to improve the cell passivation performance.

[0003] To this end, practitioners in the field have developed different battery structures to improve the battery passivation ability as much as possible. TOPCon (Tunnel 0xide Passivated Contact) technology is a process of preparing an ultra-thin tunnel oxide layer (SiOx) on the back of the battery and growing a heavily doped polysilicon layer (Poly-Si) on its surface. The two together form a passivation contact structure. The non-conductive but extremely thin tunnel oxide layer allows a high concentration of majority carriers (majority carriers) to pass through in the form of quantum tunneling, but it blocks minority carriers; the heavily doped Poly can change the energy band position of silicon, turning it into a P-type / N-type semiconductor, blocking electrons / holes from approaching. Therefore, TOPCon batteries have high passivation ability and conversion efficiency, which also makes TOPCon batteries the first choice for large-scale mass production.

[0004] However, the light absorption of the Poly layer is parasitic and does not contribute to the photocurrent (Isc). Currently, TOPCon cells are only fabricated on the back surface. If this structure is fabricated on the front surface, which serves as the light-absorbing surface, the parasitic light absorption of the Poly layer will lead to a significant reduction in Isc, which in turn reduces the cell efficiency. Therefore, if you want to fabricate a TOPCon structure on the front surface, you must overcome the parasitic light absorption problem of the Poly layer.

[0005] The traditional TOPcon structure is prepared by LPCVD (Low Pressure Chemical Vapor Deposition), which is a classic preparation method. Years of development have made this technology very mature, with simple process and low cost. However, as a vapor deposition technology, even if two silicon wafers are stacked together for processing, products will still be deposited on the other side and the side, which is called "wrap-around plating". Figure 1 and Figure 2 As shown in the figure, since the properties of the deposited materials on both sides of the battery are completely opposite, wrap-around plating will lead to leakage and degradation of battery properties.

[0006] Therefore, if LPCVD is used to prepare a double-sided TOPCon structure, it is necessary to repeatedly prepare and remove the mask, which makes the preparation process cumbersome, time-consuming, and cost-effective. Although the battery efficiency is ultimately improved, the increase in cost and the reduction in output will result in the battery cost per kilowatt-hour being unable to be effectively reduced, and the cost-effectiveness is not high. Summary of the Invention

[0007] In view of this, the purpose of the present invention is to provide a double-sided passivated battery prepared based on physical deposition technology and its preparation method, so as to realize the contact structure of full passivation on the back and local passivation on the front, which satisfies the purpose of improving the passivation ability and increasing the battery efficiency, and effectively avoids the optical loss caused by the parasitic absorption of light by the Poly layer.

[0008] To achieve the above object, the present invention adopts the following contents:

[0009] The present invention provides a method for preparing a double-sided passivated battery based on physical deposition technology, comprising the following steps performed in sequence:

[0010] Step 1: texturing, cleaning and boron diffusion process of silicon wafer;

[0011] Step 2: Use laser doping to prepare a P++ emitter at the location where metal grid lines need to be printed on the silicon wafer, and thin the borosilicate glass layer at the processing location;

[0012] Step 3: Use a chain machine and HF aqueous solution to remove the borosilicate glass on the back of the silicon wafer;

[0013] Step 4: After polishing the back of the silicon wafer with an alkaline solution, the surface of the silicon wafer is first cleaned with a hydrochloric acid solution to neutralize the alkaline solution and complex the metal ions with chloride ions. Then, a low-concentration hydrofluoric acid solution is used to remove the oxide layer on the back of the silicon wafer and the borosilicate glass remaining in the front laser area. The borosilicate glass outside the front laser area is retained to serve as a mask and a protective layer against mechanical friction.

[0014] Step 5: Using PVD technology to fabricate a TOPCon structure on the back of the silicon wafer, an ultra-thin tunneling oxide layer is first formed. Argon gas is ionized to form argon ions, which are then accelerated using a magnetic field to form high-energy ions that bombard a silicon target to deposit an amorphous silicon thin film on the silicon wafer surface. Phosphine is also introduced to dope phosphorus during the formation of the amorphous silicon deposition process.

[0015] After the TOPCon structure on the back of the silicon wafer is prepared, the TOPCon structure is formed on the front of the silicon wafer using PVD technology through a carrier frame with a local opening. First, an ultra-thin tunneling oxide layer is prepared, argon gas is ionized to form argon ions, and then a magnetic field is used to accelerate the argon ions to form high-energy ions that bombard the silicon target. At the same time, diborane is introduced to dope boron during the process of forming amorphous silicon deposition.

[0016] Step 6: Perform high-temperature annealing in an annealing furnace to activate the doping atoms in the amorphous silicon doping layer;

[0017] Step 7: After annealing, the silicon wafer is cleaned with a high-concentration hydrofluoric acid solution to remove the front borosilicate glass and natural oxide layer retained in step 4;

[0018] Step 8: Using an atomic layer deposition device to prepare an aluminum oxide passivation layer on the front surface of the silicon wafer;

[0019] Step 9: Using a plasma enhanced chemical deposition system, a silicon nitride anti-reflection film is prepared on both the front and back sides of the silicon wafer to reduce light reflection;

[0020] Step 10: Use screen printing equipment to apply metal slurry on the front and back sides of the silicon wafer, and then process it at high temperature in a sintering furnace to prepare metal grid lines, so that the metal material and silicon are combined to form an alloy, which can lead out the photogenerated carriers and complete the preparation of the double-sided passivated battery.

[0021] Among them, in the step 1: the silicon wafer is subjected to texturing treatment to remove the surface cutting damage layer and form a textured velvet structure on its surface to reduce light loss; the silicon wafer adopts an n-type silicon wafer with a thickness of 130um and a square resistance of 1Ω / □.

[0022] Among them, in the step 1: after the silicon wafer is texturized and cleaned, the silicon wafer is placed in a boron diffusion furnace tube for boron diffusion, and the boron diffusion process includes four steps: pre-oxidation, deposition, advancement, and post-oxidation.

[0023] The deposition time is reduced to 90-120 s, the advancement time is reduced to 350-400 s, and the square resistance of the silicon wafer after boron diffusion is about 150 Ω / □.

[0024] The carrier frame in step 5 is a carbon fiber carrier frame with a thickness of 0.1 to 0.2 mm, and a plurality of openings are provided at positions corresponding to the metal grid lines, that is, the opening design areas are consistent with the positions of the metal grid lines on the front side of the silicon wafer.

[0025] Wherein, the width of the opening is not greater than the width of the metal grid line on the front surface of the silicon wafer.

[0026] Wherein, in the step 5: the thickness of the phosphorus-doped amorphous silicon layer a-Si(n) is deposited to be 100-120 nm; the thickness of the boron-doped amorphous silicon layer a-Si(p) is deposited to be 110-140 nm.

[0027] Among them, in the step 6: annealing the silicon wafer in an annealing furnace at 850°C to 1000°C under a nitrogen environment for 30 minutes. If more than one silicon wafer needs to be annealed, the front sides of two silicon wafers doped with boron need to be stacked face to face during annealing.

[0028] Wherein, in step 9: the thickness of the silicon nitride anti-reflection film on the front side of the silicon wafer is 80-90 nm, and the thickness of the silicon nitride anti-reflection film on the back side of the silicon wafer is 90-100 nm.

[0029] The present invention also provides a double-sided passivated battery, which includes a silicon substrate. The front side of the silicon substrate is sequentially prepared with a P++ emitter, a local silicon oxide tunneling layer, a local boron-doped p+poly layer, an aluminum oxide layer, a silicon nitride layer, and a metal electrode from the inside to the outside. The back side of the silicon substrate is sequentially prepared with a full silicon oxide tunneling layer, a full phosphorus-doped n+poly layer, a silicon nitride layer, and a metal electrode from the inside to the outside.

[0030] The present invention has the following technical effects:

[0031] The double-sided TOPcon cell prepared by the present invention is based on PVD technology. Compared with other disclosed preparation technologies, it omits a large number of mask preparation and cleaning steps. It only needs to add one process to the current preparation process, which is simple and low-cost.

[0032] The plasma oxidation and plasma-assisted in-situ doping technology of the present invention is based on the principle of magnetron sputtering and is a physical deposition technology (PVD). After ionizing argon gas, a strong magnetic field is used to accelerate Ar+ to bombard atoms on the target material, causing them to detach from the target material and deposit on the surface of the substrate material. Moreover, due to the limitation of the plate-type carrier frame, no wrap-around plating will occur on the side and the other side, which greatly reduces the number of mask preparation and removal steps. In addition, since a plate-type carrier frame is used in the process, it is a perfect "mold". It can be processed into a mask plate with only the metal grid line positions exposed on the basis of the existing process, and a local structure can be directly prepared. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0034] Figure 1 、 Figure 2 This is a schematic diagram of the wrap-around plating produced when using the existing LPCVD process to produce silicon wafers;

[0035] Figure 3 Schematic diagram of the structure of a double-sided passivated battery prepared in an embodiment of the present invention;

[0036] Figure 4 Schematic diagram of the carrier frame involved in the process of preparing the TOPCon structure of the present invention;

[0037] Figure 5 This is a schematic diagram of the carrier frame based on the PVD technology of the present invention without generating wrap-around plating;

[0038] Figure 6 This is a data chart comparing the battery efficiency of the double-sided passivated battery in Example 1 and the traditional battery. DETAILED DESCRIPTION

[0039] In order to explain the present invention more clearly, the present invention is further described below in conjunction with preferred embodiments. Those skilled in the art should understand that the following specific description is illustrative rather than restrictive and should not be used to limit the scope of protection of the present invention.

[0040] Example 1

[0041] A double-sided passivation battery of this embodiment, such as Figure 3 As shown, the battery structure includes a silicon substrate 10 in the middle, and the front side of the silicon substrate 10 is sequentially prepared with a P++ emitter 11, a local silicon oxide tunneling layer 12, a local boron-doped p+poly layer 13, an aluminum oxide layer 14, a silicon nitride layer 15, and a metal electrode from the inside to the outside. The back side of the silicon substrate 10 is sequentially prepared with a full silicon oxide tunneling layer 21, a full phosphorus-doped n+poly layer 22, a silicon nitride layer 23, and a metal electrode from the inside to the outside.

[0042] The method for preparing the above-mentioned double-sided passivated battery in this embodiment includes the following steps:

[0043] (1) Select n-type silicon with a thickness of 130 μm and a square resistance of 1 Ω / □ as the substrate, and perform a texturing treatment on it to remove the surface damage layer and form a textured velvet structure on the surface to reduce light loss.

[0044] (2) After the texturing and cleaning is completed, the silicon wafer is placed in a boron expansion tube for boron diffusion. Boron diffusion is divided into four steps: pre-oxidation, deposition, advancement, and post-oxidation. Compared with the traditional process, it can reduce the process time and the diffusion concentration. Preferably, the deposition time is reduced to 90-120s, and the advancement time is reduced to 350-400s. After the diffusion is completed, the square resistance is about 150Ω / □.

[0045] (3) Use laser to perform laser film opening and heavy doping process on the gate line position on the front side of the silicon wafer to reduce the thickness of BSG (borosilicate glass) in the gate line area.

[0046] (4) Use a chain-type single-sided HF equipment to remove BSG on the back of the silicon wafer, and the volume ratio of HF and DI Water in the machine is 1:10.

[0047] (5) After removing the BSG on the back of the silicon wafer, the silicon wafer with local BSG on the front of the silicon wafer is retained and placed in an alkaline polishing tank. After alkaline polishing, HCl is used for the first cleaning to remove the alkaline residue and the Cl -The metal impurity ions are removed by complexation; the dilute HF solution is then used to remove the remaining BSG in the laser processing area. Since the BSG in other positions on the front of the silicon wafer is not opened by the laser, a certain thickness can be retained in low concentration HF.

[0048] (6) Using PVD magnetron sputtering equipment to coat the back of the silicon wafer, a tunneling oxide layer is prepared with a thickness of 1-2 nm. Then, Ar is formed by ionized argon. + While bombarding the Si target, PH4 gas is introduced to deposit a P-doped amorphous silicon layer with a thickness of 100-120nm.

[0049] (7) Using the existing mechanical equipment waterwheel to flip the silicon wafer, and using the local opening carrier frame, continue to use the PVD magnetron sputtering equipment to coat the film, and prepare the tunnel oxide layer in the laser opening area on the front of the silicon wafer. The silicon oxide thickness is 1-2nm, and then the Ar formed by ionized argon is used. + Diborane is introduced while bombarding the Si target. The process temperature of the PVD sputtering equipment is 200-300°C. At this time, diborane exists in the form of gas, forming a deposited B-doped amorphous silicon layer with a thickness of 110-140nm.

[0050] PVD is a plate-type device that uses a frame. The frame is made of carbon fiber, which can be made extremely thin while meeting the mechanical strength requirements. In this embodiment, a full-area carbon fiber frame with a thickness of 0.1-0.2mm is used, and corresponding openings are made at the corresponding positions of the metal grid lines. The opening area is consistent with the metal grid lines on the front of the battery. For details, see Figure 4 As shown, a number of parallel openings are formed in the center of the carrier frame surface. Since light will scatter outward from the openings during sputtering even with a mask, the width of the openings in the carrier frame does not need to be larger than the gate line width, and can even be slightly smaller.

[0051] (8) Anneal the silicon wafer in an annealing furnace at 850-1000°C under a nitrogen atmosphere for 30 minutes. The high temperature causes the PVD sputtered amorphous silicon to crystallize into Poly-Si and activate the doping atoms to complete the preparation of the TOPCon structure. If there is more than one silicon wafer, the front sides of the B-doped silicon wafers need to be stacked face to face during annealing to prevent the different doping elements on the front and back sides from diffusing and migrating at high temperatures. Annealing is to crystallize the amorphous silicon to form a Poly layer and activate the doping impurities. Since most of the BSG on the front side of the silicon wafer is retained in the above step (5), there is no need to worry about scratches or other damage to the front side of the silicon wafer.

[0052] (9) After annealing, the silicon wafer is cleaned. In a tank machine, 45-50℃ hydrogen peroxide and dilute alkali solution are first used to clean the organic impurities on the surface of the silicon wafer, and the polysilicon layer is micro-etched. This step is to minimize the impact of the diffusion and migration of boron and phosphorus elements at high temperatures. The volume ratio of hydrogen peroxide: alkali: DIWater is 2:1:200. Then, a room temperature mixed acid solution of HF and HCl is used to remove the BSG generated and retained during the boron diffusion, as well as the front BSG and the back PSG (phosphorus silicon glass). The volume ratio of HF:HCl:DIWater is 3:1:15.

[0053] (10) Using the ALD process, water and trimethylaluminum are used as reactants, and an 8-10 nm aluminum oxide passivation film is prepared on the front side of the silicon wafer at a temperature of 180-200°C.

[0054] (11) A SiNx anti-reflection film was prepared on both sides of the silicon wafer using a plasma enhanced chemical vapor deposition (PECVD) system to reduce light reflection. SiH4 and NH were used as reactants to prepare SiNx with a thickness of 80-90 nm on the front side of the silicon wafer and a SiNx with a thickness of 90-100 nm on the back side of the silicon wafer.

[0055] (12) Metal slurry is applied to the front and back sides of the silicon wafer using screen printing equipment. After high-temperature processing in a sintering furnace, metal grid lines are prepared to combine the metal material with silicon to form an alloy, thereby conducting photogenerated carriers and completing the preparation of a double-sided passivated battery. The front grid line pattern corresponds to the front laser film opening and localized poly deposition position.

[0056] The efficiency of the finished battery prepared by the method described in Example 1 was compared with that of the conventional battery with TOPCon structure prepared only on the back side. Figure 6 As shown, it can be seen that the efficiency of the finished battery prepared by the method described in Example 1 is 25.02%, while the efficiency of the battery with a conventional TOPCon structure prepared only on the back is 24.83%. Compared with the conventional battery structure, the battery efficiency of the present invention is improved by about 0.19%, which is a significant improvement. The present invention is based on PVD technology, which ionizes argon and accelerates Ar+ using a strong magnetic field to bombard the atoms on the target material, so that they are separated from the target material and deposited on the surface of the substrate material. Moreover, due to the limitation of the plate-type carrier frame, the side and the other side will not be plated around, and the effect is as follows: Figure 5 As shown, this greatly reduces the number of mask preparation and removal steps.

[0057] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not limitations on the implementation methods of the present invention. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solution of the present invention are still within the scope of protection of the present invention.

Claims

1. A method for preparing a double-sided passivated battery based on physical deposition technology, characterized in that: The method comprises the following steps in sequence: Step 1: texturing, cleaning and boron diffusion process of silicon wafer; Step 2: Use laser doping to prepare a P++ emitter at the location where metal grid lines need to be printed on the silicon wafer, and thin the borosilicate glass layer at the processing location; Step 3: Use a chain machine and HF aqueous solution to remove the borosilicate glass on the back of the silicon wafer; Step 4: After polishing the back of the silicon wafer with an alkaline solution, the surface of the silicon wafer is first cleaned with a hydrochloric acid solution to neutralize the alkaline solution and complex the metal ions with chloride ions. Then, a low-concentration hydrofluoric acid solution is used to remove the oxide layer on the back of the silicon wafer and the borosilicate glass remaining in the front laser area. The borosilicate glass outside the front laser area is retained to serve as a mask and a protective layer against mechanical friction. Step 5: Using PVD technology to fabricate a TOPCon structure on the back of the silicon wafer, an ultra-thin tunneling oxide layer is first formed. Argon gas is ionized to form argon ions, which are then accelerated using a magnetic field to form high-energy ions that bombard a silicon target to deposit an amorphous silicon thin film on the silicon wafer surface. Phosphine is also introduced to dope phosphorus during the formation of the amorphous silicon deposition process. After the TOPCon structure on the back of the silicon wafer is prepared, the TOPCon structure is formed on the front of the silicon wafer using PVD technology through a carrier frame with a local opening. First, an ultra-thin tunneling oxide layer is prepared, argon gas is ionized to form argon ions, and then a magnetic field is used to accelerate the argon ions to form high-energy ions that bombard the silicon target. At the same time, diborane is introduced to dope boron during the process of forming amorphous silicon deposition. Step 6: Perform high-temperature annealing in an annealing furnace to activate the doping atoms in the amorphous silicon doping layer; Step 7: After annealing, the silicon wafer is cleaned with a high-concentration hydrofluoric acid solution to remove the front borosilicate glass and natural oxide layer retained in step 4; Step 8: Using an atomic layer deposition device to prepare an aluminum oxide passivation layer on the front surface of the silicon wafer; Step 9: Using a plasma enhanced chemical deposition system, a silicon nitride anti-reflection film is prepared on both the front and back sides of the silicon wafer to reduce light reflection; Step 10: Use screen printing equipment to apply metal slurry on the front and back sides of the silicon wafer, and then process it at high temperature in a sintering furnace to prepare metal grid lines, so that the metal material and silicon are combined to form an alloy, which can lead out the photogenerated carriers and complete the preparation of the double-sided passivated battery.

2. The method for preparing a double-sided passivated battery based on physical deposition technology according to claim 1, characterized in that: In the step 1: the silicon wafer is subjected to a texturing treatment to remove the surface cutting damage layer and form a textured velvet structure on its surface to reduce light loss; the silicon wafer is an n-type silicon wafer with a thickness of 130um and a square resistance of 1Ω / □.

3. The method for preparing a double-sided passivated battery based on physical deposition technology according to claim 2, characterized in that: In the step 1: after the silicon wafer is texturized and cleaned, the silicon wafer is placed in a boron diffusion furnace tube for boron diffusion. The boron diffusion process includes four steps: pre-oxidation, deposition, advancement, and post-oxidation.

4. The method for preparing a double-sided passivated battery based on physical deposition technology according to claim 3, characterized in that: The deposition time is reduced to 90-120 s, the advancement time is reduced to 350-400 s, and the sheet resistance of the silicon wafer after boron diffusion is 150 Ω / □.

5. The method for preparing a double-sided passivated battery based on physical deposition technology according to claim 1, characterized in that: The carrier frame in step 5 is a carbon fiber carrier frame with a thickness of 0.1 to 0.2 mm, and a plurality of openings are provided at positions corresponding to the metal grid lines. The opening design areas are consistent with the positions of the metal grid lines on the front side of the silicon wafer.

6. The method for preparing a double-sided passivated battery based on physical deposition technology according to claim 5, characterized in that: The width of the opening is no greater than the width of the metal grid line on the front side of the silicon wafer.

7. The method for preparing a double-sided passivated battery based on physical deposition technology according to claim 1, characterized in that: In the step 5, the thickness of the phosphorus-doped amorphous silicon layer deposited is 100-120 nm; the thickness of the boron-doped amorphous silicon layer deposited is 110-140 nm.

8. The method for preparing a double-sided passivated battery based on physical deposition technology according to claim 1, characterized in that: In step 6: annealing the silicon wafer in an annealing furnace at 850° C. to 1000° C. under a nitrogen environment for 30 minutes. If more than one silicon wafer needs to be annealed, two silicon wafers need to be stacked face to face on their front sides doped with boron during annealing.

9. The method for preparing a double-sided passivated battery based on physical deposition technology according to claim 1, characterized in that: In step 9, the thickness of the silicon nitride anti-reflection film on the front side of the silicon wafer is 80 to 90 nm, and the thickness of the silicon nitride anti-reflection film on the back side of the silicon wafer is 90 to 100 nm.

10. A double-sided passivation battery, characterized in that: The battery is manufactured by the method described in any one of claims 1 to 9. The battery structure includes a silicon substrate, and the front side of the silicon substrate is sequentially prepared with a P++ emitter, a local silicon oxide tunneling layer, a local boron-doped p+poly layer, an aluminum oxide layer, a silicon nitride layer, and a metal electrode from the inside to the outside. The back side of the silicon substrate is sequentially prepared with a full silicon oxide tunneling layer, a full phosphorus-doped n+poly layer, a silicon nitride layer, and a metal electrode from the inside to the outside.

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