A kind of active and passive hybrid parallel current sharing circuit topology and method

Abstract

The application relates to a main and passive hybrid parallel current sharing circuit topology, characterized in that: containing a DC bus V dc , N SiC-MOSFET half-bridge modules, a passive current sharing circuit and an active current sharing circuit, the N SiC-MOSFET half-bridge modules, the passive current sharing circuit and the active current sharing circuit are connected with each other, wherein the N SiC-MOSFET half-bridge modules are respectively HBM1, HBM2,..., HBM N , and the N SiC-MOSFET half-bridge modules are connected in parallel at two ends of the DC bus. The active current sharing circuit is separately arranged and does not affect each other, the main and passive current sharing circuit topology has the modularization advantage and is easy to expand. The parallel power module or device can be applied to various power levels, and is very suitable for high-power and large-current application occasions of the parallel SiC-MOSFET half-bridge power module.

Description

Technical Field

[0001] This invention belongs to the field of power electronic converter technology, and particularly relates to a topology and method of a hybrid active and passive parallel current sharing circuit. Background Technology

[0002] SiC semiconductor power devices possess excellent properties such as high frequency, high efficiency, and high temperature resistance, making them promising for applications in new energy vehicles, rail transportation, new energy grid connection, and smart grids. However, due to material and technological limitations, the maximum rated operating current of currently available SiC-MOSFET power modules is only a few hundred amperes (approximately 700A), which is far from sufficient for high-power, high-current applications. To increase the maximum operating current of the power converter, multiple SiC-MOSFET modules can be connected in parallel to compensate for the relatively small rated current of a single SiC-MOSFET power module or device. When SiC-MOSFETs operate in parallel for extended periods, it is crucial to ensure current balance (transient and steady-state current balance) among the parallel SiC-MOSFET power modules. Otherwise, localized overcurrent, overheating, or global overheating may occur in some SiC-MOSFET power modules, potentially damaging the parallel SiC-MOSFET power modules and reducing system reliability. The main causes of current imbalance in parallel SiC-MOSFET power modules include inconsistent gate threshold voltages and mismatched drive signal duty cycles caused by inconsistent drive signal conditioning circuit parameters. Due to inconsistent gate threshold voltages and mismatched drive signal duty cycles, the transient currents of the parallel SiC-MOSFET power modules may be significantly unbalanced, resulting in uneven distribution of switching losses among the parallel SiC-MOSFET power modules and the inability to achieve automatic current balancing after turn-on.

[0003] To average the current of parallel devices, most current sharing methods currently employ "active" and "passive" current sharing approaches. The "active" current sharing method uses the difference in current flowing through each parallel device, employing a closed-loop control algorithm to actively adjust the gate turn-on and turn-off delays of the two parallel devices, thereby achieving current balance in the parallel power modules or devices. The "passive" current sharing method, on the other hand, introduces an additional impedance current-sharing inductor connected in series with the source of the SiC-MOSFET and a drive regulation resistor connected in series in the gate circuit, thus mitigating transient current imbalances caused by inconsistent turn-on voltages in parallel SiC-MOSFET power modules or devices during switching. However, these existing methods are only designed for parallel current imbalances in SiC-MOSFET power modules or devices with relatively small rated currents. In the existing methods described above, the differential current sensor or the additional winding current-sharing inductor is directly connected in series with the power circuit. However, these methods suffer from drawbacks such as the high cost of high-precision, high-current differential current sensors and the large impedance and size of the additional winding current-sharing inductor, making them difficult to wind. Therefore, they are not suitable for high-power, high-current parallel current sharing applications or parallel current sharing applications of DC / DC power converters. Furthermore, these methods are only applicable to the parallel connection of two SiC-MOSFET power modules or devices and lack modularity, making it difficult to extend and adapt them to the parallel connection of multiple SiC-MOSFET power modules or devices.

[0004] For high-power, high-current applications, the commonly used passive current sharing method for parallel current sharing of two power modules or devices involves using a reverse-coupled inductor between the two parallel output terminals. This reverse-coupled inductor uses a high-magnetic-density, non-saturable magnetic core. The two current output wires of the parallel power modules or devices are wound in opposite directions around this toroidal core and then connected to a single point to form a common current output terminal O, thus constituting a passive current sharing circuit. However, this method of parallel current sharing using a single magnetic ring is often only suitable for situations where two devices are connected in parallel and current balance is required. Furthermore, it requires the design of special output terminals or methods to achieve reverse current sharing within the same magnetic ring. When the current is large, the required magnetic ring volume is large, making it difficult to compress the power density. When N devices need to be connected in parallel and current balance is required, the output terminals and wiring methods become extremely complex and impractical, significantly diminishing the practical application value of this type of current sharing circuit.

[0005] For high-power, high-current applications, existing active current sharing methods for multiple parallel power modules or devices involve connecting a current sampling resistor in series between the drain (S) of each switching device and the overall output (O). This resistor has a small resistance value, a high rated power, and is difficult to miniaturize. Each resistor uses a high-precision voltage sensor to detect the voltage across it, and each sensor is connected in the same way. When multiple parallel power modules or devices are operating and there is current imbalance among them, the voltage across the resistors will differ; the resistor with the larger current will have a higher voltage, and the resistor with the smaller current will have a lower voltage. The controller adjusts the turn-on or turn-off timing of the corresponding power modules or devices based on the current sharing algorithm and the collected voltage inconsistencies. This is equivalent to adjusting the gate drive voltage of the power modules or devices. The implementation is as follows: a larger voltage controls a decrease in the drive duty cycle, and a smaller voltage controls an increase in the drive duty cycle. This adjustment of the drive duty cycle ultimately achieves current sharing. This method is complex, requiring sampling resistors and voltage sensors corresponding to the number of parallel power modules or devices, resulting in high costs.

[0006] A common active current sharing method for achieving parallel current sharing of multiple power modules or devices is to... DS A high-current, high-precision differential sensor is connected to the terminal. After collecting the unbalanced current, the turn-on delay and turn-off delay of the drive are adjusted in a timely manner according to the current sharing algorithm. When multiple parallel devices share the current, the timeliness of adjusting the turn-on delay and turn-off delay of the drive signal of each parallel power module or device is particularly important. Since active current sharing has a timeliness problem, the reliability of active current sharing in high-power and high-current situations is worth exploring. Summary of the Invention

[0007] The purpose of this invention is to provide a hybrid active and passive parallel current sharing circuit topology and method to solve the problems in the prior art where the passive current sharing circuit and method with magnetic ring through-through is not applicable to the parallel current sharing of multiple power modules and DC / DC converters under high power and high current conditions; and the high economic cost caused by the extensive use of sensors in the active current sharing method under high power and high current conditions.

[0008] To achieve the above objectives, the technical solution of the present invention is as follows: A hybrid active and passive parallel current sharing circuit topology is provided, the innovation of which lies in: including a DC bus V dc The system consists of N SiC-MOSFET half-bridge modules, a passive current sharing circuit, and an active current sharing circuit. These N SiC-MOSFET half-bridge modules are interconnected. The N SiC-MOSFET half-bridge modules are named HBM1, HBM2, ..., HBM... NN SiC-MOSFET half-bridge modules are connected in parallel across the DC bus.

[0009] Furthermore, the passive current sharing circuit includes a passive current balancing circuit, a DC active current compensator, and a capacitor C. CO Inductor L CO The passive current balancing circuit for the 300A Hall sensor and the 65A Hall sensor consists of N magnetic rings with additional windings of the same parameters, namely w1, w2...w... N Each magnetic ring has an additional winding with the same winding direction, and the additional windings are connected end to end to form a loop.

[0010] The 300A Hall sensor collects the total output current i0 of the N SiC-MOSFET half-bridge modules, and the 65A Hall sensor collects the additional winding current i. s ;

[0011] The DC active current compensator includes a full-bridge inverter circuit and a DSP controller. The full-bridge inverter circuit includes power switches Q1, Q2, Q3, and Q4, where Q1 and Q2 are connected in series with complementary drive signals in one phase, and Q3 and Q4 are connected in series with complementary drive signals in the other phase. The drive signals for Q1 and Q4 are the same, and the drive signals for Q2 and Q3 are the same. The DSP controller is connected to a 300A Hall sensor and a 65A Hall sensor, respectively, to receive the total output current i0 and the additional winding current i. s According to i0 is i s Adjust the duty cycle of the drive signals of the power switches Q1, Q2, Q3, and Q4 in the full-bridge inverter circuit by 30 times, and adjust i s compensate;

[0012] Capacitor C CO One end is connected to the midpoint of Q3 and Q4, and the beginning of the winding of magnetic ring W1, respectively. Inductor L CO One end is connected to the midpoint of Q1 and Q2, and the other end is connected to the magnetic ring w. N The winding end and capacitor C CO The other end; inductor L CO and capacitor C CO The compensation current i of the full-bridge inverter circuit output s For filtering purposes, N parallel-connected SiC-MOSFET half-bridge modules HBM1, HBM2...HBM N The midpoint output current passes through N magnetic rings with additional windings in the same direction.

[0013] Furthermore, the active current sharing circuit includes N active PWM edge adjustment circuits, N lower-level DSP controllers, N steady-state unbalanced current detection circuits, an upper-level DSP controller, and N gate driver ICs.i Transistor B ri Transistor B di N resistors R refi N capacitors C refi N resistors R refi’ N capacitors C refi’ N resistors R refi and N capacitors C refi Composition of RC filter circuit, N resistors R refi’ and N capacitors C refi’ The circuit consists of an RC filter circuit; N steady-state unbalanced current detection circuits correspond to single-turn inductors L1, L2...L... N Each single-turn inductor corresponds to the current output terminal of the N parallel SiC-MOSFET half-bridge module, with the current flowing from the current output terminal to the total current output terminal O through the N magnetic rings of the passive current sharing circuit.

[0014] Each active PWM edge-tuning circuit includes a comparator LMV. i Diode D di Diode D ri Resistance R ri and capacitor C ri The negative terminals of the comparators are all connected to capacitor C. ri One end, resistor R ri One end of the capacitor C ri The other end is grounded, and the resistor R ri The other end is connected to the upper-level DSP controller, and the outputs of the N comparators are each connected to N gate driver ICs. i The gate of the upper transistor of the corresponding N parallel SiC-MOSFET half-bridge module;

[0015] N steady-state unbalanced current detection circuits and N lower-level DSP controllers are connected accordingly. Each lower-level DSP controller has two outputs, one of which is connected to a resistor R in sequence. refi Capacitor C refi Transistor B ri collector and diode D ri The positive terminal of one output is connected to resistor R in sequence. refi’ Capacitor C refi’ Transistor B di collector and diode D di The positive terminal of diode D di and diode D ri The negative terminals are all connected to the positive terminals of the corresponding comparators; the upper-level DSP controller has three PWM signal outputs, namely V PWM S ri S di VPWM Passing through resistor R respectively ri The negative terminals of N comparators are connected in parallel to each other, and S is connected to the negative terminal of each comparator. ri Connected to transistor B respectively ri The base and steady-state unbalanced current detection circuit, S di Connected to transistor B respectively di The base and steady-state unbalanced current detection circuit, transistor B ri B di The emitters of all are grounded, where i = 1, 2, ..., N.

[0016] Furthermore, the specific structure of the steady-state unbalanced current detection circuit is as follows: it includes a sensing inductor L CS The circuits for opening and closing the uneven current detection circuits are designed to include positive voltage detection and negative voltage detection, respectively.

[0017] The structure of the positive voltage detection circuit for the unequal current detection circuit is as follows: it includes diode D. 11 D 12 D 13 D 14 D 15 Inductor L 11 resistance R 11 R 12 R 13 Capacitor C 11 Transistor Q1; Diode D 11 Positive terminal connected to sensing inductor L CS Induced AC voltage V cs The positive terminal and the negative terminal are connected to the inductor L. 11 One end, inductor L 11 The other end is connected to diode D. 14 D 15 The positive terminal of diode D 14 The negative terminal is connected to the collector of transistor Q1, and the base of transistor Q1 is connected to the output S of the upper-level DSP controller. ri Diode D 15 The negative terminals are connected to resistors R respectively. 11 one end and capacitor C 11 At one end, the emitter of transistor Q1 and resistor R 11 The other end, capacitor C 11 The other end, diode D 12 positive terminal, resistor R 12 One end of each diode is grounded, diode D 12 The negative terminal and resistor R 12 The other end is connected to diode D. 13 positive terminal and resistor R13 One end, diode D 13 The negative terminal, resistor R 13 The other end is connected to the sensing inductor L CS Induced AC voltage V cs The negative end;

[0018] The structure for negative voltage detection in the unequal current detection circuit is as follows: it includes a resistor R. 21 R 22 R 23 diode D 21 D 22 D 23 D 24 D 25 Capacitor C 21 Inductor L 21 Transistor Q2, diode D 21 Positive terminal connected to sensing inductor L CS Induced AC voltage V cs The negative terminal is connected to the inductor L. 21 One end, inductor L 21 The other end is connected to diode D. 24、 D 25 The positive terminal of diode D 24 The negative terminal is connected to the collector of transistor Q2, and the base of transistor Q2 is connected to the output S of the upper-level DSP controller. ri diode D 25 The negative terminals are connected to resistors R respectively. 21 One end, capacitor C 21 At one end, the emitter of transistor Q2 and resistor R 21 The other end, capacitor C 21 The other end, diode D 22 positive terminal, resistor R 22 One end of each diode is grounded, diode D 22 The negative terminal and resistor R 22 The other end is connected to diode D. 23 positive terminal and resistor R 23 One end, diode D 23 The negative terminal, resistor R 23 The other end is connected to the sensing inductor L CS Induced AC voltage V cs The positive end;

[0019] The structure of the positive voltage detection in the off-current imbalance detection circuit is as follows: it includes diode D. 31 D 32 D 33 D 34 D 35 Inductor L 31resistance R 31 R 32 R 33 Capacitor C 31 Transistor Q3; Diode D 31 Positive terminal connected to sensing inductor L CS Induced AC voltage V cs The positive terminal and the negative terminal are connected to the inductor L. 31 One end, inductor L 31 The other end is connected to diode D. 34 D 35 The positive terminal of diode D 34 The negative terminal is connected to the collector of transistor Q3, and the base of transistor Q3 is connected to the output S of the upper-level DSP controller. di diode D 35 The negative terminals are connected to resistors R respectively. 31 one end and capacitor C 31 At one end, the emitter of transistor Q3 and resistor R 31 The other end, capacitor C 31 The other end, diode D 32 positive terminal, resistor R 32 One end of each diode is grounded, diode D 32 The negative terminal and resistor R 32 The other end is connected to diode D. 33 positive terminal and resistor R 33 One end, diode D 33 The negative terminal, resistor R 33 The other end is connected to the sensing inductor L CS Induced AC voltage V cs The negative end;

[0020] The structure of the negative voltage detection circuit for the shutdown non-uniform current detection circuit is as follows: it includes resistor R 41 R 42 R 43 diode D 41 D 42 D 43 D 44 D 45 Capacitor C 41 Inductor L 41 Transistor Q4, diode D 41 Positive terminal connected to sensing inductor L CS Induced AC voltage V cs The negative terminal is connected to the inductor L. 41 One end, inductor L 41 The other end is connected to diode D. 44 D 45 The positive terminal of diode D 44The negative terminal is connected to the collector of transistor Q4, and the base of transistor Q4 is connected to the output S of the upper-level DSP controller. di diode D 45 The negative terminals are connected to resistors R respectively. 41 One end, capacitor C 41 At one end, the emitter of transistor Q4 and resistor R 41 The other end, capacitor C 41 The other end, diode D 42 positive terminal, resistor R 42 One end of each diode is grounded, diode D 42 The negative terminal and resistor R 42 The other end is connected to diode D. 43 positive terminal and resistor R 43 One end, diode D 43 The negative terminal, resistor R 43 The other end is connected to the sensing inductor L CS Induced AC voltage V cs The positive end;

[0021] Sensing inductor L CS That is, single-turn inductors L1, L2...L N Single-turn inductors L1, L2...L N One end of each circuit is connected to the positive terminal of Vcs in N steady-state unbalanced current detection circuits, and the single-turn inductors L1, L2...L... N The other end is connected to the negative terminal of Vcs of N steady-state unbalanced current detection circuits, with single-turn inductors L1, L2...L... N The steady-state uneven current of N parallel SiC-MOSFET half-bridge modules is sensed through the corresponding magnetic ring and converted into signals Vr+, Vr-, Vd+, and Vd-, which are then connected to the controller of the next-level DSP.

[0022] To achieve the above objectives, the technical solution of the present invention also provides a hybrid active and passive parallel current sharing method, the innovation of which lies in: specifically including a passive parallel current sharing method and an active parallel current sharing method, and the specific implementation includes the following steps:

[0023] S1: The specific implementation steps of the passive parallel current sharing method are as follows:

[0024] (1) N SiC-MOSFET half-bridge modules HBM1, HBM2...HBM N Parallel to DC bus V dc At both ends, the current output terminals of each SiC-MOSFET half-bridge module converge at point O to form the total current output terminal O;

[0025] (2) The N magnetic rings w1, w2, ..., w in the passive current balancing circuitN Each of the N magnetic rings has an additional winding of n turns, and the additional windings of the N magnetic rings are connected end to end in sequence and are passed through the current output terminals of the N parallel SiC-MOSFET half-bridge modules. Let w be the number of the i-th magnetic ring. i The inductance value is L s The inductance value at the current output terminal of each SiC-MOSFET half-bridge module is L0;

[0026] (3) Magnetic ring w i A magnetic core with high permeability that is not easily saturated is selected, therefore L0 and L s If a fully coupled relationship exists, then L s =n 2 When a brief imbalance exists among the output currents of the N parallel SiC-MOSFET half-bridge modules passing through the magnetic ring, the magnetic ring induces a reverse current i. s This is used to suppress transient current imbalance among N parallel SiC-MOSFET half-bridge modules;

[0027] (4) When operating in DC / DC mode, the magnetic ring w i Induced current i s After a short period of time, it will saturate and lose its ability to suppress transient current imbalances among the N parallel SiC-MOSFET half-bridge modules. At this point, the DSP controller receives the total output current i. o , and according to i o is i s 30 times the relationship control DC active current compensator for i s compensate;

[0028] (5) The passive current sharing circuit can suppress the current imbalance at the moment of turn-on and turn-off of N parallel SiC-MOSFET half-bridge modules. When the imbalance between N parallel SiC-MOSFET half-bridge modules is serious, the active parallel current sharing circuit and method are combined to achieve current balance between N parallel SiC-MOSFET half-bridge modules.

[0029] S2: The specific implementation steps of the active parallel current sharing method are as follows:

[0030] (1) The N single-turn inductors L1, L2...L in the steady-state unbalanced current detection circuit N The inductors L0, which pass through N magnetic rings and are connected in parallel to the current output terminals of N SiC-MOSFET half-bridge modules, are fully coupled.

[0031] (2) When there is a steady-state current imbalance among N parallel SiC-MOSFET half-bridge modules, the single-turn inductor of the steady-state imbalance current detection circuit induces a voltage v. csThis voltage is converted into the corresponding V by turning on the positive voltage detection circuit, turning on the negative voltage detection circuit, turning off the positive voltage detection circuit, and turning off the negative voltage detection circuit. r+ V r- V d+ V d- This voltage reflects the unbalanced current among the N parallel SiC-MOSFET half-bridge modules;

[0032] (3) The steady-state unbalanced current detection circuit in step (2) detects the current based on the S output from the upper-level DSP controller. ri and S di The signal selectively detects the turn-on current imbalance and turn-off current imbalance among N parallel SiC-MOSFET half-bridge modules;

[0033] (4) The voltage V corresponding to the turn-on uneven current detected in step (3) among the N parallel SiC-MOSFET half-bridge modules Ci It is converted into the lower-level DSP controller to control the PWM duty cycle δ of the DSP's internal DAC module. ri The voltage V corresponding to the unbalanced turn-off current among the N parallel SiC-MOSFET half-bridge modules detected. Ci This is converted into the duty cycle δ of the PWM module controlled by the lower-level DSP controller. di ;

[0034] (5) δ in step (4) ri The lower-level DSP controller controls the internal DAC module to output the corresponding N parallel SiC-MOSFET half-bridge module turn-on edge adjustment reference v. refi δ di The lower-level DSP controller controls the DAC module to output the corresponding N parallel SiC-MOSFET half-bridge modules' turn-off edge adjustment reference v. refi’ ;

[0035] (6) v in step (5) refi and v refi’ The drive signal v from the upper-level DSP controller is supplied to the positive terminal of the comparator of the active PWM edge adjustment circuit. PWM The signal S from the upper-level DSP controller is given to the negative terminal of the comparator in the active PWM edge adjustment circuit; ri For low S di When v is high refi With the drive signal v from the upper-level DSP controller PWM Compare and adjust the turn-on drive signals of the corresponding N parallel SiC-MOSFET half-bridge modules in advance or delay; when the signal S from the upper-level DSP controller... ri For high S di When v is lowrefi’ With the drive signal v from the upper-level DSP controller PWM The system compares and adjusts the turn-off drive signals of N parallel SiC-MOSFET half-bridge modules by advancing or delaying them, and finally outputs the corresponding adjusted drive signal PWM. Oi ;

[0036] (7) The PWM output of the comparator in step (6) Oi via corresponding gate driver ICs i After increasing the driving capability, the signal is sent to the gate of the upper transistor of the corresponding N parallel SiC-MOSFET half-bridge module and controlled to turn it on or off. This closed-loop control can achieve transient and steady-state balance of the output current of the N parallel SiC-MOSFET half-bridge modules.

[0037] Furthermore, if the rated currents of the N parallel SiC-MOSFET half-bridge modules are the same, then the magnetic core parameters of the passive current balancing circuits of the N passive current sharing circuits and the parameters of the additional windings wound around each magnetic core are the same, and the active PWM edge adjustment circuits and steady-state unbalanced current detection circuits of the N active current sharing circuits have the same function. If the rated currents of the N parallel SiC-MOSFET half-bridge modules are different, then the magnetic core parameters of the passive current balancing circuits of the N passive current sharing circuits and the parameters of the additional windings wound around each magnetic core are linearly related to the rated currents of the N parallel SiC-MOSFET half-bridge modules, and the settings of the active PWM edge adjustment circuits and steady-state unbalanced current detection circuits of the N active current sharing circuits are linearly related to the rated currents of the N parallel SiC-MOSFET half-bridge modules.

[0038] Furthermore, in step (3), the S output by the upper-level DSP controller... ri and S di The specific process of selectively detecting the turn-on and turn-off current imbalances among N parallel SiC-MOSFET half-bridge modules is as follows: The signal S output by the upper-level DSP controller... ri For low S di To detect and convert the uneven turn-on current among N parallel SiC-MOSFET half-bridge modules into V during high-time operation. r+ and V r- S ri To enable low-pass bypass current unevenness detection circuit, S di For the high bypass shutdown uneven current detection circuit, the signal S output by the upper-level DSP controller ri For high S di To detect the turn-off current imbalance among N parallel SiC-MOSFET half-bridge modules at low speeds and convert it into V d+ and V d- , where S riFor high bypass, open the uneven current detection circuit, S di This is a low-bypass turn-off unbalanced current detection circuit; this circuit can detect the turn-on and turn-off unbalanced currents of N parallel SiC-MOSFET half-bridge modules, and express the results as voltage values ​​V. Ci The representation is shown in the diagram, where C represents r+, r-, d+, and d-, and i represents the serial number of the corresponding steady-state unbalanced current detection circuit.

[0039] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0040] (1) The active current sharing circuits are set up separately and do not affect each other. The topology of the active and passive current sharing circuits has the advantages of modularity and is easy to expand.

[0041] (2) A constant number (2) of high-precision current sensors are used, which is economical and has a low cost.

[0042] (3) It enables parallel power modules or devices to be applied to various power levels, making it very suitable for high-power, high-current applications of parallel SiC-MOSFET half-bridge power modules.

[0043] (4) It can be used in high power density and high current DC / DC converters. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of a hybrid active and passive parallel current sharing circuit topology according to the present invention.

[0045] Figure 2 For the present invention Figure 1 A schematic diagram of the specific structure of the steady-state unbalanced current detection circuit.

[0046] Figure 3 This invention provides an analysis model for the series connection of N magnetic rings with additional windings in a passive current sharing circuit.

[0047] Figure 4 The present invention provides a common-mode model in which the current output terminals of the N parallel SiC-MOSFET half-bridge modules respectively correspond to the N magnetic rings passing through the passive current balancing circuit and converging at point O.

[0048] Figure 5 This is the equivalent circuit analysis model of the full-bridge inverter circuit of the present invention.

[0049] Figure 6 This is a schematic diagram of the passive current sharing circuit of the present invention applied to a three-parallel SiC-MOSFET half-bridge module.

[0050] Figure 7This is a schematic diagram illustrating the principle of converting steady-state unbalanced current into voltage in a three-parallel SiC-MOSFET half-bridge module under different operating conditions according to the present invention.

[0051] Figure 8 This is a schematic diagram illustrating the principle of how a single-turn inductor in the steady-state unbalanced current detection circuit of the present invention converts the steady-state unbalanced current between parallel modules into a voltage.

[0052] Figure 9 This is a schematic diagram of the active PWM edge adjustment circuit of the present invention adjusting the rising and falling edges of the drive signal from the upper-level DSP controller.

[0053] Figure 10 This is a circuit topology diagram illustrating a specific implementation process of the present invention.

[0054] Figure 11 To measure the steady-state unbalanced current detection circuit during the actual implementation process, the single-inductor converts the unbalanced current between the three parallel SiC-MOSFET half-bridge modules during turn-on and turn-off into voltage (V). CS The experimental waveform diagram.

[0055] Figure 12 The waveforms of the switching device currents and the total output current waveforms of the three parallel SiC-MOSFET half-bridge modules during actual implementation, without the parallel current sharing circuit and method of this invention, are measured.

[0056] Figure 13 The waveforms of the switching device currents and the total output current waveforms of the three parallel SiC-MOSFET half-bridge power modules during actual implementation, without the parallel current sharing circuit and method of this invention, are measured.

[0057] Figure 14 The waveforms of the switching device currents and the total output current were measured when the three parallel SiC-MOSFET half-bridge power modules were turned on using the topology and method of this invention during the actual implementation process.

[0058] Figure 15 The waveforms of the switching device currents and the total output current when the three parallel SiC-MOSFET half-bridge power modules are turned off are measured during the actual implementation process using the topology and method of this invention. Detailed Implementation

[0059] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0060] This invention provides a hybrid active and passive parallel current sharing circuit topology, the specific structure of which is as follows: Figure 1 As shown, it includes the DC bus V dcThe system consists of N SiC-MOSFET half-bridge modules, a passive current sharing circuit, and an active current sharing circuit. These N SiC-MOSFET half-bridge modules are interconnected. The N SiC-MOSFET half-bridge modules are named HBM1, HBM2, ..., HBM... N N SiC-MOSFET half-bridge modules are connected in parallel across the DC bus.

[0061] The passive current sharing circuit of this invention includes a passive current balancing circuit, a DC active current compensator, and a capacitor C. CO Inductor L CO The 300A and 65A Hall sensors have passive current balancing circuits consisting of N magnetic rings with additional windings of the same parameters, namely w1, w2...w... N Each magnetic ring has an additional winding with the same winding direction, and the additional windings are connected end to end to form a loop.

[0062] A 300A Hall sensor collects the total output current i0 of the N SiC-MOSFET half-bridge module, and a 65A Hall sensor collects the additional winding current i. s ;

[0063] The DC active current compensator includes a full-bridge inverter circuit and a DSP controller. The full-bridge inverter circuit includes power switches Q1, Q2, Q3, and Q4. In one phase, Q1 and Q2 are connected in series with complementary drive signals, and in the other phase, Q3 and Q4 are connected in series with complementary drive signals. The drive signals for Q1 and Q4 are the same, and the drive signals for Q2 and Q3 are the same. The DSP controller is connected to a 300A Hall sensor and a 65A Hall sensor, respectively, to receive the total output current i0 and the additional winding current i. s According to i0 is i s Adjust the duty cycle of the drive signals of the power switches Q1, Q2, Q3, and Q4 in the full-bridge inverter circuit by 30 times, and adjust i s compensate;

[0064] Capacitor C CO One end is connected to the midpoint of Q3 and Q4, and the beginning of the winding of magnetic ring W1, respectively. Inductance L CO One end is connected to the midpoint of Q1 and Q2, and the other end is connected to the magnetic ring w. N The winding end and capacitor C CO The other end; inductor L CO and capacitor C CO The compensation current i of the full-bridge inverter circuit output s For filtering purposes, N parallel-connected SiC-MOSFET half-bridge modules HBM1, HBM2...HBM N The midpoint output current passes through N magnetic rings with additional windings in the same direction.

[0065] The active current sharing circuit includes N active PWM edge adjustment circuits, N lower-level DSP controllers, N steady-state unbalanced current detection circuits, an upper-level DSP controller, and N gate driver ICs. i Transistor B ri Transistor B di N resistors R refi N capacitors C refi N resistors R refi’ N capacitors C refi’ N resistors R refi and N capacitors C refi Composition of RC filter circuit, N resistors R refi’ and N capacitors C refi’ The circuit consists of an RC filter circuit; N steady-state unbalanced current detection circuits correspond to single-turn inductors L1, L2...L... N Each single-turn inductor corresponds to the current output terminal of the N parallel SiC-MOSFET half-bridge module, with the current flowing from the current output terminal to the total current output terminal O through the N magnetic rings of the passive current sharing circuit.

[0066] Each active PWM edge-tuning circuit includes a comparator LMV. i Diode D di Diode D ri Resistance R ri and capacitor C ri The negative terminals of the comparators are all connected to capacitor C. ri One end, resistor R ri One end of the capacitor C ri The other end is grounded, and the resistor R ri The other end is connected to the upper-level DSP controller, and the outputs of the N comparators are each connected to N gate driver ICs. i The gate of the upper transistor of the corresponding N parallel SiC-MOSFET half-bridge module;

[0067] N steady-state unbalanced current detection circuits and N lower-level DSP controllers are connected accordingly. Each lower-level DSP controller has two outputs, one of which is connected to a resistor R in sequence. refi Capacitor C refi Transistor B ri collector and diode D ri The positive terminal of one output is connected to resistor R in sequence. refi’ Capacitor C refi’ Transistor B di collector and diode D di The positive terminal of diode D di and diode D riThe negative terminals are all connected to the positive terminals of the corresponding comparators; the upper-level DSP controller has three PWM signal outputs, namely V PWM S ri S di V PWM Passing through resistor R respectively ri The negative terminals of N comparators are connected in parallel to each other, and S is connected to the negative terminal of each comparator. ri Connected to transistor B respectively ri The base and steady-state unbalanced current detection circuit, S di Connected to transistor B respectively di The base and steady-state unbalanced current detection circuit, transistor B ri B di The emitters of all are grounded, where i = 1, 2, ..., N.

[0068] The specific structure of the steady-state unbalanced current detection circuit is as follows: Figure 2 As shown, Figure 2 This is a schematic diagram of the steady-state unbalanced current detection circuit of the present invention, which detects unbalanced current during turn-on and turn-off respectively; the unbalanced current quantities during turn-on and turn-off are converted into corresponding positive and negative voltages and sampled. It includes a sensing inductor L... CS The circuits for opening and closing the uneven current detection circuits are designed to include positive voltage detection and negative voltage detection, respectively.

[0069] The structure of the positive voltage detection circuit for the unequal current detection circuit is as follows: it includes diode D. 11 D 12 D 13 D 14 D 15 Inductor L 11 resistance R 11 R 12 R 13 Capacitor C 11 Transistor Q1; Diode D 11 Positive terminal connected to sensing inductor L CS Induced AC voltage V cs The positive terminal and the negative terminal are connected to the inductor L. 11 One end, inductor L 11 The other end is connected to diode D. 14 D 15 The positive terminal of diode D 14 The negative terminal is connected to the collector of transistor Q1, and the base of transistor Q1 is connected to the output S of the upper-level DSP controller. ri Diode D 15 The negative terminals are connected to resistors R respectively. 11 one end and capacitor C 11At one end, the emitter of transistor Q1 and resistor R 11 The other end, capacitor C 11 The other end, diode D 12 positive terminal, resistor R 12 One end of each diode is grounded, diode D 12 The negative terminal and resistor R 12 The other end is connected to diode D. 13 positive terminal and resistor R 13 One end, diode D 13 The negative terminal, resistor R 13 The other end is connected to the sensing inductor L CS Induced AC voltage V cs The negative end;

[0070] The structure for negative voltage detection in the unequal current detection circuit is as follows: it includes a resistor R. 21 R 22 R 23 diode D 21 D 22 D 23 D 24 D 25 Capacitor C 21 Inductor L 21 Transistor Q2, diode D 21 Positive terminal connected to sensing inductor L CS Induced AC voltage V cs The negative terminal is connected to the inductor L. 21 One end, inductor L 21 The other end is connected to diode D. 24 D 25 The positive terminal of diode D 24 The negative terminal is connected to the collector of transistor Q2, and the base of transistor Q2 is connected to the output S of the upper-level DSP controller. ri diode D 25 The negative terminals are connected to resistors R respectively. 21 One end, capacitor C 21 At one end, the emitter of transistor Q2 and resistor R 21 The other end, capacitor C 21 The other end, diode D 22 positive terminal, resistor R 22 One end of each diode is grounded, diode D 22 The negative terminal and resistor R 22 The other end is connected to diode D. 23 positive terminal and resistor R 23 One end, diode D 23 The negative terminal, resistor R 23 The other end is connected to the sensing inductor LCS Induced AC voltage V cs The positive end;

[0071] The structure of the positive voltage detection in the off-current imbalance detection circuit is as follows: it includes diode D. 31 D 32 D 33 D 34 D 35 Inductor L 31 resistance R 31 R 32 R 33 Capacitor C 31 Transistor Q3; Diode D 31 Positive terminal connected to sensing inductor L CS Induced AC voltage V cs The positive terminal and the negative terminal are connected to the inductor L. 31 One end, inductor L 31 The other end is connected to diode D. 34 D 35 The positive terminal of diode D 34 The negative terminal is connected to the collector of transistor Q3, and the base of transistor Q3 is connected to the output S of the upper-level DSP controller. di Diode D 35 The negative terminals are connected to resistors R respectively. 31 one end and capacitor C 31 At one end, the emitter of transistor Q3 and resistor R 31 The other end, capacitor C 31 The other end, diode D 32 positive terminal, resistor R 32 One end of each diode is grounded, diode D 32 The negative terminal and resistor R 32 The other end is connected to diode D. 33 positive terminal and resistor R 33 One end, diode D 33 The negative terminal, resistor R 33 The other end is connected to the sensing inductor L CS Induced AC voltage V cs The negative end;

[0072] The structure of the negative voltage detection circuit for the shutdown non-uniform current detection circuit is as follows: it includes resistor R 41 R 42 R 43 diode D 41 D 42 D 43 D 44 D 45 Capacitor C 41 Inductor L 41Transistor Q4, diode D 41 Positive terminal connected to sensing inductor L CS Induced AC voltage V cs The negative terminal is connected to the inductor L. 41 One end, inductor L 41 The other end is connected to diode D. 44 D 45 The positive terminal of diode D 44 The negative terminal is connected to the collector of transistor Q4, and the base of transistor Q4 is connected to the output S of the upper-level DSP controller. di diode D 45 The negative terminals are connected to resistors R respectively. 41 One end, capacitor C 41 At one end, the emitter of transistor Q4 and resistor R 41 The other end, capacitor C 41 The other end, diode D 42 positive terminal, resistor R 42 One end of each diode is grounded, diode D 42 The negative terminal and resistor R 42 The other end is connected to diode D. 43 positive terminal and resistor R 43 One end, diode D 43 The negative terminal, resistor R 43 The other end is connected to the sensing inductor L CS Induced AC voltage V cs The positive end;

[0073] Sensing inductor L CS That is, single-turn inductors L1, L2...L N Single-turn inductors L1, L2...L N One end of each circuit is connected to the positive terminal of Vcs in N steady-state unbalanced current detection circuits, and the single-turn inductors L1, L2...L... N The other end is connected to the negative terminal of Vcs of N steady-state unbalanced current detection circuits, with single-turn inductors L1, L2...L... N The steady-state uneven current of N parallel SiC-MOSFET half-bridge modules is sensed through the corresponding magnetic ring and converted into signals Vr+, Vr-, Vd+, and Vd-, which are then connected to the controller of the next-level DSP.

[0074] This invention also provides a hybrid active and passive parallel current sharing method, specifically including a passive parallel current sharing method and an active parallel current sharing method, the implementation of which includes the following steps:

[0075] S1: The specific implementation steps of the passive parallel current sharing method are as follows:

[0076] (1) N SiC-MOSFET half-bridge modules HBM1, HBM2...HBM N Parallel to DC bus V dc At both ends, the current output terminals of each SiC-MOSFET half-bridge module converge at point O to form the total current output terminal O;

[0077] (2) The N magnetic rings w1, w2, ..., w in the passive current balancing circuit N Each of the N magnetic rings has an additional winding of n turns, and the additional windings of the N magnetic rings are connected end to end in sequence and are passed through the current output terminals of the N parallel SiC-MOSFET half-bridge modules. Let w be the number of the i-th magnetic ring. i The inductance value is L s The inductance value at the current output terminal of each SiC-MOSFET half-bridge module is L0;

[0078] (3) Magnetic ring w i A magnetic core with high permeability that is not easily saturated is selected, therefore L0 and L s If a fully coupled relationship exists, then L s =n 2 When a brief imbalance exists among the output currents of the N parallel SiC-MOSFET half-bridge modules passing through the magnetic ring, the magnetic ring induces a reverse current i. s This is used to suppress transient current imbalance among N parallel SiC-MOSFET half-bridge modules;

[0079] (4) When operating in DC / DC mode, the magnetic ring w i Induced current i s After a short period of time, it will saturate and lose its ability to suppress transient current imbalances among the N parallel SiC-MOSFET half-bridge modules. At this point, the DSP controller receives the total output current i. o , and according to i o is i s 30 times the relationship control DC active current compensator for i s compensate;

[0080] (5) The passive current sharing circuit can suppress the current imbalance at the moment of turn-on and turn-off of N parallel SiC-MOSFET half-bridge modules. When the imbalance between N parallel SiC-MOSFET half-bridge modules is serious, the active parallel current sharing circuit and method are combined to achieve current balance between N parallel SiC-MOSFET half-bridge modules.

[0081] S2: The specific implementation steps of the active parallel current sharing method are as follows:

[0082] (1) The N single-turn inductors L1, L2...L in the steady-state unbalanced current detection circuit NThe inductors L0, which pass through N magnetic rings and are connected in parallel to the current output terminals of N SiC-MOSFET half-bridge modules, are fully coupled.

[0083] (2) When there is a steady-state current imbalance among N parallel SiC-MOSFET half-bridge modules, the single-turn inductor of the steady-state imbalance current detection circuit induces a voltage v. cs This voltage is converted into the corresponding V by turning on the positive voltage detection circuit, turning on the negative voltage detection circuit, turning off the positive voltage detection circuit, and turning off the negative voltage detection circuit. r+ V r- V d+ V d- This voltage reflects the unbalanced current among the N parallel SiC-MOSFET half-bridge modules;

[0084] (3) The steady-state unbalanced current detection circuit in step (2) detects the current based on the S output from the upper-level DSP controller. ri and S di The signal selectively detects the turn-on and turn-off current imbalances among the N parallel SiC-MOSFET half-bridge modules.

[0085] The specific process is as follows: the signal S output by the upper-level DSP controller... ri For low S di To detect and convert the uneven turn-on current among N parallel SiC-MOSFET half-bridge modules into V during high-time operation. r+ and V r- S ri To enable low-pass bypass current unevenness detection circuit, S di For the high bypass shutdown uneven current detection circuit, the signal S output by the upper-level DSP controller ri For high S di To detect the turn-off current imbalance among N parallel SiC-MOSFET half-bridge modules at low speeds and convert it into V d+ and V d- , where S ri For high bypass, open the uneven current detection circuit, S di This is a low-bypass turn-off unbalanced current detection circuit; this circuit can detect the turn-on and turn-off unbalanced currents of N parallel SiC-MOSFET half-bridge modules, and express the results as voltage values ​​V. Ci The representation is shown in the diagram, where C represents r+, r-, d+, and d-, and i represents the serial number of the corresponding steady-state unbalanced current detection circuit.

[0086] (4) The voltage V corresponding to the turn-on uneven current detected in step (3) among the N parallel SiC-MOSFET half-bridge modules Ci It is converted into the lower-level DSP controller to control the PWM duty cycle δ of the DSP's internal DAC module.ri The voltage V corresponding to the unbalanced turn-off current among the N parallel SiC-MOSFET half-bridge modules detected. Ci This is converted into the duty cycle δ of the PWM module controlled by the lower-level DSP controller. di ;

[0087] (5) δ in step (4) ri The lower-level DSP controller controls the internal DAC module to output the corresponding N parallel SiC-MOSFET half-bridge module turn-on edge adjustment reference v. refi δ di The lower-level DSP controller controls the DAC module to output the corresponding N parallel SiC-MOSFET half-bridge modules' turn-off edge adjustment reference v. refi’ ;

[0088] (6) v in step (5) refi and v refi’ The drive signal v from the upper-level DSP controller is supplied to the positive terminal of the comparator of the active PWM edge adjustment circuit. PWM The signal S from the upper-level DSP controller is given to the negative terminal of the comparator in the active PWM edge adjustment circuit; ri For low S di When v is high refi With the drive signal v from the upper-level DSP controller PWM Compare and adjust the turn-on drive signals of the corresponding N parallel SiC-MOSFET half-bridge modules in advance or delay; when the signal S from the upper-level DSP controller... ri For high S di When v is low refi’ With the drive signal v from the upper-level DSP controller PWM The system compares and adjusts the turn-off drive signals of N parallel SiC-MOSFET half-bridge modules by advancing or delaying them, and finally outputs the corresponding adjusted drive signal PWM. Oi ;

[0089] (7) The PWM output of the comparator in step (6) Oi via corresponding gate driver ICs i After increasing the driving capability, the signal is sent to the gate of the upper transistor of the corresponding N parallel SiC-MOSFET half-bridge module and controlled to turn it on or off. This closed-loop control can achieve transient and steady-state balance of the output current of the N parallel SiC-MOSFET half-bridge modules.

[0090] If the rated currents of N parallel SiC-MOSFET half-bridge modules are the same, then the magnetic core parameters of the passive current balancing circuits of the N passive current sharing circuits and the parameters of the additional windings wound around each magnetic core are the same. The active PWM edge adjustment circuits and steady-state unbalanced current detection circuits of the N active current sharing circuits have the same function. If the rated currents of the N parallel SiC-MOSFET half-bridge modules are different, then the magnetic core parameters of the passive current balancing circuits of the N passive current sharing circuits and the parameters of the additional windings wound around each magnetic core are linearly related to the rated currents of the N parallel SiC-MOSFET half-bridge modules. The settings of the active PWM edge adjustment circuits and steady-state unbalanced current detection circuits of the N active current sharing circuits are also linearly related to the rated currents of the N parallel SiC-MOSFET half-bridge modules.

[0091] The passive current balancing circuit provided by this invention provides transient current imbalance suppression impedance L0 for N SiC-MOSFET half-bridge modules and also provides a connection medium for the sensing inductor of the steady-state unbalanced current detection circuit. Its working principle is as follows:

[0092] like Figure 3 As shown, let the inductance passing through the magnetic ring be L0, and the additional windings of the magnetic ring each have n turns. Calculate this inductance as L. s The relationship between the two is L. s =n 2 L0. If the magnetic core selected for the magnetic ring has relatively high permeability, then the mutual inductance between the two is... according to Figure 3-1 We can obtain:

[0093]

[0094] The output current and the magnetic flux generated by the additional winding, such as Figure 3-1 As shown, the direction of the magnetic flux generated by the output current is opposite to the direction of the magnetic flux generated by the additional winding, exhibiting a reverse coupling relationship. The equivalent circuit is as follows: Figure 3-2 As shown. By Figure 3-2 According to KVL's law, we can obtain v 1O +v 2O +···+v NO =0. Substituting equation (1) into the equation, we get Combining this with equation (1), we can deduce that:

[0095]

[0096] To simplify Figure 3-2 The analysis of the equivalent circuit involves converting the primary currents i1, i2, ... i N Decomposed into common-mode (CM) current i CM Sum and difference mode (DM) current i DM1 i DM2 ...i DMNIt is given by the following two equations:

[0097]

[0098]

[0099] It can be deduced that the DM current is 0.

[0100] i DM1 +i DM2 +...+i DMN =0 (5)

[0101] In summary, the common-mode current flows to the output terminal, while the differential-mode current only flows between the additional windings of the passive current-sharing circuit. The differential-mode current represents the unbalanced current of the parallel SiC-MOSFET half-bridge module.

[0102] According to equations (3), (4), and (5), the relationships between differential-mode voltage, common-mode voltage, and input / output voltage can be obtained:

[0103]

[0104] In the formula, the voltages of CM and DM are expressed as:

[0105]

[0106]

[0107] As shown in equation (7), the common-mode voltage of the magnetic ring is 0, so the additional winding closed loop has no effect on the common-mode current. Therefore, the reactive power generated by the passive current sharing circuit is negligible.

[0108] According to equations (6), (7), and (8), we can obtain:

[0109]

[0110] From equations (7) and (9), the equivalent circuits of CM and DM with additional winding closed loops can be obtained, such as Figure 4 As shown. From Figure 4 It can be seen that the additional winding closed loop has no effect on the CM current, but provides additional impedance for the DM current. Therefore, it can suppress the unbalanced current between the parallel SiC-MOSFET half-bridge modules.

[0111] The common-mode equivalent circuit analysis model converging at point O is as follows Figure 4-1 Differential-mode equivalent circuit analysis model, such as Figure 4-2 ,Depend on Figure 4-1 and Figure 4-2 It can be seen that the output voltage of the parallel SiC-MOSFET half-bridge module can be expressed as:

[0112]

[0113] v 1O +v 2O +···+v NO Substituting 0 into equation (10), we get:

[0114]

[0115] It can be seen that the output voltage at output point O is equal to the average output voltage of N parallel SiC-MOSFET half-bridge modules. To ensure effective operation of the additional winding closed loop under various conditions, the worst-case scenario of current imbalance is considered. When only one SiC-MOSFET half-bridge module is turned on and the rest are turned off, the voltage across L0 reaches its maximum value V. UBmax The formula is given as follows:

[0116]

[0117] Assume V UBmax The maximum mismatch duration is ΔT max The maximum permissible transient unbalanced current is ΔI. b The minimum inductance of L0 can then be calculated as:

[0118]

[0119] Figure 5 In the middle, the equivalent circuit analysis model of the full-bridge inverter circuit without the connection of N magnetic ring additional winding series circuit is as follows: Figure 5-1 The equivalent circuit analysis model when N magnetic rings with additional windings connected in series is as follows: Figure 5-2 ; Figure 5-2 The model solved Figure 5-1 The additional winding of the passive current balancing circuit in the passive current sharing circuit has caused magnetic ring saturation when applied to DC / DC converters. Figure 5-1 This shows the equivalent circuit diagram of the additional winding loop without a DC current compensator. The resistance of the wires in the short-circuit loop of the additional winding is assumed to be R. S The sum of the additional winding inductances is NL. S The additional winding current is i S According to KVL, we can obtain Assume the initial state is Combining the two equations, we can obtain Because of the resistance in the winding, this current will decay to zero, and the decay time constant is... To prevent its decay to 0, the settings are as shown in the diagram. Figure 5-2 The DC current compensator shown in the circuit diagram has a current after compensation of [value missing]. This DC current compensator only compensates for the current in the additional winding circuit, so it does not require particularly high responsiveness.

[0120] Figure 6 This diagram shows three SiC-MOSFET half-bridge modules with a passive current sharing circuit, designed to investigate steady-state current imbalance between parallel modules. The passive current sharing circuit can suppress transient current imbalance but not steady-state current imbalance; prolonged steady-state current imbalance can lead to magnetic ring saturation.

[0121] Figure 7 middle, Figure 7-1 Under the condition of inconsistent threshold voltage, Figure 7-2 This is due to the current imbalance between parallel SiC-MOSFET half-bridge modules caused by duty cycle mismatch. Figure 7-1 In the middle, V GS V represents the gate voltage of three SiC-MOSFETs. th1 V th2 and V th3 (V th1 <V th2 <V th3 ) represents the threshold voltage of the three SiC-MOSFETs, v L1 v L2 and v L3 i1, i2, and i3 are the voltages on the toroidal core, i1, i2, and i3 are the output currents of the three SiC-MOSFETs, and v r1 v r2 v r3 v d1 v d2 and v d3 This is the sensing voltage of the steady-state unbalanced current detection circuit.

[0122] t0: The gate voltage of the SiC-MOSFET reaches V th1 With switch S1 of HBM1 on, D4 and D6 are in a free state. The voltage V of L1 is... L1 2V dc / 3, the voltage between L2 and L3 is -V dc / 3. During the time interval t0-t1, v L1 For +, v L2 and v L3 When the output current is -, the output current i1 increases, while the output currents i2 and i3 decrease.

[0123] t1: The gate voltage of the SiC-MOSFET reaches V th2 With S3 of HBM2 on, D6 is in a free state. The voltage between L1 and L2 is V. dc / 3, the voltage of L3 is -2V dc / 3. During the time interval t1-t2, v L1 and v L2 For +, v L3 When the output current is -, the output currents i1 and i2 increase, and the output current i3 decreases.

[0124] t2: The gate voltage of the SiC-MOSFET reaches V th3 HBM3's S5 is turned on. During the time interval t2-t3, all SiC-MOSFETs are turned on, and the voltages of L1, L2, and L3 are zero.

[0125] t3: The gate voltage of the SiC-MOSFET drops to V th3 S5 of HBM3 is turned off. The voltage between L1 and L2 is V. dc / 3, the voltage of L3 is -2V dc / 3. During the time interval t3-t4, v L1 and v L2 For +, v L3 When the output current is -, the output currents i1 and i2 increase, and the output current i3 decreases.

[0126] t4: The gate voltage of the SiC-MOSFET drops to V th2 HBM2's S3 is off. The voltage across L1 is 2V. dc / 3, the voltage between L2 and L3 is -(V dc / 3). During the time interval t4-t5, v L1 For +, and v L2 and v L3 When the value is +, the output current i1 increases, while the output currents i2 and i3 decrease.

[0127] t5: The gate voltage of the SiC-MOSFET drops to V th1 HBM1's S1 is turned off. All SiC-MOSFETs are turned off, and the voltages of L1, L2, and L3 are zero.

[0128] The change in output current during conduction and turn-off can be expressed as:

[0129]

[0130] Here, Δd1 and Δd2 represent the duty cycle mismatch caused by the inconsistency of the threshold voltage. Analysis shows that the steady-state unbalanced current is caused by the duty cycle mismatch resulting from the inconsistency of the threshold voltage.

[0131] Other factors contributing to duty cycle mismatch include variations in the gate drive signal, non-ideal gate drive circuitry, manufacturing tolerances, temperature variations, and control loop errors. Figure 7-2 This is a schematic diagram for analyzing steady-state unbalanced current caused by duty cycle mismatch. Figure 7-2Among them, V GS1 , V GS2 and V GS3 are the gate voltages of three SiC-MOSFETs, and D1, D2, and D3 (D1 < D2 < D3) are the duty cycles of the three SiC-MOSFETs. v L1 , v L2 and v L3 are the voltages on the toroidal core, and i1, i2, and i3 are the output currents of the three SiC-MOSFETs.

[0132] During the time interval of t0 - t3, the voltage analysis of L1, L2, and L3 is the same as Figure 7-1 .

[0133] t3: S1 of HBM1 is turned off, the voltage of L1 is -2V dc / 3, and the voltages of L2 and L3 are V dc / 3. During the time interval of t3 - t4, v L1 is positive, v L2 and v L3 are negative, resulting in a decrease in the output current i1 and an increase in the output currents i2 and i3.

[0134] t4: S3 of HBM2 is turned off, the voltages of L1 and L2 are -V dc / 3, and the voltage of L3 is 2V dc / 3. During the time interval of t4 - t5, v L1 and v L2 are negative, v L3 is positive, resulting in a decrease in the output currents i1 and i2 and an increase in the output current i3.

[0135] t5: S5 of HBM3 is turned off, all SiC-MOSFETs are turned off, and the voltages on L1, L2, and L3 are 0.

[0136] The changes in the output current during conduction and turn-off can be expressed as:

[0137]

[0138] where Δd1, Δd2, Δd3, and Δd4 are duty cycle mismatches. It can be analyzed that the steady-state unbalanced current is caused by duty cycle mismatch.

[0139] The above analysis shows that the steady-state unbalanced current is caused by duty cycle mismatch. If the duty cycle mismatch is not solved, it will lead to magnetic ring saturation and uneven conduction losses between modules. Therefore, an active current sharing circuit needs to be adopted to suppress the steady-state unbalanced current.

[0140] Figure 8 This is the circuit diagram for detecting the steady-state unbalanced current of the present invention. In Figure 8middle, Figure 8-1 Schematic diagram of positive voltage sampling principle Figure 8-2 Schematic diagram of negative voltage sampling principle Figure 8-3 A schematic diagram showing the conversion of unbalanced current to corresponding positive voltage during startup. Figure 8-4 A schematic diagram showing the conversion of unbalanced current to corresponding positive voltage during turn-off. Figure 8-5 A schematic diagram illustrating the conversion of unbalanced current into corresponding negative voltage during startup. Figure 8-6 A schematic diagram showing the conversion of unbalanced current into corresponding negative voltage during shutdown. Figure 8 The toroidal core has three windings, L0 and L... s This belongs to a passive current sharing circuit, and the inductor L cs With L0 and L s A fully coupled sensing winding is formed. The turns ratio of the three windings is n:1:1. The sensing winding is used to detect the steady-state unbalanced current at the output of the SiC-MOSFET half-bridge module. When the unbalanced current flows through the toroidal core, a voltage fluctuation is induced on the sensing winding, indicating a duty cycle mismatch. The induced voltage on the sensing winding can be either positive or negative; therefore, separate positive and negative voltage detection circuits are required during turn-on and turn-off transitions. The voltage detection circuit includes a holding capacitor C. i1 (i = 1, 2, 3), a filter inductor L i1 Five diodes (D) i1 ~D i5 ), three resistors (R) i1 R i2 R i3 ) and a transistor Q i ,like Figure 8 As shown. Capacitor C i1 Used to maintain the sensing voltage v cs ,R i1 It is a discharge resistor. (D) i2 D i3 ,R i2 and R i3 Used to stabilize the voltage potential of the induction winding. Q i It is a bypass transistor used to bypass the voltage detection circuit when the voltage detection circuit is on. D i4 Used to block the application applied to transistor Q i The negative voltage on it prevents transistor Q from being i It is disrupted. During the conduction transition of the SiC-MOSFET, rising edge detection enables, Q1 and Q2 turn off, Q3 and Q4 turn on, and falling edge detection disables. If the voltage v cs The value is positive, and the capacitor C is positive. 11 Will be through D 11 -L 11 -D 15 -C11 -D 12 -D 13 The current flows through the charging path, while the capacitor C... 21 Because the voltage is controlled by diode D 21 Blocking without charging. Conversely, if the voltage v cs If it is negative, then the capacitor C 21 Will be through D 21 -L 21 -D 25 -C 21 -D 22 -D 23 The current flows through the charging path, while the capacitor C... 11 Because the voltage is controlled by diode D 11 Blocking without charging. C 11 and C 21 The voltages are respectively V r+ and V r- This indicates a duty cycle mismatch during the turn-off transition. During the turn-off transition of the SiC-MOSFET, falling edge detection is enabled, Q3 and Q4 are turned off, while Q1 and Q2 are turned on, and rising edge detection is disabled. If the voltage v cs If positive, the capacitor C 31 Will be through D 31 -L 31 -D 35 -C 31 -D 32 -D 33 The current flows through the charging path, while the capacitor C 41 Because the voltage is controlled by diode D 41 Blocking without charging. Conversely, if the voltage v cs If it is negative, then the capacitor C 41 Will be through D 41 -L 41 -D 45 -C 41 -D 42 -D 43 The current flows through the charging path, while the capacitor C... 31 The voltage will be due to diode D 31 Blocking without charging. C 31 and C 41 The voltages are respectively V d+ and V d- This indicates a duty cycle mismatch during the turn-off transition.

[0141] The working principle of the steady-state unbalanced current detection circuit is as follows: Figure 8 As shown. The equivalent circuits for the inductor charging and discharging intervals are respectively as follows: Figure 8-1 and Figure 8-2 As shown. The working process of the steady-state unbalanced current detection circuit is analyzed, starting from... Figure 7-1 Four typical cases were selected, including two typical cases of positive sensing voltage detection and two typical cases of negative sensing voltage detection, such as... Figure 8-3 to Figure 8-6 As shown.

[0142] Figure 8-3 In the diagram, the inductor charging interval is t0-t2, and the inductor discharging interval is t2-t. z Based on the inductor voltage-second balance, the equivalent voltage during the time interval t0-t2 is:

[0143]

[0144] Where ΔD1 = (Δd1 + Δd2). It can be derived that:

[0145]

[0146] Where T s This represents the switching cycle of the SiC-MOSFET.

[0147] Based on the charge balance of the capacitor, we can obtain the following equation:

[0148]

[0149] According to equations (17) and (18), the voltage across the capacitor can be derived as follows:

[0150]

[0151] Similarly, in Figure 8-4 In the diagram, the inductor charging interval is t1-t2, and the inductor discharging interval is t2-t. z The voltage during the time interval t0-t2 is V. dc / 3, V in equation (19) x+ Replace ΔD1 with V respectively dc By using / 3 and Δd2, the voltage across the holding capacitor can be obtained.

[0152] Figure 8-5 In the diagram, the inductor charging interval is t1-t2, and the inductor discharging interval is t2-t. z The equivalent voltage during the time interval from t0 to t2 can be obtained as follows:

[0153]

[0154] By using V in equation (19) x+ Replace with V x- This allows you to obtain the voltage across the holding capacitor.

[0155] Figure 8-6In the diagram, the inductor charging interval is t0-t1, and the inductor discharging interval is t1-t. z The voltage during the time interval t0-t1 is V. dc / 3, V in equation (19) x+ Replace ΔD1 with V respectively dc By using / 3 and Δd1, the voltage across the holding capacitor can be obtained. For Figure 6 The voltage across the holding capacitor can be derived in a similar manner for the other cases shown.

[0156] When N SiC-MOSFET half-bridge modules are connected in parallel, the voltage error caused by duty cycle mismatch during conduction can be defined as:

[0157] δ rm =v rm+ -v rm- (m=1,2,......,N) (21)

[0158] Among them, “v rm+ " and "v rm- "V" represents the DC voltage, indicating the positive and negative detection voltages of the SiC-MOSFET module m, respectively. rm+ "The higher the value, the earlier the module is activated compared to other modules," "v" rm- The higher the value, the later the module is activated compared to other modules. Because v rm+ and v rm- It is induced by the DM voltage in (8), and the sum of the DM voltages is zero. Therefore, the sum of the voltage errors caused by duty cycle mismatch during conduction is

[0159]

[0160] For turn-off transition, the voltage error caused by duty cycle mismatch during the turn-off transition period can be defined as:

[0161] δ dm =v dm+ -v dm- (m=1,2,......,N) (23)

[0162] Where v dm+ and v dm- ν represents the DC voltage, indicating the positive and negative detection voltages of the SiC-MOSFET module m, respectively. dr+ The higher the value, the later the module shuts down compared to other modules. dr- The higher the value, the earlier the module shuts down compared to other modules. Because v... dm+ and v dm- It is induced by the DM voltage in (12), and the sum of the DM voltages is zero. Therefore, the sum of the voltage errors caused by duty cycle mismatch during the turn-off transition is

[0163]

[0164] Based on (10) and (13), we can calculate Figure 6 V in r1 V r2 V r3 V d1 V d2 V d3 .

[0165] Furthermore, to suppress steady-state unbalanced current, an active PWM edge adjustment circuit is used to adjust the duty cycle mismatch to 0 to achieve current balance. Therefore, in (22) and (24), δ r_total and δ d_total This is used as a control reference value for PWM edge regulation during turn-on and turn-off transitions. The voltage required for duty cycle regulation for each SiC-MOSFET can be expressed as...

[0166]

[0167] The circuit diagram of the active PWM edge adjustment strategy is as follows: Figure 1 As shown. During the turn-on and turn-off processes, the steady-state unbalanced current detection circuit converts the steady-state unbalanced current into a DC voltage, i.e., δ. rm and δ dm The DSP controller samples these voltages and employs a closed-loop control algorithm. Figure 1 In the middle, v pwm This represents the comparator input voltage generated by the main controller drive signal with an RC filter. The control voltage is another input to the comparator, derived from the DSP controller, and adjusts the PWM edges for lead or lag. The control voltages v0 are generated using the rising and falling edges respectively. refi and v refi' The PWM edges are controlled by the master controller. Rising and falling edge enable signals are issued by the master controller, which controls transistor S. ri and S di During the passage of the missile, S ri Close, S di Open, v refi The signal is transferred to the comparator to control the rising edge of the PWM. During the turn-off transition, S... ri Open, S di Close, v refi' The control is transferred to the comparator to manage the falling edge of the PWM. oi This represents the comparator's output, which is sent to the gate driver. To better illustrate the working principle of active PWM edge modulation, let's take a three-parallel SiC-MOSFET half-bridge module as an example, such as... Figure 9 As shown. Figure 9 In the middle, V GSi (i = 1, 2, 3) represents the gate signal of the SiC-MSOFET before adjustment, V GSref V is the target gate signal for active PWM edge modulation. GSi’ This refers to the gate voltage after adjustment in a SiC-MSOFET. pwm v refi v refi’ and PWM oi Definition same as Figure 1 The reference control voltage v of the target gate signal ref0 and v ref0′ For v pwm Half of it.

[0168] During the conversion process, V GS1 Leading V GSref One phase φ1, while V GS2 and V GS3 Lagging behind V respectively GSref A phase φ2 and φ3. To adjust V... GS1 To match the target gate signal V GSref The DSP controller generates a value greater than v. ref0 Δ δr1 Control voltage v ref1 Connect this control voltage to v PWM The comparison is performed, and the comparator outputs a PWM signal. o1 This will generate a phase delay φ1. Therefore, the controlled gate signal V GS1' With target gate signal V GSref Same. To adjust V GS2 and V GS3 Matching target gate signal V GSref The control voltage v generated by the DSP controller ref2 and v ref3 Compared to v ref0 Small Δ δr2 and Δ δr3 Connect these control voltages with v PWM Comparison, at the comparator output PWM o2 and PWM o3 The preceding phases φ2 and φ3 are generated, indicating that... Finally, the controlled gate signal V... GS2' and V GS3' Adjust it to match the target gate signal V. GSref match.

[0169] During the turn-off transition, the gate signal V GS1 and V GS2 Each ahead of V GSref The φ4 and φ5 phases, and VGS3 Lagging behind V GSref The φ6 phase. To adjust V... GS1 To match the target gate signal V GSref The control voltage v generated by the DSP controller ref1' and v ref2' Compared to v ref0' Small Δ δd1 and Δ δd2 Then these control voltages are compared with v PWM The comparison yields phase delays, which are then applied to the comparator output PWM. o1 and PWM o2 φ4 and φ5 are generated. Therefore, the regulating gate signal V GS1' and V GS2' With target gate signal V GSref Matching. To adjust V GS3 To match the target gate signal V GSref The DSP controller generates a value greater than v. ref0' Δ δd3 Control voltage v ref3' The control voltage is related to v. PWM Comparison, at the comparator output PWM o3 This generates a leading phase φ6. Therefore, the regulating gate signal V GS3' With target gate signal V GSref match.

[0170] By utilizing active PWM edge modulation, the gate signals of three parallel SiC-MOSFETs can be adjusted to align with the target gate signal. This method effectively eliminates any potential duty cycle mismatches, thereby achieving steady-state current balance in the parallel SiC-MOSFET module.

[0171] The specific verification implementation methods of the present invention are as follows: Figure 10 As shown, Figure 10 An embodiment of a three-SiC-MOSFET half-bridge power module of the present invention is shown. In this embodiment, the DC input power supply Vdc is 600V. The total output current is i. O =300A, the number of parallel power modules is N=3, using 1200V / 120A SiC-MOSFET half-bridge power modules, with each SiC-MOSFET module having the same output current i1=i2=i3=100A. The maximum voltage induced on a single-turn inductor does not exceed 400V. To keep the unbalanced current within 3% of the output current of the SiC-MOSFET half-bridge power module, ΔI is selected. b=3A, therefore the minimum inductance value required for a single-turn inductor L0 can be calculated as 5.625uH. A toroidal inductor is wound with R10KZ material of Mn-Zn high permeability produced by DMEGC (Dongci). The selected toroidal core model is H42*26*18P. For a single-turn inductor, the number of turns is 1, so the inductance value is 10.268uH. The additional winding turns of the toroidal core are calculated to be 75 turns, therefore the current in the closed circuit is calculated to be 3A.

[0172] Figure 11 The measured waveform of the voltage generated by the unbalanced current between parallel power modules induced by the inductor of the steady-state unbalanced current detection circuit of the active current sharing circuit provided by the present invention.

[0173] Figure 12 Showing Figure 10 The three parallel SiC-MOSFET half-bridge power modules in the invention do not contain the parallel current sharing circuit and method of the present invention, and the waveforms of the current of each parallel switching device and the total output current when turned on.

[0174] Figure 13 Showing Figure 10 The three parallel SiC-MOSFET half-bridge power modules in the invention do not contain the parallel current sharing circuit and method of the present invention, and the waveforms of the current of each parallel switching device and the total output current when turned off are shown.

[0175] Figure 14 Showing Figure 10 The three parallel SiC-MOSFET half-bridge power modules in the invention use the topology and method of this invention, and the waveforms of the current of each parallel switching device and the total output current when turned on are shown.

[0176] Figure 15 Showing Figure 10 The three parallel SiC-MOSFET half-bridge power modules in the diagram use the topology and method of this invention. The waveforms of the current of each parallel switching device and the total output current when turned off are shown. Comparing the four waveforms, it can be seen that the active and passive current sharing circuits provided by this invention can achieve good current balancing effects.

[0177] Although this embodiment only shows an example with three half-bridge power modules, it is important to emphasize that this invention can be easily applied to situations where N power modules or devices are directly connected in parallel and current balancing is required among them. In implementation, the passive current sharing circuit requires the addition of a corresponding number of toroidal cores and additional windings with the same parameters; the active current sharing circuit requires the addition of an unbalanced current sampling circuit, an active PWM edge adjustment circuit, and a DSP controller, corresponding to the passive current sharing circuit. Therefore, this invention possesses excellent modularity, is easily expandable, simple to implement, and inexpensive.

[0178] The above description is merely a preferred embodiment of the invention and not a limitation thereof. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this invention should be included within the protection scope of this invention.

Claims

1. A hybrid active and passive parallel current sharing circuit topology, characterized in that: Includes DC bus V dc , N A SiC-MOSFET half-bridge module, a passive current sharing circuit, and an active current sharing circuit. N The SiC-MOSFET half-bridge module, the passive current sharing circuit, and the active current sharing circuit are interconnected, among which... N Each SiC-MOSFET half-bridge module is respectively , ... , N A SiC-MOSFET half-bridge module is connected in parallel across the DC bus. The passive current sharing circuit includes a passive current balancing circuit, a DC active current compensator, and a capacitor. C CO ,inductance L CO The passive current balancing circuit consists of a 300A Hall sensor and a 65A Hall sensor. N It consists of magnetic rings with additional windings having the same parameters, respectively. , ... Each magnetic ring has an additional winding with the same winding direction, and the additional windings are connected end to end to form a loop. The 300A Hall sensor collects data. N The total output current of the SiC-MOSFET half-bridge module i 0 A 65A Hall sensor collects the additional winding current. i s ; The DC active current compensator includes a full-bridge inverter circuit and DSP The controller, the full-bridge inverter circuit includes power switching transistors. Q 1 , Q 2 , Q 3 , Q 4 One of them is Q 1 , Q 2 The two phases are connected in series and their drive signals are complementary, while the other phase is... Q 3 , Q 4 Series connection and complementary drive signals Q 1 With Q 4 Same drive signal Q 2 and Q 3 The drive signals are the same; DSP The controller is connected to a 300A Hall sensor and a 65A Hall sensor respectively, thus receiving the total output current. i 0 and additional winding current i s ,according to i 0 yes i s 30x adjustment of the power switching transistors of the full-bridge inverter circuit Q 1 , Q 2 , Q 3 , Q 4 The duty cycle of the drive signal, and for i s compensate; capacitance C CO One end is connected to Q 3 and Q 4 Midpoint, magnetic ring The beginning of the winding, inductance L CO One end connected to Q 1 and Q 2 The midpoint is connected to the magnetic ring at the other end. The winding ends and capacitors C CO The other end; inductor L CO and capacitor C CO Compensation current for the output of the full-bridge inverter circuit i s It serves as a filter. N A parallel SiC-MOSFET half-bridge module , ... The midpoint output current passes through the same direction respectively. N A magnetic ring with additional windings.

2. The active and passive hybrid parallel current sharing circuit topology according to claim 1, characterized in that: The active current sharing circuit includes N One with source PWM Edge adjustment circuit N subordinates DSP controller, N A steady-state unbalanced current detection circuit, upper stage DSP controller, N Gate drive ICs i ,triode B ri ,triode B di , N resistors R refi , N one capacitor C refi , N resistors R refi’ , N one capacitor C refi’ , N resistors R refi and N one capacitor C refi composition RC Filtering circuit N resistors R refi’ and N one capacitor C refi’ composition RC Filtering circuit; N Each steady-state unbalanced current detection circuit corresponds to a single-turn inductor. L 1 , L 2 ... L N Single-turn inductors correspond to respectively according to N The current flows from the current output terminal of each parallel SiC-MOSFET half-bridge module to the total current output terminal. O The direction through the passive current sharing circuit N One magnetic ring; Each active PWM Edge adjustment circuits all include comparators LMV i ,diode D di ,diode D ri ,resistance R ri and capacitor C ri The negative terminals of the comparators are all connected to capacitors. C ri One end, resistor R ri One end of the capacitor C ri The other end is grounded, resistor R ri The other end connects to the upper level DSP Controller N The outputs of each comparator are each driven by N gate drivers. ICs i And corresponding connections N The gate of the upper transistor in a parallel SiC-MOSFET half-bridge module; N A steady-state unbalanced current detection circuit and N subordinates DSP The controllers are connected to each corresponding lower level. DSP The controller has two outputs, one of which is connected to resistors in sequence. R refi ,capacitance C refi ,triode B ri collector and diode D ri The positive terminal of one output is connected to a resistor in sequence. R refi’ ,capacitance C refi’ ,triode B di collector and diode D di The positive terminal of the diode D di and diodes D ri The negative terminals are all connected to the positive terminals of the corresponding comparators; superior DSP The controller has three channels PWM Signal outputs, respectively V PWM , S ri , S di ; V PWM Passing through resistors respectively R ri Connect to the negative terminal of each comparator. N The negative terminals of the comparators are connected in parallel. S ri Connected to the transistors respectively B ri Base and steady-state unbalanced current detection circuit, S di Connected to the transistors respectively B di The base and steady-state unbalanced current detection circuit, transistor B ri , B di The emitters of all are grounded, where i = 1, 2, ..., N.

3. The active and passive hybrid parallel current sharing circuit topology according to claim 2, characterized in that: The specific structure of the steady-state unbalanced current detection circuit is as follows: it includes a sensing inductor... L CS The circuits for opening and closing the uneven current detection circuits are designed to include positive voltage detection and negative voltage detection, respectively. The structure of the positive voltage detection circuit for the unequal current detection circuit is as follows: it includes a diode. D 11 , D 12 , D 13 , D 14 , D 15 ,inductance L 11 ,resistance R 11 , R 12 , R 13 ,capacitance C 11 tertiary pipe Q 1 ;diode D 11 Positive terminal connected to sensing inductor L CS Induced AC voltage v cs The positive terminal and the negative terminal are connected to the inductor. L 11 One end, inductor L 11 The other end is connected to a diode. D 14 , D 15 The positive terminal of the diode D 14 Negative terminal connected to a transistor Q 1 collector, transistor Q 1 The base corresponds to the upper level. DSP Controller output S ri ,diode D 15 The negative terminals are connected to resistors respectively. R 11 one end and capacitor C 11 One end, tertiary tube Q 1 emitter, resistor R 11 The other end, capacitor C 11 The other end, diode D 12 positive terminal, resistor R 12 One end of each diode is grounded. D 12 The negative terminal and the resistor R 12 The other end is connected to a diode. D 13 positive terminal and resistor R 13 One end, diode D 13 negative terminal, resistor R 13 The other end is connected to a sensing inductor. L CS Induced AC voltage v cs The negative end; The structure for negative voltage detection in the unequal current detection circuit is as follows: it includes a resistor. R 21 , R 22 , R 23 ,diode D 21 , D 22 , D 23 , D 24 , D 25 ,capacitance C 21 ,inductance L 21 tertiary pipe Q 2 ,diode D 21 Positive terminal connected to sensing inductor L CS Induced AC voltage v cs The negative terminal is connected to the inductor. L 21 One end, inductor L 21 The other end is connected to diodes. D 24、 D 25 The positive terminal of the diode D 24 Negative terminal connected to a transistor Q 2 collector, transistor Q 2 The base corresponds to the upper level. DSP Controller output S ri ,diode D 25 The negative terminals are connected to resistors respectively. R 21 One end of the capacitor C 21 One end, tertiary tube Q 2 emitter, resistor R 21 The other end, capacitor C 21 The other end, diode D 22 positive terminal, resistor R 22 One end of each diode is grounded. D 22 The negative terminal and the resistor R 22 The other end is connected to a diode. D 23 positive terminal and resistor R 23 One end, diode D 23 negative terminal, resistor R 23 The other end is connected to a sensing inductor. L CS Induced AC voltage v cs The positive end; The structure of the positive voltage detection circuit for the turn-off unequal current detection circuit is as follows: it includes a diode. D 31 , D 32 , D 33 , D 34 , D 35 ,inductance L 31 ,resistance R 31 , R 32 , R 33 ,capacitance C 31 tertiary pipe Q 3 ;diode D 31 Positive terminal connected to sensing inductor L CS Induced AC voltage v cs The positive terminal and the negative terminal are connected to the inductor. L 31 One end, inductor L 31 The other end is connected to a diode. D 34 , D 35 The positive terminal of the diode D 34 Negative terminal connected to a transistor Q 3 collector, transistor Q 3 The base corresponds to the upper level. DSP Controller output S di ,diode D 35 The negative terminals are connected to resistors respectively. R 31 one end and capacitor C 31 One end, tertiary tube Q 3 emitter, resistor R 31 The other end, capacitor C 31 The other end, diode D 32 positive terminal, resistor R 32 One end of each diode is grounded. D 32 The negative terminal and the resistor R 32 The other end is connected to a diode. D 33 positive terminal and resistor R 33 One end, diode D 33 negative terminal, resistor R 33 The other end is connected to a sensing inductor. L CS Induced AC voltage v cs The negative end; The structure of the negative voltage detection circuit for the shutdown unequal current detection circuit is as follows: it includes a resistor. R 41 , R 42 , R 43 ,diode D 41 , D 42 , D 43 , D 44 , D 45 ,capacitance C 41 ,inductance L 41 tertiary pipe Q 4 ,diode D 41 Positive terminal connected to sensing inductor L CS Induced AC voltage v cs The negative terminal is connected to the inductor. L 41 One end, inductor L 41 The other end is connected to diodes. D 44、 D 45 The positive terminal of the diode D 44 Negative terminal connected to a transistor Q 4 collector, transistor Q 4 The base corresponds to the upper level. DSP Controller output S di ,diode D 45 The negative terminals are connected to resistors respectively. R 41 One end of the capacitor C 41 One end, tertiary tube Q 4 emitter, resistor R 41 The other end, capacitor C 41 The other end, diode D 42 positive terminal, resistor R 42 One end of each diode is grounded. D 42 The negative terminal and the resistor R 42 The other end is connected to a diode. D 43 positive terminal and resistor R 43 One end, diode D 43 negative terminal, resistor R 43 The other end is connected to a sensing inductor. L CS Induced AC voltage v cs The positive end; Sensing Inductor L CS That is, a single-turn inductor L 1 , L 2 ... L N single-turn inductor L 1 , L 2 ... L N One end of the inductor is connected to the positive terminal of Vcs of N steady-state unbalanced current detection circuits. L 1 , L 2 ... L N The other end is connected to the negative terminal of Vcs of N steady-state unbalanced current detection circuits, and is a single-turn inductor. L 1 , L 2 ... L N Sensing through the corresponding magnetic ring N The steady-state uneven current of the parallel SiC-MOSFET half-bridge modules is converted and processed into signals Vr+, Vr-, Vd+, and Vd-, which are then connected to the controller of the next-level DSP.

4. A method for parallel current sharing combining active and passive current sharing, characterized in that: Specifically, this includes passive parallel current sharing methods and active parallel current sharing methods, and their implementation includes the following steps: S1: The specific implementation steps of the passive parallel current sharing method are as follows: (1) N SiC-MOSFET half-bridge module HBM 1 HBM 2 … HBM N Parallel to DC bus V dc At both ends, the current output terminals of each SiC-MOSFET half-bridge module converge at... O The point structure successfully constructs the total current output terminal. O ; (2) Passive current balancing circuit N One magnetic ring w 1 , w 2 … w N Each wrapped around n Additional windings, and N The additional windings of the magnetic rings are connected end to end in sequence and are respectively... N The current output terminal of the parallel SiC-MOSFET half-bridge module passes through, let's call it the... i One magnetic ring w i The inductance value L s The inductance value at the current output terminal of each SiC-MOSFET half-bridge module is L 0 ; (3) Magnetic ring w i A magnetic core with high permeability that is not easily saturated is selected, therefore L 0 and L s If a fully coupled relationship exists, then L s =n 2 L 0 When passing through the magnetic ring N When there is a brief imbalance in the output currents of the parallel SiC-MOSFET half-bridge modules, the magnetic ring induces a reverse current. i s And thereby suppress N Transient current imbalance among the parallel SiC-MOSFET half-bridge modules; (4) Working at DC / DC In mode, magnetic ring w i Induced current i s It will saturate and lose its inhibitory effect after a short period of time. N The function of addressing transient current imbalance between parallel SiC-MOSFET half-bridge modules is then performed by... DSP The controller receives the total output current. i o and according to i o yes i s 30 times the relationship control DC active current compensator i s compensate; (5) Passive current sharing circuits can suppress N The current imbalance at the turn-on and turn-off moments of the parallel SiC-MOSFET half-bridge module, when N When the imbalance between parallel SiC-MOSFET half-bridge modules is severe, it can be addressed by combining an active parallel current sharing circuit and method. N Current balancing among parallel SiC-MOSFET half-bridge modules; S2: The specific implementation steps of the active parallel current sharing method are as follows: (1) Steady-state unbalanced current detection circuit N A single-turn inductor L 1 , L 2 ... L N Passing through respectively N A magnetic ring and N The inductor at the current output terminal of the parallel SiC-MOSFET half-bridge module L 0 They are in a fully coupled relationship; (2) When N When there is a steady-state current imbalance among the parallel SiC-MOSFET half-bridge modules, the single-turn inductor of the steady-state imbalance current detection circuit induces a voltage. v cs This voltage is converted into corresponding values ​​by turning on the positive voltage detection circuit, turning on the negative voltage detection circuit, turning off the positive voltage detection circuit, and turning off the negative voltage detection circuit. V r+ , V r- , V d+ , V d- This voltage reflects N Unbalanced current between parallel SiC-MOSFET half-bridge modules; (3) The steady-state unbalanced current detection circuit in step (2) is based on the upper level DSP Controller output S ri and S di Signals are selectively detected separately. N Uneven current during turn-on and uneven current during turn-off among parallel SiC-MOSFET half-bridge modules; (4) Detected in step (3) N Voltage corresponding to the uneven current during turn-on among the parallel SiC-MOSFET half-bridge modules V Ci Converted to a lower level DSP Controller control DSP internal DAC Module PWM Duty cycle δ ri Detected N Voltage corresponding to the unbalanced turn-off current among the parallel SiC-MOSFET half-bridge modules V Ci Converted to a lower level DSP The controller controls its internal components. PWM Module duty cycle δ di ; (5) In step (4) δ ri Through lower levels DSP The controller controls its internal components. DAC Module output corresponding N Turn-on edge adjustment reference for a parallel SiC-MOSFET half-bridge module v refi , δ di Through lower levels DSP Controller control DAC Module output corresponding N A reference for the turn-off edge adjustment of a parallel SiC-MOSFET half-bridge module v refi’ ; (6) In step (5) v refi and v refi’ Give to the active PWM The positive terminal of the comparator in the edge adjustment circuit comes from the upper stage. DSP Controller drive signals v PWM Give to the active PWM The negative terminal of the comparator in the edge adjustment circuit; when it comes from the upper stage DSP Controller signals S ri For low S di When it is high v refi With superiors DSP Controller drive signals v PWM Compare and adjust accordingly N The turn-on drive signal of each parallel SiC-MOSFET half-bridge module is advanced or delayed; when it comes from the upper level DSP Controller signals S ri For high S di When it is low v refi’ With superiors DSP Controller drive signals v PWM Compare and adjust N The turn-off drive signal of each parallel SiC-MOSFET half-bridge module is advanced or delayed, ultimately resulting in a correspondingly adjusted drive signal output. PWM Oi ; (7) The comparator output in step (6) PWM Oi via the corresponding gate driver ICs i After increasing the driving capability, it is sent to the corresponding N The gate of the upper transistor in a parallel SiC-MOSFET half-bridge module is controlled to turn it on or off. This closed-loop control can achieve... N The transient and steady-state current balance of the output of the parallel SiC-MOSFET half-bridge module.

5. The active and passive hybrid parallel current sharing method according to claim 4, characterized in that: The aforementioned N If the rated currents of the parallel SiC-MOSFET half-bridge modules are the same, then N The magnetic core parameters and the additional winding parameters of each passive current-sharing circuit are the same for the passive current balancing circuit. N An active current sharing circuit PWM The edge adjustment circuit and the steady-state unbalanced current detection circuit have the same function; the aforementioned N If the rated currents of the parallel SiC-MOSFET half-bridge modules are different, then N The magnetic core parameters of the passive current balancing circuit of a passive current sharing circuit and the additional winding parameters of each magnetic core. N The rated currents of the parallel SiC-MOSFET half-bridge modules exhibit a linear relationship. N An active current sharing circuit PWM Edge adjustment circuit and steady-state unbalanced current detection circuit settings and N The rated current of each parallel SiC-MOSFET half-bridge module exhibits a linear relationship.

6. The active and passive hybrid parallel current sharing method according to claim 4, characterized in that: In step (3) mentioned above, according to the superior DSP Controller output S ri and S di Signals are selectively detected separately. N The specific process of uneven current during turn-on and uneven current during turn-off among the parallel SiC-MOSFET half-bridge modules is as follows: Upper-level... DSP Controller output signal S ri For low S di For high-time detection N The uneven current distribution during turn-on between the parallel SiC-MOSFET half-bridge modules is converted into... V r+ and V r- ,in S ri To enable low-pass bypass and unbalanced current detection circuit, S di For high bypass shutdown uneven current detection circuit, upper level DSP Controller output signal S ri For high S di For low-time detection N The turn-off current imbalance between the parallel SiC-MOSFET half-bridge modules is converted into... V d+ and V d- ,in S ri To enable uneven current detection circuit for high bypass, S di For low-frequency non-bypass shutdown uneven current detection circuit; This circuit can N The turn-on and turn-off unbalanced currents of each parallel SiC-MOSFET half-bridge module are detected and expressed as voltage values. V Ci The representation is shown in the diagram, where C represents r+, r-, d+, and d-, and i represents the serial number of the corresponding steady-state unbalanced current detection circuit.

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