Two-stage pipelined delta-sigma modulator

Abstract

A two-stage pipeline delta-sigma modulator, by extracting the residual signal of the overall first-stage delta-sigma loop, amplifying and leading to the input end of the second-stage delta-sigma loop module, and finally directly subtracting the digital outputs of the two-stage delta-sigma loop modules through a weighted subtractor to obtain the final output of the modulator. The two-stage pipeline delta-sigma modulator avoids the noise leakage problem caused by the mismatch between the analog and digital filters in the traditional double-loop multi-stage noise shaping (MASH) architecture delta-sigma modulator, greatly reducing the precision requirement for the analog domain coefficients.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and more particularly to a two-stage pipelined ΔΣ modulator. Background Technology

[0002] With the rapid growth of the mobile device market, the ever-evolving wireless communication technologies place increasingly higher demands on the signal bandwidth, conversion accuracy, and energy efficiency of the transceiver's core module, the analog-to-digital converter (ADC). Compared to other technologies, the continuous-time (CT) delta-Sigma modulator (DSM) can achieve high signal bandwidth and high accuracy while maintaining good energy efficiency. The CT delta-Sigma modulator architecture has been widely applied in wireless communication technologies and continues to receive attention from researchers.

[0003] The ever-evolving wireless communication technology standards are constantly increasing the demand for data transmission rates, leading to a rapid increase in the signal bandwidth of analog-to-digital converters (ADCs) in their applications. However, due to energy efficiency limitations, the sampling frequency cannot be increased indefinitely, severely restricting the oversampling rate. Therefore, increasing the order of the loop filter to enhance noise shaping capabilities has become a good way to improve accuracy. However, high-order feedback loops are prone to instability. Therefore, multi-stage noise-shaping (MASH) structures, which use multiple cascaded low-order single-loop circuits supplemented by digital filter processing to achieve high-order noise shaping, effectively increase the noise shaping order without sacrificing stability. However, the mismatch between analog and digital filters in the MASH architecture causes quantization noise from the preceding stage to leak into the final output, significantly impacting accuracy. Simply increasing the accuracy of the analog filter implementation or fitting analog domain coefficients using digital filter integration calibration techniques both involve significant energy consumption, resulting in limited accuracy improvement. How to design the structure of a MASH DSM to alleviate the mismatch problem while achieving good energy efficiency has been a focus of researchers. Summary of the Invention

[0004] To address the aforementioned issues, this invention proposes a two-stage pipelined ΔΣ modulator. The residual signal of the first-stage ΔΣ loop is extracted, amplified, and then fed to the input of the second-stage ΔΣ loop module. Finally, the digital outputs of the two ΔΣ loop modules are directly subtracted using a weighted subtractor to obtain the modulator's final output. By specially designing the signal transfer function of the first-stage ΔΣ loop module, the resulting higher-order noise transfer function effectively suppresses the quantization noise introduced during the quantization process of the quantizer module in the first-stage ΔΣ loop module. The quantization noise introduced in the second-stage ΔΣ loop module is simultaneously suppressed by the inter-stage gain and the noise transfer function provided by the second-stage ΔΣ loop. Thus, the entire transfer function is implemented in the analog domain, cleverly avoiding noise leakage caused by analog-digital filter mismatch in traditional dual-loop MASH architecture ΔΣ modulators, and significantly reducing the accuracy requirements for analog domain coefficients.

[0005] This invention can be achieved through the following technical solutions:

[0006] This invention provides a two-stage pipelined ΔΣ modulator, including a first-stage ΔΣ loop module and a second-stage ΔΣ loop module, characterized in that it further includes a residual signal extraction module and a digital processing module;

[0007] The first-stage ΔΣ loop module includes a first digital processing module, a first loop filter, a first quantizer, and a first DAC;

[0008] The second-stage ΔΣ loop module includes a second digital processing module, a second loop filter, a second quantizer, and a second DAC;

[0009] The residual signal extraction module includes an interstage DAC;

[0010] The digital processing module includes a digital subtractor and a gainer;

[0011] The input terminal of the first digital processing module is a continuous input signal input terminal, and the output terminal of the first digital processing module is connected to the input terminal of the first loop filter.

[0012] The output of the first loop filter is connected to the input of the first quantizer via the first sampling clock. The output of the first quantizer is divided into three paths: one path is connected to the second input of the first digital processing module via the first DAC, one path is connected to the first input of the digital subtractor, and one path is connected to the interstage DAC.

[0013] The interstage DAC output is subtracted from the continuous input signal and then connected to the input of the interstage gainer. The output of the interstage gainer is connected to the input of the second digital processing module.

[0014] The input terminal of the second loop filter is connected to the output terminal of the second digital processing module. The output terminal of the second loop filter is connected to the input terminal of the second quantizer via the second sampling clock. The output terminal of the second quantizer is divided into two paths: one path is connected to the second input terminal of the second digital processing module via the second DAC, and the other path is connected to the second input terminal of the digital subtractor via the gain unit. The output terminal of the digital subtractor is the output terminal of this two-stage pipelined ΔΣ modulator.

[0015] Meanwhile, the present invention also provides a two-stage pipelined ΔΣ modulator, including a first-stage ΔΣ loop module and a second-stage ΔΣ loop module, characterized in that it further includes a residual signal extraction module and a digital processing module;

[0016] The first-stage ΔΣ loop module includes a first digital processing module, a first loop filter, a first quantizer, and a first DAC;

[0017] The second-stage ΔΣ loop module includes a second digital processing module, a second loop filter, a second quantizer, and a second DAC;

[0018] The digital processing module includes a digital subtractor and a gainer;

[0019] The residual signal extraction module includes a current mirror module;

[0020] The input terminal of the first digital processing module is a continuous input signal input terminal, and the output terminal of the first digital processing module is divided into two paths: one path is connected to the residual signal extraction module, and the other path is connected to the input terminal of the first loop filter.

[0021] The output of the first loop filter is connected to the input of the first quantizer via the first sampling clock. The output of the first quantizer is divided into two paths: one path is connected to the second input of the first digital processing module via the first DAC, and the other path is connected to the first input of the digital subtractor.

[0022] The input terminal of the second loop filter is connected to the output terminal of the second digital processing module. The output terminal of the second loop filter is connected to the input terminal of the second quantizer via the second sampling clock. The output terminal of the second quantizer is divided into two paths: one path is connected to the second input terminal of the second digital processing module via the second DAC, and the other path is connected to the second input terminal of the digital subtractor via the gain unit. The output terminal of the digital subtractor is the output terminal of this two-stage pipelined ΔΣ modulator.

[0023] Furthermore, the signal transfer function of the second-stage ΔΣ loop module needs to be specifically set to STF. 2a =1-(1-z) -1 )n When designing the loop filter, a feedforward integrator cascade architecture is adopted, where n represents the order of the loop filter in the second-stage loop, which can also be equivalent to the number of cascaded first-order integrators in the loop, depending on the design requirements of the ΔΣ analog-to-digital converter.

[0024] Both the first loop filter and the second loop filter are continuous-time loop filters.

[0025] The output signal of the residual signal extraction module is used as the input signal of the second-stage ΔΣ loop module. The output of the quantizer of the first-stage ΔΣ loop module is fed back to the input of the loop filter of the first-stage ΔΣ loop module through the DAC of the first-stage ΔΣ loop module. The output of the quantizer of the second-stage ΔΣ loop module is fed back to the input of the loop filter of the second-stage ΔΣ loop module through the DAC of the second-stage ΔΣ loop module.

[0026] Furthermore, the output of the first quantizer is fed back to the input of the first loop filter via the first DAC, and coupled with the continuous input signal; the output of the second quantizer is fed back to the input of the second loop filter via the second DAC, and coupled with the signal obtained after amplification of the residual continuous signal extracted from the first-stage loop.

[0027] Furthermore, both the first loop filter and the second loop filter are continuous-time loop filters.

[0028] Compared with the prior art, the beneficial technical effects of the present invention are as follows:

[0029] 1) This invention avoids the noise leakage problem caused by the mismatch between analog and digital filters in the traditional dual-ring MASH architecture ΔΣ modulator. It forms high-order noise shaping and suppression for each noise source in the modulator, and its noise transfer function is realized in the analog domain. This greatly alleviates the matching requirements between analog and digital filters, effectively improves the accuracy of the multi-ring architecture and maintains high energy efficiency.

[0030] 2) The key step in the implementation of this invention is to extract the residual continuous signal containing quantization noise from the overall first-stage ΔΣ loop.

[0031] 3) One approach is to add an interstage DAC module, whose input is connected to the input of the first DAC. The residual signal is extracted by directly coupling the input continuous signal and the output signal of the interstage DAC at the input of the second loop filter. Even with a high system sampling frequency, it can still guarantee accurate interstage gain and good in-band linearity.

[0032] 4) Another method is to extract the residual continuous signal at the corresponding node in the loop filter using circuit techniques such as current mirrors, and directly inject it into the input of the second loop filter. This method has lower hardware overhead, and as the interstage gain increases, it effectively reduces power consumption and chip area. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of a traditional dual-ring MASH DSM.

[0034] Figure 2 This is a schematic diagram of the structure of an embodiment of the two-stage pipelined ΔΣ modulator of the present invention;

[0035] Figure 3 These are schematic diagrams illustrating two implementations of the residual signal extraction module in an embodiment of the two-stage pipelined ΔΣ modulator of the present invention.

[0036] Figure 4 This is a comparison chart of the sensitivity of the pipelined DSM provided by the two-stage pipelined ΔΣ modulator embodiment of the present invention to the deviation of the RC time constant with that of the traditional dual-loop MASH DSM.

[0037] Figure 5 This is a comparison chart showing the sensitivity of the pipelined DSM provided in the embodiment of the two-stage pipelined ΔΣ modulator of the present invention to the finite gain deviation of the operational amplifier between the two-loop MASH DSM and the conventional dual-loop MASH DSM. Detailed Implementation

[0038] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings and preferred embodiments.

[0039] Figure 1 This is a schematic diagram of a traditional dual-loop MASH architecture ΔΣ modulator. The main structure consists of two cascaded stages of traditional continuous-time low-order single-loop ΔΣ modulators. The second-stage ΔΣ loop takes the quantization noise generated by the quantizer in the first-stage ΔΣ loop as input. The outputs of the two ΔΣ loops are then processed by a digital filter to eliminate the quantization noise from the first stage, thus obtaining the final modulator output. However, due to the inevitable mismatch between the coefficients of the analog domain loop filter and the digital domain digital filter in the circuit implementation, such as… Figure 1 The mismatch between the analog and digital filters that occurs in the traditional dual-loop MASH architecture ΔΣ modulator shown, i.e., NTF 1a ≠NTF 1d STF 2a ≠STF 2d (Subscripts “a” and “b” represent the analog domain and digital domain, respectively). The actual output expression is shown in equation (1), and the quantization noise E q1This noise leaks into the final output, severely limiting the implementation of high-precision analog-to-digital conversion. Therefore, this problem can be greatly alleviated by the pipelined noise suppression technique described below.

[0040] Y MASH =STF 1a STF 2d X-NTF 1d NTF 2a E q2 +(NTF 1a STF 2d -NTF 1d STF 2a E q1 (1)

[0041] Where Y MASH This is the final output of a traditional dual-loop MASH DSM system. STF and NTF are the signal transfer function and noise transfer function, respectively. Eq represents the quantization error. The subscripts a and d indicate that the function is implemented in the analog domain and digital domain, respectively. The subscripts "1" and "2" indicate that the item belongs to the first and second-level loops, respectively. All symbols in the following text are marked in this way.

[0042] Implementation, for example Figure 2 As shown, the two-stage pipelined ΔΣ modulator embodiment of the present invention includes a ΔΣ dual-loop module, a residual signal extraction module, and a digital subtractor module. The ΔΣ dual-loop module includes a first-stage ΔΣ loop module and a second-stage ΔΣ loop module. The residual signal extracted from the entire first-stage ΔΣ loop module is used as the input to the second-stage ΔΣ loop module. The digital subtractor module connects the outputs from the first-stage and second-stage ΔΣ loop modules, and the signals at its outputs are directly subtracted by this subtractor to obtain the output of the entire two-stage pipelined ΔΣ analog-to-digital converter.

[0043] Specifically, both loops in the ΔΣ dual-loop module include loop filters, quantizers, and digital-to-analog converters (DACs). The first-stage ΔΣ loop module includes a first loop filter, which is connected sequentially to a first sample-and-hold circuit and a first quantizer. The output of the first quantizer is coupled to the input of the first loop filter via the first DAC and the input of the first loop filter. The second-stage ΔΣ loop module includes a second loop filter, which is connected sequentially to a second sample-and-hold circuit and a second quantizer. The output of the second quantizer is coupled to the output of the residual signal amplifier via the second DAC and the input of the second loop filter, and the output of the second loop filter is fed back to the input of the second loop filter. The second-stage ΔΣ loop module must meet the following conditions:

[0044] NTF2+STF2=1 (2)

[0045] Here, STF2 and NTF2 represent the signal transfer function and noise transfer function generated by the second-stage ΔΣ loop module. Furthermore, both the first and second loop filters are continuous-time loop filters. Due to the low-pass filtering and anti-aliasing intrinsic characteristics of continuous-time loop filters, the design requirements of the preceding anti-aliasing filter in practical applications are greatly reduced. In addition, the input impedance of the continuous-time loop filter is resistive, making it easy for the preceding stage to drive, thus its bandwidth limit is significantly higher than that of the discrete-time loop filter.

[0046] The extraction of residual signals mainly relies on residual signal extraction modules, such as... Figure 3 As shown, the residual signal extraction module needs to extract the same signal as the input signal of the first loop filter from the overall first-stage loop, that is, the signal value to be extracted is E. q1 ·NTF1=E q1 ·(1-z -1 ) n E q1 NTF1 represents the quantization noise generated by the first-stage ΔΣ loop module, and NTF1 represents the noise shaping function generated by the first-stage ΔΣ loop module, where (1-z) -1 ) n The expression for the maximum out-of-band gain of an nth-order NTF.

[0047] This residual signal extraction module can be implemented in two ways, such as Figure 3 As shown, the first method involves adding an interstage DAC module, whose input is connected to the output of the first quantizer, meaning its input is equivalent to the input of the first DAC. The continuous input signal and the output signal of the interstage DAC are directly coupled at the input of the second loop filter to extract the residual signal. This method can still guarantee good in-band linearity and accurate interstage gain even when the system sampling frequency is high. The second method uses circuit techniques such as current mirrors to extract the current signal flowing into the output node of the active integrator in the first loop filter as a feature signal, which is then directly injected into the input of the second loop filter. Because the first sample-and-hold circuit and the first quantizer connected to the back end of the first loop filter are easily designed as structures where current cannot flow in, such as the gate of a transistor, this feature signal current is consistent with the charging and discharging current on the integrating capacitor.

[0048] The residual signal is extracted, amplified, and fed to the input of the second ΔΣ loop module. This second ΔΣ loop module constructs the first-stage quantization noise, which has been processed simultaneously by the first-stage loop noise transfer function and the second-stage loop signal transfer function. In the final digital subtraction, a two-stage loop NTF double-shaping process is constructed for the first quantization noise, while the second quantization noise is double-shaped by the inter-stage gain and the single-stage loop NTF. Thus, a strong shaping effect is achieved through two independent loops, avoiding the noise cancellation process of traditional dual-loop MASH modulators. This eliminates the analog-to-digital matching requirement, significantly reducing the design requirements for analog filters and effectively improving the accuracy of the multi-loop DSM architecture while maintaining high energy efficiency.

[0049] The specific workflow is as follows: First, the input continuous signal passes through the loop filter and quantizer in the first-stage ΔΣ loop module, generating a signal with quantization noise E. q1 The digital output of the first quantizer is converted into an analog signal by the first DAC and fed back to the input of the first loop filter. After the negative feedback loop stabilizes, the output signal of the first quantizer is the digital output signal Y1 of the first-stage ΔΣ loop module. The residual signal E is extracted by the residual signal extraction module. q1 The NTF1 amplifier amplifies the signal and uses it as the input signal for the second-stage ΔΣ loop module. This signal passes through the second loop filter and is then input to the second quantizer in the second-stage ΔΣ loop module, generating a signal containing quantization noise E. q2 The digital output is converted into an analog signal by the second DAC and fed back to the input of the second loop filter in the second-stage ΔΣ loop module. After the negative feedback loop stabilizes, the output signal of the second quantizer in the second-stage ΔΣ loop module is the digital output signal Y2 of the second-stage ΔΣ loop module.

[0050] Y1 = STF1·X + NTF1·E q1 (3)

[0051] Y2=STF2·G·NTF1·E q1 +NTF2·E q2 (4)

[0052] The digital outputs (Y1, Y2) of the first and second stage ΔΣ loop modules are used as inputs to a digital subtractor and subtracted to obtain the final modulator output signal Y. MASH :

[0053] Y MASH =Y1-(1 / G)·Y2=STF1·X+NTF1·(1-STF2)·E q1 -(1 / G)·NTF2·E q2 (5)

[0054] Equations (1) and (4) can be transformed into:

[0055] Y MASH =STF1·X+NTF1·NTF2·E q1 -(1 / G)·NTF2·E q2 (6)

[0056] Therefore, compared with the expression of the traditional dual-ring MASH architecture ΔΣ modulator shown in Equation (1), it can be seen from Equation (6) that the two-stage pipelined ΔΣ modulator proposed in this invention eliminates the quantization noise elimination process and thus has better robustness.

[0057] Specifically, for continuous-time ΔΣ loops, the continuous-time loop filter is generally implemented based on a resistor-capacitor (RC) active integrator. Since the transfer function coefficients of the continuous-time filter are determined by the RC product, which is heavily influenced by process-voltage-temperature (PVT), changes in PVT have a significant impact on the coefficients in the filter's transfer function. This change in coefficients directly affects the conversion accuracy of the noise-cancelled MASH architecture. However, if the noise cancellation process of the MASH architecture is eliminated and the mechanism for suppressing quantization noise in the MASH architecture is changed, the more severe filter coefficient mismatch problem caused by PVT changes will not have a significant impact on the modulator's accuracy. Therefore, the two-stage pipelined continuous-time ΔΣ modulator proposed in this invention can significantly improve the robustness of multi-loop architectures.

[0058] Taking the ΔΣ modulator with a 2-2MASH architecture as an example, simulations can be used to verify the sensitivity of the two-stage pipeline architecture with inter-stage noise coupling to mismatch compared to the traditional dual-ring MASH architecture. Figure 4 and Figure 5 This illustrates the pipelined architecture in this embodiment, which, compared to the traditional dual-ring MASH architecture, is less sensitive to RC time constant deviations and analog-to-digital filter mismatches caused by operational amplifier gain variations.

[0059] Those skilled in the art should understand that these are merely illustrative examples, and various changes or modifications can be made to these embodiments without departing from the principles and essence of the present invention. Therefore, the scope of protection of the present invention is defined by the appended claims.

Claims

1. A two-stage pipelined ΔΣ modulator, comprising a first-stage ΔΣ loop module and a second-stage ΔΣ loop module, characterized in that, It also includes a residual signal extraction module and a digital processing module; The first-stage ΔΣ loop module includes a first digital processing module, a first loop filter, a first quantizer, and a first DAC; The second-stage ΔΣ loop module includes a second digital processing module, a second loop filter, a second quantizer, and a second DAC; The residual signal extraction module includes an interstage DAC; The digital processing module includes a digital subtractor and a gainer; The input terminal of the first digital processing module is a continuous input signal input terminal, and the output terminal of the first digital processing module is connected to the input terminal of the first loop filter. The output of the first loop filter is connected to the input of the first quantizer via the first sampling clock. The output of the first quantizer is divided into three paths: one path is connected to the second input of the first digital processing module via the first DAC, one path is connected to the first input of the digital subtractor, and one path is connected to the interstage DAC. The interstage DAC output is subtracted from the continuous input signal and then connected to the input of the interstage gainer. The output of the interstage gainer is connected to the input of the second digital processing module. The input terminal of the second loop filter is connected to the output terminal of the second digital processing module. The output terminal of the second loop filter is connected to the input terminal of the second quantizer via the second sampling clock. The output terminal of the second quantizer is divided into two paths: one path is connected to the second input terminal of the second digital processing module via the second DAC, and the other path is connected to the second input terminal of the digital subtractor via the gain unit. The output terminal of the digital subtractor is the output terminal of this two-stage pipelined ΔΣ modulator.

2. A two-stage pipelined ΔΣ modulator, comprising a first-stage ΔΣ loop module and a second-stage ΔΣ loop module, characterized in that, It also includes a residual signal extraction module and a digital processing module; The first-stage ΔΣ loop module includes a first digital processing module, a first loop filter, a first quantizer, and a first DAC; The second-stage ΔΣ loop module includes a second digital processing module, a second loop filter, a second quantizer, and a second DAC; The digital processing module includes a digital subtractor and a gainer; The residual signal extraction module includes a current mirror module; The input terminal of the first digital processing module is a continuous input signal input terminal, and the output terminal of the first digital processing module is divided into two paths, one of which is connected to the residual signal extraction module and the other of which is connected to the input terminal of the first loop filter; the output terminal of the residual signal extraction module is connected to the first input terminal of the second digital processing module through interstage gain. The output of the first loop filter is connected to the input of the first quantizer via the first sampling clock. The output of the first quantizer is divided into two paths: one path is connected to the second input of the first digital processing module via the first DAC, and the other path is connected to the first input of the digital subtractor. The input terminal of the second loop filter is connected to the output terminal of the second digital processing module. The output terminal of the second loop filter is connected to the input terminal of the second quantizer via the second sampling clock. The output terminal of the second quantizer is divided into two paths: one path is connected to the second input terminal of the second digital processing module via the second DAC, and the other path is connected to the second input terminal of the digital subtractor via the gain unit. The output terminal of the digital subtractor is the output terminal of this two-stage pipelined ΔΣ modulator.

3. The two-stage pipelined ΔΣ modulator according to claim 1 or 2, characterized in that, The signal transfer function STF of the second-stage ΔΣ loop module 2a =1-(1-z -1 ) n， Where n represents the order of the loop filter in the second-stage loop, and is also equal to the number of cascaded first-order integrators in the loop.

4. The two-stage pipelined ΔΣ modulator according to claim 1 or 2, characterized in that, The output of the first quantizer is fed back to the input of the first loop filter via the first DAC, and coupled with the continuous input signal; the output of the second quantizer is fed back to the input of the second loop filter via the second DAC, and coupled with the signal obtained after amplification of the residual continuous signal extracted from the first loop.

5. The two-stage pipelined ΔΣ modulator according to claim 1 or 2, characterized in that, Both the first loop filter and the second loop filter are continuous-time loop filters.

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