Semiconductor structure and its preparation method

Abstract

This invention discloses a semiconductor structure and its fabrication method. The semiconductor structure includes: a substrate having an isolation layer and a plurality of active regions arranged in an array, the plurality of active regions being arranged in columns along a first direction and spaced apart along a second direction; the isolation layer being located between the surfaces of the active regions and the active regions; a plurality of word line trenches located within the substrate and penetrating the active regions and the isolation layer along the second direction; and at least one isolation trench formed between two columns of active regions and extending along the first direction, the isolation trench penetrating the plurality of word line trenches to divide the sidewalls forming the word line trenches into multiple segments. The semiconductor structure according to embodiments of the present invention can avoid word line trench bending caused by expansion stress during thermal oxidation, which is beneficial for subsequent filling of the word line gate metal.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor structure and its fabrication method. Background Technology

[0002] In DRAM processes, the use of buried wordline (BWL) NMOS transistors can reduce short-channel effects and thus decrease device leakage to some extent. In the front-end array area (AIA) formation process, an AA-shaped island structure is first formed on the silicon substrate using dry etching. However, as device size shrinks, the linewidth (line CD) of the BWL after etching also decreases. A "mountain"-shaped trench for the BWL is etched into the AIA, and then the exposed silicon is thermally oxidized to form a gate oxide layer. The silicon hidden within the deposited oxide layer is also more susceptible to thermal oxidation, causing expansion of the semiconductor structure along the word line direction and generating expansion stress. The accumulation of expansion stress causes the BWL to bend, which adversely affects the gate metal filling in subsequent processes. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor structure and its fabrication method. The semiconductor structure can avoid word line trench bending caused by expansion stress during thermal oxidation, thereby facilitating the subsequent filling of word line gate metal.

[0004] A semiconductor structure according to an embodiment of the present invention includes: a substrate having an isolation layer and a plurality of active regions arranged in an array, the plurality of active regions being arranged in columns along a first direction and the columns of active regions being spaced apart along a second direction, the isolation layer being located between the surface of the active regions and the active regions; a plurality of word line trenches being located within the substrate and penetrating the active regions and the isolation layer along the second direction; and at least one isolation trench being formed between two columns of the active regions and extending along the first direction, the isolation trench penetrating the plurality of word line trenches to divide the sidewalls forming the word line trenches into multiple segments.

[0005] According to some embodiments of the present invention, the isolation trenches are multiple and spaced apart along the second direction.

[0006] According to some embodiments of the present invention, the isolation trenches are evenly spaced along the second direction, and multiple rows of active regions are provided between adjacent isolation trenches.

[0007] According to some embodiments of the present invention, at least three columns of active regions are provided between adjacent isolation trenches.

[0008] According to some embodiments of the present invention, the isolation trench is formed between two adjacent columns of the active regions.

[0009] According to some embodiments of the present invention, the isolation trench is formed on at least one column of the active regions and is formed by removing a portion of the active regions and the isolation layer.

[0010] According to some embodiments of the present invention, the multiple columns of active regions are divided into multiple groups along the second direction, the distance between two adjacent groups of active regions is greater than the distance between two adjacent columns of active regions within a group, and the isolation trench is formed between two adjacent groups of active regions.

[0011] According to some embodiments of the present invention, the depth of the isolation trench is 4 / 5 to 6 / 5 times the depth of the word line trench.

[0012] This invention also proposes a method for preparing a semiconductor structure.

[0013] A method for fabricating a semiconductor structure according to an embodiment of the present invention includes: providing a substrate, the substrate having an isolation layer and a plurality of active regions arranged in an array, the plurality of active regions being arranged in columns along a first direction and the columns of active regions being spaced apart along a second direction, the isolation layer being located between the surface of the active regions and the active regions; forming a first mask layer on the isolation layer and selectively etching the first mask layer to form at least one isolation opening, the isolation opening extending along the first direction; forming a first hard mask layer on the surface of the first mask layer, the first hard mask layer filling the isolation layer. The first hard mask layer is selectively etched to form multiple initial word line openings; the first mask layer is etched along the initial word line openings to form word line openings, and the first hard mask layer is removed; the substrate is etched along the word line openings and the isolation openings to form multiple word line trenches and at least one isolation trench, the word line trenches extending along the second direction and penetrating the active region and the isolation layer, the isolation trench being formed between the active regions and penetrating the multiple word line trenches to divide the sidewalls forming the word line trenches into multiple segments; the first mask layer is removed.

[0014] According to some embodiments of the present invention, before forming the first mask layer on the surface of the isolation layer, the method further includes: sequentially forming a second hard mask layer and a second mask layer on the surface of the isolation layer; in the step of etching the first mask layer along the initial opening of the word line to form the word line opening, etching the first mask layer until the second mask layer is reached; in the step of etching the substrate along the word line opening and the isolation opening, etching the second mask layer mask, the second hard mask layer mask, and the substrate along the word line opening and the isolation opening; and in the step of removing the first mask layer, simultaneously removing the second hard mask layer and the second mask layer.

[0015] According to some embodiments of the present invention, in the step of forming a first mask layer on the surface of the isolation layer and selectively etching the first mask layer to form at least one isolation opening, the isolation opening is located between two adjacent columns of the active regions.

[0016] According to some embodiments of the present invention, in the steps of forming a first mask layer on the surface of the isolation layer and selectively etching the first mask layer to form at least one isolation opening, the isolation opening is located corresponding to at least one column of the active regions.

[0017] According to some embodiments of the present invention, the multiple columns of active regions are divided into multiple groups along the second direction, the distance between two adjacent groups of active regions is greater than the distance between two adjacent columns of active regions, and the isolation opening is correspondingly formed between two adjacent groups of active regions.

[0018] According to some embodiments of the present invention, the step of selectively etching the first mask layer to form at least one isolation opening includes: forming a first photoresist layer defining the isolation opening on the surface of the first mask layer; and removing the first photoresist layer after forming the isolation opening.

[0019] According to some embodiments of the present invention, the step of selectively etching the second mask layer to form a plurality of initial word line openings includes: forming a second photoresist layer on the surface of the first mask layer that defines the initial word line openings; and removing the second photoresist layer after forming the word line openings.

[0020] According to the semiconductor structure and fabrication method of the present invention, by forming isolation trenches, the sidewalls of the word line trenches can be cut into multiple segments. This creates a gap between each segment of the word line trench during the subsequent thermal oxidation process, thereby releasing the stress generated by expansion during thermal oxidation and preventing the word line trenches from bending, thus avoiding interference with the subsequent filling of the metal gate within the word line trenches. Furthermore, forming the isolation trenches first and then the word line trenches enhances the structural strength during the semiconductor structure formation process, preventing collapse due to structural instability caused by forming the word line trenches first and then the isolation trenches. Attached image description:

[0021] Figure 1- Figure 20 Figures 1, 3, 5, 7, 9, 11, 13, 15, 17, and 19 are cross-sectional views along the second direction in the semiconductor structure fabrication method according to an embodiment of the present invention. Figure 2 , Figure 4 , Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 Figure 15 Figure 16 , Figure 20 The images shown are cross-sectional views along the first direction of each step in the semiconductor structure fabrication method according to an embodiment of the present invention, and correspond one-to-one with the cross-sectional views along the second direction. Figure 1a , Figure 3a , Figure 5a-1 , Figure 7a-1 , Figure 9a-1 , Figure 11a-1 , Figure 13a-1 , Figure 15a-1 , Figure 17a-1 , Figure 19a-1 This is a schematic diagram along the second direction of each step in the method for fabricating a semiconductor structure according to an embodiment of the present invention. Figure 1a , Figure 3a , Figure 5a-2 , Figure 7a-2 , Figure 9a-2 , Figure 11a-2 , Figure 13a-2 , Figure 15a-2 , Figure 17a-2 , Figure 19a-2 This is a schematic diagram along the second direction of each step in the method for fabricating a semiconductor structure according to another embodiment of the present invention. Figure 1b , Figure 3b , Figure 5b , Figure 7b , Figure 9b , Figure 11b , Figure 13b , Figure 15b , Figure 17b , Figure 19b This is a schematic diagram along the second direction of each step in the method for fabricating a semiconductor structure according to another embodiment of the present invention.

[0022] Figure 21 This is a top view schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0023] Figure 22 This is a top view schematic diagram of a semiconductor structure according to another embodiment of the present invention;

[0024] Figure 23 This is a top view schematic diagram of a semiconductor structure according to yet another embodiment of the present invention;

[0025] Figure 24 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention.

[0026] Figure label:

[0027] 100: Semiconductor structure;

[0028] 1: Substrate; 11: Active area; 12: Isolation layer; 13: Word line trench; 14: Isolation trench;

[0029] 21: First mask layer; 22: First hard mask layer; 23: Second mask layer; 24: Second hard mask layer;

[0030] 31: Initial opening of the character line; 32: Opening of the character line; 33: Isolation opening;

[0031] 41: First photoresist layer; 42: Second photoresist layer. Detailed Implementation

[0032] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the semiconductor structure 100 and its preparation method proposed in this invention.

[0033] The semiconductor structure 100 and its fabrication method according to an embodiment of the present invention are described below with reference to the accompanying drawings.

[0034] Combination Figure 19a-1 , Figure 19a-2 , Figure 19b as well as Figure 20 As shown, the semiconductor structure 100 according to an embodiment of the present invention may include a substrate 1, a plurality of word line trenches 13 and at least one isolation trench 14.

[0035] The substrate 1 is provided with an isolation layer 12 and a plurality of active regions 11 arranged in an array. The plurality of active regions 11 are arranged in columns along a first direction and the columns of active regions 11 are spaced apart along a second direction. Specifically, the plurality of active regions 11 are formed into multiple columns, each column including a plurality of active regions 11. The plurality of active regions 11 are spaced apart and extend along the first direction. The plurality of active regions 11 in each column are spaced apart along the first direction, and the columns of active regions 11 are spaced apart along the second direction. The active regions 11 in adjacent columns are staggered in the first direction, and an isolation area is defined between the plurality of active regions 11.

[0036] The isolation layer 12 is located between the surface of the active region 11 and the active region 11, such as Figure 20 As shown, the isolation layer 12 covers the surface of the active region 11 and fills between multiple active regions 11. The isolation layer 12 isolates the multiple active regions 11 to prevent them from interfering with each other.

[0037] like Figures 20-23As shown, the semiconductor structure 100 further includes a plurality of word line trenches 13. The word line trenches 13 are located within the substrate 1 and penetrate the active region 11 and the isolation layer 12 along a second direction. Specifically, the word line trenches 13 can be used to form a buried word line structure. The plurality of word line trenches 13 extend along the second direction and are spaced apart along a third direction, wherein the second direction is perpendicular to the third direction, and the first direction intersects the second direction but is not perpendicular to it. The word line trenches 13 are formed within the active region 11 and penetrate the active region 11 and the isolation layer 12 along the second direction. Figure 20 In the example shown, the character line groove 13 is formed within the active region 11, which is formed into a "mountain" shaped structure.

[0038] like Figure 19a-1 , Figure 19a-2 as well as Figure 19b As shown and Figures 21-23 As shown, the semiconductor structure 100 further includes at least one isolation trench 14. The isolation trench 14 can be one or more. Preferably, there can be multiple isolation trenches 14, which are spaced apart along the second direction. The isolation trench 14 is formed between two rows of active regions 11 and extends along the first direction. The isolation trench 14 penetrates multiple word line trenches 13 to divide the sidewalls of the word line trenches 13 into multiple segments. That is, the isolation trench 14 extends along the first direction and is formed between the active regions 11, meaning that the isolation trench 14 is not formed within the active regions 11 to avoid affecting the subsequent gate structure formation process. The isolation trench 14 is intersected with and penetrates the word line trenches 13 to cut the word line trenches 13 into multiple segments in the second direction, thereby cutting the sidewalls of the word line trenches 13 into multiple segments. In this way, in the subsequent thermal oxidation process, there is a gap between each segment of the word line trench 13, which can release the stress generated by expansion during the thermal oxidation process, thereby preventing the word line trenches 13 from bending and thus avoiding affecting the subsequent filling of the metal gate in the word line trenches 13.

[0039] In some embodiments of the present invention, there can be multiple isolation grooves 14 spaced apart along the second direction. This allows the letter groove 13 to be cut into multiple segments by multiple isolation grooves 14, thereby further facilitating the release of expansion stress during thermal oxidation. It should be noted that "multiple" here refers to two or more; for example, there can be two, three, or four isolation grooves 14, etc. The specific number of isolation grooves 14 can be set according to actual needs. Optionally, as... Figures 21-23As shown, the isolation trench 14 can be formed as a long strip extending along the first direction, or the isolation trench 14 can also be formed as a curve extending along the first direction. The isolation trench 14 can also be formed as other shapes, as long as the word line trench 13 can be cut into multiple segments to form an interval area between the multiple segments of word line trench 13, which is conducive to stress release. Furthermore, multiple isolation trenches 14 can be evenly spaced along the second direction, and there can be multiple rows of active areas 11 between adjacent isolation trenches 14.

[0040] In some embodiments of the present invention, the isolation trenches 14 are evenly spaced along the second direction. Specifically, the evenly spaced distribution of multiple isolation trenches 14 can cut the word line trenches 13 into multiple segments of equal length along the second direction, so that the stress release of the multiple segments of word line trenches 13 is consistent, thereby helping to maintain the consistency of the word line trenches 13 in the second direction and preventing bending. Multiple rows of active regions 11 can be spaced between adjacent isolation trenches 14. Optionally, at least three rows of active regions 11 are provided between adjacent isolation trenches 14, that is, an isolation trench 14 is formed every three rows of active regions 11. For example, the isolation trenches 14 can be spaced between three, four, five, or even more rows of active regions 11, depending on actual needs. This can prevent the word line trenches 13 from bending and also prevent excessive isolation trenches 14 from causing instability in the semiconductor structure 100, which is detrimental to subsequent processes.

[0041] In some embodiments of the present invention, such as Figure 19a-1 and Figure 21 As shown, the isolation trench 14 is formed between two adjacent rows of active regions 11. That is, the isolation trench 14 can be formed within the isolation layer 12 between adjacent active regions 11. The isolation trench 14 is formed by etching the isolation layer 12 between adjacent active regions 11, thereby maintaining the front-end process for forming the active regions 11 unchanged and simplifying the fabrication process of the semiconductor structure 100. The width of the isolation trench 14 can be smaller than the width between the active regions 11, so that a portion of the isolation layer 12 remains on the opposite sides of two adjacent active regions 11 to isolate the adjacent active regions 11.

[0042] In other embodiments of the invention, such as Figure 19a-2 and Figure 23 As shown, the isolation trench 14 is formed on at least one row of active regions 11 and is formed by removing part of the active regions 11 and the isolation layer 12. Specifically, the isolation trench 14 can be formed by removing at least one row of active regions 11, thereby keeping the front-end process of forming the active regions 11 unchanged. Moreover, the increased width of the isolation trench 14 can further facilitate stress release. Optionally, the isolation trench 14 can be formed on one row of active regions 11 by removing one row of active regions 11.

[0043] In some embodiments of the present invention, such as Figure 19b and Figure 22 As shown, the spacing between adjacent rows of active regions 11 in the multi-row active regions 11 is different. The spacing between some adjacent rows of active regions 11 is greater than the spacing between other adjacent active regions 11. The isolation trench 14 can be formed between two rows of active regions 11 with a large spacing. This is not only beneficial to the formation of the isolation trench 14, but also beneficial to the definition of the position of the isolation trench 14 in the mask layer during the process of forming the isolation trench 14.

[0044] Optionally, the multiple active areas 11 are divided into multiple groups along the second direction. The distance between two adjacent groups of active areas 11 is greater than the distance between two adjacent columns of active areas 11 within a group. An isolation trench 14 is formed between two adjacent groups of active areas 11. Specifically, along the second direction, the multiple active areas 11 can be divided into multiple groups. Each group of active areas 11 may include multiple columns. The spacing between multiple columns of active areas 11 is the same. The distance between two adjacent columns of active areas 11 in two adjacent groups of active areas 11 is greater than the spacing between adjacent active areas 11 within a group. That is, the width of the isolation layer 12 between two adjacent groups of active areas 11 in the second direction is greater than the distance of the isolation layer 12 between adjacent columns of active areas 11 within a group. An isolation trench 14 is formed between two groups of active areas 11, which is conducive to the formation of the isolation trench 14.

[0045] In some embodiments of the present invention, the depth of the isolation groove 14 is 4 / 5 to 6 / 5 times the depth of the word line groove 13, that is, the depth of the isolation groove 14 is greater than or equal to 0.8 times the depth of the word line groove 13 and less than or equal to 1.2 times the depth of the word line groove 13. This can avoid the isolation groove 14 being too shallow and affecting stress release, and can also avoid the isolation groove 14 being too deep and unfavorable to subsequent processes.

[0046] The following describes a method for fabricating a semiconductor structure 100 according to an embodiment of the present invention with reference to the accompanying drawings. The method for fabricating the semiconductor structure 100 can be used to fabricate the semiconductor structure 100 described above.

[0047] like Figure 24As shown, a method for fabricating a semiconductor structure 100 according to an embodiment of the present invention may include: providing a substrate 1, the substrate 1 having an isolation layer 12 and a plurality of active regions 11 arranged in an array, the plurality of active regions 11 being arranged in a row along a first direction and the multiple rows of active regions 11 being spaced apart along a second direction, the isolation layer 12 being located between the surface of the active regions 11 and the active regions 11; forming a first mask layer 21 on the surface of the isolation layer 12, and selectively etching the first mask layer 21 to form at least one isolation opening 33, the isolation opening 33 extending along the first direction; forming a first hard mask layer 22 on the surface of the first mask layer 21, the first hard mask layer 22... The isolation opening 33 is filled, and the first hard mask layer 22 is selectively etched to form a plurality of word line initial openings 31; the first hard mask layer 22 is etched along the word line initial openings 31 to form word line openings 32, and the first hard mask layer 22 is removed; the substrate 1 is etched along the word line openings 32 and the isolation openings 33 to form a plurality of word line trenches 13 and at least one isolation trench 14, the word line trenches 13 extending along the second direction and penetrating the active region 11 and the isolation layer 12, the isolation trench 14 being formed between the active regions 11 and penetrating the plurality of word line trenches 13 to divide the sidewalls forming the word line trenches 13 into multiple segments; the first mask layer 21 is removed.

[0048] Figure 1- Figure 20 The following is a cross-sectional view of each step of the method for fabricating the semiconductor structure 100 according to an embodiment of the present invention. The method for fabricating the semiconductor structure 100 according to an embodiment of the present invention will be described below with reference to the accompanying drawings.

[0049] Referring to Figure 1- Figure 2 As shown, step S1: Provide a substrate 1, the substrate 1 having a plurality of active regions 11 arranged in an array and an isolation layer 12. The method of forming the substrate 1 may include: defining a plurality of active regions 11 for forming memory transistors on a semiconductor substrate, etching the semiconductor substrate to form a plurality of active regions 11, depositing an isolation layer 12 on the surface of the active regions 11, the isolation layer 12 covering the surface of the active regions 11 and filling the gaps between the active regions 11, the isolation layer 12 may be a silicon oxide layer.

[0050] The multiple active regions 11 are formed into multiple columns, each column includes multiple active regions 11, the multiple active regions 11 are spaced apart and extend along a first direction, the multiple active regions 11 in each column are spaced apart along the first direction, the multiple columns of active regions 11 are spaced apart along a second direction, the active regions 11 in adjacent columns are staggered in the first direction, and an isolation area is defined between the multiple active regions 11.

[0051] In some embodiments of the present invention, such as Figure 1a As shown, the multiple rows of active regions 11 are evenly spaced apart. In other embodiments of the present invention, such as... Figure 1bAs shown, the spacing between some adjacent columns of active regions 11 is different from the spacing between other adjacent columns of active regions 11.

[0052] As shown in Figure 3- Figure 8 As shown, step S2: a first mask layer 21 is formed on the isolation layer 12, and the first mask layer 21 is selectively etched to form at least one isolation opening 33, the isolation opening 33 extending along the first direction.

[0053] Specifically, the surface of the isolation layer 12 is planarized, and then a first mask layer 21 is formed on the isolation layer 12, as described in some embodiments of the present invention, such as... Figure 3a , 3b as well as Figure 4 As shown, the method for forming the semiconductor structure 100 further includes: before forming the first mask layer 21, a second hard mask layer 24 and a second mask layer 23 may be sequentially formed on the surface of the isolation layer 12, and then the first mask layer 21 is formed on the surface of the second mask layer 23. That is, after planarizing the surface of the isolation layer 12, the second hard mask layer 24, the second mask layer 23, and the first mask layer 21 are sequentially formed on the surface of the isolation layer 12, which facilitates the subsequent transfer of patterns. The first mask layer 21 may be a silicon oxide layer, the second hard mask layer 24 may be one or a combination of silicon nitride, titanium nitride, or silicon nitride, and the second mask layer 23 may be a silicon oxynitride layer.

[0054] like Figure 5a-1 , Figure 5a-2 , Figure 5b as well as Figure 6 As shown, a first photoresist layer 41 defining an isolation opening 33 is formed on the surface of the first mask layer 21. The first photoresist layer 41 extends along a first direction and defines a photolithographic pattern along the first direction. The photolithographic pattern is located in the region where the isolation opening 33 is formed to define the formation position of the isolation opening 33. Figure 7a-1 , Figure 7a-2 , Figure 7b as well as Figure 8 As shown, a photolithographic pattern is transferred onto a first mask layer 21 using a photolithography process to form at least one isolation opening 33 on the first mask layer 21, and then the first photoresist layer 41 is removed. Optionally, there can be multiple isolation openings 33, which are spaced apart along a second direction and extend along a first direction.

[0055] Step S3: A first hard mask layer 22 is formed on the surface of the first mask layer 21. The first hard mask layer 22 fills the isolation opening 33, and the first hard mask layer 22 is selectively etched to form a plurality of word line initial openings 31. Specifically, as shown... Figure 9a-1 , Figure 9a-2 , Figure 9b as well as Figure 10As shown, a first hard mask layer 22 is formed on the first mask layer 21. The first hard mask layer 22 covers the surface of the first mask layer 21 and fills the isolation opening 33 of the first mask layer 21. (Referring to Figure 11-) Figure 14 As shown, the first hard mask layer 22 is then etched to form a plurality of word line initial openings 31 on the first hard mask layer 22. The word line initial openings 31 are used to define the areas where word line trenches 13 are formed. Forming the first hard mask layer 22 facilitates the formation of a pattern with a plurality of word line initial openings 31, which then facilitates the transfer of the word line initial openings 31 to the first mask layer 21, the word line initial openings 31 extending along the second direction.

[0056] Combination Figure 11a-1 , Figure 11a-2 , Figure 11b and Figure 12 As shown, the step of etching the first hard mask layer 22 to form a plurality of initial word line openings 31 may include: forming a second photoresist layer 42 on the surface of the first hard mask layer 22 that defines a plurality of initial word line openings 31, wherein the initial word line openings 31 correspond to the location of the active region 11, such as... Figure 13a-1 , Figure 13a-2 , Figure 13b and Figure 14 As shown, the first hard mask layer 22 is then etched using a photolithography process to form a pattern with multiple initial openings 31 for word lines, and then the second photoresist layer 42 is removed.

[0057] Combination Figure 15a-1 , Figure 15a-2 , Figure 15b and Figure 16 As shown, in step S4: the first mask layer 21 is etched along the initial word line opening 31 to form the word line opening 32, and the first hard mask layer 22 is removed. Thus, the first mask layer 21 is etched with the first hard mask layer 22 as a mask to transfer the pattern of the initial word line opening 31 to the first mask layer 21. Multiple word line openings 32 are formed in the first mask layer 21, and the first hard mask layer 22 is removed. In this way, word line openings 32 defining word line trenches 13 and isolation openings 33 defining isolation trenches 14 can be formed in the first mask layer 21.

[0058] Figure 17- Figure 20As shown, in step S5: the substrate 1 is etched along the word line opening 32 and the isolation opening 33 to form multiple word line trenches 13 and at least one isolation trench 14. That is, the substrate 1 is etched using the first mask layer 21 as a mask. The first mask layer 21 has word line openings 32 and isolation openings 33. The pattern of the first mask layer 21 is transferred to the substrate 1, thereby forming multiple word line trenches 13 and isolation trenches 14 intersecting with the word line trenches 13 in the substrate 1. The word line trenches 13 extend along the second direction and penetrate the active region 11 and the isolation layer 12. The isolation trenches 14 are formed between the active regions 11 and penetrate the multiple word line trenches 13 to divide the sidewalls of the word line trenches 13 into multiple segments. In this way, there are gaps between the multiple segments of word line trenches 13 in the second direction. During the subsequent thermal oxidation process, the expansion stress of the sidewalls of the word line trenches 13 can be reduced, preventing the word line trenches 13 from bending and affecting the subsequent filling of the metal gate.

[0059] like Figure 17a-1 , Figure 17a-2 , Figure 17b and Figure 18 As shown, step S6: Remove the first mask layer 21. Before forming the first mask layer 21, a second hard mask layer 24 and a second mask layer 23 may be formed on the isolation layer 12. In the process of etching the first mask layer 21 to form the isolation opening 33 and the word line opening 32, the second mask layer 23 may form an etching barrier layer. Before etching the substrate 1 using the first mask layer 21 as the mask, the second mask layer 23 and the second hard mask layer 24 may be etched first to transfer the patterns of the word line opening 32 and the isolation opening 33 to the second mask layer 23 and the second hard mask layer 24. Then, the first mask layer 21 and the second mask layer 23 are removed, and the second hard mask layer 24 is used as the mask etching substrate 1. Finally, the second hard mask layer 24 is removed to form a word line trench 13 penetrating the active region 11. Figure 20 In the example shown, the active area 11 can be formed into a "mountain" structure, that is, each active area 11 forms two character line grooves 13, and at the same time, an isolation groove 14 is formed along the extension direction of the active area 11, penetrating the character line grooves 13.

[0060] In some embodiments of the present invention, the isolation opening 33 is located between two adjacent columns of active regions 11, specifically, as shown in the example. Figure 5a-1 As shown, the patterned openings of the first photoresist layer 41 are located between adjacent active regions 11, as... Figure 7a-1As shown, when etching the first mask layer 21, the pattern of the first photoresist layer 41 is transferred to the first mask layer 21 to form an isolation opening 33. The isolation opening 33 is located above the isolation layer 12 between two adjacent columns of active regions 11, so that the final isolation trench 14 is formed between two adjacent columns of active regions 11, thus eliminating the need to improve the formation process of the front active region 11. When there are multiple isolation trenches 14, multiple columns of active regions 11 can be spaced apart between adjacent isolation trenches 14.

[0061] In other embodiments of the invention, the isolation opening 33 is located on at least one column of the active regions 11, specifically, as shown in the figure. Figure 5a-2 As shown, the patterned opening of the first photoresist layer 41 is located above at least one active region 11, as... Figure 7a-2 As shown, during the etching of the second mask layer 21, the pattern of the first photoresist layer 41 is transferred to the first mask layer 21 to form an isolation opening 33. The isolation opening 33 is located above at least one active region 11. Figure 5a-2 In the specific example shown, the pattern of the first photoresist layer 41 is located above a column of active regions 11; in such a case... Figure 17a-2 and Figure 19a-2 In the example shown, the isolation opening 33 is formed above a column of active regions 11, wherein the width of the isolation opening 33 is greater than the width of the active regions 11 along the second direction. Etching along the isolation opening 33 removes a column of active regions 11 and an adjacent portion of the isolation layer 12 located below the isolation opening 33 to form an isolation trench 14. This eliminates the need to change the formation process of the front active regions 11, and increases the area and width of the isolation opening 11, which is beneficial to the formation of the isolation opening 33. It also enables the formation of a larger gap between the multiple word line trenches 13, which further facilitates the release of expansion stress.

[0062] In some other embodiments of the present invention, the multiple rows of active regions 11 are divided into multiple groups along the second direction, and the distance between two adjacent groups of active regions 11 is greater than the distance between two adjacent rows of active regions 11 within a group. Isolation openings 33 are correspondingly formed between adjacent groups of active regions 11, for example... Figure 1b As shown, in the process of forming the active region 11, a row of active regions 11 can be left empty at a certain distance to define the area for forming the isolation trench 14. That is, the multiple arrayed active regions 11 are divided into multiple groups in the second direction, and each group can include multiple rows of active regions 11. The adjacent groups of active regions 11 can be spaced apart by a certain distance, and the isolation trench 14 is formed between the two groups of active regions 11. Figure 5b As shown, the patterned openings of the first photoresist layer 41 correspond to the isolation layer 12 located between two adjacent groups of active regions 11, as... Figure 7bAs shown, during the etching of the second mask layer 21, the pattern of the first photoresist layer 41 is transferred to the first mask layer 21 to form an isolation opening 33. The isolation opening 33 is located above the isolation layer 12 between the two groups of active regions 11, thereby correspondingly forming an isolation trench 14 in the isolation layer 12 between the two adjacent groups of active regions 11. Furthermore, the spacing between the two adjacent groups of active regions 11 is greater than the distance between the two adjacent columns of active regions 11 within the group, that is, the spacing width between the two adjacent groups of active regions 11 is larger, which is conducive to forming a wider isolation trench 14. Moreover, since the spacing between the adjacent active regions 11 here is different from others, it is also conducive to the corresponding formation of the pattern opening when etching the first photoresist layer 41.

[0063] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A semiconductor structure, characterized by, include: The substrate has an isolation layer and a plurality of active regions arranged in an array, the plurality of active regions being arranged in columns along a first direction and the columns of active regions being spaced apart along a second direction, the isolation layer being located between the surface of the active regions and the active regions; Multiple word line grooves, wherein the word line grooves are located within the substrate and penetrate the active region and the isolation layer along a second direction; At least one isolation trench is formed between the two columns of the active regions and extends along the first direction, the isolation trench penetrating the plurality of word line trenches to divide the sidewalls forming the word line trenches into multiple segments.

2. The semiconductor structure of claim 1, wherein, The isolation trenches are multiple and spaced apart along the second direction.

3. The semiconductor structure of claim 2, wherein, The isolation trenches are evenly spaced along the second direction, and multiple rows of active areas are provided between adjacent isolation trenches.

4. The semiconductor structure according to claim 3, characterized in that, At least three columns of active zones are provided between adjacent isolation trenches.

5. The semiconductor structure according to claim 1, characterized in that, The isolation trench is formed between two adjacent columns of the active area.

6. The semiconductor structure according to claim 1, characterized in that, The isolation trench is formed on at least one column of the active regions and is formed by removing a portion of the active regions and the isolation layer.

7. The semiconductor structure according to claim 1, characterized in that, The active regions are divided into multiple groups along the second direction, and the distance between two adjacent groups of active regions is greater than the distance between two adjacent columns of active regions within a group. The isolation trench is formed between two adjacent groups of active regions.

8. The semiconductor structure according to claim 1, characterized in that, The depth of the isolation trench is 4 / 5 to 6 / 5 times the depth of the word line trench.

9. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate having an isolation layer and a plurality of active regions arranged in an array, the plurality of active regions being arranged in columns along a first direction and the columns of active regions being spaced apart along a second direction, the isolation layer being located between the surface of the active regions and the active regions; A first mask layer is formed on the isolation layer, and the first mask layer is selectively etched to form at least one isolation opening, the isolation opening extending along the first direction; A first hard mask layer is formed on the surface of the first mask layer, the first hard mask layer fills the isolation opening, and the first hard mask layer is selectively etched to form a plurality of word line initial openings; The first mask layer is etched along the initial opening of the word line to form the word line opening, and the first hard mask layer is removed. The substrate is etched along the word line opening and the isolation opening to form a plurality of word line trenches and at least one isolation trench. The word line trenches extend along the second direction and penetrate the active region and the isolation layer. The isolation trench is formed between the active regions and penetrates the plurality of word line trenches to divide the sidewalls forming the word line trenches into multiple segments. Remove the first mask layer.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, Before the first mask layer is formed on the surface of the isolation layer, the following is also included: A second hard mask layer and a second mask layer are sequentially formed on the surface of the isolation layer; In the step of etching the first mask layer along the initial opening of the word line to form the word line opening, the etching of the first mask layer stops at the second mask layer; In the step of etching the substrate along the word line opening and the isolation opening, the second mask layer, the second hard mask layer and the substrate are etched along the word line opening and the isolation opening; In the step of removing the first mask layer, the second mask layer and the second hard mask layer are removed sequentially.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that, In the step of forming a first mask layer on the surface of the isolation layer and selectively etching the first mask layer to form at least one isolation opening, the isolation opening is located between two adjacent columns of the active regions.

12. The method for preparing a semiconductor structure according to claim 10, characterized in that, In the step of forming a first mask layer on the surface of the isolation layer and selectively etching the first mask layer to form at least one isolation opening, the isolation opening is located on at least one column of the active regions.

13. The method for preparing a semiconductor structure according to claim 10, characterized in that, The active regions are divided into multiple groups along the second direction. The distance between two adjacent groups of active regions is greater than the distance between two adjacent columns of active regions within a group. The isolation opening is formed between two adjacent groups of active regions.

14. The method for preparing a semiconductor structure according to claim 10, characterized in that, The step of selectively etching the first mask layer to form at least one isolation opening includes: forming a first photoresist layer defining the isolation opening on the surface of the first mask layer; and removing the first photoresist layer after forming the isolation opening.

15. The semiconductor structure according to claim 10, characterized in that, The step of selectively etching the second mask layer to form a plurality of initial word line openings includes: forming a second photoresist layer on the surface of the first hard mask layer that defines the initial word line openings; and removing the second photoresist layer after forming the word line openings.

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