Semiconductor structure and method of forming the same

Abstract

The application relates to a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises the following steps: forming a substrate, the substrate comprising a substrate, a stack layer and a protection structure covering the sidewall of the stack layer, the substrate comprising a wafer inner area and a wafer edge area, the stack layer being located at least in the wafer inner area, and the protection structure being located in the wafer edge area, the stack layer comprising alternately stacked support layers and sacrificial layers; defining a first inner area and a second inner area in the wafer inner area; forming a plurality of capacitor holes in the stack layer in the first inner area and the second inner area; forming a lower electrode layer in the capacitor holes; forming an opening in the first inner area; removing all the sacrificial layers in the first inner area along the opening, and the second inner area retaining part of the sacrificial layers; forming a dielectric layer and an upper electrode layer in the first inner area. The application ensures the accuracy of the feature size of the capacitor hole and reduces the probability of peeling of the lower electrode layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] DRAM (Dynamic Random Access Memory) includes multiple memory cells arranged in an array and bit lines electrically connected to the memory cells. Each memory cell includes a transistor and a capacitor, thus forming a 1T1C (1 Transistor 1 Capacitor) structure. The transistor is used to control the switching on and off of the memory cell, and the capacitor is used for data storage. The transistor includes a first source-drain region and a second source-drain region, wherein the first source-drain region is electrically connected to the capacitor, and the second source-drain region is electrically connected to the bit line.

[0003] In the formation of semiconductor structures such as DRAM, a stacked layer is typically formed on a substrate first. After etching the stacked layer to form capacitor vias, capacitors are then formed within these vias. However, during the etching process, the edges of the stacked layer may be under-etched, causing the capacitor vias in the edge regions to fail to penetrate the stacked layer due to insufficient etching. Furthermore, limitations in the photolithography process (such as defocusing) can lead to significant differences between the feature size of the capacitor vias at the stacked layer edges and the predetermined feature size. Insufficient etching or excessive differences between the feature size and the predetermined size can cause problems such as tilting or collapse of the capacitor vias in subsequent processes, as well as peeling of the lower electrode layer deposited within the vias. These issues severely affect the performance of the capacitors and the overall electrical performance of the DRAM and other semiconductor structures, resulting in reduced product yield.

[0004] Therefore, how to reduce the peeling of the lower electrode layer during the semiconductor structure formation process, improve the performance of the semiconductor structure, and increase the manufacturing yield of the semiconductor structure are technical problems that urgently need to be solved. Summary of the Invention

[0005] This invention provides a semiconductor structure and a method for forming the same, which reduces the problem of stripping of the lower electrode layer during the semiconductor structure formation process, improves the performance of the semiconductor structure, and increases the manufacturing yield of the semiconductor structure.

[0006] To address the above problems, the present invention provides a method for forming a semiconductor structure, comprising:

[0007] A substrate is formed, the substrate including a substrate, a stacked layer located above the substrate along a first direction, and a protective structure at least covering the sidewalls of the stacked layer, the substrate including an inner wafer region and a wafer edge region distributed around the outer periphery of the inner wafer region, the stacked layer being located at least in the inner wafer region, the protective structure being located in the wafer edge region, the stacked layer including a support layer and a sacrificial layer alternately stacked along the first direction, the first direction being perpendicular to the top surface of the substrate;

[0008] A first internal region and a second internal region distributed around the periphery of the first internal region are defined within the inner region of the wafer.

[0009] A plurality of capacitor holes are formed in the stacked layer of the first inner region and the second inner region, and all of the capacitor holes in the first inner region penetrate the stacked layer along the first direction;

[0010] A lower electrode layer is formed inside the capacitor hole, covering the inner wall of the capacitor hole;

[0011] An opening is formed within the first internal region to expose the topmost sacrificial layer of the stacked layers;

[0012] All of the sacrificial layer in the first internal region is removed along the opening to expose the sidewall of the lower electrode layer in the first internal region, while at least a portion of the sacrificial layer is retained in the second internal region;

[0013] A dielectric layer covering the surface of the lower electrode layer and an upper electrode layer covering the surface of the dielectric layer are formed in the first internal region.

[0014] In some embodiments, the specific steps for forming the substrate include:

[0015] Provide substrate;

[0016] A wafer interior region and a wafer edge region distributed around the outer periphery of the wafer interior region are defined in the substrate;

[0017] A first sacrificial layer is formed in the inner region of the wafer of the substrate;

[0018] A first support layer is formed to cover the first sacrificial layer, and a first protective layer is simultaneously formed to cover the wafer edge region of the substrate and the sidewall of the first sacrificial layer;

[0019] A second sacrificial layer is formed covering the first support layer, and a second protective layer is simultaneously formed covering the first protective layer;

[0020] A second support layer is formed to cover the second sacrificial layer, and a third protective layer is formed to cover the second protective layer. The first sacrificial layer, the first support layer, the second sacrificial layer, and the second support layer together serve as the stacked layer, and the first protective layer, the second protective layer, and the third protective layer together serve as the protective structure.

[0021] In some embodiments, the specific steps of forming a first support layer covering the first sacrificial layer and simultaneously forming a first protective layer covering the wafer edge region of the substrate and the sidewalls of the first sacrificial layer include:

[0022] A first support material is deposited on the substrate, the first support material covering the first sacrificial layer serves as the first support layer, and the first support material covering the wafer edge region of the substrate and the sidewall of the first sacrificial layer serves as the first protective layer.

[0023] In some embodiments, the specific steps of defining an internal wafer region and a wafer edge region distributed around the outer periphery of the internal wafer region in the substrate include:

[0024] The theoretical defocused area of ​​the substrate during the photolithography process is obtained, and the range including the entire theoretical defocused area is taken as the wafer edge region, and the area surrounded by the wafer edge region is taken as the wafer interior region.

[0025] In some embodiments, the specific steps of defining a first internal region and a second internal region distributed around the periphery of the first internal region in the wafer internal region include:

[0026] The theoretically insufficient etching area of ​​the substrate during the photolithography process is obtained, and the area that includes the entire theoretically insufficient etching area and is surrounded by the wafer edge area is taken as the second internal region, and the area in the wafer internal region that is surrounded by the second internal region is taken as the first internal region.

[0027] In some embodiments, the specific steps of forming a lower electrode layer covering the inner wall of the capacitor hole include:

[0028] A lower electrode layer is formed to cover the inner wall of the capacitor hole;

[0029] A filling layer is formed that fills the capacitor hole and covers the lower electrode layer.

[0030] In some embodiments, the specific steps of forming an opening in the first internal region to expose the topmost sacrificial layer of the stacked layers include:

[0031] The second support layer in the first internal region of the stacked layers is etched to form a plurality of openings that expose the second sacrificial layer.

[0032] In some embodiments, the specific steps of removing all of the sacrificial layer within the first internal region along the opening include:

[0033] At least all of the second sacrificial layer within the first internal region is removed along the opening, exposing the first support layer within the first internal region;

[0034] The first support layer in the first internal region is etched along the opening to expose the first sacrificial layer in the first internal region;

[0035] At least all of the first sacrificial layer within the first internal region is removed along the opening.

[0036] To address the aforementioned problems, the present invention also provides a semiconductor structure formed using the semiconductor structure formation method described above, characterized in that it comprises:

[0037] The substrate includes an inner region of a wafer and an outer periphery of the inner region of the wafer, the inner region of the wafer including a first inner region and a second inner region surrounding the outer periphery of the first inner region;

[0038] A stacked structure is located above the substrate along a first direction. The stacked structure further includes a sacrificial layer and a plurality of support layers spaced apart along the first direction. The sacrificial layer is located at least in the second inner region and the wafer edge region, and the sacrificial layer is located between two adjacent support layers. The first direction is perpendicular to the top surface of the substrate.

[0039] A protective structure is located at the edge region of the wafer and at least covers the sidewalls of the stacked structure;

[0040] A capacitor, located only in the first internal region, includes a lower electrode layer extending through the stacked structure along the first direction, a dielectric layer covering the surface of the lower electrode layer, and an upper electrode layer covering the surface of the dielectric layer.

[0041] In some embodiments, it also includes:

[0042] A dummy capacitor, located only in the second internal region, includes a lower electrode layer that does not penetrate the stacked structure along the first direction.

[0043] In some embodiments, the protective structure includes:

[0044] A first protective layer at least covers the sidewalls of the sacrificial layer in the wafer edge region;

[0045] A second protective layer covers the first protective layer and the sidewalls of the stacked structure;

[0046] A third protective layer covers the second protective layer. The materials of the first and third protective layers are the same as the material of the support layer, and the material of the second protective layer is the same as the material of the sacrificial layer.

[0047] The semiconductor structure and its formation method provided by the present invention define an inner wafer region and an edge wafer region in a substrate, and define a first inner region and a second inner region distributed around the outer periphery of the first inner region in the inner wafer region. Capacitor holes are formed only in the inner wafer region, and openings for removing sacrificial layers in the stacked layers are formed only in the first inner region. At the same time, by forming a protective structure on the sidewalls of the stacked layers, the etchant is prevented from etching the sacrificial layers in the second inner region and the wafer edge region from the sidewalls of the stacked layers during the removal of the sacrificial layers. This ensures the accuracy of the feature size of the capacitor holes and allows the remaining sacrificial layers in the second inner region to support the capacitor holes in the second inner region. This reduces the probability of the lower electrode layer in the second inner region being peeled off, improves the performance of the semiconductor structure, and increases the manufacturing yield of the semiconductor structure. Attached Figure Description

[0048] Appendix Figure 1 This is a flowchart of a method for forming a semiconductor structure according to a specific embodiment of the present invention;

[0049] Appendix Figure 2 - Appendix Figure 10 This is a schematic diagram of the main process structure in the formation of the semiconductor structure according to a specific embodiment of the present invention. Detailed Implementation

[0050] The specific embodiments of the semiconductor structure and its formation method provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0051] This specific embodiment provides a semiconductor structure, with appended... Figure 1 This is a flowchart illustrating the method for forming a semiconductor structure according to a specific embodiment of the present invention. Figure 2 - Appendix Figure 10 This is a schematic diagram of the main process structure in the formation of the semiconductor structure according to a specific embodiment of the present invention. For example... Figures 1-10 As shown, the method for forming the semiconductor structure includes the following steps:

[0052] Step S11: Forming a substrate, the substrate including a substrate 20, a stacked layer 51 located above the substrate 20 along a first direction D1, and a protective structure 52 at least covering the sidewalls of the stacked layer 51. The substrate 20 includes an internal wafer region and a wafer edge region P3 distributed around the outer periphery of the internal wafer region. The stacked layer 51 is located at least in the internal wafer region, and the protective structure 52 is located in the wafer edge region P3. The stacked layer 51 includes a support layer and a sacrificial layer alternately stacked along the first direction D1, the first direction D1 being perpendicular to the top surface of the substrate 20. Figure 5 As shown;

[0053] Step S12, define a first internal region P1 and a second internal region P2 distributed around the periphery of the first internal region P1 in the internal region of the wafer, as follows: Figure 6 As shown;

[0054] Step S13: A plurality of capacitor holes 60 are formed in the stacked layer 51 of the first internal region P1 and the second internal region P2. All the capacitor holes 60 in the first internal region P1 penetrate the stacked layer 51 along the first direction D1, such as... Figure 6 and Figure 7 As shown, where, Figure 6 This is a cross-sectional diagram showing the formation of capacitor vias in the stacked layers. Figure 7 This is a top view diagram after capacitor holes are formed in the stacked layers;

[0055] Step S14: A lower electrode layer 80 is formed within the capacitor hole 60, covering the inner wall of the capacitor hole 60, as shown below. Figure 8 As shown;

[0056] Step S15, an opening 90 is formed in the first internal region P1 to expose the topmost sacrificial layer of the stacked layers 51, as shown below. Figure 9 As shown;

[0057] Step S16: Remove all of the sacrificial layer in the first internal region P1 along the opening 90 to expose the sidewall of the lower electrode layer 80 in the first internal region P1, while retaining at least a portion of the sacrificial layer in the second internal region P2.

[0058] Step S17: A dielectric layer covering the surface of the lower electrode layer 80 and an upper electrode layer covering the surface of the dielectric layer are formed in the first internal region P1.

[0059] In some embodiments, the specific steps for forming the substrate include:

[0060] Substrate 20 is provided;

[0061] A wafer interior region and a wafer edge region P3 distributed around the outer periphery of the wafer interior region are defined in the substrate;

[0062] A first sacrificial layer 511 is formed in the wafer interior region of the substrate 20;

[0063] A first support layer 512 is formed to cover the first sacrificial layer 511, and a first protective layer 521 is formed to cover the wafer edge region P3 of the substrate 20 and the sidewall of the first sacrificial layer 511.

[0064] A second sacrificial layer 513 is formed to cover the first support layer 512, and a second protective layer 522 is formed to cover the first protective layer 521.

[0065] A second support layer 514 is formed to cover the second sacrificial layer 513, and a third protective layer 523 is formed to cover the second protective layer 522. The first sacrificial layer 511, the first support layer 512, the second sacrificial layer 513 and the second support layer 514 together serve as the stacked layer 51, and the first protective layer 521, the second protective layer 522 and the third protective layer 523 together serve as the protective structure 52.

[0066] In some embodiments, the specific steps of forming a first support layer 512 covering the first sacrificial layer 511 and simultaneously forming a first protective layer 521 covering the wafer edge region P3 of the substrate 20 and the sidewall of the first sacrificial layer 511 include:

[0067] A first support material 30 is deposited on the substrate 20. The first support material 30 covering the first sacrificial layer 511 serves as the first support layer, and the first support material 30 covering the wafer edge region P3 of the substrate 20 and the sidewall of the first sacrificial layer 511 serves as the first protective layer 521.

[0068] Specifically, the substrate 20 may be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example for illustration. In one example, the substrate 20 is a wafer, which includes an internal region located in the middle of the wafer and an edge region located at the edge of the wafer. For example, a first sacrificial material 21 can be deposited on the top surface of the substrate 20 using chemical vapor deposition, physical vapor deposition, or atomic layer deposition processes. The first sacrificial material 21 is then etched back to remove the first sacrificial material 21 from the edge region P3 of the wafer, leaving only the first sacrificial material 21 in the internal region of the wafer, resulting in... Figure 2The structure is shown. Next, the first support material 30 is deposited on the substrate 20 such that the first support material 30 continuously covers the remaining first sacrificial material 21 and the substrate 20 of the wafer edge region P3, as shown. Figure 3 As shown. Then, a second sacrificial material 40 is deposited covering the sidewalls of the first support material 30 and the substrate 20. The edges of the second sacrificial material 40 are stepped, as shown. Figure 4 As shown. Then, a second support material is deposited covering the second sacrificial material 40. The first sacrificial material 21 retained in the wafer interior region serves as the first sacrificial layer 511, the first support material 30 in the wafer interior region serves as the first support layer 512, the second sacrificial material 40 in the wafer interior region serves as the second sacrificial layer 513, and the second support material in the wafer interior region serves as the second support layer 514. The first sacrificial layer 511, the first support layer 512, the second sacrificial layer 513, and the second support layer 514 together serve as the stacked layer 51. The first support material 30 in the wafer edge region P3 serves as the first protective layer 521, the second sacrificial material 40 in the wafer edge region P3 of the substrate 20 and the second sacrificial material 40 covering the sidewall of the substrate 20 together serve as the second protective layer 522, and the second support material covering the second protective layer 522 serves as the third protective layer 523. The first protective layer 521, the second protective layer 522, and the third protective layer 523 together serve as the protective structure 52. In one example, the first sacrificial layer material 21 and the second sacrificial material 40 have the same material composition, for example, both are oxide materials; the first support material 30 and the second support material also have the same material composition, for example, both are nitride materials.

[0069] In this specific embodiment, the stacked layer 51 and the protective structure 52 are formed simultaneously, thereby helping to simplify the semiconductor structure manufacturing process and improve the manufacturing efficiency of the semiconductor structure. The protective structure 52 is used to isolate the edge of the stacked layer 51 from the etchant when removing the sacrificial layer (e.g., the first sacrificial layer 511 and the second sacrificial layer 513) in the stacked layer 51, preventing the etchant from etching the sacrificial layer starting from the edge of the stacked layer 51 (e.g., the sidewall of the stacked layer 51), so that the sacrificial layer at the edge of the stacked layer 51 is retained to support the capacitor via at the edge of the stacked layer 51.

[0070] In some embodiments, the specific steps of defining an internal wafer region and a wafer edge region P3 distributed around the outer periphery of the internal wafer region in the substrate 20 include:

[0071] The theoretical defocused area of ​​the substrate during the photolithography process is obtained, and the range including the entire theoretical defocused area is taken as the wafer edge region P3, and the area surrounded by the wafer edge region is taken as the wafer interior region.

[0072] In some embodiments, the specific steps for defining a first internal region P1 and a second internal region P2 distributed around the periphery of the first internal region P1 include:

[0073] The theoretical etch-insufficient area of ​​the substrate during the photolithography process is obtained, and the area that includes the entire range of the theoretical etch-insufficient area and is surrounded by the wafer edge area P3 is taken as the second internal area P2, and the area in the wafer internal area that is surrounded by the second internal area P2 is taken as the first internal area P1.

[0074] For example, the capacitor aperture is formed by forming an etching pattern in a mask above the stacked layers using photolithography, and then etching the stacked layers downwards along the etching pattern in the mask. During the process of forming the etching pattern in the mask using photolithography, defocusing may occur, which affects the feature size of the capacitor aperture formed by etching the stacked layers downwards. In this specific embodiment, the region where defocusing occurs during the formation of the capacitor aperture 60 on the substrate 20 using photolithography can be obtained by constructing a theoretical model or by statistically analyzing historical data, and the region where defocusing occurs is taken as the theoretical defocusing region. After obtaining the theoretical defocusing region, the union of all the theoretical defocusing regions is taken as the wafer edge region P3. Due to the limitations of the photolithography equipment itself, defocusing occurs at the edge of the substrate 20 during the photolithography process. The reason for taking the union of all the theoretical defocusing regions as the wafer edge region P3 is that defocusing will cause a large difference between the feature size of the etched capacitor aperture (e.g., the aperture diameter or the width of the capacitor aperture along the second direction D2) and the preset size, thereby affecting the performance of the final semiconductor structure.

[0075] For example, the region where the capacitor hole does not penetrate the stacked layer 51 along the first direction D1 during the formation of the capacitor hole on the substrate 20 by photolithography can be obtained by constructing a theoretical model or by statistically analyzing historical data. This region is then used as the theoretical etch-insufficient region. After obtaining the theoretical etch-insufficient region, the union of all the theoretical etch-insufficient regions within the region surrounded by the wafer edge region P3 is taken as the second internal region P2, and the region surrounded by the second internal region P2 is taken as the first internal region P1.

[0076] In some embodiments, the specific steps of forming a lower electrode layer 80 covering the inner wall of the capacitor hole 60 include:

[0077] A lower electrode layer 80 is formed to cover the inner wall of the capacitor hole 60;

[0078] A filling layer 81 is formed that fills the capacitor hole 60 and covers the lower electrode layer 80.

[0079] Specifically, after forming the stacked layer 51, a plurality of capacitor holes 60 can be formed in the first internal region P1 and the second internal region P2 by etching the stacked layer 51. All the capacitor holes 60 in the first internal region P1 penetrate the stacked layer 51 along the first direction D1, while at least one capacitor hole 60 in the second internal region P2 does not penetrate the stacked layer 51 along the first direction D1. Since the wafer edge region P3 is a region prone to defocusing, capacitor holes are not formed in the wafer edge region P3, thereby ensuring the characteristic dimensions of the formed capacitor holes while reducing the manufacturing cost of the semiconductor structure. After forming the capacitor holes 60, a conductive material such as titanium nitride is deposited on the inner wall of the capacitor holes 60, and a lower electrode layer 80 covering the inner wall of the capacitor holes 60 is formed in the first internal region P1 and the second internal region P2. Next, a dielectric material such as nitride is deposited within the capacitor hole 60, forming a filling layer 81 in the first internal region P1 and the second internal region P2 that fills the capacitor hole 60 and covers the lower electrode layer 80, such as... Figure 8 As shown. The filling layer 81 is used to support the lower electrode layer 80 and improve the structural stability of the lower electrode layer 80.

[0080] In some embodiments, the specific steps of forming an opening 90 within the first internal region P1 to expose the topmost sacrificial layer of the stacked layers 51 include:

[0081] The second support layer 514 in the first internal region P1 of the stacked layer 51 is etched to form a plurality of openings 90 that expose the second sacrificial layer 513.

[0082] In some embodiments, the specific steps of removing all of the sacrificial layer within the first internal region P1 along the opening 90 include:

[0083] At least all of the second sacrificial layer 513 within the first internal region P1 is removed along the opening 90, exposing the first support layer 512 within the first internal region P1;

[0084] The first support layer 512 in the first internal region P1 is etched along the opening 90 to expose the first sacrificial layer 511 in the first internal region P1.

[0085] At least all of the first sacrificial layer 511 within the first internal region P1 is removed along the opening 90.

[0086] For example, a dry etching process can be used to etch only a portion of the second support layer 514 within the first internal region P1 of the stacked layer 51, forming multiple openings 90 in the first internal region P1 that expose the second sacrificial layer 513. Next, a wet etching process can be used to remove all of the second sacrificial layer 513 in the first internal region P1 and a portion of the second sacrificial layer 513 in the second internal region P2 along the openings 90. At this time, due to the obstruction of the protective structure 52, the wet etchant cannot etch the second sacrificial layer 513 in the third region P3 from the sidewall of the stacked layer 51. Then, the first support layer 512 within the first internal region P1 is etched along the openings 90, exposing the first sacrificial layer 511. Afterward, a wet etching process is used again along the openings 90 to remove all of the first sacrificial layer 511 in the first internal region P1 and a portion of the second sacrificial layer 513 in the second internal region P2, resulting in... Figure 9 The structure is shown. At this time, due to the obstruction of the protective structure 52, the wet etchant cannot etch the first sacrificial layer 511 of the third region P3 from the sidewall of the stacked layer 51. The remaining first sacrificial layer 511 and second sacrificial layer 513 of the second inner region P2 can stably support the lower electrode layer of the second inner region P2, avoiding peeling problems of the lower electrode layer of the second inner region P2. Figure 10 This is a top view of the semiconductor structure after the opening is formed. Figure 10 The image shows multiple storage regions on the substrate 20 separated by isolation channels 100. Among them, Figure 10 In the diagram, the first boundary line B1 represents the boundary between the second internal region P2 and the wafer edge region P3, and the second boundary line B2 represents the boundary between the first internal region P1 and the second internal region P2. Those skilled in the art should understand that the first boundary line B1 and the second boundary line B2 are only used to illustrate the relative positional relationship between the first internal region P1, the second internal region P2, and the third region P3; in the actual semiconductor structure, the first boundary line B1 and the second boundary line B2 do not exist.

[0087] In one example, by adjusting the size of the first inner region P1 (e.g., the width of the first inner region P1 along the second direction D2), the size of the second inner region P2 (e.g., the width of the second inner region P2 along the second direction D2), the size of the wafer edge region P3 (e.g., the width of the wafer edge region P3 along the second direction D2), the spacing between the first inner region P1 and the second inner region P2, and the spacing between the second inner region P2 and the wafer edge region P3, it is achieved that when removing the sacrificial layers (including the first sacrificial layer 511 and the second sacrificial layer 513), all the sacrificial layers in the first inner region P1 can be removed, at least a portion of the sacrificial layers in the second inner region P2 are retained, and all the sacrificial layers in the wafer edge region P3 are retained.

[0088] This specific embodiment also provides a semiconductor structure, formed using the semiconductor structure formation method described above. A schematic diagram of the semiconductor structure provided in this specific embodiment can be found in [reference needed]. Figures 5-10 The semiconductor structure provided in this specific embodiment can be adopted as follows: Figures 1-10 The semiconductor structure shown is formed using the method described. Figures 5-10 As shown, the semiconductor structure includes:

[0089] Substrate 20, the substrate 20 includes an inner wafer region and a wafer edge region P3 distributed around the outer periphery of the inner wafer region, the inner wafer region includes a first inner region P1 and a second inner region P2 distributed around the outer periphery of the first inner region P1;

[0090] The stacked structure is located above the substrate 20 along the first direction D1. The stacked structure also includes a sacrificial layer and a plurality of support layers spaced apart along the first direction D1. The sacrificial layer is located at least in the second inner region P2 and the wafer edge region P3, and the sacrificial layer is located between two adjacent support layers. The first direction D1 is perpendicular to the top surface of the substrate 20.

[0091] The protective structure 52 is located in the wafer edge region P3 and at least covers the sidewalls of the stacked structure;

[0092] A capacitor, located only in the first internal region P1, includes a lower electrode layer 80 extending through the stacked structure along the first direction D1, a dielectric layer covering the surface of the lower electrode layer 80, and an upper electrode layer covering the surface of the dielectric layer.

[0093] In some embodiments, the semiconductor structure further includes:

[0094] A pseudo capacitor, located only in the second internal region P2, includes a lower electrode layer that does not penetrate the stacked structure along the first direction D1.

[0095] In some embodiments, the protective structure 52 includes:

[0096] The first protective layer 521 at least covers the sidewall of the sacrificial layer in the wafer edge region P1;

[0097] The second protective layer 522 covers the first protective layer 521 and the sidewalls of the stacked structure;

[0098] The third protective layer 523 covers the second protective layer 522. The materials of the first protective layer 521 and the third protective layer 523 are the same as the material of the support layer, and the material of the second protective layer 522 is the same as the material of the sacrificial layer.

[0099] The semiconductor structure and its formation method provided in this specific embodiment define an inner wafer region and an edge wafer region in a substrate, and define a first inner region and a second inner region distributed around the outer periphery of the first inner region in the inner wafer region. Capacitor holes are formed only in the inner wafer region, and openings for removing the sacrificial layer in the stacked layer are formed only in the first inner region. At the same time, by forming a protective structure on the sidewall of the stacked layer, the etchant is prevented from etching the sacrificial layer in the second inner region and the edge wafer region from the sidewall of the stacked layer during the removal of the sacrificial layer. This ensures the accuracy of the feature size of the capacitor holes and allows the remaining sacrificial layer in the second inner region to support the capacitor holes in the second inner region. This reduces the probability of the lower electrode layer in the second inner region being peeled off, improves the performance of the semiconductor structure, and increases the manufacturing yield of the semiconductor structure.

[0100] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is formed, the substrate including a substrate, a stacked layer located above the substrate along a first direction, and a protective structure at least covering the sidewalls of the stacked layer, the substrate including an inner wafer region and a wafer edge region distributed around the outer periphery of the inner wafer region, the stacked layer being located at least in the inner wafer region, the protective structure being located in the wafer edge region, the stacked layer including a support layer and a sacrificial layer alternately stacked along the first direction, the first direction being perpendicular to the top surface of the substrate; A first internal region and a second internal region distributed around the periphery of the first internal region are defined within the inner region of the wafer. A plurality of capacitor holes are formed in the stacked layer of the first inner region and the second inner region, and all of the capacitor holes in the first inner region penetrate the stacked layer along the first direction; A lower electrode layer is formed inside the capacitor hole, covering the inner wall of the capacitor hole; An opening is formed within the first internal region to expose the topmost sacrificial layer of the stacked layers; All of the sacrificial layer in the first internal region is removed along the opening to expose the sidewalls of the lower electrode layer in the first internal region, while at least a portion of the sacrificial layer is retained in the second internal region; A dielectric layer covering the surface of the lower electrode layer and an upper electrode layer covering the surface of the dielectric layer are formed in the first internal region.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The specific steps for forming the substrate include: Provide substrate; A wafer interior region and a wafer edge region distributed around the outer periphery of the wafer interior region are defined in the substrate; A first sacrificial layer is formed in the inner region of the wafer of the substrate; A first support layer is formed to cover the first sacrificial layer, and a first protective layer is simultaneously formed to cover the wafer edge region of the substrate and the sidewall of the first sacrificial layer; A second sacrificial layer is formed covering the first support layer, and a second protective layer is simultaneously formed covering the first protective layer; A second support layer is formed to cover the second sacrificial layer, and a third protective layer is formed to cover the second protective layer. The first sacrificial layer, the first support layer, the second sacrificial layer, and the second support layer together serve as the stacked layer, and the first protective layer, the second protective layer, and the third protective layer together serve as the protective structure.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, The specific steps of forming a first support layer covering the first sacrificial layer, and simultaneously forming a first protective layer covering the wafer edge region of the substrate and the sidewalls of the first sacrificial layer, include: A first support material is deposited on the substrate, the first support material covering the first sacrificial layer serves as the first support layer, and the first support material covering the wafer edge region of the substrate and the sidewall of the first sacrificial layer serves as the first protective layer.

4. The method for forming a semiconductor structure according to claim 1, characterized in that, The specific steps for defining an internal wafer region and a wafer edge region distributed around the outer periphery of the internal wafer region in the substrate include: The theoretical defocused area of ​​the substrate during the photolithography process is obtained, and the range including the entire theoretical defocused area is taken as the wafer edge region, and the area surrounded by the wafer edge region is taken as the wafer interior region.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, The specific steps for defining a first internal region and a second internal region distributed around the periphery of the first internal region within the wafer include: The theoretically insufficient etching area of ​​the substrate during the photolithography process is obtained, and the area that includes the entire theoretically insufficient etching area and is surrounded by the wafer edge area is taken as the second internal region, and the area in the wafer internal region that is surrounded by the second internal region is taken as the first internal region.

6. The method for forming a semiconductor structure according to claim 5, characterized in that, The specific steps for forming a lower electrode layer covering the inner wall of the capacitor hole include: A lower electrode layer is formed to cover the inner wall of the capacitor hole; A filling layer is formed that fills the capacitor hole and covers the lower electrode layer.

7. The method for forming a semiconductor structure according to claim 2, characterized in that, The specific steps for forming an opening in the first internal region to expose the topmost sacrificial layer of the stacked layers include: The second support layer in the first internal region of the stacked layers is etched to form a plurality of openings that expose the second sacrificial layer.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, The specific steps for removing all of the sacrificial layer within the first internal region along the opening include: At least all of the second sacrificial layer within the first internal region is removed along the opening, exposing the first support layer within the first internal region; The first support layer in the first internal region is etched along the opening to expose the first sacrificial layer in the first internal region; At least all of the first sacrificial layer within the first internal region is removed along the opening.

9. A semiconductor structure, formed using the semiconductor structure formation method as described in claim 1, characterized in that, include: The substrate includes an inner region of a wafer and an outer periphery of the inner region of the wafer, the inner region of the wafer including a first inner region and a second inner region surrounding the outer periphery of the first inner region; A stacked structure is located above the substrate along a first direction. The stacked structure further includes a sacrificial layer and a plurality of support layers spaced apart along the first direction. The sacrificial layer is located at least in the second inner region and the wafer edge region, and the sacrificial layer is located between two adjacent support layers. The first direction is perpendicular to the top surface of the substrate. A protective structure is located at the edge region of the wafer and at least covers the sidewalls of the stacked structure; A capacitor, located only in the first internal region, includes a lower electrode layer extending through the stacked structure along the first direction, a dielectric layer covering the surface of the lower electrode layer, and an upper electrode layer covering the surface of the dielectric layer.

10. The semiconductor structure according to claim 9, characterized in that, Also includes: A dummy capacitor, located only in the second internal region, includes a lower electrode layer that does not penetrate the stacked structure along the first direction.

11. The semiconductor structure according to claim 9, characterized in that, The protective structure includes: A first protective layer at least covers the sidewalls of the sacrificial layer in the wafer edge region; A second protective layer covers the first protective layer and the sidewalls of the stacked structure; A third protective layer covers the second protective layer. The materials of the first and third protective layers are the same as the material of the support layer, and the material of the second protective layer is the same as the material of the sacrificial layer.

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