Display panel and display device

Abstract

A display panel has a display area including a main display area and a sub-display area, the main display area surrounding at least a portion of the sub-display area. The display panel includes: a substrate located at least in the display area; a pixel circuit layer located on one side of the substrate and at least in the display area, the pixel circuit layer including a plurality of surrounding pixel circuits located in the main display area and at least partially surrounding the sub-display area; and a light-blocking layer located in the main display area and between the substrate and the pixel circuit layer, the orthographic projection of the light-blocking layer on the substrate at least partially overlapping the orthographic projections of the plurality of surrounding pixel circuits on the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the continuous development of science and technology, users have increasingly higher demands for the screen ratio (the ratio of the screen area to the front panel area of ​​the display device).

[0003] In the field of display technology, the concept of full-screen has emerged, which means that optical devices such as cameras in the display device are placed below the display screen to increase the ratio between the area of ​​the display screen and the area of ​​the front panel of the display device, and make the ratio approach 100%. Summary of the Invention

[0004] On one hand, a display panel is provided, the display panel having a display area, the display area including a main display area and a sub-display area, the main display area surrounding at least a portion of the sub-display area; the display panel includes: a substrate, at least located in the display area; a pixel circuit layer, located on one side of the substrate and at least in the display area, the pixel circuit layer including a plurality of surrounding pixel circuits, the plurality of surrounding pixel circuits being located in the main display area and at least partially surrounding the sub-display area; a light-blocking layer, located in the main display area and between the substrate and the pixel circuit layer, the orthographic projection of the light-blocking layer on the substrate at least partially overlapping the orthographic projection of the plurality of surrounding pixel circuits on the substrate.

[0005] In some embodiments, the light-blocking layer includes a plurality of light-blocking patterns. At least a portion of a pixel circuit is projected onto the substrate, within the projection range of a light-blocking pattern onto the substrate.

[0006] In some embodiments, the surrounding pixel circuitry includes a driving transistor. The orthographic projection of the active layer of the driving transistor onto the substrate lies within the orthographic projection range of the light-blocking pattern onto the substrate.

[0007] In some embodiments, the surrounding pixel circuit further includes a compensation transistor coupled to the driving transistor. The orthographic projection of the active layer of the compensation transistor onto the substrate lies within the range of the orthographic projection of the light-blocking pattern onto the substrate.

[0008] In some embodiments, the plurality of surrounding pixel circuits are arranged in multiple columns along a first direction and in multiple rows along a second direction. In a portion of the surrounding pixel circuits located on the same side of the sub-display area, the light-blocking patterns corresponding to at least two adjacent surrounding pixel circuits along the first direction are connected, and / or, the light-blocking patterns corresponding to at least two adjacent surrounding pixel circuits along the second direction are connected.

[0009] In some embodiments, the plurality of light-blocking patterns are connected to form a single structure. The light-blocking layer surrounds the sub-display area.

[0010] In some embodiments, the light-blocking layer includes at least two concentrically arranged light-blocking rings. Each light-blocking ring includes a plurality of connected light-blocking patterns, and the light-blocking ring surrounds at least a portion of the sub-display area.

[0011] In some embodiments, the light-blocking layer further includes at least one connecting pattern. Two adjacent light-blocking patterns are connected to each other by the connecting pattern.

[0012] In some embodiments, the display panel further includes: a first voltage signal line and a transition layer disposed in the pixel circuit layer; the light-blocking layer is connected to the first voltage signal line through the transition layer.

[0013] In some embodiments, the material of the light-blocking layer includes molybdenum or graphite.

[0014] In some embodiments, the plurality of surrounding pixel circuits are arranged in multiple columns along a first direction and in multiple rows along a second direction. Along the first direction, at least six columns of surrounding pixel circuits are provided on either side of the sub-display area, and along the second direction, at least three rows of surrounding pixel circuits are provided on either side of the sub-display area.

[0015] In some embodiments, the plurality of pixel circuit layers further includes a plurality of redundant pixel circuits. The plurality of redundant pixel circuits are located in the main display area and surround at least a portion of the sub-display area; the plurality of redundant pixel circuits are closer to the sub-display area than the surrounding pixel circuits.

[0016] In some embodiments, the plurality of surrounding pixel circuits are arranged in multiple columns along a first direction and in multiple rows along a second direction; the plurality of redundant pixel circuits are arranged in at least one column along the first direction and in at least one row along the second direction. Along the first direction, the sum of the number of columns of surrounding pixel circuits and the number of columns of redundant pixel circuits on either side of the sub-display area is greater than or equal to six columns. Along the second direction, the sum of the number of rows of surrounding pixel circuits and the number of rows of redundant pixel circuits on either side of the sub-display area is greater than or equal to three rows.

[0017] In some embodiments, the display panel further includes a plurality of first light-emitting devices located in the main display area; the pixel circuit layer further includes a plurality of first pixel circuits located in the main display area. The plurality of first pixel circuits are coupled to the plurality of first light-emitting devices; at least a portion of the plurality of surrounding pixel circuits are first pixel circuits.

[0018] In some embodiments, the display panel further includes a plurality of second light-emitting devices located in the sub-display area; the pixel circuit layer further includes a plurality of second pixel circuits located in the main display area. The plurality of second pixel circuits are connected to the plurality of second light-emitting devices via conductive lines; at least a portion of the plurality of surrounding pixel circuits are second pixel circuits.

[0019] In some embodiments, the display panel further includes a plurality of second light-emitting devices located in the sub-display area; the pixel circuit layer further includes a plurality of second pixel circuits located in the sub-display area. The plurality of second pixel circuits are coupled to the plurality of second light-emitting devices.

[0020] In some embodiments, the display panel further includes a border area located on at least one side of the display area and a plurality of second light-emitting devices located in the sub-display area; the pixel circuit layer further includes a plurality of second pixel circuits located in the border area, the plurality of second pixel circuits being coupled to the plurality of second light-emitting devices via conductive lines.

[0021] On the other hand, a display device is provided, comprising: the display panel described in any of the above embodiments.

[0022] In some embodiments, the display device further includes: an optical element located on the side of the light-blocking layer away from the pixel circuit layer, wherein the orthographic projection of the optical element on the substrate is located within the sub-display area. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size, etc., of the products involved in the embodiments of this disclosure.

[0024] Figure 1 This is a structural diagram of a display device according to some embodiments of the present disclosure;

[0025] Figure 2 This is a structural diagram of a display panel according to some embodiments of the present disclosure;

[0026] Figure 3a This is a structural diagram of another display device according to some embodiments of the present disclosure;

[0027] Figure 3b This is a structural diagram of another display device according to some embodiments of the present disclosure;

[0028] Figure 4a This is a structural diagram of a display device in one implementation method;

[0029] Figure 4b This is a schematic diagram illustrating total internal reflection of light at the interface between the backsheet and the air in one implementation method.

[0030] Figure 4c This is a structural diagram of a pixel circuit layer in a display panel in one implementation method;

[0031] Figure 4d This is a schematic diagram illustrating a progressive dark ring appearing on the display panel in one implementation method.

[0032] Figure 4e This is a schematic diagram of the characteristic transfer line of the driving transistor in the display panel at a preset gray level of L64 in one implementation.

[0033] Figure 4f This is a schematic diagram of the characteristic transfer line of the driving transistor in the display panel at a preset gray level of L128 in one implementation method;

[0034] Figure 5 This is a partial structural diagram of a display panel according to some embodiments of the present disclosure;

[0035] Figure 6a This is a partial structural diagram of another display panel according to some embodiments of the present disclosure;

[0036] Figure 6b This is a partial structural diagram of another display panel according to some embodiments of the present disclosure;

[0037] Figure 7 This is a structural diagram of a pixel circuit and a light-emitting device according to some embodiments of the present disclosure;

[0038] Figure 8a This is a top view of some film layers of a display panel according to some embodiments of the present disclosure;

[0039] Figure 8b This is a top view of some of the film layers of a display panel according to some embodiments of the present disclosure;

[0040] Figure 9aThis is a top view of some of the film layers of a display panel according to some embodiments of the present disclosure;

[0041] Figure 9b This is a top view of some of the film layers of a display panel according to some embodiments of the present disclosure;

[0042] Figure 10 This is a top view of some of the film layers of a display panel according to some embodiments of the present disclosure;

[0043] Figure 11 This is a top view of some of the film layers of a display panel according to some embodiments of the present disclosure;

[0044] Figure 12a This is a top view of some of the film layers of a display panel according to some embodiments of the present disclosure;

[0045] Figure 12b This is a top view of some of the film layers of a display panel according to some embodiments of the present disclosure;

[0046] Figure 13 This is a top view of some of the film layers of a display panel according to some embodiments of the present disclosure;

[0047] Figure 14 This is a top view of some of the film layers of a display panel according to some embodiments of the present disclosure;

[0048] Figure 15 This is a top view of some of the film layers of a display panel according to some embodiments of the present disclosure;

[0049] Figure 16 This is a structural diagram of a light-blocking layer and substrate according to some embodiments of the present disclosure;

[0050] Figure 17 This is a structural diagram of another light-blocking layer and substrate according to some embodiments of the present disclosure;

[0051] Figure 18 This is a structural diagram of a pixel circuit layer and a light-blocking layer according to some embodiments of the present disclosure;

[0052] Figure 19 This is a top view of some of the film layers of a display panel according to some embodiments of the present disclosure;

[0053] Figure 20a This is a top view of some of the film layers of a display panel according to some embodiments of the present disclosure;

[0054] Figure 20b This is a top view of some of the film layers of a display panel according to some embodiments of the present disclosure;

[0055] Figure 21 This is a top view of some of the film layers of a display panel according to some embodiments of the present disclosure;

[0056] Figure 22 This is a top view of some of the film layers of a display panel according to some embodiments of the present disclosure;

[0057] Figure 23 This is a top view of some of the film layers of a display panel according to some embodiments of the present disclosure;

[0058] Figure 24 This is a top view of some of the film layers of a display panel according to some embodiments of the present disclosure;

[0059] Figure 25 This is a top view of some of the film layers of a display panel according to some embodiments of the present disclosure;

[0060] Figure 26 This is a top view of some of the film layers of a display panel according to some embodiments of the present disclosure;

[0061] Figure 27 This is a top view of some of the film layers of a display panel according to some embodiments of the present disclosure;

[0062] Figure 28 This is a top view of some of the film layers of a display panel according to some embodiments of the present disclosure;

[0063] Figure 29 This is a top view of some of the film layers of a display panel according to some embodiments of the present disclosure;

[0064] Figure 30 This is a cross-sectional view of a light-blocking layer connected to a first voltage signal line according to some embodiments of the present disclosure. Detailed Implementation

[0065] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0066] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0067] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0068] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0069] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0070] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0071] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0072] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0073] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0074] As used herein, "perpendicular" and "equal" include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity could be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range for approximate equality could be, for example, a difference between the two equalities less than or equal to 5% of either one.

[0075] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0076] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0077] In the circuit structures (e.g., pixel circuits) provided in the embodiments of this disclosure, the transistors used in the circuit structures can be thin film transistors (TFTs), metal oxidized semiconductors (MOSs), or other switching devices with the same characteristics. In the embodiments of this disclosure, thin film transistors are used as an example for illustration.

[0078] In the circuit structure provided in the embodiments of this disclosure, the first terminal of each transistor is one of the source and the drain, and the second terminal of each transistor is the other of the source and the drain. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable; that is, the first and second terminals of the transistors in the embodiments of this disclosure can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first terminal is the source and the second terminal is the drain; for example, when the transistor is an N-type transistor, the first terminal is the drain and the second terminal is the source.

[0079] In the circuit structure provided by the embodiments of this disclosure, nodes such as the first node and the second node do not represent actual existing components, but rather represent the junction points of related couplings in the circuit diagram. In other words, these nodes are equivalent to the junction points of related couplings in the circuit diagram.

[0080] The transistors included in the circuit structures provided in the embodiments of this disclosure may all be N-type transistors, or all may be P-type transistors, or a subset may be N-type transistors and a subset may be P-type transistors. In this disclosure, "effective level" refers to the level that enables the transistor to conduct. Specifically, P-type transistors can conduct under the control of a low-level signal, and N-type transistors can conduct under the control of a high-level signal.

[0081] The following is an illustrative example of the circuit structure provided in the embodiments of this disclosure, in which all transistors are P-type transistors. Some embodiments of this disclosure provide a display panel 100 and a display device 1000, which will be described in detail below.

[0082] Some embodiments of this disclosure provide a display device 1000, such as Figure 1As shown. The display device 1000 can be any display device that displays either moving (e.g., video) or stationary (e.g., still image) text or images. More specifically, the display device of the described embodiment is contemplated for implementation in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0083] In some embodiments, such as Figure 3a As shown, the display device 1000 includes a heat dissipation film 40.

[0084] In some examples, the heat dissipation film 40 is located on the non-display side of the display device 1000.

[0085] For example, the non-display side of the display device 1000 refers to the side opposite to the side of the display screen.

[0086] By adopting the above-mentioned configuration, the heat in the display device 1000 can be dissipated in a timely manner through the heat dissipation film 40, thus preventing the accumulation of heat inside the display device 1000 and affecting the display effect of the display device 1000.

[0087] In some examples, the heat dissipation film 40 may include a protective layer 41, a heat dissipation layer 42, a buffer layer 43, a foam layer 44, a mesh adhesive layer 45, etc., stacked in sequence.

[0088] For example, the material of the protective layer 41 may include a release adhesive. The protective layer 41 can provide a certain degree of protection for the heat dissipation film 40 and the display panel 100 before the optical elements mentioned below are assembled. During the assembly process of the display device 1000, for example before the optical elements are assembled, the protective layer 41 in the heat dissipation film 40 can be peeled off.

[0089] For example, the material of the heat dissipation layer 42 may include copper foil. The copper foil may be self-adhesive copper foil, double-conductive copper foil, single-conductive copper foil, etc. All of the above copper foils have excellent conductivity. On the one hand, the heat in the display panel 100 can be dissipated through the heat dissipation layer 42. On the other hand, the heat dissipation layer 42 can also play the role of electromagnetic shielding and electrostatic discharge for the pixel circuit layer 20 on the side of the substrate 10.

[0090] For example, the material of the buffer layer 43 may include PET (Polyethylene Terephthalate). The buffer layer can buffer and dissipate the impact of external forces on the heat dissipation film 40, preventing damage to the heat dissipation film 40.

[0091] For example, the material of the foam layer 44 may include polyurethane foam, conductive foam, aluminum foil foam, etc. These materials all have excellent thermal conductivity, allowing them to quickly dissipate the heat generated by the display panel 100, preventing heat accumulation from adversely affecting the display panel 100 and causing a decrease in display performance. Furthermore, because the foam layer material is relatively soft, it can protect the display panel 100, thereby absorbing and buffering external forces when they impact the display panel 100, preventing damage to the display panel 100.

[0092] For example, the material of the mesh adhesive layer 45 can be a pressure-sensitive adhesive, which can bond the heat dissipation film 40 to the substrate 10, thereby fixing the heat dissipation film 40 to the substrate 10.

[0093] In some examples, such as Figure 3b As shown, the heat dissipation film 40 has an opening that is positioned opposite to the sub-display area A2.

[0094] It should be noted that the opening of the aforementioned heat dissipation film 40 refers to, for example, Figure 3b As shown, the through-hole is formed in the structure of the heat dissipation film 40 after the protective layer 41 is peeled off. The through-hole penetrates the heat dissipation layer 42, the buffer layer 43, the foam layer 44, and the mesh adhesive layer 45.

[0095] For example, the center of the opening of the heat dissipation film 40 may coincide with the center of the sub-display area A2, and the area of ​​the opening of the heat dissipation film 40 may be greater than or equal to the area of ​​the sub-display area A2.

[0096] In some examples, such as Figure 3b As shown, the display device 1000 also includes an optical element 50.

[0097] For example, the optical element 50 may be a camera, an infrared sensor, or a fingerprint sensor.

[0098] This disclosure uses optical element 50 as an example of a camera for illustration.

[0099] During the operation of the camera, external light can pass through the part of the display device 1000 located in the sub-display area A2 and enter the camera, so that the camera can collect the light and realize the function of taking pictures.

[0100] For example, the orthographic projection of the optical element 50 onto the heat dissipation film 40 is located within the opening of the heat dissipation film 40 and the sub-display area A2.

[0101] For example, the optical element 50 is positioned opposite the opening of the heat dissipation film 40, and the area of ​​the orthographic projection of the optical element 50 onto the heat dissipation film 40 is less than or equal to the area of ​​the opening of the heat dissipation film 40. The optical element 50 is positioned opposite the sub-display area A2, and the area of ​​the orthographic projection of the optical element 50 onto the heat dissipation film 40 is less than or equal to the area of ​​the sub-display area A2.

[0102] Understandably, the heat dissipation film 40 is typically a single, opaque layer. By creating an opening in the heat dissipation film 40, and ensuring that the orthographic projection of the optical element 50 onto the heat dissipation film 40 lies within the opening and the sub-display area A2, external light can pass through the sub-display area A2 without being blocked by the heat dissipation film 40 and can normally reach the optical element 50. This ensures that the optical element 50 collects sufficient light and can function properly.

[0103] For example, such as Figure 3b As shown, the display device 1000 also includes a back film 60 located between the substrate 10 and the heat dissipation film 40.

[0104] For example, the back film 60 can cover the surface of the substrate 10 near the heat dissipation film 40, thereby protecting the substrate 10, pixel circuit layer 20 and light-emitting device 30 and other structures, preventing damage to the above structures and ensuring the normal display of the display panel 100.

[0105] For example, the material of the back film 60 can be a light-transmitting material. Light incident on one side of the back film 60 can penetrate the back film 60 and exit from the other side. In this way, when the optical element 50 of the display panel 100 is working, external light can pass through the sub-display area A2 and the back film 60 of the display panel 100 in sequence and be incident on the optical element 50, so that the optical element 50 can collect enough light, thereby enabling functions such as taking pictures.

[0106] For example, the display device 1000 also includes a frame, a display driver IC (integrated circuit), and other electronic components.

[0107] In some embodiments, such as Figure 1 As shown, the above-mentioned display device 1000 includes: a display panel 100.

[0108] In some embodiments, such as Figure 2 As shown, the display panel 100 has a display area A and a border area F located on at least one side of the display area A.

[0109] For example, the border area F can surround a portion of the display area A; that is, the border area F can be located on one side, two sides, three sides, etc., of the display area A. For example, ... Figure 2 As shown, the border area F can surround the display area A, thus enclosing the display area A.

[0110] In some examples, such as Figure 2 As shown, the display area A of the display panel 100 includes a main display area A1 and a sub-display area A2, with the main display area A1 surrounding at least a portion of the sub-display area A2.

[0111] For example, the main display area A1 can surround a portion of the secondary display area A2. Or, for example... Figure 3a As shown, the main display area A1 can surround the secondary display area A2, thus enclosing the secondary display area A2.

[0112] The shapes of display area A and sub-display area A2 are varied and can be selected according to actual needs.

[0113] For example, the shape of display area A can be rectangular, approximately rectangular, circular, or elliptical. Among them, an approximately rectangular shape is not a rectangle in the strict sense, and its four interior corners can be rounded, or one of its sides can be not a straight line.

[0114] For example, the shape of the secondary display area A2 can also be rectangular, approximately rectangular, circular, or elliptical, etc., and can be set according to actual needs.

[0115] For ease of description, this disclosure uses the circular shape of the sub-display area A2 as an example.

[0116] For example, the light transmittance of the portion of the display panel 100 located in the sub-display area A2 is greater than the light transmittance of the portion of the display panel 100 located in the main display area A1.

[0117] For example, light can pass through the portion of the display panel 100 located in the sub-display area A2 and be emitted from one side of the display panel 100 to the other side of the display panel 100.

[0118] In some examples, such as Figure 3a and Figure 3b As shown, the display panel 100 includes: a substrate 10, a pixel circuit layer 20 located on one side of the substrate 10, and a light-emitting device layer 30.

[0119] For example, the substrate 10 can be a flexible substrate. This flexible substrate can be, for example, a PET substrate, a PEN (Polyethylene naphthalate dimethyl acid glycol ester) substrate, or a PI (Polyimide) substrate. Therefore, the display panel 100 described above is a flexible display panel.

[0120] For example, the substrate 10 is located at least in the display area A.

[0121] For example, the substrate 10 may be located in the display area A of the display panel 100.

[0122] For example, the substrate 10 may be located in the display area A and the border area F of the display panel 100.

[0123] For example, the pixel circuit layer 20 includes a plurality of pixel circuits 21. The light-emitting device layer 30 includes a plurality of light-emitting devices 31.

[0124] For example, the structure of the pixel circuit 21 includes various types, which can be selected and set according to actual needs. For example, the structure of the pixel circuit 21 may include "6T1C", "7T1C", "6T2C" or "7T2C" etc. Here, "T" represents a transistor, and the number before "T" represents the number of transistors, and "C" represents a storage capacitor, and the number before "C" represents the number of storage capacitors.

[0125] This disclosure uses the "7T1C" structure of the pixel circuit 21 as an example for illustration. Among other things, Figure 7 The equivalent circuit diagram of pixel circuit 21 is shown.

[0126] For example, such as Figure 7 As shown, the pixel circuit 21 includes: a first reset transistor T1, a second reset transistor T2, a switching transistor T3, a driving transistor T4, a compensation transistor T5, a first light-emitting control transistor T6, a second light-emitting control transistor T7, and a storage capacitor Cst.

[0127] For example, such as Figure 7As shown, the gate of the first reset transistor T1 is coupled to the reset signal line Reset, the first terminal of the first reset transistor T1 is coupled to the first initial signal line Vinit1, and the second terminal of the first reset transistor T1 is coupled to the fourth node N4, which is also coupled to the second terminal of the compensation transistor T5. The first reset transistor T1 is configured to turn on under the control of the reset signal transmitted by the reset signal line Reset, transmitting the first initial signal received at the first initial signal line Vinit1 to the fourth node N4, thus resetting the fourth node N4.

[0128] For example, such as Figure 7 As shown, the gate of the second reset transistor T2 is coupled to the first scan signal line Gate1, the first terminal of the second reset transistor T2 is coupled to the second initial signal line Vinit2, and the second terminal of the second reset transistor T2 is coupled to the first node N1, that is, coupled to the light-emitting device 31. The second reset transistor T2 is configured to be turned on under the control of the first scan signal transmitted on the first scan signal line Gate1, transmitting the second initial signal received at the second initial signal line Vinit2 to the first node N1, thereby resetting the first node N1.

[0129] For example, such as Figure 7 As shown, the gate of switching transistor T3 is coupled to the second scan signal line Gate2, the first terminal of switching transistor T3 is coupled to the data line Data, and the second terminal of switching transistor T3 is coupled to the second node N2, which is also coupled to the first terminal of driving transistor T4. Switching transistor T3 is configured to conduct under the control of the second scan signal transmitted through the second scan signal line Gate2, transmitting the data signal received at the data line Data to the second node N2.

[0130] For example, such as Figure 7 As shown, the gate of driving transistor T4 is coupled to the fourth node N4, the first terminal of driving transistor T4 is coupled to the second node N2, and the second terminal of driving transistor T4 is coupled to the third node N3. Driving transistor T4 is configured to conduct under the control of the voltage of the fourth node N4, transmitting a signal (e.g., a data signal) from the second node N2 to the third node N3.

[0131] For example, such as Figure 7As shown, the gate of compensation transistor T5 is coupled to the second scan signal line Gate2, the first terminal of compensation transistor T5 is coupled to the third node N3, which is also coupled to the second terminal of driving transistor T4, and the second terminal of compensation transistor T5 is coupled to the fourth node N4, which is also coupled to the gate of driving transistor T4. Compensation transistor T5 is configured to be turned on under the control of the second scan signal transmitted through the second scan signal line Gate2, transmitting the electrical signal (e.g., a data signal) from the third node N3 to the fourth node N4.

[0132] For example, such as Figure 7 As shown, the gate of the first light-emitting control transistor T6 is coupled to the enable signal line EM, the first terminal of the first light-emitting control transistor T6 is coupled to the voltage signal line VDD, and the second terminal of the first light-emitting control transistor T6 is coupled to the second node N2. The first light-emitting control transistor T6 is configured to conduct under the control of the enable signal transmitted through the enable signal line EM, transmitting the voltage signal received at the first voltage signal line VDD to the second node N2.

[0133] For example, such as Figure 7 As shown, the gate of the second light-emitting control transistor T7 is coupled to the enable signal line EM, the first terminal of the second light-emitting control transistor T7 is coupled to the third node N3, and the second terminal of the second light-emitting control transistor T7 is coupled to the first node N1. The second light-emitting control transistor T7 is configured to conduct under the control of the enable signal transmitted through the enable signal line EM, transmitting an electrical signal (e.g., a voltage signal) from the third node N3 to the first node N1.

[0134] For example, such as Figure 7 As shown, the first terminal of the storage capacitor Cst is coupled to the fourth node N4, and the second terminal of the storage capacitor Cst is coupled to the first voltage signal line VDD.

[0135] For example, the light-emitting device 31 may include an anode layer, a light-emitting functional layer, a cathode layer, etc., stacked sequentially. The light-emitting functional layer may include a light-emitting layer. Optionally, the light-emitting functional layer may further include at least one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.

[0136] For example, the pixel driving circuit can be coupled to the anode layer of the light-emitting device.

[0137] By applying a common voltage signal to the cathode layer of the light-emitting device 31 and applying a driving signal to the anode layer of the light-emitting device 31 using the corresponding pixel circuit 21, an electric field can be formed between the anode layer and the cathode layer of the light-emitting device 31. This electric field can drive different charge carriers (i.e., holes and electrons) to recombine in the light-emitting layer, thereby making the light-emitting device 31 emit light.

[0138] Optionally, the operation of the pixel circuit 21 includes a reset stage, a data writing and compensation stage, and a light emission stage performed sequentially.

[0139] For example, during the reset phase, under the control of the reset signal, the first reset transistor T1 is turned on, transmitting the first initial signal to the fourth node N4 to reset the fourth node N4. Since the fourth node N4 is coupled to the first terminal of the storage capacitor Cst, the gate of the driving transistor T4, and the second terminal of the compensation transistor T5, resetting the fourth node N4 can simultaneously reset the first terminal of the storage capacitor Cst, the gate of the driving transistor T4, and the second terminal of the compensation transistor T5. The driving transistor T4 can be turned on under the control of the first initial signal.

[0140] For example, during the data writing and compensation phase, the second reset transistor T2 is turned on under the control of the first scan signal, while the switching transistor T3 and the compensation transistor T5 are turned on under the control of the second scan signal. The second reset transistor T2 transmits the second start signal to the first node N1 to reset the first node N1. Since the first node N1 is coupled to the anode of the light-emitting device 31, the anode of the light-emitting device 31 can be reset simultaneously when the first node N1 is reset. The switching transistor T3 transmits the data signal to the second node N2, and the driving transistor T4 transmits the data signal from the second node N2 to the third node N3. The compensation transistor T5 transmits the data signal from the third node N3 to the fourth node N4 to charge the driving transistor T4 until the threshold voltage of the driving transistor T4 is compensated.

[0141] For example, during the light-emitting phase, the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are simultaneously turned on under the control of the enable signal. The first light-emitting control transistor T6 transmits the voltage signal to the second node N2. The driving transistor T4 transmits the voltage signal from the second node N2 to the third node N3. The second light-emitting control transistor T7 transmits the voltage signal from the third node N3 to the first node N1.

[0142] For example, under the action of the driving signal (such as the voltage signal mentioned above) from the first node N1 and the common voltage signal from the common voltage line VSS, a driving current can be generated, and the light-emitting device 31 emits light under the action of the driving current.

[0143] For example, the aforementioned multiple pixel circuits 21 and multiple light-emitting devices 31 can be coupled one-to-one. Alternatively, one pixel circuit 21 can be coupled to multiple light-emitting devices 31, or multiple pixel circuits 21 can be coupled to one light-emitting device 31. In the display panel 100, each light-emitting device 31 can emit light under the driving action of its corresponding pixel circuit 21. The light emitted by multiple light-emitting devices 31 cooperates with each other, thereby enabling the display panel 100 to perform its display function.

[0144] The present disclosure will now illustrate the structure of the display panel 100 by taking the example of a pixel circuit 21 coupled to a light-emitting device 31.

[0145] It should be noted that, Figure 3a and Figure 3b It only illustrates the positional relationship between the pixel circuit layer and the light-emitting device layer, as well as the positional relationship between the pixel circuit and the light-emitting device. It does not illustrate the specific film layer relationships and connections between the pixel circuit and the light-emitting device. Therefore... Figure 3a and Figure 3b It does not impose restrictions on the specific film layer relationships and connection relationships between pixel circuits and light-emitting devices.

[0146] For example, such as Figure 5 and Figure 6a As shown, the aforementioned pixel circuits are located in areas other than the sub-display area A2. The aforementioned light-emitting devices 31 are located in display area A of the display panel 100, with some of these devices located in the main display area and others in the sub-display area. The light-emitting device 31 located in the main display area A1 is a first light-emitting device 31a, and the light-emitting device 31 located in the sub-display area A2 is a second light-emitting device 31b. Pixel circuits 21 coupled to the multiple first light-emitting devices 31a are located in the main display area A1, and pixel circuits 21 coupled to the multiple second light-emitting devices 31b are located in the main display area A1, the bezel area F, or the sub-display area A2. Thus, light-emitting devices 31 emit light in all display areas A of the display panel 100 under the driving action of the pixel circuits 21, enabling the display panel 100 to achieve a full-screen display.

[0147] In one implementation, such as Figure 4a As shown, in a display device, in order for the camera to function properly, a certain amount of external light needs to pass through the FDC (Full Display with Camera) area to reach the camera, so that the camera can obtain enough light to perform the photo-taking function (here, the FDC area refers to the area opposite the camera along the thickness direction of the display device). Therefore, the part of the full-screen display device located in the FDC area is light-transmitting, and the FDC area corresponds, for example, to the aforementioned sub-display area A2.

[0148] However, in full-screen display devices, external light and light emitted by the light-emitting device, after a series of refractions and / or reflections, reach the interface between the back film and the air (i.e., the lower surface of the back film). Since the refractive index of the back film material is greater than that of air, when the incident angle of the light rays incident on this interface satisfies the condition for total internal reflection—for example, when the incident angle is greater than the critical angle—the light rays will undergo total internal reflection at the interface and be reflected to the active layer of the transistors in the pixel driving circuit located in the peripheral area of ​​the FDC region. This causes a drift in the threshold voltage of the transistors in the pixel driving circuit. Taking the driving transistor in the pixel driving circuit as an example, the aforementioned light will cause the threshold voltage of the driving transistor to drift, which in turn makes it easier for the driving current supplied by the driving transistor to the light-emitting device to decrease during the light-emitting stage of the pixel driving circuit. This, in turn, reduces the brightness of the display image in the peripheral area of ​​the FDC region, resulting in phenomena such as… Figure 4d The phenomenon shown is a "progressive dark ring". This phenomenon generally appears 5 minutes after the display device starts displaying the image and gradually disappears about 6 hours after the display device is turned off.

[0149] It should be noted that, firstly, as Figure 4b As shown, the incident angle of the light rays incident on the interface between the back film and air is set to α, the refractive index of the back film material is n1 = 1.45, the refractive index of air is n2 = 1, and the refraction angle is β. According to the law of refraction, the parameters satisfy n1*sinα = n2*sinβ. When the refraction angle β is 90°, that is, when the light rays undergo total internal reflection at the interface, the incident angle α = 44°. That is, the critical angle is 44°. When the incident angle α is greater than or equal to 44°, the light rays undergo total internal reflection at the interface. After a series of refractions and / or reflections, when the incident angle of the light rays incident on the interface between the back film and air is greater than or equal to 44°, the light rays will undergo total internal reflection and then be incident on the active layer of the driving transistor located in the peripheral area of ​​the FDC region. This causes the threshold voltage of the driving transistor to drift, and thus, during the light emission stage, it is easy to reduce the driving current provided by the driving transistor to the light emission device, thereby reducing the brightness of the display screen in the peripheral area of ​​the FDC region, resulting in a phenomenon such as... Figure 4d The phenomenon of "progressive dark rings" is shown.

[0150] Secondly, such as Figure 4b and Figure 4cAs shown, the distance between the lower surface of the active layer of the transistor in the pixel driving circuit and the lower surface of the back film (i.e., the interface between the back film and air) is set as d. The normal NL of the light rays incident on the interface between the back film and air is set to be located at the boundary line of the FDC region. The maximum distance from the boundary line of the FDC region to the area that the light rays can illuminate after total internal reflection at the interface between the back film and air is set as W. Taking d = 11 μm as an example, according to tanα = W / d, we can get W = 96 μm. That is to say, after a series of refractions and / or reflections, when the incident angle of the light rays incident on the interface between the back film and air is greater than or equal to 44°, the light rays will be incident on the peripheral area surrounding the FDC region after total internal reflection. The peripheral area of ​​the FDC region is the area within a distance of 96 μm from the boundary line of the FDC region. The active layers of the driving transistors in the surrounding area of ​​the FDC region are all affected by this light, causing the threshold voltage of the driving transistors to drift. Consequently, during the light-emitting stage of the pixel driving circuit, the driving current supplied by the driving transistors to the light-emitting device is easily reduced, resulting in a decrease in the brightness of the displayed image in the surrounding area of ​​the FDC region, as shown in the image. Figure 4d The phenomenon of "progressive dark rings" is shown.

[0151] Simulation tests were performed on the driving transistors in the pixel driving circuits corresponding to the aforementioned "progressive dark rings". The data obtained were the driving current I and display brightness corresponding to different threshold voltages Vth of the driving transistors under the same preset gray level, as well as the driving current I and display brightness corresponding to different preset gray levels L64, L128, and L255. The specific data are shown in Table 1.

[0152] Table 1

[0153]

[0154] Taking a preset grayscale of L64 as an example, referring to Table 1, as the threshold voltage Vth of the driving transistor drifts from -2.7 to -2.1, the driving current provided by the driving transistor changes from 2.092 to 1.54. The percentage change in driving current at this preset grayscale changes from -4.80% to -5.15%, and the actual display brightness changes from 22.72 to 16.72. It can be seen that, under the same preset grayscale, the threshold voltage of the driving transistor drifts due to illumination of the active layer, which in turn causes a change in the actual display brightness of the light-emitting device (i.e., a decrease in display brightness), resulting in a brightness difference perceptible to the human eye, i.e., the "progressive dark ring" phenomenon mentioned above.

[0155] With a preset grayscale of L64 and threshold voltages of the driving transistor of -2.7, -2.6, -2.5, -2.4, -2.3, -2.2, and -2.1, simulation tests were performed on the gate voltage Vg and driving current I of the driving transistor. The simulation results were plotted as the corresponding characteristic curve Vg-I, as shown below. Figure 4e As shown. With a preset grayscale of L128 and threshold voltages of the driving transistor at -2.7, -2.6, -2.5, -2.4, -2.3, -2.2, and -2.1, simulation tests were performed on the gate voltage Vg and driving current I of the driving transistor. The simulation results were plotted as the corresponding characteristic curve Vg-I, as shown. Figure 4f As shown, under the same preset grayscale, with different threshold voltages of the driving transistor and the same gate voltage Vg, the corresponding driving currents are different. The larger the threshold voltage drift of the driving transistor, the smaller the corresponding driving current, and the lower the display brightness of the light-emitting device, i.e., the darker the displayed image. Under different preset grayscales, the drift of the threshold voltage of the driving transistor can cause a significant change in its corresponding driving current, thereby reducing the actual luminous brightness of the light-emitting device and resulting in the "progressive dark ring" phenomenon.

[0156] Based on this, such as Figure 5 As shown, in some embodiments of the present disclosure, the display panel 100 has a pixel circuit layer 20 located at least in the display area A, and the multiple pixel circuits 21 in the pixel circuit layer 20 include multiple surrounding pixel circuits 21a.

[0157] In some examples, the pixel circuit layer 20 may be entirely located in display area A. For instance, the pixel circuit layer 20 may be entirely located in the main display area A1. Alternatively, the pixel circuit layer 20 may be partially located in the main display area A1 and partially located in the sub-display area A2.

[0158] In other examples, the pixel circuit layer 20 may be located partly in the display area A and partly in other areas of the display panel 100, such as the border area F.

[0159] For example, the multiple pixel circuits 21 located in the main display area A1 can all be surrounding pixel circuits 21a. Alternatively, the multiple pixel circuits 21 located in the main display area A1 can also include multiple surrounding pixel circuits 21a and multiple other pixel circuits. For details on other pixel circuits, please refer to the description below, which will not be repeated here.

[0160] In some examples, the aforementioned multiple surrounding pixel circuits 21a are arranged in an array.

[0161] For example, multiple surrounding pixel circuits 21a are arranged in multiple columns along the first direction X and in multiple rows along the second direction Y.

[0162] For example, the angle between the first direction X and the second direction Y can be 80°, 85°, 90°, 95° or 100°, etc.

[0163] For ease of explanation, this disclosure uses an example where the angle between the first direction X and the second direction Y is 90°.

[0164] In some examples, such as Figure 5 and Figure 6a As shown, multiple surrounding pixel circuits 21a are located in the main display area A1 of the display panel 100.

[0165] Taking an example where all the pixel circuits 21 located in the main display area A1 are surrounding pixel circuits 21a. These surrounding pixel circuits 21a include, for example, multiple first surrounding pixel circuits 212a and multiple second surrounding pixel circuits 214a. Among these surrounding pixel circuits 21a, the first surrounding pixel circuits 212a are coupled to the first light-emitting device 31a located in the main display area A1, and the second surrounding pixel circuits 214a are coupled to the second light-emitting device 31b located in the sub-display area A2.

[0166] To clearly illustrate the connection relationship between the second surrounding pixel circuit 214a and the second light-emitting device 31b, Figure 5 Only a portion of the connection between the second surrounding pixel circuit 214a and the corresponding second light-emitting device 31b is shown.

[0167] For example, all of the aforementioned surrounding pixel circuits 21a may be located in the main display area A1 of the display panel 100. For instance... Figure 5 As shown, the first surrounding pixel circuit 212a and the second surrounding pixel circuit 214a can be arranged in multiple columns along the first direction X and in multiple rows along the second direction Y. At least one column of first surrounding pixel circuit 212a can be arranged between two adjacent columns of second surrounding pixel circuit 214a. In this way, it is possible to avoid setting the pixel circuit 21 coupled to the second light-emitting device 31b in the bezel area F of the display panel 100, thereby reducing the width of the bezel area F in the display panel 100 and improving the screen ratio of the display panel 100 and the display device 1000, which is beneficial to realizing the full-screen display of the display panel 100 and the display device 1000.

[0168] For example, the aforementioned plurality of surrounding pixel circuits 21a can surround a portion of the sub-display area A2. Alternatively, the aforementioned plurality of surrounding pixel circuits 21a can completely surround the sub-display area A2.

[0169] In some embodiments, such as Figure 3b As shown, the display panel 100 also includes a light-blocking layer 70 located between the substrate 10 and the pixel circuit layer 20.

[0170] For example, the light-blocking layer 70 may be located in the main display area A1 of the display panel 100.

[0171] For example, the light-blocking layer 70 can reflect or absorb light incident on its surface, so that the light cannot pass through the light-blocking layer 70 from one side and exit from the other side of the light-blocking layer 70.

[0172] In some embodiments, the orthographic projection of the light-blocking layer 70 onto the substrate 10 at least partially overlaps with the orthographic projection of the plurality of surrounding pixel circuits 21a onto the substrate 10.

[0173] For example, such as Figure 8a and Figure 8b As shown, a portion of the orthographic projection of the surrounding pixel circuit 21a onto the substrate 10 coincides with a portion of the orthographic projection of the light-blocking layer 70 onto the substrate 10. In other words, a portion of the surrounding pixel circuit 21a is disposed corresponding to the light-blocking layer 70, and a portion of the orthographic projection of the surrounding pixel circuit 21a onto the substrate 10 coincides with at least a portion of the orthographic projection of the light-blocking layer 70 onto the substrate 10.

[0174] For example, a portion of the orthographic projection of the pixel circuit 21a onto the substrate 10 includes the orthographic projection of the active layer surrounding at least one transistor in the pixel circuit 21a onto the substrate 10.

[0175] With the above-described configuration, after a series of refractions and / or reflections, the light from the external light source and the light emitted by the light-emitting device enters the interface between the back film 60 and the air. Part of the light undergoes total internal reflection at this interface and then travels into the interior of the display panel 100. This portion of the light that travels into the interior of the display panel 100 after total internal reflection is blocked by the light-blocking layer 70. This prevents the light from illuminating the portion of the structure corresponding to the light-blocking layer 70 in the surrounding pixel circuit 21a (e.g., the active layer of at least one transistor in the surrounding pixel circuit 21a), thus mitigating the threshold voltage drift problem of the surrounding pixel circuit 21a. Consequently, it can alleviate the phenomenon of reduced driving current in the surrounding pixel circuit 21a, reduce the decrease in display brightness, and mitigate the "progressive dark ring" phenomenon in the display panel 100 and the display device 1000.

[0176] For example, such as Figure 9a and Figure 9b As shown, the orthographic projection of the surrounding pixel circuit 21a on the substrate 10 is located within the range of the orthographic projection of the light-blocking layer 70 on the substrate 10. That is, the surrounding pixel circuit 21a is disposed in a manner corresponding to the light-blocking layer 70, and at least a portion of the orthographic projection of the surrounding pixel circuit 21a on the substrate 10 coincides with at least a portion of the orthographic projection of the light-blocking layer 70 on the substrate 10.

[0177] For example, the orthographic projection of the surrounding pixel circuit 21a onto the substrate 10 includes the orthographic projection of the plurality of transistors included in the surrounding pixel circuit 21a onto the substrate 10. In this case, the light-blocking layer 70 can block the area containing all the transistors surrounding the pixel circuit 21a, such as... Figure 9a As shown, this simplifies the manufacturing process of the light-blocking layer 70.

[0178] For example, the orthographic projection of the pixel circuit 21a onto the substrate 10 includes the orthographic projection of the active layer surrounding the plurality of transistors included in the pixel circuit 21a onto the substrate 10. In this case, the light-blocking layer 70 can be patterned, such as... Figure 9b As shown, only the active layer of each transistor in the surrounding pixel circuit 21a is masked.

[0179] With the above-described configuration, after a series of refractions and / or reflections, the light emitted by the external light source and the light-emitting device 31 enters the interface between the back film 60 and the air. Part of the light undergoes total internal reflection at this interface and then travels into the interior of the display panel 100. This portion of the light that travels into the interior of the display panel 100 after total internal reflection is blocked by the light-blocking layer 70. This prevents the light from illuminating the transistors in the surrounding pixel circuit 21a, mitigating the threshold voltage drift problem of each surrounding pixel circuit 21a. Consequently, it can mitigate or even eliminate the phenomenon of reduced driving current in the surrounding pixel circuit 21a, thus mitigating or even eliminating the reduction in display brightness. Furthermore, it can mitigate or even eliminate the phenomenon of a "progressive dark ring" appearing in the display panel 100 and the display device 1000.

[0180] For example, such as Figure 10 As shown, the orthographic projection of the plurality of surrounding pixel circuits 21a in the pixel circuit layer 20 onto the substrate 10 is located within the range of the orthographic projection of the light-blocking layer 70 onto the substrate 10.

[0181] By adopting the above-mentioned arrangement, the light-blocking layer 70 can block the portion of light that is incident on the interior of the display panel 100 after total internal reflection, preventing it from illuminating the multiple surrounding pixel circuits 21a. This can alleviate the threshold voltage drift problem of the surrounding pixel circuits 21a, alleviate or even eliminate the phenomenon of reduced driving current of the surrounding pixel circuits 21a, thereby alleviating or even eliminating the phenomenon of reduced display brightness, and further alleviating or even eliminating the phenomenon of "progressive dark ring" in the display panel 100 and the display device 1000.

[0182] In some examples, such as Figure 11 and Figure 12aAs shown, the light-blocking layer 70 includes a plurality of light-blocking patterns 71. At least a portion of the orthographic projection of the pixel circuit 21a onto the substrate 10 is located within the range of the orthographic projection of the light-blocking pattern 71 onto the substrate 10.

[0183] For example, a portion or all of a surrounding pixel circuit 21a is projected onto the substrate 10 in orthogonal projection, which is within the range of a light-blocking pattern 71 projected onto the substrate 10 in orthogonal projection.

[0184] For example, the orthographic projection of a portion of a transistor in a surrounding pixel circuit 21a onto the substrate 10 lies within the range of the orthographic projection of a light-blocking pattern 71 onto the substrate 10. Similarly, the orthographic projection of a single transistor in a surrounding pixel circuit 21a onto the substrate 10 lies within the range of the orthographic projection of a light-blocking pattern 71 onto the substrate 10. Furthermore, the orthographic projections of portions of multiple transistors in a surrounding pixel circuit 21a onto the substrate 10 lie within the range of the orthographic projection of a light-blocking pattern 71 onto the substrate 10. Finally, the orthographic projections of all transistors in a surrounding pixel circuit 21a onto the substrate 10 lie within the range of the orthographic projection of a light-blocking pattern 71 onto the substrate 10.

[0185] For example, the shape of the light-blocking pattern 71 can be varied and can be set according to the actual situation.

[0186] For example, the shape of the light-blocking pattern 71 can be a polygon or a polygonal shape, etc.

[0187] For example, there is a one-to-one correspondence between multiple light-blocking patterns 71 and multiple surrounding pixel circuits 21a. That is, each light-blocking pattern 71 corresponds to one surrounding pixel circuit 21a. At least a portion of one light-blocking pattern 71 and one surrounding pixel circuit 21a are arranged facing each other.

[0188] Since multiple surrounding pixel circuits 21a surround the sub-display area A2, and multiple light-blocking patterns 71 in the light-blocking layer 70 are correspondingly arranged with the multiple surrounding pixel circuits 21a, the multiple light-blocking patterns 71 in the light-blocking layer 70 are arranged around the sub-display area A2.

[0189] In some embodiments, the surrounding pixel circuit 21a may include a driving transistor T4.

[0190] In some examples, such as Figure 8a As shown, the orthographic projection of the active layer of the driving transistor T4 onto the substrate 10 lies within the range of the orthographic projection of the light-blocking pattern 71 onto the substrate 10. Here, a portion surrounding the pixel circuit 21a refers, for example, to the active layer of the driving transistor T4.

[0191] For example, the orthographic projection boundary line of the active layer of the driving transistor T4 on the substrate 10 is located within the orthographic projection boundary line of the light-blocking pattern 71 on the substrate 10. Alternatively, the orthographic projection boundary line of the active layer of the driving transistor T4 on the substrate 10 at least partially coincides with the orthographic projection boundary line of the light-blocking pattern 71 on the substrate 10.

[0192] With the above-described configuration, after a series of refractions and / or reflections, the light emitted by the external light source and the light-emitting device 31 enters the interface between the back film 60 and the air. Part of the light undergoes total internal reflection at this interface and then travels into the interior of the display panel 100. Before this portion of light, after total internal reflection, enters the active layer of the driving transistor T4 in at least one surrounding pixel circuit 21a, it is blocked by the light-blocking pattern 71 in the light-blocking layer 70. This prevents the light from illuminating the active layer of the driving transistor T4 in the at least one surrounding pixel circuit 21a. This mitigates the threshold voltage drift of the driving transistor T4, reduces the decrease in the driving current of the surrounding pixel circuit 21a, and consequently reduces the decrease in display brightness, thus mitigating the "progressive dark ring" phenomenon in the display panel 100 and the display device 1000.

[0193] In some embodiments, such as Figure 8b As shown, the surrounding pixel circuit 21a also includes a compensation transistor T5 coupled to the driving transistor T4.

[0194] In some examples, such as Figure 8b As shown, the orthographic projection of the active layer of the compensation transistor T5 onto the substrate 10 is located within the range of the orthographic projection of the light-blocking pattern 71 onto the substrate 10. At this time, the portion surrounding the pixel circuit 21a refers, for example, to the active layer of the driving transistor T4 and the active layer of the compensation transistor T5.

[0195] For example, the orthographic projection of the active layer of the compensation transistor T5 onto the substrate 10 lies within the boundary line of the orthographic projection of the light-blocking pattern onto the substrate 10. Alternatively, the boundary line of the orthographic projection of the active layer of the compensation transistor T5 onto the substrate 10 at least partially coincides with the boundary line of the orthographic projection of the light-blocking pattern onto the substrate 10.

[0196] With the above-described configuration, after a series of refractions and / or reflections, the light emitted by the external light source and the light-emitting device 31 enters the interface between the back film 60 and the air. Part of the light undergoes total internal reflection at this interface and then travels into the interior of the display panel 100. Before this portion of light, after total internal reflection, enters the active layer of the driving transistor T4 and the compensation transistor T5 in at least one surrounding pixel circuit 21a, it is blocked by the light-blocking pattern 71 in the light-blocking layer 70. This prevents the light from illuminating the active layers of one or more driving transistors T4 and the compensation transistor T5 surrounding pixel circuit 21a, thus mitigating the drift of the threshold voltage of these transistors. This, in turn, mitigates the decrease in driving current of the surrounding pixel circuit 21a, reduces the decrease in display brightness, and further mitigates the "progressive dark ring" phenomenon in the display panel 100 and the display device 1000.

[0197] For example, the active layers of the driving transistor T4 and the compensation transistor T5 in the same surrounding pixel circuit 21a can be correspondingly arranged with the same light-blocking pattern 71. That is, the active layers of the driving transistor T4 and the compensation transistor T5 in the same surrounding pixel circuit 21a are located within the range of the orthogonal projection of a light-blocking pattern 71 onto the substrate 10.

[0198] It should be noted that in one implementation, the threshold voltages of the driving transistor and the compensation transistor in the pixel driving circuit drift under the influence of light. In this case, during the data writing and compensation stages, the data signal transmitted by the compensation transistor will not be able to effectively compensate for the threshold voltage of the driving transistor. For example, the voltage of the fourth node will be too high after compensation, which will result in insufficient conduction of the driving transistor. Consequently, the driving current generated by the driving transistor will be small during the light emission stage, which will reduce the display brightness of the light-emitting device and cause the display panel and display device to exhibit a "progressive dark ring" phenomenon.

[0199] In this disclosure, the above-mentioned arrangement is adopted, and the orthographic projections of the active layer of the driving transistor T4 and the active layer of the compensation transistor T5 on the substrate 10 are located within the range of the orthographic projection of the light-blocking pattern 71 on the substrate 10. Thus, after a series of refractions and / or reflections, the light emitted by the external light source and the light source are incident on the interface between the back film 60 and the air, some of the light undergoes total internal reflection at the interface and then shines into the interior of the display panel 100. The portion of light that has undergone total internal reflection will be blocked by the light-blocking pattern 71 in the light-blocking layer 70 before it enters the active layer of the driving transistor T4 and the active layer of the compensation transistor T5 in at least one surrounding pixel circuit 21a. This prevents the light from illuminating the active layers of the driving transistor T4 and the compensation transistor T5 in one or more surrounding pixel circuits 21a, thereby mitigating the drift of the threshold voltage of the driving transistor T4 and the compensation transistor T5. This allows the compensation transistor T5 to effectively compensate for the threshold voltage of the driving transistor T4, thereby mitigating the decrease in the driving current of the surrounding pixel circuit 21a, thus mitigating the decrease in display brightness, and further mitigating the "progressive dark ring" phenomenon in the display panel 100 and the display device 1000.

[0200] It is understood that the structure of the light-blocking layer 70 can be varied, and the light-blocking pattern 71 in the light-blocking layer 70 can be set in various ways, which can be selected according to actual needs.

[0201] In some embodiments, such as Figure 11 As shown, the multiple light-blocking patterns 71 in the light-blocking layer can be independent of each other and not connected to each other.

[0202] For example, the multiple light-blocking patterns 71 in the light-blocking layer 70 can all be unconnected light-blocking patterns 71.

[0203] In other embodiments, such as Figure 13 As shown, the light-blocking layer 70 also includes at least one connecting pattern 72. Two adjacent light-blocking patterns 71 are connected to each other through the connecting pattern 72.

[0204] For example, the connecting pattern 72 can be a strip pattern extending in a certain direction, connecting two adjacent light-blocking patterns 71 together.

[0205] There are various ways to connect the multiple light-blocking patterns 71 in the light-blocking layer 70, which can be set according to the actual situation. This disclosure does not impose any restrictions on this.

[0206] For example, the multiple light-blocking patterns 71 in the light-blocking layer 70 can all be two adjacent light-blocking patterns 71 connected to each other, or they can all be multiple light-blocking patterns 71 connected in sequence. Alternatively, among the multiple light-blocking patterns 71 in the light-blocking layer 70, some light-blocking patterns 71 can be adjacent light-blocking patterns 71 that are not connected, while the remaining light-blocking patterns are adjacent light-blocking patterns 71 that are connected.

[0207] In some examples, in a portion of the surrounding pixel circuit 21a located on the same side of the sub-display area A2, at least two adjacent surrounding pixel circuits 21a along the first direction X are connected to each other, corresponding to light-blocking patterns 71.

[0208] For example, such as Figure 13 As shown, the outer contours of the connected light-blocking patterns 71 can extend along the first direction X. All the connected light-blocking patterns 71 can be arranged in multiple rows.

[0209] For example, in the portion of the surrounding pixel circuits 21a located on opposite sides of the sub-display area A2, the light-blocking patterns 71 corresponding to two adjacent surrounding pixel circuits 21a along the first direction X are not connected. That is, in the same row of light-blocking patterns, two adjacent light-blocking patterns 71 located on opposite sides of the sub-display area A2 will not pass through the sub-display area A2 to connect. In this way, the light-blocking patterns 71 can avoid adversely affecting the light transmittance of the sub-display area A2, thus avoiding reducing the light transmittance of the sub-display area A2. This allows the optical element 50 located in the sub-display area A2 to collect sufficient light, thereby enabling the display panel 100 and the display device 1000 to achieve better photographic results.

[0210] In other examples, in a portion of the surrounding pixel circuit 21a located on the same side of the sub-display area A2, at least two adjacent surrounding pixel circuits 21a along the second direction Y have their corresponding light-blocking patterns 71 connected.

[0211] For example, such as Figure 12b As shown, the outer contours of the connected light-blocking patterns 71 can extend along the second direction Y. All the connected light-blocking patterns 71 can be arranged in multiple columns.

[0212] For example, in the portion of the surrounding pixel circuits 21a located on opposite sides of the sub-display area A2, the light-blocking patterns 71 corresponding to two adjacent surrounding pixel circuits 21a along the second direction Y are not connected. That is, in the same column of light-blocking patterns, two adjacent light-blocking patterns 71 located on opposite sides of the sub-display area A2 will not be connected along the second direction Y through the sub-display area A2. In this way, the light transmittance of the sub-display area A2 can be avoided, and the light transmittance of the sub-display area A2 can be prevented from decreasing. As a result, the optical element 50 located in the sub-display area A2 can collect sufficient light, and the display panel 100 and the display device 1000 can achieve better photographic results.

[0213] In some other examples, such as Figure 14 and Figure 15 As shown, at least four of the multiple light-blocking patterns 71 included in the light-blocking layer 70 can be interconnected in both the first direction X and the second direction Y by connecting patterns 72.

[0214] In some other examples, such as Figure 16 As shown, the multiple light-blocking patterns 71 included in the light-blocking layer 71 are connected and form an integral structure. The light-blocking layer 70 surrounds the sub-display area A2.

[0215] For example, "integrated structure" refers to multiple connected patterns arranged on the same layer, and the two patterns are continuous and not separated.

[0216] For example, among the plurality of light-blocking patterns 71 described above, some of the connected light-blocking patterns 71 may be arranged sequentially along a first direction X, and / or, some of the connected light-blocking patterns 71 may extend along a second direction Y, and / or, the remaining connected light-blocking patterns 71 may extend along any direction other than the first and second directions. The overall outline formed by all the connected light-blocking patterns 71 may surround at least a portion of the sub-display area A2.

[0217] Optionally, the light-blocking pattern 71 in the light-blocking layer 70 can be a single, integral graphic, corresponding to the surrounding pixel circuitry 21a in the display panel 100. This integral graphic means that, except for the area located in the sub-display area A2, there are no cutout structures in the remaining areas. This simplifies the manufacturing process of the light-blocking layer 70 in the display panel 100 while improving the light-blocking effect of the light-blocking layer 70 on the light incident on the pixel circuitry layer 20.

[0218] Optionally, the light-blocking pattern 71 in the light-blocking layer 70 can be a single, integral graphic. This integral graphic, except for the area located in the sub-display area A2 which is cut out, can also have cut-out structures in other areas, only blocking a portion of the pixel circuitry 21, such as the area where the active layer is located. This reduces the amount of material used in the light-blocking layer 70.

[0219] In some other examples, such as Figure 17 As shown, the light-blocking layer 70 includes at least two concentrically arranged light-blocking rings. The light-blocking rings include a plurality of connected light-blocking patterns, and the light-blocking rings surround at least a portion of the sub-display area A2.

[0220] For example, the center of the multiple light-blocking rings may coincide with the center of the sub-display area A2.

[0221] For example, the light-blocking ring can be a closed shape, such as a circle, ellipse, rectangle, etc. In this case, the light-blocking ring can surround the entire area of ​​the sub-display area A2.

[0222] For example, the light-blocking ring can also be a non-closed shape, such as a portion of a circle or rectangle. In this case, the light-blocking ring can surround a portion of the sub-display area A2.

[0223] For ease of description, this disclosure uses a closed circle as an example to illustrate the concept.

[0224] For example, the light-blocking layer 70 may include two or more light-blocking rings arranged concentrically.

[0225] By adopting the above-described arrangement, external light and light emitted from the light-emitting device, after a series of refractions and / or reflections, enter the interface between the back film 60 and the air, and some of the light is emitted after total internal reflection at the interface. The portion of the light emitted after total internal reflection is blocked by the light-blocking ring in the light-blocking layer 70, which can prevent it from illuminating at least a portion of the structure of the surrounding pixel circuit 21a corresponding to the light-blocking ring. This can alleviate the threshold voltage drift problem of the surrounding pixel circuit 21a, thus alleviating the phenomenon of reduced driving current of the surrounding pixel circuit, and further alleviating the phenomenon of reduced display brightness in the area surrounding the sub-display area A2. In addition, it can further alleviate the phenomenon of "progressive dark ring" in the display panel 100 and the display device 1000.

[0226] Furthermore, as mentioned above, when the refractive index of the back film 60 material is 1.45 and the distance from the pixel circuit layer 20 to the interface between the back film and the air is 11 μm, the difference between the outer diameter of the largest light-blocking ring and the inner diameter of the smallest light-blocking ring in the two or more concentrically arranged light-blocking rings included in the light-blocking layer 70 is at least (96 × 2) μm, i.e., 192 μm. Thus, the pixel circuit 21 exposed to light can be blocked, avoiding the influence of light on the threshold voltage of the pixel circuit, thereby mitigating the phenomenon of reduced driving current of the pixel circuit, and further mitigating the phenomenon of reduced display brightness in the area surrounding the sub-display area A2, and further mitigating the phenomenon of "progressive dark ring" in the display panel 100 and the display device 1000.

[0227] In some embodiments, such as Figure 5 and Figure 6a As shown, along the first direction X, at least six columns of surrounding pixel circuits 21a are provided on either side of the sub-display area A2. Along the second direction Y, at least three rows of surrounding pixel circuits 21a are provided on either side of the sub-display area A2.

[0228] For example, along the first direction X, six or eight columns of surrounding pixel circuits 21a are provided on either side of the sub-display area A2.

[0229] For example, along the second direction Y, three or five rows of surrounding pixel circuits 21a are provided on either side of the sub-display area A2.

[0230] It should be noted that, as mentioned above, with a refractive index of 1.45 for the back film 60, an active layer in the pixel circuit layer 20, and a distance of 11 μm from the back film to the air interface, the area illuminated by external light and light emitted by the light-emitting device 31, after a series of refractions and / or reflections, is the area within 96 μm of the boundary line of the sub-display area A2. Taking a pixel circuit with a dimension of 32 μm along the first direction X and 16 μm along the second direction Y as an example, the aforementioned area within 96 μm of the boundary line of the sub-display area A2 corresponds to the dimensions of 6 columns of pixel circuits 21 along the first direction X and the dimensions of 3 rows of pixel circuits 21 along the second direction Y.

[0231] In this disclosure, the above-described arrangement is used, in the first direction X, at least six columns of surrounding pixel circuits 21a are provided on either side of the sub-display area A2, and a light-blocking layer 70 is provided in the area of ​​the at least six columns of surrounding pixel circuits 21a. This allows the light-blocking layer 70 to block the corresponding at least six columns of surrounding pixel circuits 21a, preventing light incident on the interface between the back film 60 and the air from undergoing total internal reflection and then incident on the at least six columns of surrounding pixel circuits 21a. This also prevents the active layer of the transistors in the at least six columns of surrounding pixel circuits 21a from being illuminated, prevents the threshold voltage drift of the transistors in the at least six columns of surrounding pixel circuits 21a, and prevents the display brightness of the light-emitting device 31 coupled to the at least six columns of surrounding pixel circuits 21a from decreasing. Along the second direction Y, at least three rows of surrounding pixel circuits 21a are provided on each of the opposite sides of the sub-display area A2. A light-blocking layer 70 is provided in the area corresponding to the at least three rows of surrounding pixel circuits 21a. The light-blocking layer 70 can block the corresponding at least three rows of surrounding pixel circuits, preventing light incident on the interface between the back film 60 and the air from being totally internally reflected and then incident on the at least three rows of surrounding pixel circuits 21a. This prevents the active layer of the transistors in the at least three rows of surrounding pixel circuits 21a from being illuminated, prevents the threshold voltage of the transistors in the at least three rows of surrounding pixel circuits 21a from drifting, and prevents the display brightness of the light-emitting devices coupled to the at least three rows of surrounding pixel circuits 21a from decreasing. In this way, the "progressive dark ring" phenomenon is prevented from appearing on the display panel 100 and the display device 1000.

[0232] In some embodiments, such as Figure 18 As shown, the pixel circuits in the pixel circuit layer 20 also include a plurality of first pixel circuits 21b located in the main display area A1.

[0233] For example, the first pixel circuit 21b can be coupled to the first light-emitting device 31a located in the main display area A1, thereby providing a driving signal to the first light-emitting device 31a to drive the first light-emitting device 31a to emit light.

[0234] In some examples, such as Figure 6a As shown, the orthographic projections of the plurality of first pixel circuits 21b onto the substrate 10 and the orthographic projections of the plurality of first light-emitting devices 31a onto the substrate 10 at least partially overlap.

[0235] For example, the first pixel circuit 21b is positioned directly opposite the corresponding first light-emitting device 31a. Alternatively, the first pixel circuit 21b and the corresponding first light-emitting device 31a may be partially positioned directly opposite each other. That is, the first light-emitting device 31a is located directly above or near the first pixel circuit 21b.

[0236] In some examples, at least a portion of the surrounding pixel circuits 21a is a first pixel circuit 21b. That is, at least a portion of the surrounding pixel circuits 21a and the light-emitting device 31 driven by them are arranged facing each other or partially facing each other.

[0237] In some embodiments, the plurality of pixel circuits in the pixel circuit layer 20 further include: a plurality of second pixel circuits 21d.

[0238] In some examples, such as Figure 5 As shown, multiple second pixel circuits 21d are located in the main display area A1. The multiple second pixel circuits 21d and multiple second light-emitting devices 31b are coupled together via conductive lines.

[0239] For example, the second pixel circuit 21d can be coupled to the second light-emitting device 31b located in the sub-display area A2, thereby providing a driving signal to the second light-emitting device 31b and driving the second light-emitting device 31b to emit light.

[0240] Here, there is a certain distance between the second pixel circuit 21d and the corresponding second light-emitting device 31b. Therefore, it is necessary to connect the second pixel circuit 21d and the corresponding second light-emitting device 31b through a conductive line.

[0241] For example, at least a portion of the multiple surrounding pixel circuits 21a are second pixel circuits 21d. That is, a conductive line connection is also required between the portion of the surrounding pixel circuit 21a and the corresponding light-emitting device 31.

[0242] In other examples, such as Figure 6b As shown, multiple second pixel circuits 21d are located in the sub-display area A2.

[0243] For example, the arrangement density of the plurality of second pixel circuits 21d located in the sub-display area A2 is less than the arrangement density of the plurality of pixel circuits 21 located in the display area A.

[0244] For example, the area occupied by the second pixel circuit 21d located in the sub-display area A2 on the display panel 100 is smaller than the area occupied by the pixel circuit 21 located in the display area A on the display panel 100.

[0245] By adopting the above configuration, the light transmittance of the sub-display area A2 in the display panel 100 is greater than that of the main display area A1 in the display panel 100. As a result, the optical element 50 located in the sub-display area A2 can receive enough light, thereby enabling the optical element 50 to work normally.

[0246] For example, multiple second pixel circuits 21d are coupled to multiple second light-emitting devices 31b, thereby providing driving signals to the second light-emitting devices 31b to drive them to emit light.

[0247] For example, the aforementioned multiple second pixel circuits 21d may be located only in the area near the boundary of the sub-display area A2, and no second pixel circuits 21d may be provided at the center of the sub-display area A2, while the multiple second light-emitting devices 31b may be evenly distributed within the sub-display area A2.

[0248] Therefore, the orthographic projections of the plurality of second pixel circuits 21d onto the substrate 10 and the orthographic projections of the plurality of second light-emitting devices 31b onto the substrate 10 at least partially overlap. Among the plurality of second pixel circuits 21d, some second pixel circuits 21d are disposed directly opposite to the corresponding second light-emitting devices 31b, while others are disposed partially opposite to the corresponding second light-emitting devices 31b.

[0249] In some other examples, such as Figure 6a As shown, multiple second pixel circuits 21d are located in the border area F.

[0250] For example, multiple second pixel circuits 21d are coupled to multiple second light-emitting devices 31b, thereby providing driving signals to the second light-emitting devices 31b to drive them to emit light.

[0251] For example, since the second pixel circuit 21d is located in the border area F and the second light-emitting device 31b is located in the sub-display area A2, there is a certain distance between the second pixel circuit 21d and the corresponding second light-emitting device 31b, and the second pixel circuit 21d and the corresponding second light-emitting device 31b are coupled through conductive lines.

[0252] In some embodiments, such as Figure 18 As shown, the pixel circuit layer 20 also includes a plurality of redundant pixel circuits 21c.

[0253] For example, the multiple redundant pixel circuits 21c are electrically insulated from the signal lines (such as the first scan signal line Gate1, the second scan signal line Gate2, the data signal line Data, the enable signal line EM, etc. mentioned above) and the anode layer of the light-emitting device 31. That is, the multiple redundant pixel circuits 21c are not coupled to the signal lines (such as the first scan signal line Gate1, the second scan signal line Gate2, the data signal line Data, the enable signal line EM, etc. mentioned above), and the multiple redundant pixel circuits 21c are not coupled to the anode layer of the light-emitting device 31.

[0254] By adopting the above configuration method, multiple redundant pixel circuits 21c can be set up, which can improve the uniformity of the surrounding pixel circuit 21a and avoid the problem of threshold voltage deviation of the surrounding pixel circuit 21a. This can solve the problem of display abnormality of the light-emitting device 31 coupled to the surrounding pixel circuit 21a near the boundary of the sub-display area A2.

[0255] For example, such as Figure 18 As shown, multiple redundant pixel circuits 21c are located in the main display area A1 and surround at least a portion of the sub-display area A2.

[0256] For example, multiple redundant pixel circuits 21c may surround a portion of the sub-display area A2. Alternatively, multiple redundant pixel circuits 21c may surround the entire sub-display area A2.

[0257] For example, the multiple redundant pixel circuits 21c are closer to the sub-display area A2 than the surrounding pixel circuits 21a.

[0258] With the above-described configuration, when external light and light emitted by the light-emitting device are incident on the interface between the back film 60 and the air, a portion of the light undergoes total internal reflection at this interface and is then emitted. The portion of this light emitted after total internal reflection is blocked by the redundant pixel circuit 21c, preventing it from passing through the pixel circuit layer 20 and escaping from the light-emitting side of the display panel 100. This prevents abnormalities in the display image of the display panel 100 and the display device 1000, thereby improving the display effect of the display panel 100 and the display device 1000.

[0259] In some embodiments, such as Figure 18 As shown, in the case where the pixel circuit layer 20 includes multiple surrounding pixel circuits 21a and multiple redundant pixel circuits 21c, the multiple surrounding pixel circuits 21a are arranged in multiple columns along the first direction X and in multiple rows along the second direction Y. The multiple redundant pixel circuits 21c are arranged in at least one column along the first direction X and in at least one row along the second direction Y.

[0260] In some examples, multiple redundant pixel circuits 21c are arranged in one or more columns along the first direction X.

[0261] In some examples, multiple redundant pixel circuits 21c are arranged in one or more rows along the second direction Y.

[0262] By adopting the above configuration, during the fabrication of the pixel circuit layer 20, the redundant pixel circuit 21c can be fabricated together with the surrounding pixel circuit 21a, and the redundant pixel circuit 21c is not coupled to the signal lines and light-emitting devices, thereby simplifying the fabrication process of the surrounding pixel circuit 21a and the redundant pixel circuit 21c in the pixel circuit layer 20.

[0263] In some examples, along the first direction X, the sum of the number of columns of the surrounding pixel circuit 21a and the number of columns of the redundant pixel circuit 21c on either side of the sub-display area A2 is greater than or equal to six.

[0264] For example, along the first direction X, the number of columns of redundant pixel circuits 21c set on either side of the sub-display area A2 can be less than or equal to 5 columns.

[0265] For example, if the number of columns of redundant pixel circuits 21c provided on either side of the sub-display area A2 along the first direction X is 2, the number of columns of the surrounding pixel circuits 21a can be greater than or equal to 4.

[0266] For example, if the number of columns of redundant pixel circuits 21c set on either side of the sub-display area A2 along the first direction X is 5, the number of columns of the surrounding pixel circuits 21a can be greater than or equal to 1.

[0267] In some examples, along the second direction Y, the sum of the number of rows of the surrounding pixel circuit 21a and the number of rows of the redundant pixel circuit 21c on either side of the sub-display area A2 is greater than or equal to three rows.

[0268] For example, along the second direction Y, the number of rows of redundant pixel circuits 21c set on either side of the sub-display area A2 can be less than or equal to 2 rows.

[0269] For example, in the second direction Y, if the number of rows of redundant pixel circuits 21c set on either side of the sub-display area A2 is 2, the number of rows of the surrounding pixel circuits 21a can be greater than or equal to 1.

[0270] For example, if the number of rows of redundant pixel circuits 21c set on either side of the sub-display area A2 along the first direction X is 1, the number of rows of the surrounding pixel circuits 21a can be greater than or equal to 2.

[0271] By adopting the above-described configuration, the blocking effect of the light-blocking layer on the surrounding pixel circuit 21a and the improvement effect on the "progressive dark ring" can be ensured. Furthermore, when external light and light emitted from the second light-emitting device 31b in the sub-display area A2 are projected onto the pixel circuit layer 20 of the display panel 100 after a series of refractions and / or reflections, the active layer of the redundant pixel circuit 21c will be partially illuminated. Since the redundant pixel circuit 21c is not connected to the light-emitting device 31, it will not affect the brightness of the light-emitting device. Therefore, the light-blocking layer 70 can be placed only in the area corresponding to the redundant pixel circuit 21a, without the need for it, thus reducing the amount of material used in the light-blocking layer 70.

[0272] In some embodiments, the display panel 100 further includes: a semiconductor layer Poly, a first conductive layer Gate1, a second conductive layer Gate2, an interlayer dielectric layer ILD, a third conductive layer SD1, a first planarization layer PLN1, a fourth conductive layer SD2, a second planarization layer PLN2, an anode layer AND, a pixel delimiting layer PDL, etc., which are sequentially stacked on the side of the light-blocking layer 70 away from the substrate 10.

[0273] For example, the pixel circuit layer 20 includes: the semiconductor layer Poly, the first conductive layer Gate1, the second conductive layer Gate2, the interlayer dielectric layer ILD, the third conductive layer SD1, the first planarization layer PLN1, and the fourth conductive layer SD2, which are stacked sequentially as described above.

[0274] in, Figure 19 The diagram illustrates the top view of the light-blocking layer 70. Figure 20a The diagram illustrates the top view of the Poly semiconductor layer. Figure 20b The diagram illustrates the top view of the structure after the light-blocking layer 70 and the semiconductor layer ACT are stacked in sequence. Figure 21 The diagram shows the top view of the first conductive layer, Gate1. Figure 22 The diagram shows the top view of the second conductive layer, Gate2. Figure 23 The diagram illustrates the top view of the interlayer dielectric layer (ILD). Figure 24 The diagram shows the top view of the third conductive layer SD1. Figure 25 The diagram shows the top view of the first planarization layer PLN1. Figure 26 The diagram shows the top view of the fourth conductive layer SD2. Figure 27 The diagram shows the top view of the second planarization layer PLN2. Figure 28 The diagram illustrates the top view of the anode layer AND. Figure 29 The diagram illustrates the top view of the pixel delimiter layer (PDL).

[0275] For example, the interlayer dielectric layer (ILD), the first planarization layer (PLN1), and the second planarization layer (PLN2) are generally made of transparent materials. Figure 23 Only the locations of vias on the interlayer dielectric layer (ILD) are shown. Figure 25 Only the location diagram of the vias on the first planarization layer PLN1 is shown, and only the location diagram of the vias on the second planarization layer PLN2 is shown.

[0276] For example, a first gate insulating layer may be disposed between the semiconductor layer Poly and the first conductive layer Gate1, and a second gate insulating layer may be disposed between the first conductive layer Gate1 and the second conductive layer Gate2.

[0277] For example, the materials of the interlayer dielectric layer ILD, the first planarization layer PLN1, the second planarization layer PLN2, the first gate insulating layer, and the second gate insulating layer can be insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0278] For example, the material of the semiconductor layer Poly may include amorphous silicon, monocrystalline silicon, polycrystalline silicon, or metal oxide semiconductor material.

[0279] For example, the materials of the first conductive layer Gate1, the second conductive layer Gate2, the third conductive layer SD1, and the fourth conductive layer SD2 are all conductive materials. The materials of the first conductive layer Gate1 and the second conductive layer Gate2 can be the same, for example, and the materials of the third conductive layer SD1 and the fourth conductive layer SD2 can be the same.

[0280] For example, the materials of the first conductive layer Gate1, the second conductive layer Gate2, the third conductive layer SD1, or the fourth conductive layer SD2 can be metallic materials, such as Al (aluminum), Ag (silver), Cu (copper), Cr (chromium), etc.

[0281] It should be noted that the orthographic projection of the semiconductor layer Poly onto the substrate overlaps with the orthographic projection of the first conductive layer Gate1 onto the substrate. After the first conductive layer Gate1 is formed on the side of the semiconductor layer Poly away from the substrate, it can be used as a mask to dope the semiconductor layer Poly. This results in the portion of the semiconductor layer Poly covered by the first conductive layer Gate1 forming the active pattern of each transistor, while the portion of the semiconductor layer Poly not covered by the first conductive layer Gate1 forms a conductor, which can form the first or second electrode of each transistor. The overlapping portion of the first conductive layer Gate1 and the semiconductor layer Poly forms the gate pattern (i.e., the gate) of each transistor.

[0282] For example, the relative positional relationships between the transistors and storage capacitors included in the pixel circuit 21 are as follows: Figure 9b As shown. Along the first direction X, compensation transistor T5 and switching transistor T3 are arranged in the same row, and first light-emitting control transistor T6 and second light-emitting control transistor T7 are arranged in the same row. Along the first direction X, driving transistor T4 is located between second light-emitting control transistor T7 and first light-emitting control transistor T6. Along the second direction Y, driving transistor T4 is also located between switching transistor T3 and first light-emitting control transistor T6. Along the first direction X, compensation transistor T5 is located between second reset transistor T2 and switching transistor T3. Along the second direction Y, second reset transistor T2 is also located on the side of second light-emitting control transistor T7 away from switching transistor T3. The position of storage capacitor Cst is the same as the position of driving transistor T4.

[0283] By adopting the above arrangement, the transistors and storage capacitors in the pixel circuit 21 can be arranged more closely, saving the area on the display panel 100 along the first direction X and along the second direction Y. This allows for the arrangement of more pixel circuits 21 within a certain area, thereby increasing the pixel density of the display panel 100 and the display device 1000, which is beneficial for the high PPI design of the display panel 100 and the display device 1000.

[0284] In some embodiments, such as Figure 30 As shown, the display panel 100 also includes a first voltage signal line VDD and a transition layer Co disposed in the pixel circuit layer 20.

[0285] For example, the first voltage signal line VDD is located on the fourth conductive layer SD2.

[0286] For example, the transition layer Co can be disposed in the same layer as the fourth conductive layer SD2.

[0287] For example, the adapter layer Co may include an adapter pattern.

[0288] For example, the light-blocking layer 70 is connected to the first voltage signal line VDD via an adapter pattern.

[0289] For example, the transition pattern can sequentially pass through the first planarization layer PLN1, the interlayer dielectric layer ILD, the second insulating layer GI2, and the vias on the first insulating layer GI1, and connect to the light-blocking layer 70.

[0290] For example, the transition pattern can be located in the border area F, thereby connecting the transition pattern to the light-blocking layer 70 in the border area F.

[0291] In some examples, the material of the light-blocking layer 70 includes molybdenum or graphite.

[0292] By adopting the above configuration, the material of the light-blocking layer 70 can conduct electricity. When the light-blocking layer 70 is connected to the first voltage signal line VDD, since the signal transmitted by the first voltage signal line VDD is a constant voltage signal, a constant voltage signal can be present on the light-blocking layer 70. This can avoid the instability of the voltage signal in the pixel circuit layer 20 (e.g., the scan signal line Gate) on the light-blocking layer 70, prevent the signal of the pixel circuit layer from being interfered with, and improve the stability of the signal transmitted by the pixel circuit layer 20.

[0293] In other examples, the light-blocking layer 70 can also be coupled to other signal lines that transmit constant voltage signals, such as the common voltage signal line VSS, the first initial signal line Vinit1, the second initial signal line Vinit2, etc., thereby avoiding the instability of the voltage signal in the pixel circuit layer 20 (e.g., the scan signal line Gate) on the light-blocking layer 70, preventing the signal of the pixel circuit layer from being interfered with, and improving the stability of the signal transmitted by the pixel circuit layer 20.

[0294] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, characterized by, The display panel has a display area, the display area includes a main display area and a sub-display area, the main display area surrounds at least part of the sub-display area; The display panel includes: A substrate, at least in the display area; A pixel circuit layer, on one side of the substrate and at least in the display area, the pixel circuit layer includes a plurality of surrounding pixel circuits, the plurality of surrounding pixel circuits are in the main display area and at least partially surround the sub-display area; A light blocking layer, in the main display area, and between the substrate and the pixel circuit layer, the light blocking layer at least partially overlaps the plurality of surrounding pixel circuits in the substrate in orthographic projection; the light blocking layer includes a plurality of light blocking patterns; the orthographic projection of at least part of a surrounding pixel circuit on the substrate is in the orthographic projection range of a light blocking pattern on the substrate; the light blocking layer includes a light blocking ring or at least two concentrically arranged light blocking rings; the light blocking ring includes a plurality of light blocking patterns connected, and the light blocking ring surrounds at least part of the sub-display area.

2. The display panel of claim 1, wherein, The surrounding pixel circuit includes a driving transistor; The active layer of the driving transistor in orthographic projection on the substrate is in the orthographic projection range of the light blocking pattern on the substrate.

3. The display panel of claim 2, wherein, The surrounding pixel circuit further includes a compensation transistor coupled to the driving transistor; The active layer of the compensation transistor in orthographic projection on the substrate is in the range of the orthographic projection of the light blocking pattern on the substrate.

4. The display panel of claim 1, wherein, The display panel further includes a first voltage signal line and a transfer layer arranged in the pixel circuit layer; The light blocking layer is connected with the first voltage signal line through the transfer layer.

5. The display panel of claim 1, wherein, The material of the light blocking layer includes molybdenum or graphite.

6. The display panel of claim 1, wherein, The plurality of surrounding pixel circuits are arranged as a plurality of columns along a first direction and a plurality of rows along a second direction; Along the first direction, at least six columns of surrounding pixel circuits are arranged on any one side of the opposite sides of the sub-display area, Along the second direction, at least three rows of surrounding pixel circuits are arranged on any one side of the opposite sides of the sub-display area.

7. The display panel of claim 1, wherein, The pixel circuit layer further includes a plurality of redundant pixel circuits; The plurality of redundant pixel circuits are in the main display area and surround at least part of the sub-display area; The plurality of redundant pixel circuits are closer to the sub-display area than the surrounding pixel circuits.

8. The display panel of claim 7, wherein, The plurality of surrounding pixel circuits are arranged as a plurality of columns along a first direction and a plurality of rows along a second direction; the plurality of redundant pixel circuits are arranged as at least one column along the first direction and at least one row along the second direction; Along the first direction, the sum of the number of columns of surrounding pixel circuits and the number of columns of redundant pixel circuits arranged on any one side of the opposite sides of the sub-display area is greater than or equal to six columns; Along the second direction, the sum of the number of rows of surrounding pixel circuits and the number of rows of redundant pixel circuits arranged on any one side of the opposite sides of the sub-display area is greater than or equal to three rows.

9. The display panel of claim 1, wherein, The display panel further includes a plurality of first light emitting devices in the main display area; The pixel circuit layer further comprises a plurality of first pixel circuits in the main display area, the plurality of first pixel circuits being coupled with the plurality of first light emitting devices; At least part of the plurality of surrounding pixel circuits are first pixel circuits.

10. The display panel of any one of claims 1-9, wherein, The display panel further comprises a plurality of second light emitting devices in the sub-display area; The pixel circuit layer further comprises a plurality of second pixel circuits in the main display area, the plurality of second pixel circuits being coupled with the plurality of second light emitting devices through conductive wires; At least part of the plurality of surrounding pixel circuits are second pixel circuits.

11. The display panel of any one of claims 1-10, wherein, The display panel further comprises a plurality of second light emitting devices in the sub-display area; The pixel circuit layer further comprises a plurality of second pixel circuits in the sub-display area, the plurality of second pixel circuits being coupled with the plurality of second light emitting devices.

12. The display panel according to any one of claims 1 to 10, wherein, The display panel further has a bezel area on at least one side of the display area and a plurality of second light emitting devices in the sub-display area; The pixel circuit layer further comprises a plurality of second pixel circuits in the bezel area, the plurality of second pixel circuits being coupled with the plurality of second light emitting devices through conductive wires.

13. A display device comprising: The display device comprises the display panel as claimed in any one of claims 1-12.

14. The display device of claim 13, wherein, The display device further comprises: An optical element on the side of the light-blocking layer away from the pixel circuit layer, a normal projection of the optical element on the substrate substrate being in the sub-display area.

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