Ldo circuit and chip

Abstract

The application discloses an LDO circuit and a chip, and the LDO circuit comprises a differential amplifier, a first power tube, a voltage control circuit, a feedback circuit, a second power tube and a voltage division control circuit. According to the LDO circuit and the chip, in the power-on stage of a power supply voltage, the voltage control circuit is used for controlling the voltage of the control end of the first power tube to follow the power-on change of the power supply voltage, the first power tube is turned off, the output voltage of the LDO circuit is prevented from being power-on overshoot, and meanwhile, the voltage division control circuit is closed by a control signal to make the second power tube turn off and not participate in the power-on stage; after the power-on of the power supply voltage, the voltage control circuit is closed, and when linear transient change occurs in the power supply voltage, the voltage division control circuit is opened by the control signal to make the second power tube turn on, the first power tube of the LDO circuit is prevented from being mistakenly turned off to cause the output to power off and trigger functions such as reset and soft start when the linear transient change occurs in the power supply voltage.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to an LDO circuit and chip. Background Technology

[0002] The LDO circuit inside the chip needs to supply power to the fuse, so it is necessary to consider high current (about 20mA) and low on-resistance Rdson (about 10Ω), which leads to the need for a large power transistor. The large power transistor introduces the problem of rapid power-up overshoot, especially for the rapid power-up of automotive-grade products (such as a power-up rate of 1V / 1us), so a power-up protection circuit is required to prevent overshoot.

[0003] like Figure 1 As shown, the existing solution uses an RC circuit composed of resistor R3, capacitor C1 and pull-up transistor Q2. The delay of the RC circuit is directly related to the power supply voltage VIN's power-on slope. When the power supply voltage VIN is powered on quickly, the gate of pull-up transistor Q2 remains low due to the delay. Therefore, pull-up transistor Q2 turns on first, and the gate G1 of power transistor Q1 is pulled high to the power supply voltage VIN. Power transistor Q1 is then turned off, so the voltage VCC output at the output terminal Vout will not overshoot.

[0004] However, when the power supply voltage VIN is powered on normally, the output voltage VCC at the output terminal Vout also stabilizes at the expected value, and the chip works normally inside. When the power supply voltage VIN experiences a line transient, the power-on protection circuit will sense the slope of the change in the power supply voltage VIN and turn on the pull-up transistor Q2 and turn off the power transistor Q1, thus causing a short-term power drop in voltage VCC. The severity depends on the slope of the line transient. Consequently, the length of the power drop can lead to some logic errors, such as triggering a reset POR and a soft restart, which are all things that the system does not want to happen. Figure 2 This shows that when the power supply voltage VIN changes line transiently from 3V to 45V at a rate of 1V / 1us, the voltage VCC experiences a severe power loss.

[0005] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide an LDO circuit and chip that can prevent power-on overshoot in the output voltage of the LDO circuit when the power supply voltage is powered on, and also ensure that the output voltage of the LDO circuit does not drop when the power supply voltage undergoes a linear transient change.

[0007] To achieve the above objectives, embodiments of the present invention provide an LDO circuit, comprising: a differential amplifier, a first power transistor, a voltage control circuit, a feedback circuit, a second power transistor, and a voltage divider control circuit;

[0008] The control terminal of the first power transistor is connected to the output terminal of the differential amplifier, the second terminal of the first power transistor is connected to the power supply voltage, the first terminal of the first power transistor is connected to the feedback circuit to generate the output voltage, the feedback circuit generates the feedback voltage based on the output voltage, the first input terminal of the differential amplifier is used to receive the reference voltage, and the second input terminal of the differential amplifier is used to receive the feedback voltage.

[0009] The voltage control circuit is connected to the control terminal of the first power transistor and the power supply voltage. The voltage control circuit is used to control the voltage at the control terminal of the first power transistor to follow the change of the power supply voltage. The first terminal of the second power transistor is connected to the first terminal of the first power transistor, and the second terminal of the second power transistor is connected to the power supply voltage. The control terminal of the second power transistor is connected to the voltage divider control circuit. The voltage divider control circuit is used to generate a control voltage for controlling the second power transistor based on the control signal.

[0010] In one or more embodiments of the present invention, the aspect ratio of the second power transistor is greater than that of the first power transistor.

[0011] In one or more embodiments of the present invention, the aspect ratio of the second power transistor is 7 to 12 times that of the first power transistor.

[0012] In one or more embodiments of the present invention, the voltage divider control circuit includes a voltage divider unit and a switching unit. The switching unit is connected to the voltage divider unit and is used to control the opening and closing of the voltage divider unit. The voltage divider unit is connected to the power supply voltage and the control terminal of the second power transistor. The voltage divider unit is used to generate a first control voltage and a second control voltage to the control terminal of the second power transistor based on its own opening and closing to turn the second power transistor on or off.

[0013] In one or more embodiments of the present invention, the voltage divider unit includes a first voltage divider resistor and a second voltage divider resistor. A first terminal of the first voltage divider resistor is connected to a power supply voltage, and a second terminal of the first voltage divider resistor is connected to a control terminal of a second power transistor. The second voltage divider resistor is connected in series with a switching unit and between the control terminal of the second power transistor and ground voltage. The switching unit is used to control the connection and disconnection of the current path between the second voltage divider resistor and the control terminal of the second power transistor; or

[0014] The first voltage divider resistor is connected in series with the switching unit and between the power supply voltage and the control terminal of the second power transistor. The switching unit is used to control the connection and disconnection of the current path between the first voltage divider resistor and the control terminal of the second power transistor. The first end of the second voltage divider resistor is connected to the control terminal of the second power transistor, and the second end of the second voltage divider resistor is connected to the ground voltage.

[0015] In one or more embodiments of the present invention, the switching unit includes a switching transistor, the control terminal of which receives a control signal to turn the voltage divider unit on or off.

[0016] In one or more embodiments of the present invention, the voltage control circuit includes a current mirror and a controllable current source. The controllable current source is used to generate a compensation current based on a second control signal. The current mirror is connected to the controllable current source, the power supply voltage, and the control terminal of the first power transistor. The current mirror is used to inject the compensation current into the control terminal of the first power transistor when the power supply voltage is powered on.

[0017] In one or more embodiments of the present invention, the voltage control circuit further includes a first capacitor, a first terminal of which is connected to the control terminal of the first power transistor, and a second terminal of which is connected to the second terminal of the first power transistor.

[0018] In one or more embodiments of the present invention, the LDO circuit further includes a second capacitor, the first terminal of the second capacitor being connected to the first terminal of the second power transistor, and the second terminal of the second capacitor being connected to ground voltage.

[0019] The present invention also discloses a chip including the LDO circuit described above.

[0020] Compared with the prior art, the LDO circuit and chip according to the embodiments of the present invention, during the power-on phase, controls the voltage at the control terminal of the first power transistor to follow the power-on voltage change and turn off the first power transistor, preventing the output voltage of the LDO circuit from overshooting during power-on. At the same time, the voltage divider control circuit is turned off by the control signal to turn off the second power transistor so that it does not participate in the power-on phase. After the power supply voltage is powered on, the voltage control circuit is turned off. At the same time, when the power supply voltage undergoes a linear transient change or when the LDO circuit needs to provide strong driving capability, the voltage divider control circuit is turned on by the control signal to turn on the second power transistor, preventing the first power transistor of the LDO circuit from being mistakenly turned off during the linear transient change of the power supply voltage, which would cause the output to lose power and trigger functions such as reset and soft start. Attached Figure Description

[0021] Figure 1 It is a circuit schematic diagram of an LDO circuit based on existing technology.

[0022] Figure 2It is a waveform diagram of the voltage at each node and the output voltage of an LDO circuit based on existing technology.

[0023] Figure 3 This is a circuit schematic diagram of an LDO circuit according to an embodiment of the present invention.

[0024] Figure 4 This is a waveform diagram of the node voltages and output voltage of an LDO circuit according to an embodiment of the present invention. Detailed Implementation

[0025] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0026] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0027] The terms "coupled," "connected," or "linked" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in this invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0028] like Figure 3 As shown, an LDO circuit includes: a differential amplifier OPAMP, a first power transistor Q1, a voltage control circuit 10, a feedback circuit 20, a second power transistor Q2, and a voltage divider control circuit 30.

[0029] In this circuit, the control terminal of the first power transistor Q1 is connected to the output terminal of the differential amplifier OPAMP, the second terminal of the first power transistor Q1 is connected to the power supply voltage VIN, and the first terminal of the first power transistor Q1 is connected to the feedback circuit 20 to form the output terminal VOUT of the LDO circuit, generating the output voltage VCC. The feedback circuit 20 generates a feedback voltage based on the output voltage VCC. The first input terminal of the differential amplifier OPAMP is used to receive the reference voltage, and the second input terminal of the differential amplifier OPAMP is used to receive the feedback voltage.

[0030] The feedback circuit 20 includes a first resistor R1 and a second resistor R2. The first end of the first resistor R1 is connected to the first end of the first power transistor Q1, and the second end of the first resistor R1 is connected to the first end of the second resistor R2 to generate a feedback voltage based on the output voltage VCC. The second end of the second resistor R2 is connected to ground.

[0031] In one embodiment, the first power transistor Q1 is a P-channel MOS transistor, the first terminal of the first power transistor Q1 is the drain, the second terminal of the first power transistor Q1 is the source, and the control terminal of the first power transistor Q1 is the gate. In other embodiments, the first power transistor Q1 can be an N-channel MOS transistor.

[0032] Voltage control circuit 10 is connected to the control terminal of the first power transistor Q1 and the power supply voltage VIN. Voltage control circuit 10 controls the voltage at the control terminal of the first power transistor Q1 to follow the changes in power supply voltage VIN when power supply voltage VIN is applied. The first terminal of the second power transistor Q2 is connected to the first terminal of the first power transistor Q1, and the second terminal of the second power transistor Q2 is connected to the power supply voltage VIN. The control terminal of the second power transistor Q2 is connected to voltage divider control circuit 30. Voltage divider control circuit 30 generates a control voltage based on a control signal after power supply voltage VIN is applied to turn on the second power transistor Q2.

[0033] In one embodiment, the second power transistor Q2 is a P-channel MOSFET, with its first terminal being the drain, its second terminal being the source, and its control terminal being the gate. In other embodiments, the second power transistor Q2 and the first power transistor Q1 can both be N-channel MOSFETs.

[0034] Both the first power transistor Q1 and the second power transistor Q2 can be P-channel MOSFETs, or both can be N-channel MOSFETs. Using MOSFETs of the same channel ensures good matching when both power transistors Q1 and Q2 are turned on simultaneously.

[0035] like Figure 3As shown, the voltage control circuit 10 includes a current mirror, a controllable current source I1, and a first capacitor C1. The controllable current source I1 generates a compensation current based on a second control signal. During the power-on phase of the power supply voltage VIN, the controllable current source I1 is turned on by the second control signal to generate the compensation current. After power-on, the controllable current source I1 is turned off by the second control signal. In other words, the voltage control circuit 10 can be turned on and off by the second control signal. The current mirror is connected to the controllable current source I1, the power supply voltage VIN, and the control terminal of the first power transistor Q1. The current mirror is used to inject the compensation current into the control terminal of the first power transistor Q1 when the power supply voltage VIN is powered on. The first terminal of the first capacitor C1 is connected to the control terminal of the first power transistor Q1, and the second terminal of the first capacitor C1 is connected to the second terminal of the first power transistor Q1.

[0036] The current mirror includes a first MOSFET Q4 and a second MOSFET Q5. The control terminals of the first MOSFET Q4 and the second MOSFET Q5 are connected together. The control terminal of the first MOSFET Q4, its drain, and the controllable current source I1 are connected together. The second terminals of the first MOSFET Q4 and the second MOSFET Q5 are connected together with the power supply voltage VIN.

[0037] In one embodiment, the first MOSFET Q4 and the second MOSFET Q5 have the same width-to-length ratio, and the compensation current is 100 to 400 mA. During the power-on phase of the power supply voltage VIN, the first MOSFET Q4 acts as a pull-up MOSFET to ensure that the voltage at the control terminal of the first power transistor Q1 rises with the power supply voltage VIN, thereby preventing overshoot of the output voltage VCC at the output terminal VOUT. When the power supply voltage VIN stabilizes, the voltage control circuit 10 is turned off. The first capacitor C1 increases the coupling capability between the control terminal of the first power transistor Q1 and the power supply voltage VIN, ensuring that the first power transistor Q1 is turned off during the power-on phase of the power supply voltage VIN, thus preventing overshoot of the output voltage VCC at the output terminal VOUT. In other embodiments, the first capacitor C1 may be omitted.

[0038] like Figure 3 As shown, the voltage divider control circuit 30 includes a voltage divider unit 31 and a switching unit 32. The switching unit 32 is connected to the voltage divider unit 31 and is used to control the opening and closing of the voltage divider unit 31. The voltage divider unit 31 is connected to the power supply voltage VIN and the control terminal of the second power transistor Q2. The voltage divider unit 31 generates a first control voltage and a second control voltage based on its own opening and closing to the control terminal of the second power transistor Q2 to turn the second power transistor Q2 on or off.

[0039] Specifically, the voltage divider unit 31 includes a first voltage divider resistor R3 and a second voltage divider resistor R4. The first end of the first voltage divider resistor R3 is connected to the power supply voltage VIN, and the second end of the first voltage divider resistor R3 is connected to the control terminal of the second power transistor Q2. The second voltage divider resistor R4 is connected in series with the switching unit 32 and is connected between the control terminal of the second power transistor Q2 and the ground voltage. The switching unit 32 is used to control the connection and disconnection of the current path between the second voltage divider resistor R4 and the control terminal of the second power transistor Q2.

[0040] In other embodiments, the first voltage divider resistor R3 can be connected in series with the switching unit 32 and connected between the power supply voltage VIN and the control terminal of the second power transistor Q2. The switching unit 32 is used to control the connection and disconnection of the current path between the first voltage divider resistor R3 and the control terminal of the second power transistor Q2. The first end of the second voltage divider resistor R4 is connected to the control terminal of the second power transistor Q2, and the second end of the second voltage divider resistor R4 is connected to the ground voltage.

[0041] In one embodiment, the switching unit 32 includes a switching transistor Q3. The first terminal of the switching transistor Q3 is connected to the second terminal of the second voltage divider resistor R4, and the second terminal of the switching transistor Q3 is connected to ground. The control terminal of the switching transistor Q3 receives a first control signal VCTRL to turn the voltage divider unit 31 on or off. Alternatively, the switching transistor Q3 can be connected in series between the control terminal of the second power transistor Q2 and the first terminal of the second voltage divider resistor R4. The switching transistor Q3 is an N-channel MOSFET, with its first terminal being the drain, its second terminal being the source, and its control terminal being the gate. In other embodiments, the switching transistor Q3 can be a P-channel MOSFET.

[0042] The LDO circuit also includes a second capacitor C2. The first terminal of the second capacitor C2 is connected to the first terminal of the second power transistor Q2, and the second terminal of the second capacitor C2 is connected to ground. The second capacitor C2 acts as a load capacitor to filter out the ripple of the output voltage VCC at the output terminal VOUT.

[0043] In one embodiment, the aspect ratio of the second power transistor Q2 is greater than that of the first power transistor Q1. The aspect ratio of the second power transistor Q2 is 7 to 12 times that of the first power transistor Q1, and preferably, the aspect ratio of the second power transistor Q2 is 9 times that of the first power transistor Q1.

[0044] Therefore, it can be seen that the driving capability of the second power transistor Q2 is stronger than that of the first power transistor Q1. The first power transistor Q1 is a small power transistor used for power-on, while the second power transistor Q2 is a high-power transistor with strong drive to cope with line transient and high current demand situations.

[0045] Specifically, during the power-on phase of the power supply voltage VIN, the first control signal VCTRL is at a low level. Therefore, the control terminal of the second power transistor Q2 is pulled up to the power supply voltage VIN through the first voltage divider resistor R3, and the second power transistor Q2 is in the off state, not participating in the power-on overshoot. During the power-on phase of the power supply voltage VIN, the first power transistor Q1 is turned off under the control of the voltage control circuit 10, thereby preventing power-on overshoot.

[0046] When the power supply voltage VIN is powered on, if a strong driving capability is needed or if the power supply voltage VIN experiences a line transition (e.g., when the fuse burns out or more current needs to be driven), the corresponding first control signal VCTRL jumps high. The first control signal VCTRL controls the high-voltage switching transistor Q3 to turn on. At this time, the voltage at the control terminal of the second power transistor Q2 is determined by the first voltage divider resistor R3 and the second voltage divider resistor R4. Since the pull-down second voltage divider resistor R4 is stronger (the resistance of the second voltage divider resistor R4 is about 1 / 10 of the resistance of the first voltage divider resistor R3, such as R4 = 20K and R3 = 200K), the second power transistor Q2 turns on and participates in the output of the LDO circuit. The output of the LDO circuit will not experience a power failure.

[0047] like Figure 4 As shown, during the power-on phase of the power supply voltage VIN, the output voltage VCC generated by the LDO circuit will not overshoot. When the power supply voltage VIN experiences a line transient, the output voltage VCC will not lose power, nor will it cause the power transistor in the LDO circuit to be turned off.

[0048] The present invention also discloses a chip including the LDO circuit described above.

[0049] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings; the invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments and various different choices and modifications of the invention without departing from the scope and spirit of the invention. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. An LDO circuit, characterized in that, include: Differential amplifier, first power transistor, voltage control circuit, feedback circuit, second power transistor, and voltage divider control circuit; The control terminal of the first power transistor is connected to the output terminal of the differential amplifier, the second terminal of the first power transistor is connected to the power supply voltage, the first terminal of the first power transistor is connected to the feedback circuit to generate the output voltage, the feedback circuit generates the feedback voltage based on the output voltage, the first input terminal of the differential amplifier is used to receive the reference voltage, and the second input terminal of the differential amplifier is used to receive the feedback voltage. The voltage control circuit is connected to the control terminal of the first power transistor and the power supply voltage. The voltage control circuit is used to control the voltage of the control terminal of the first power transistor to follow the change of the power supply voltage. The first terminal of the second power transistor is connected to the first terminal of the first power transistor. The second terminal of the second power transistor is connected to the power supply voltage. The control terminal of the second power transistor is connected to the voltage divider control circuit. The voltage divider control circuit is used to generate a control voltage for controlling the second power transistor based on the first control signal. During the power-on phase, the voltage control circuit controls the voltage at the control terminal of the first power transistor to turn off the first power transistor as the power supply voltage changes. The voltage divider control circuit controls the turn-off of the second power transistor based on its own shutdown. After the power supply voltage is powered on, the voltage control circuit turns off, and when the first control signal is generated, the voltage divider control circuit turns on based on the first control signal to generate a control voltage to turn on the second power transistor.

2. The LDO circuit as described in claim 1, characterized in that, The width-to-length ratio of the second power transistor is greater than that of the first power transistor.

3. The LDO circuit as described in claim 2, characterized in that, The aspect ratio of the second power transistor is 7 to 12 times that of the first power transistor.

4. The LDO circuit as described in claim 1, characterized in that, The voltage divider control circuit includes a voltage divider unit and a switching unit. The switching unit is connected to the voltage divider unit and is used to control the opening and closing of the voltage divider unit. The voltage divider unit is connected to the power supply voltage and the control terminal of the second power transistor. The voltage divider unit is used to generate a first control voltage and a second control voltage based on its own opening and closing to the control terminal of the second power transistor to turn the second power transistor on or off.

5. The LDO circuit as described in claim 4, characterized in that, The voltage divider unit includes a first voltage divider resistor and a second voltage divider resistor. A first terminal of the first voltage divider resistor is connected to the power supply voltage, and a second terminal of the first voltage divider resistor is connected to the control terminal of the second power transistor. The second voltage divider resistor is connected in series with a switching unit and between the control terminal of the second power transistor and ground. The switching unit is used to control the connection and disconnection of the current path between the second voltage divider resistor and the control terminal of the second power transistor; or The first voltage divider resistor is connected in series with the switching unit and between the power supply voltage and the control terminal of the second power transistor. The switching unit is used to control the connection and disconnection of the current path between the first voltage divider resistor and the control terminal of the second power transistor. The first end of the second voltage divider resistor is connected to the control terminal of the second power transistor, and the second end of the second voltage divider resistor is connected to the ground voltage.

6. The LDO circuit as described in claim 4, characterized in that, The switching unit includes a switching transistor, and the control terminal of the switching transistor receives a first control signal to turn the voltage divider unit on or off.

7. The LDO circuit as described in claim 1, characterized in that, The voltage control circuit includes a current mirror and a controllable current source. The controllable current source is used to generate a compensation current based on a second control signal. The current mirror is connected to the controllable current source, the power supply voltage, and the control terminal of the first power transistor. The current mirror is used to inject the compensation current into the control terminal of the first power transistor when the power supply voltage is powered on.

8. The LDO circuit as described in claim 7, characterized in that, The voltage control circuit further includes a first capacitor, the first end of which is connected to the control terminal of the first power transistor, and the second end of which is connected to the second end of the first power transistor.

9. The LDO circuit as described in claim 1, characterized in that, The LDO circuit also includes a second capacitor, the first terminal of which is connected to the first terminal of the second power transistor, and the second terminal of which is connected to ground voltage.

10. A chip, characterized in that, Includes the LDO circuit as described in any one of claims 1 to 9.

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