An implementation method and device of a convolution structure based on avoidable overflow and a medium

Abstract

This invention discloses a method, apparatus, and medium for implementing an overflow-avoidable convolutional structure, belonging to the field of computer technology. The method includes: designing an overflow-avoidable convolutional structure; wherein the convolutional structure performs grouped convolutions on the input channels, and the output is an accumulation of the grouped convolutions; designing a matching quantization-aware training method, using different methods to quantize different parameters in the convolutional structure. This invention proposes an overflow-avoidable convolutional structure using a low-bit accumulator, aiming to improve the inference efficiency of the model by storing intermediate convolutional results using a low-bit-width accumulator while maintaining model accuracy.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method, apparatus and medium for implementing a convolutional structure that can avoid overflow. Background Technology

[0002] Deep neural network models for intelligent vision applications have a large number of parameters and extremely high computational complexity, which hinders their application in mobile and embedded devices where computational power, size, and power consumption are limited. Registers are storage devices in computers used to temporarily store data; they can store operands, addresses, status flags, and other data. An accumulator is a special type of register primarily used to store the results of operations. When performing arithmetic operations such as addition, subtraction, multiplication, and division, the results are typically stored in the accumulator. Many processor integer calculation instructions are more efficient than their corresponding floating-point calculations, and the complexity of multiplication is usually proportional to the square of the bit width of the operands; therefore, reducing the precision of the representation can effectively reduce complexity. Low-bit quantization of deep learning models can effectively reduce the overhead of storage, computation, and communication during model deployment, and is a common model compression and inference optimization technique. For convolutional neural network quantization, using accumulators with lower bit widths to store intermediate convolution results can improve the efficiency of convolution operations, but this can lead to serious overflow problems of intermediate result values, affecting model accuracy.

[0003] Existing overflow-aware quantization algorithms are heuristic, only considering narrowing the integer range of quantized model parameters and feature values ​​based on the overflow level of each layer, often wasting a significant amount of integer representation space. Furthermore, in low-bit quantization, this often leads to a noticeable loss of model accuracy. The structural design of ordinary convolutional layers requires numerous multiply-accumulate operations, greatly increasing the risk of numerical overflow in low-bit accumulators. Existing lightweight convolutions group convolutions, significantly reducing the overflow probability of accumulators during the convolution process. However, the expressive power of lightweight convolutions is significantly lower than that of ordinary convolutions, resulting in a significantly lower performance ceiling for them. Summary of the Invention

[0004] In order to at least partially solve one of the technical problems existing in the prior art, the present invention aims to provide a method, apparatus and medium for implementing a convolutional structure that can avoid overflow.

[0005] The technical solution adopted in this invention is:

[0006] An implementation method based on an overflow-avoidable convolutional structure includes the following steps:

[0007] Design a convolutional structure with low bit quantization to avoid overflow; wherein the convolutional structure performs grouped convolution on the input channels and the output is the sum of the grouped convolutions;

[0008] Design a matching quantization perception training method, and use different methods to quantize different parameters in the convolutional structure.

[0009] Furthermore, the convolutional structure is implemented using an accumulator with a relatively low bit width.

[0010] Furthermore, the convolutional structure operates as follows:

[0011] The number of input channels in a convolutional layer is C in The number of output channels is C out The kernel size is k*k, the convolutional layer parameter W has dimensions Cout*Cin*k*k, and the input feature F in The dimension is C in / H*W, where H and W are the length and width of the input feature, respectively; grouping the input channels into groups of N, we can divide them into G=C in / N groups;

[0012] For output channel j, calculate the convolution result for each group.

[0013] Convolution results of each group The input is fed into the BatchNorm layer and the activation layer, and the convolution results of different groups belonging to the same output channel j are combined. Adding them together yields the output feature Fout of the j-th channel of the convolutional layer. j .

[0014] Furthermore, the convolution result The calculation formula is as follows:

[0015]

[0016] In the formula, W represents the convolution operation; j,i,:,: The dimension of is k*k, representing the convolution kernel parameters corresponding to the j-th output channel and the ith input channel of the current convolutional layer; Fin i,:,: The dimension is H*W, which represents the image feature of the i-th input channel of the current convolutional layer;

[0017]

[0018] In the formula, BatchNorm() represents the normalization operation in the proposed convolutional structure, which is a commonly used normalization operator in neural networks; ReLU() represents the feature activation operation in the proposed convolutional structure, which is a commonly used activation function in neural networks.

[0019] Furthermore, the accompanying quantization-aware training method uses different methods to quantize different parameters in the convolutional structure, including:

[0020] For activation values ​​in a convolutional structure, layer-wise quantization is used; for convolution parameters in a convolutional structure, channel-wise quantization is used.

[0021] After quantization, a full integer inference process is executed; during deployment, the BatchNorm layer in the convolutional structure is integrated into the adjacent previous grouped convolutional layer, so the inference process does not involve BatchNorm operations.

[0022] Furthermore, the step of using layer-wise quantization for activation values ​​in the convolutional structure and channel-wise quantization for convolutional parameters in the convolutional structure includes:

[0023] Using a uniform and symmetric quantization method, the integer q is mapped to the real number r, as shown in the following expression:

[0024] r=S*q (1)

[0025] In the formula, r is the original unquantized weights and activation values, q is the quantized integer value, and S is the quantization parameter;

[0026] For activation values, the same quantization parameter is used for activation values ​​in each layer, i.e., layer-wise quantization;

[0027] For the weights, the weights of each channel use the same quantization parameter, i.e., channel-wise quantization.

[0028] Furthermore, the quantization is 8-bit quantization;

[0029] After quantization, a full integer inference process is performed, including:

[0030] Quantize the input features and convolution parameters into 8-bit integers:

[0031] The first convolution step yields intermediate group convolution results, which are then stored in a 16-bit wide accumulator.

[0032] The intermediate grouped convolution results are downscaled from 16-bit to 8-bit, and then the intermediate quantized feature values ​​of the 8-bit type are saturated and projected.

[0033] The intermediate group convolution results are summed to obtain 16-bit quantized feature values ​​for the corresponding output channels, and then downscaled to 8-bit quantized feature values, which are used as inputs for the next layer.

[0034] Furthermore, the quantization of the input features and convolution parameters into 8-bit integers includes:

[0035] Define the matrix in the reasoning process as:

[0036] r3=r1r2 (2)

[0037] In the formula, r1 and r2 are input matrices of size N*N, and r3 is the output result of matrix multiplication;

[0038] Combining formulas (1) and (2), we obtain formula (3):

[0039]

[0040] In the formula, S1, S2, and S3 are the quantization coefficients that map integers q1, q2, and q3 to the real number space, respectively. Let r be the integer corresponding to the element in the i-th row and j-th column of the input matrix r1. Let be the integer corresponding to the element in the j-th row and k-th column of the input matrix r2. This is the integer corresponding to the element in the i-th row and k-th column of the matrix multiplication output r1;

[0041] According to formula (3), the following equation is obtained:

[0042]

[0043]

[0044] Where M is the overall scaling factor in the downscale process.

[0045] Another technical solution adopted in this invention is:

[0046] An implementation device based on an overflow-avoidable convolutional structure, comprising:

[0047] At least one processor;

[0048] At least one memory for storing at least one program;

[0049] When the at least one program is executed by the at least one processor, the at least one processor performs the method as described above.

[0050] Another technical solution adopted in this invention is:

[0051] A computer-readable storage medium storing a processor-executable program, which, when executed by a processor, performs the method described above.

[0052] The beneficial effects of this invention are: This invention proposes a convolutional structure that uses a low-bit accumulator to avoid numerical overflow, aiming to improve the inference efficiency of the model by using a low-bit-width accumulator to store intermediate convolutional results while maintaining model accuracy. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following description is provided with accompanying drawings of the relevant technical solutions in the embodiments of the present invention or the prior art. It should be understood that the accompanying drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a schematic diagram of a convolutional structure that can avoid overflow in an embodiment of the present invention;

[0055] Figure 2 This is a schematic diagram of the quantized full integer inference process in an embodiment of the present invention;

[0056] Figure 3 This is a flowchart illustrating the steps of an implementation method based on an overflow-avoidable convolutional structure in an embodiment of the present invention. Detailed Implementation

[0057] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0058] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0059] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0060] Furthermore, in the description of this invention, unless otherwise stated, "multiple" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0061] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0062] Terminology Explanation:

[0063] BatchNorm layer: The normalization layer used in the proposed convolutional structure is a commonly used normalization operator in neural networks. For the input feature values, the BatchNorm layer first performs a channel-wise normalization operation by subtracting the mean and dividing by the variance, and then performs channel-wise scaling and offset operations.

[0064] Layer-wise quantization: A quantization mode in which all model weights in a neural network layer share the same quantization parameter. The quantization parameter is S in formula (1).

[0065] Channel-wise quantization: A quantization mode in which model weights belonging to the same output channel in a neural network layer share the same quantization parameter. The quantization parameter is S in formula (1). Model weights belonging to different output channels do not share quantization parameters.

[0066] Downscale process: After multiplying two 8-bit matrices, the result is stored in a high-bit (e.g., 16-bit) accumulator. The high-bit (e.g., 16-bit) matrix multiplication result needs to be converted into an 8-bit output through scaling, shifting, and truncation operations for subsequent integer operations. This process of converting the result stored in the high-bit accumulator into an 8-bit output is the downscale process. Specifically, the 16-bit type is converted to an 8-bit type, and then saturated projection is performed, with a saturation range of [0, 255]. The downscale process can be seen as a fixed-point multiplication achieved by performing a multiplication using the integer scaling factor M0 (calculated in Equation 8) plus a rounding / shifting operation.

[0067] like Figure 3 As shown, this embodiment provides an implementation method based on an overflow-avoidable convolutional structure, including the following steps:

[0068] S1: Design a convolutional structure to avoid overflow. This convolutional structure performs grouped convolutions on the input channels, and the output is an accumulation of these grouped convolutions.

[0069] Optionally, step S1 specifically includes the following steps:

[0070] S1-1: Convolutional structures to avoid overflow, such as... Figure 1 As shown, the number of input channels in the convolutional layer is C. in The number of output channels is C out The kernel size is k*k, the convolutional layer parameter W has dimensions Cout*Cin*k*k, and the input feature F in The dimension is C in *H*W, where H and W are the length and width of the input feature, respectively. First, the input channels are grouped, with each group containing N input channels ( Figure 1 If N equals 2, then it can be divided into G = C in / N groups.

[0071] S1-2: For output channel j, first calculate the convolution result of each group.

[0072]

[0073] in, This represents the convolution operation. W in formula (1) j,i,:,: The dimension is k*k, Fin i,:,: The dimension is H*W. Here... Specifically, this means that a filter kernel of size k*k performs a convolution operation on features of size H*W. C can be calculated using formula (1). out* Convolution results of G groups

[0074] S1-3: Convert the convolution result The input is fed into the activation layer and the BatchNorm layer, and different groups belonging to the same output channel j are separated. Adding them together yields the output feature Fout of the j-th channel of the convolutional layer. j :

[0075]

[0076] S2: Design a matching quantization-aware training method, using different methods to quantize different parameters in the convolutional structure.

[0077] Optionally, step S2 specifically includes the following steps:

[0078] S2-1: For activation values, use layer-wise quantization. For convolution parameters, use channel-wise quantization. We intend to use a uniform symmetric quantization method to map integer q to real number r, as shown in the following formula:

[0079] r=S*q (3)

[0080] Where r represents the original unquantized weights and activation values, and q represents the quantized integer values. For example, with 8-bit quantization, q ∈ {-127, 126, ..., 126, 127}, or q ∈ {0, 1, ..., 254, 255}. S is the quantization parameter. For activation values, the same quantization parameter is used for each layer, i.e., layer-wise quantization. For weights, the same quantization parameter is used for the weights of each channel, i.e., channel-wise quantization.

[0081] S2-2: During deployment, the BatchNorm layer is integrated into the adjacent preceding grouped convolutional layer, so the inference process does not involve BatchNorm operations. For example... Figure 2 As shown, taking 8-bit quantization as an example, the specific process is as follows: steps A1-A4:

[0082] A1. Quantize the input features and convolution parameters into 8-bit integers. First, define the matrix in the inference process as:

[0083] r3=r1r2 (4)

[0084] Where r1 and r2 are N*N input matrices, and r3 is the output result of matrix multiplication. Combining formulas (3) and (4), we can obtain formula (5):

[0085]

[0086] We can obtain the following formula:

[0087]

[0088]

[0089] Where M is the overall scaling factor in the downscale process, which empirically always lies within the interval (0, 1), and therefore can be represented in a normalized form:

[0090] M=2 -n M0 (8)

[0091] Taking 8-bit quantization as an example, TensorFlow Lite uses int32 to represent the integer synthesis scaling factor M0 in the downscale process, but we want to use a lower number of bits, such as 16 bits, to represent M0.

[0092] A2. After the first convolution step, the intermediate group convolution results are obtained and stored in a low-bit-width accumulator (e.g., 16 bits). Since each group contains a small number of input channels, numerical overflow of the accumulator can be avoided.

[0093] A3. The intermediate group convolution results undergo a downscale process, converting them from 16-bit to 8-bit type, and then performing a saturated projection with a saturation range of [0, 255]. The downscale process can be seen as a fixed-point multiplication achieved by performing a multiplication using an integer scaling factor M0, plus a rounding shift operation. As shown in formula (8), M0 is located in the interval [0.5, 1), and n is a non-negative integer, so M0 is well-suited to represent fixed-point multipliers. For example, if int16 is used, the integer representing M0 is closest to 2. 15 The int16 value of M0. Since M0 > 0.5, this value is always at least 2. 14 Therefore, it always has a relative precision of at least 14 bits. Thus, multiplication with M0 can be implemented as fixed-point multiplication. Simultaneously, multiplying by 2... -n This step can be achieved through efficient displacement calculations.

[0094] A4. The convolution results of the intermediate groups are added together to obtain the 16-bit quantized feature value of the corresponding output channel, and then downscaled to an 8-bit quantized feature value, which is used as the input of the next layer.

[0095] In summary, existing methods are heuristic algorithms that only consider narrowing the integer range of model parameters and eigenvalues ​​after quantization based on the overflow level of each layer, thus wasting a significant amount of integer representation space. Furthermore, at low-bit quantization, numerical overflow may occur, leading to a loss of model accuracy. The method in this embodiment decomposes the cumulative multiplication and addition steps of the convolution process, avoiding continuous large-scale cumulative multiplication and addition operations, thereby preventing numerical overflow in the accumulator. Simultaneously, the BatchNorm operation is used to normalize the cumulative multiplication and addition results of multiple groups, making their distribution range controllable. Then, by fusing the results of multiple groups, information exchange between channels is performed, maximizing the preservation of the expressive power of the convolutional layer.

[0096] As an optional implementation, the overflow-avoiding convolutional structure proposed in this embodiment can be implemented using an accumulator with a lower bit width, ensuring that the quantized model does not experience numerical overflow and maintains an accuracy similar to the original model. Furthermore, compared to the traditional quantized convolution process, this embodiment significantly reduces the number of bits required to store intermediate feature maps, improving the parallel computing efficiency of the device.

[0097] This embodiment also provides an implementation apparatus based on an overflow-avoidable convolutional structure, including:

[0098] At least one processor;

[0099] At least one memory for storing at least one program;

[0100] When the at least one program is executed by the at least one processor, the at least one processor performs the following: Figure 3 The method shown.

[0101] This embodiment provides an implementation device based on an overflow-avoidable convolutional structure, which can execute the overflow-avoidable convolutional structure implementation method provided in the method embodiment of the present invention, and can execute any combination of implementation steps of the method embodiment, possessing the corresponding functions and beneficial effects of the method.

[0102] This application also discloses a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device can read the computer instructions from the computer-readable storage medium and execute the computer instructions, causing the computer device to perform... Figure 3 The method shown.

[0103] This embodiment also provides a storage medium storing instructions or programs that can execute the implementation method based on an overflow-avoidable convolutional structure provided in the method embodiment of the present invention. When the instructions or programs are run, any combination of implementation steps of the method embodiment can be executed, and the method has the corresponding functions and beneficial effects.

[0104] In some alternative embodiments, the functions / operations mentioned in the block diagrams may not occur in the order shown in the operation diagrams. For example, depending on the functions / operations involved, two consecutively shown blocks may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order. Furthermore, the embodiments presented and described in the flowcharts of this invention are provided by way of example to provide a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is altered and sub-operations described as part of a larger operation are executed independently.

[0105] Furthermore, although the invention has been described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the described functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the invention. Rather, given the properties, functions, and internal relationships of the various functional modules in the apparatus disclosed herein, the actual implementation of the module will be understood within the scope of conventional skill of an engineer. Therefore, those skilled in the art can implement the invention as set forth in the claims using ordinary techniques without excessive experimentation. It is also understood that the specific concepts disclosed are merely illustrative and not intended to limit the scope of the invention, which is determined by the full scope of the appended claims and their equivalents.

[0106] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0107] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device.

[0108] More specific examples of computer-readable media (a non-exhaustive list) include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0109] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0110] In the foregoing description of this specification, references to terms such as "one embodiment," "another embodiment," or "some embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0111] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0112] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A method for implementing a convolutional structure that avoids overflow, characterized in that, Includes the following steps: Design convolutional structures to avoid overflow; The convolutional structure described therein performs grouped convolutions on the input channels, and the output is the sum of the grouped convolutions; Design a corresponding quantization-aware training method, using different methods to quantize different parameters in the convolutional structure, including: For activation values ​​in a convolutional structure, layer-wise quantization is used; for convolutional parameters in a convolutional structure, channel-wise quantization is used. After quantization, a full integer inference process is executed; during deployment, the BatchNorm layer in the convolutional structure is integrated into the adjacent previous grouped convolutional layer, so the inference process does not involve BatchNorm operations; The quantization is 8-bit quantization; after quantization, a full integer inference process is performed, including: Quantize the input features and convolution parameters into 8-bit integers: The intermediate group convolution results are obtained after the first convolution step and stored in a 16-bit wide accumulator; The intermediate grouped convolution results are downscaled from 16-bit to 8-bit, and then the intermediate quantized feature values ​​of the 8-bit type are saturated and projected. The intermediate group convolution results are summed to obtain 16-bit quantized feature values ​​for the corresponding output channels, and then downscaled to 8-bit quantized feature values, which are used as inputs for the next layer. The convolutional structure works as follows: The number of input channels of a convolutional layer is The number of output channels is The kernel size is Convolutional layer parameters The dimension is Input features The dimension is , and These are the length and width of the input feature, respectively; the input channels are grouped, with each group containing... Each input channel is divided into Groups; For output channels Calculate the convolution result for each group. , =1, 2, …, G ; Convolution results of each group The input is fed into the BatchNorm layer and the activation layer, and those belonging to the same output channel are... Convolution results of different groups Add them together to get the first convolutional layer. Output characteristics of each channel ; The convolution result The calculation formula is as follows: In the formula, This represents the convolution operation; The dimension is , indicating the corresponding number of the current convolutional layer The output channel and the first Convolution kernel parameters for each input channel; The dimension is , indicating the th convolutional layer Image features of each input channel; The output features The calculation formula is as follows: In the formula, This represents the normalization operation in a convolutional structure. This represents the eigenvalue activation operation in the convolutional structure.

2. The implementation method based on an overflow-avoidable convolutional structure according to claim 1, characterized in that, The activation values ​​in the convolutional structure are quantized using layer-wise quantization; the convolutional parameters in the convolutional structure are quantized using channel-wise quantization, including: Using a uniform and symmetric quantization method, integers are... Mapping to real numbers The expression is as follows: （1） In the formula, These are the original, unquantized weights and activation values. It is the quantized integer value. These are quantization parameters; For activation values, the same quantization parameter is used for activation values ​​in each layer, i.e., layer-wise quantization; For the weights, the weights of each channel use the same quantization parameter, i.e., channel-wise quantization.

3. The implementation method based on an overflow-avoidable convolutional structure according to claim 2, characterized in that, The step of quantizing the input features and convolution parameters into 8-bit integers includes: Define the matrix in the reasoning process as: （2） In the formula, and It is the input matrix. It is the output of matrix multiplication; Combining formulas (1) and (2), we obtain formula (3): （3） In the formula, , , They are respectively integers Quantization coefficients mapped to the real number space. For the input matrix The first in Line 1 The integers corresponding to the elements of the column. For the input matrix The first in Line 1 The integers corresponding to the elements of the column. The output of matrix multiplication The first in Line 1 The integers corresponding to the elements of the column; According to formula (3), the following equation is obtained: （4） （5） in, It is the overall scaling factor in the downscale process.

4. An implementation device based on an overflow-avoidable convolutional structure, characterized in that, include: At least one processor; At least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements the method of any one of claims 1-3.

5. A computer-readable storage medium storing a processor-executable program, characterized in that, The processor-executable program, when executed by the processor, is used to perform the method as described in any one of claims 1-3.

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