Microprocessing Chip and Code Download Method

Abstract

The present application relates to the field of chip testing technology, and specifically to a microprocessor chip and a code downloading method. The microprocessor chip is provided with a first-in-first-out FIFO module, a state machine, a bus module and a storage module; wherein the FIFO module is used to receive a test excitation signal based on an external clock and perform time domain conversion on the test excitation signal; the state machine is used to encode the test excitation signal after the time domain conversion into a bus signal; the bus module is used to transmit the bus signal to the storage module to realize the downloading, storage and / or programming of the code data. The microprocessor chip and the code downloading method provided by the present application are helpful to improve the downloading speed of the code data and improve the testing efficiency of the chip.

Description

Technical Field

[0001] This application relates to the technical field of chip testing, and particularly to a microprocessor chip and a code downloading method. Background Art

[0002] With the wide application of System on Chip (SoC) in recent years, solving the testability problem of SoC chips has become a hot topic of concern and research. There are mainly two tests during the chip production process: Chip Probing (CP) and Final Test (FT). Among them, the FT test is to test the packaged chip, which generally requires more strict requirements and aims to detect faulty chips as much as possible. In related technologies, test codes are generally downloaded into the chip through the Joint Test Action Group (JTAG) for testing, but this method has problems such as slow download speed, affecting chip test efficiency and test cost. Summary of the Invention

[0003] In view of this, this application provides a microprocessor chip and a code downloading method, which helps to improve the download speed of code data and the test efficiency of the chip.

[0004] In a first aspect, an embodiment of the present invention provides a microprocessor chip, which is provided with a First Input First Output (FIFO) module, a state machine, a bus module, and a storage module; wherein,

[0005] The FIFO module is configured to receive a test excitation signal based on an external clock and perform time-domain conversion on the test excitation signal;

[0006] The state machine is configured to encode the time-domain converted test excitation signal into a bus signal;

[0007] The bus module is configured to transmit the bus signal to the storage module to implement the download storage and / or programming of code data.

[0008] In some embodiments, the test excitation signal includes one or a combination of more of the following: a reset signal, code length information, an incoming start address, code data, a data valid signal, and a transmission end flag, wherein:

[0009] The reset signal is used to reset the external clock and the FIFO module;

[0010] The code length information is used to count the transmitted code data and / or perform data verification after the transmission of the code data;

[0011] The incoming start address is used to indicate the storage start address of the code data;

[0012] The code data is stored with the specified address as the storage start address and in the order of increasing address;

[0013] The data valid signal is used to indicate that the currently incoming code data is valid data;

[0014] The transmission end flag is used to indicate the end of the transmission of the code data, and is also used to indicate that CRC check is performed on the code data and the check result is transmitted externally.

[0015] In some embodiments, the FIFO module is an asynchronous FIFO, which is used to realize the temporary storage of the code data and the clock domain conversion;

[0016] The FIFO module includes: a multi-bit code signal pin; when the test excitation signal includes the code data and the incoming start address, the code data and the incoming start address share the multi-bit code signal pin time-division multiplexing.

[0017] In some embodiments, the microprocessing chip is further provided with a check module;

[0018] The check module includes a sending end and a receiving end. The sending end is used to receive the data transmitted by the IO port of the microprocessing chip, and the receiving end is connected to the read data port of the FIFO module;

[0019] The check module is specifically configured to perform CRC check calculation on the code data obtained by the receiving end and the CRC initial value to obtain a CRC check result and temporarily store it in the data register; when the receiving end obtains the next valid code data, perform CRC check calculation on the currently obtained code data and the CRC check result stored in the data register to obtain a new CRC check result; when the transmission of the code data ends, compare the finally calculated CRC check result with the CRC reference value obtained externally. If the comparison is consistent, the alarm signal remains low; if the comparison is inconsistent, the alarm signal is pulled high.

[0020] In some embodiments, the state machine includes:

[0021] An idle state. When the bus module is reset and idle, the state machine is in the idle state. When the FIFO module receives valid data, it switches from the idle state to the bus request state;

[0022] A bus request state, which is used to initiate a bus receive request to the bus module, and after the bus module responds to the bus receive request, it switches to the start state and unconditionally jumps to the address and command transmission state;

[0023] An address and command transmission state, which is used to send the address and command included in the test excitation signal to the bus module and jump to the data transmission state when the bus module is idle;

[0024] A data transmission state, which is used to transmit the code data included in the test excitation signal to the bus module. When the bus module is idle and the transmission of the code data is not finished, it jumps back to the address and command transmission state;

[0025] A verification state, which is used to enter the state of performing CRC verification on the code data when the transmission of the code data ends, and unconditionally jumps to the idle state after the verification of the code data is finished.

[0026] In a second aspect, an embodiment of the present invention provides a method for downloading code of a microprocessing chip, and the method includes:

[0027] Receiving a test excitation signal based on an external clock and performing time-domain conversion on the test excitation signal;

[0028] Encoding the time-domain converted test excitation signal into a bus signal;

[0029] Storing the bus signal to implement the download storage and / or programming of code data.

[0030] In some embodiments, the test excitation signal includes one or a combination of more of the following: a reset signal, code length information, an incoming start address, code data, a data valid signal, and a transmission end flag, where:

[0031] The reset signal is used to reset the external clock and the FIFO module. The beneficial effect is to reset the external clock, drive the excitation signal and related logic. The reset signal is used to reset the related logic at the start of each download to prevent the occurrence of an uncertain state;

[0032] The code length information is used to count the transmitted code data and / or for data verification after the transmission of the code data ends;

[0033] The incoming start address is used to indicate the storage start address of the code data;

[0034] The code data is stored with the specified address as the storage start address and in the order of increasing address, which can meet the requirements of programming the storage device and downloading to a preset allocated area, improving the utilization and programming flexibility of the storage device;

[0035] The data valid signal is used to indicate that the currently incoming code data is valid data;

[0036] The transmission end flag is used to indicate the end of the transmission of code data, and is used to indicate performing a CRC check on the code data and transmitting the check result externally.

[0037] Beneficial effects of the code length information and the combination of code data: Code download realizes the verification of data after crossing clock domains between the sending end and inside the chip. The CRC hardware implementation algorithm is used to verify the start address and data information, preventing abnormalities from occurring to the valid signal after passing through the chip IO and crossing clock domains.

[0038] In some embodiments, the method further includes:

[0039] When valid code data is obtained, perform a CRC check calculation on the code data and the CRC initial value, obtain the CRC check result and temporarily store it in the data register.

[0040] When the receiving end obtains the next valid code data, perform a CRC check calculation on the currently obtained code data and the CRC check result stored in the data register to obtain a new CRC check result.

[0041] When the transmission of code data ends, compare the finally calculated CRC check result with the CRC reference value obtained externally. If the comparison is consistent, the alarm signal remains low; if the comparison is inconsistent, the alarm signal is pulled high.

[0042] In some embodiments, encoding the test excitation signal after time domain conversion into a bus signal includes state transitions of a state machine, including:

[0043] Idle state. When the bus module is reset and idle, the state machine is in the idle state, and when the FIFO module receives valid data, it switches from the idle state to the bus request state.

[0044] Bus request state, used to initiate a bus reception request to the bus module, and after the bus module responds to the bus reception request, switch to the start state and unconditionally jump to the address and command transmission state.

[0045] Address and command transmission state, used to send the address and command included in the test excitation signal to the bus module, and jump to the data transmission state when the bus module is idle.

[0046] Data transmission state, used to transmit the code data included in the test excitation signal to the bus module. When the bus module is idle and the transmission of the code data has not ended, jump back to the address and command transmission state.

[0047] The verification state is used to enter the state of performing CRC verification on the code data when the code data transmission ends, and unconditionally jumps to the idle state after the verification of the code data ends.

[0048] In some embodiments, the test excitation signal containing code data can be encoded into a bus signal and transmitted to the storage module for storage. In this way, there is no situation of modifying the code data in the storage module, and the download and storage of the code data in the storage module are realized.

[0049] In some embodiments, the test excitation signal containing code data can be encoded into a bus signal and transmitted to the storage module to replace and store some of the code data in the storage module. In this way, there is a situation of modifying the code data in the storage module, and the programming of the code data in the storage module can be realized.

[0050] In the embodiments of the present invention, the FIFO module performs time-domain conversion on the externally input test excitation signal, which is beneficial to the transmission of the test excitation signal between the various modules of the microprocessing chip. Moreover, in the embodiments of the present invention, the test excitation signal is converted into a bus signal, and the code data can be transmitted to other modules of the microprocessing chip or stored in a bus manner through the internal bus architecture of the microprocessing chip, realizing the download and storage or programming function of the code data. Compared with the single-line download mode, the present invention's embodiment of downloading code data in a bus manner helps to improve the code download speed and the test efficiency of the chip. Description of the Drawings

[0051] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0052] Figure 1 It is a schematic structural diagram of a microprocessing chip provided by an embodiment of the present invention;

[0053] Figure 2 It is another schematic structural diagram of a microprocessing chip provided by an embodiment of the present invention;

[0054] Figure 3 It is still another schematic structural diagram of a microprocessing chip provided by an embodiment of the present invention;

[0055] Figure 4 It is a flowchart of a code download method for a microprocessing chip provided by an embodiment of the present invention;

[0056] Figure 5Flowchart of another method for downloading code of the microprocessing chip provided by an embodiment of the present invention;

[0057] Figure 6 Flowchart of a method for performing CRC check on code data provided by an embodiment of the present invention;

[0058] Figure 7 Schematic diagram of state transition of a state machine provided by an embodiment of the present invention. Detailed implementation manners

[0059] For a better understanding of the technical solution of the present application, the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0060] It should be clear that the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.

[0061] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "the" and "said" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0062] It should be understood that the term " / and / " used herein is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, a and / or b can represent: a exists alone, a and b exist simultaneously, and b exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after.

[0063] See Figure 1 , which is a schematic diagram of the structure of a microprocessing chip provided by an embodiment of the present invention. Figure 1 The microprocessing chip shown can be a control module, a digital signal processing (DSP) chip, a microprocessor unit (MPU), a micro CPU, etc., which can process digital signals, analog signals, or can perform functions such as signal control, instruction processing, and operation, such as a micro central control chip, a system-on-chip. The embodiments of the present invention do not specifically limit the chip implementation form of the microprocessing chip.

[0064] In order to implement code downloading and chip testing in the microprocessing chip, a download hardware module is provided in the microprocessing chip of the embodiment of the present invention. As Figure 1As shown in the figure, the download hardware module includes a FIFO module, a state machine, a bus module, and a storage module. Among them, the FIFO module can be connected to a test signal generation module outside the chip to receive the test excitation signal generated by the test signal generation module. Optionally, the test signal generation module and the microprocessing chip can use different clocks. After receiving the test excitation signal based on the external clock, the FIFO module performs time-domain conversion on the test excitation signal. That is, the FIFO module converts the test excitation signal based on the external clock into a signal based on the microprocessing chip clock. The FIFO module transmits the time-domain converted test excitation signal to the state machine. The state machine is used to encode the time-domain converted test excitation signal into a bus signal and send it to the bus module. The bus module is used to transmit the bus signal to the storage module to implement the download storage and / or programming of code data. In some embodiments, the FIFO module can be an asynchronous FIFO to implement the temporary storage and clock domain conversion of code data.

[0065] In some embodiments, the test excitation signal containing code data can be encoded into a bus signal and transmitted to the storage module for storage. In this way, there is no situation of modifying the code data in the storage module, and the download storage of the code data in the storage module is realized.

[0066] In some embodiments, the test excitation signal containing code data can be encoded into a bus signal and transmitted to the storage module to replace and store some of the code data in the storage module. In this way, there is a situation of modifying the code data in the storage module, and the programming of the code data in the storage module can be realized.

[0067] In the embodiments of the present invention, the time-domain conversion of the externally input test excitation signal by the FIFO module is beneficial to the transmission of the test excitation signal between the various modules of the microprocessing chip. Moreover, in the embodiments of the present invention, the test excitation signal is converted into a bus signal, and the code data can be transmitted to other modules or stored in the microprocessing chip in a bus manner through the internal bus architecture of the microprocessing chip, realizing the download storage or programming function of the code data. Compared with the single-line download mode, the bus-based download of code data in the embodiments of the present invention helps to improve the code download speed and the test efficiency of the chip.

[0068] See Figure 2 , which is a schematic structural diagram of another microprocessing chip provided by the embodiments of the present invention. On the basis of the Figure 1 shown microprocessing chip structure, Figure 2The microprocessor chip shown also includes a verification module. The verification module is used to perform CRC verification on the test excitation signal, specifically, on the code data included in the test excitation signal, and generate an alarm signal when the verification fails. In the embodiments of the present invention, the CRC verification of the code data can prevent the code data from being abnormal after passing through the chip IO port and across the clock domain.

[0069] As Figure 2 shown, the verification module may include a sending end and a receiving end. The sending end is used to receive the data transmitted by the IO port of the microprocessor chip, and the receiving end is connected to the read data port of the FIFO module. Among them, the verification module is specifically used to perform CRC verification calculation on the code data obtained by the receiving end and the CRC initial value, obtain the CRC verification result and temporarily store it in the data register. When the receiving end obtains the next valid code data, the verification module performs CRC verification calculation on the currently obtained code data and the CRC verification result stored in the data register to obtain a new CRC verification result. When the transmission of the code data ends, the finally calculated CRC verification result is compared with the CRC reference value obtained from the outside. If the comparison is consistent, the alarm signal remains low; if the comparison is inconsistent, the alarm signal is pulled high.

[0070] See Figure 3 , which is a schematic structural diagram of another microprocessor chip provided by the embodiments of the present invention. In the Figure 3 structure shown, Figure 1 and Figure 2 the bus modules shown in can be implemented as an AHB host interface, and the storage module can be implemented as an SRAM. The AHB host interface is connected to the SRAM through AMBA AHB. In the Figure 3 microprocessor chip shown, due to the time-domain conversion of the test excitation signal input from the outside by the FIFO module, the state machine, AHB host interface, AMBA AHB, SRAM, and verification module are all in the local clock domain of the microprocessor chip. The input part of the FIFO module is in the external clock domain.

[0071] The following will be combined with the Figures 1 - 3 microprocessor chip shown to illustrate the test excitation signal transmitted from the outside.

[0072] In some embodiments, the test excitation signal may include one or a combination of more of: a reset signal, code length information, an incoming start address, code data, a data valid signal, and a transmission end flag. Among them:

[0073] The reset signal is used to reset the external clock and the FIFO module. The external clock and the related logic for driving the excitation signal can be reset through the reset signal. The reset signal can be used to reset the related logic at each download start to prevent the appearance of an uncertain state.

[0074] The code length information is used to count the transmitted code data and / or for data verification after the transmission of the code data ends. Based on the code length information, data verification can be performed on the code data at the chip sending end and after crossing the clock domain inside the chip. Optionally, the data verification can be CRC verification, that is, the start address and data information are verified through the CRC hardware implementation algorithm to prevent abnormalities in the code data after passing through the chip IO and crossing the clock domain.

[0075] The incoming start address is used to indicate the storage start address of the code data, which is beneficial for downloading the code data to the preset allocation area of the storage module.

[0076] The code data is stored with the specified address as the storage start address and in the order of increasing addresses. This storage method of the code data is beneficial for downloading and storing the code data to the preset allocation area of the storage module, improving the utilization and programming flexibility of the storage device. Moreover, this storage method of the code data supports continuous writing of data to addresses incrementing by word and supports continuous writing of data to different addresses.

[0077] The data valid signal is used to indicate that the currently incoming code data is valid data.

[0078] The transmission end flag is used to indicate the end of the transmission of the code data and is used to indicate performing CRC verification on the code data and transmitting the verification result to the outside. The possible signal conditions of the test excitation signal will be described below in combination with different embodiments.

[0079] In some embodiments, the test excitation signal received by the FIFO module from the outside may include code data and a data valid signal. Among them, the code data may be test code to be downloaded, etc. The data valid signal is used to indicate that the currently incoming code data is valid data. Optionally, the currently incoming code data is transmitted to the storage module in the form of bus data after time-domain conversion by the FIFO module and bus format conversion by the state machine. When the code data is stored in the storage module, it starts storing at a specified address and stores in the order of increasing address. In the embodiments of the present invention, the code data starts storing at a specified address and stores in the order of increasing address, supporting continuous writing of data to addresses increasing by word and supporting continuous writing of data to different addresses, realizing the orderly storage of code data in the storage module. In some embodiments, the specified address may be a preset fixed address; in other embodiments, the specified address may be an address incoming from the outside. For example, the externally input test excitation signal includes an incoming start address, and the incoming start address incoming from the outside is used to represent the above-mentioned specified address. In some embodiments, the FIFO module includes: a multi-bit code signal pin; when the test excitation signal includes the code data and the incoming start address, the code data and the incoming start address share the multi-bit code signal pin time-division multiplexing.

[0080] In some embodiments, the test excitation signal received by the FIFO module from the outside includes a reset signal, code data, a data valid signal, and a transmission end flag. Among them, before the start of code data transmission, the FIFO module obtains the reset signal from outside the chip, and the external clock and the FIFO module can be reset through the reset signal. After that, the FIFO module obtains the code data and the data valid signal. When the FIFO module receives the transmission end flag, it determines that the code data transmission ends.

[0081] In some embodiments, the test excitation signal may further include a transmission start flag. When the FIFO module receives the transmission start flag after receiving the reset signal, the transmission start flag is used to indicate the start of code data transmission. Optionally, the transmission start flag and the transmission end flag can share the same signal pin of the FIFO module time-division multiplexing. Before the start of code data transmission, this signal pin can be set to a first voltage signal, and this first voltage signal is used as the transmission start flag. When the code data transmission ends, this signal pin can be set to a second voltage signal, and this second voltage signal is used as the transmission end flag. Optionally, the first voltage signal can be a high-level signal, and the second voltage signal can be a low-level signal.

[0082] In some embodiments, the test excitation signal received by the FIFO module from the outside may include code data, a data valid signal, and a transmission end flag. In this embodiment, the transmission of the code data is directly started, and there is no need to set a reset signal before the transmission of the code data.

[0083] In some embodiments, when the microprocessing chip is in a specific time period, such as when the microprocessing chip is in a reset state, the test excitation signal may only include a reset signal.

[0084] In the above embodiments, CRC verification of the code data is not considered. In some other embodiments, a CRC verification mechanism can be designed. For example, the test excitation signal received by the FIFO module from the outside includes a reset signal, code data, a data valid signal, and a transmission end flag. Among them, before the start of the code data transmission, the FIFO module obtains the reset signal from outside the chip, and the external clock and the FIFO module can be reset through the reset signal. After that, the FIFO module obtains the code data and the data valid signal. When the FIFO module receives the transmission end flag, it determines that the code data transmission is over and starts the CRC verification of the code data. Specifically, the code data can be CRC-verified by a verification module.

[0085] In some embodiments, a custom test excitation signal is provided. The custom test excitation signal may include a reset signal, a multi-bit code signal, a data valid signal, and a download start end flag signal. For the functions of the reset signal and the data valid signal, refer to the above description and will not be elaborated here. The following will further explain the multi-bit code signal and the download start end flag signal.

[0086] In some embodiments, the multi-bit code signal can be used to represent the above-mentioned incoming start address at the start stage of the code data download, and then used to represent the code data. In a specific implementation, the FIFO module may have a multi-bit code signal pin, and the incoming start address and the code data can time-division multiplex the multi-bit code signal pin to respectively obtain the incoming start address and the code data input from the outside. In some other embodiments, the code length information, the incoming start address, and the code data can time-division multiplex the multi-bit code signal pin, thereby respectively obtaining the code length information, the incoming start address, and the code data input from the outside. In the embodiments of the present invention, multiple signals time-division multiplex the signal pins of the FIFO module, which can reduce the number of IO ports used by the microprocessing chip.

[0087] In some embodiments, the download start / end flag signal is a first voltage signal when starting to download code data, indicating the start of code data transmission, i.e., the above-mentioned transmission start flag. When the code data transmission ends, the download start / end flag signal is a second voltage signal indicating the end of code data transmission, corresponding to the above-mentioned transmission end flag. In some embodiments, the first voltage signal can be a high-level signal and the second voltage signal can be a low-level signal. Optionally, the first voltage signal and the second voltage signal can occupy the same signal pin of the FIFO module. In some embodiments, in addition to indicating the end of code data transmission, the transmission end identifier can also be used to instruct the verification module to perform CRC verification on the code data and transmit the verification result externally.

[0088] Combined with Figures 1 to 3 the microprocessor chip shown, an embodiment of the present invention provides a method for downloading code of a microprocessor chip. As Figure 4 shown, the processing steps of this method include:

[0089] 401. The FIFO module receives a test excitation signal based on an external clock, performs time-domain conversion on the test excitation signal, and transmits the time-domain converted test excitation signal to the state machine.

[0090] 402. The state machine encodes the time-domain converted test excitation signal into a bus signal.

[0091] 403. The bus module transmits the bus signal to the storage module to achieve downloading and storing and / or programming of code data.

[0092] In the embodiment of the present invention, performing time-domain conversion on the externally input test excitation signal by the FIFO module is beneficial to the transmission of the test excitation signal between the various modules of the microprocessor chip. And downloading code data in the form of a bus helps to improve the downloading speed of the code data and improve the test efficiency of the chip.

[0093] See Figure 5 , which is a flowchart of another method for downloading code of a microprocessor chip provided by an embodiment of the present invention. In the embodiment of the present invention, the above-mentioned test excitation signal includes a reset signal, code length information, incoming start address, code data, data valid signal, and download start / end flag signal. As Figure 5 shown, the process of the microprocessor chip downloading code data includes:

[0094] 501. The FIFO module receives the externally input reset signal, and performs clock and logic reset on the external clock and the FIFO module through the reset signal. In some embodiments, the FIFO module can transmit the reset signal to the verification module and perform clock and logic reset on the verification module.

[0095] 502. The FIFO module receives the externally input code length information, and after time domain conversion, transmits the code length information to the verification module. The code length information can be used to count the subsequently transmitted code data, and / or verify the code data after the transmission of the code data is completed.

[0096] 503. The FIFO module receives the externally input incoming start address, and after time domain conversion, sends it to the state machine. The state machine converts the incoming start address into the bus format and then sends it to the bus module. The incoming start address is used to represent the storage start address of the subsequently incoming code data. As Figure 3 shown, the state machine can send the incoming start address to the AHB host interface, and the AHB host interface can store the subsequently transmitted code data in the SRAM according to the incoming start address.

[0097] 504. The FIFO module receives the externally input download start end flag signal, code data, and data valid signal, and after time domain conversion, sends them to the state machine. The state machine converts the download start end flag signal, code data, and data valid signal into the bus format and then sends them to the bus module.

[0098] Among them, the download start end flag signal can be a high-level signal to serve as a transmission start flag indicating the start of the code data transmission, and the download start end flag signal remains high during the code data transmission process. The data valid signal is used to indicate that the currently incoming code data is valid data. After receiving the code data, the bus module (such as Figure 3 the AHB host interface in it) can use the incoming start address as the storage start address and store it in the storage module (such as Figure 3 the SRAM in it) in the address increment manner.

[0099] 505. When the download start end flag signal is at a low level, it serves as a transmission end flag indicating the end of the code data transmission, and the state machine instructs the verification module to verify the code data.

[0100] 506. After the verification module successfully verifies the code data, it sends a verification success signal to the state machine, and the state machine determines the end of the current download of the code data. Optionally, if the verification module fails to verify the code data, the verification module can issue an alarm signal.

[0101] In step 504 above, the download start end flag signal used to indicate the start of the code data transmission can be sent after the reset signal and before the code length information; of course, it can also be sent after the code length information and before the code data is sent. The sending timing of each signal can be adjusted according to the actual situation.

[0102] Through the method of the embodiments of the present invention, the orderly and reliable download of code data can be realized, the uncertain state during the download of code data can be prevented, and the abnormality of code data after passing through the chip IO port and across the clock domain can be prevented.

[0103] See Figure 6 , which is a flowchart of a method for performing CRC check on code data provided by the embodiments of the present invention. As Figure 6 shown, the processing steps of this method may include:

[0104] 601. The FIFO module receives the first code data input externally, performs time domain conversion on the first code data, and then sends it to the check module. It can be understood that the first code data after the FIFO time domain conversion is also sent to the state machine for storage in the storage module.

[0105] 602. The check module performs CRC calculation on the first code data using the CRC initial value to obtain the first CRC check result.

[0106] 603. The FIFO module receives the second code data input externally, performs time domain conversion on the second code data, and then sends it to the check module. It can be understood that the second code data after the FIFO time domain conversion is also sent to the state machine for storage in the storage module.

[0107] 604. The check module performs CRC calculation on the second code data using the first CRC check result to obtain the second CRC check result.

[0108] 605. The check module repeats the above steps 603 and 604 until the last data of the code data to be downloaded is received, and the finally calculated CRC check result is obtained.

[0109] 606. The check module receives the externally input CRC reference value.

[0110] 607. The check module compares the finally calculated CRC check result with the CRC reference value. If the comparison is consistent, the alarm signal remains low level; if the comparison is inconsistent, the alarm signal is pulled high.

[0111] In some embodiments, when calculating the CRC check result of the code data, the check module can use the code length information to count the code data or participate in the calculation of the CRC check result.

[0112] In the embodiments of the present invention, the code data sent to the check module has passed through the input of the IO port of the FIFO module and the conversion across the clock domain. Through the CRC check of the code data by the check module, the abnormality of the code data after passing through the chip IO port and across the clock domain can be prevented.

[0113] SeeFigure 7 , is a schematic diagram of state transition of a state machine provided by an embodiment of the present invention. Figure 7 As shown, the state machine includes: idle state (IDLE state), bus request state (BUSREQ state), start state (START state), address and command transmission state (ADDR state), data transmission state (WD state) and check state (CRC state). The transition conditions between states are:

[0114] IDLE state: when the FIFO module receives a reset signal and the AHB bus is in an idle state, the state machine is in an idle state. When the FIFO receives valid data, it switches from the idle state to the BUSREQ state. The valid data received by the FIFO may be, for example, any one or more of the following signals: code length information, incoming startup address, download startup end flag signal, and data valid signal.

[0115] BUSREQ state, when FIFO receives valid data and switches to BUSREQ state, the state machine initiates a bus receive request to the AHB host interface. After responding to the bus receive request, the AHB host interface jumps to the START state and unconditionally jumps from the START state to the ADDR state.

[0116] ADDR state, in the ADDR state, the state machine transmits the address and command contained in the test stimulus signal to the AHB host interface, and jumps to the WD state when the AHB bus is idle. Among them, the address and command transmitted by the state machine to the AHB host interface may include the incoming startup address, the download startup end flag signal, the data valid signal, etc. When the state machine transmits the incoming startup address to the AHB host interface, the AHB host interface uses the incoming startup address as the storage start address of the subsequent incoming code data.

[0117] WD state: In the WD state, the AHB host interface downloads code data to the storage module through the AHB bus. When the AHB bus is idle and the transmission of code data is not completed, the state machine jumps back to the ADDR state until code data is received again.

[0118] CRC state, when the download start end flag signal indicates that the code data transmission is completed, the state machine jumps to the CRC check state and performs CRC check on the code data through the check module. When the check module completes the code data check, the state machine unconditionally jumps to the IDLE state.

[0119] In the embodiment of the present invention, the code data download process can be made to comply with the AHB host interface timing by controlling the state transition conditions of each state machine, which is beneficial for downloading the code data to the storage module through the AHB bus.

[0120] It should be understood that Figures 1 to 3 The division of each module of the microprocessing chip shown is only a schematic division. In specific implementation, each module can be combined or separated physically. On the basis of not considering the division of each module in the microprocessing chip, an embodiment of the present invention also provides a method for downloading code of a microprocessing chip, including:

[0121] Receiving a test excitation signal based on an external clock and performing time-domain conversion on the test excitation signal;

[0122] Encoding the time-domain converted test excitation signal into a bus signal;

[0123] Storing the bus signal to implement the download storage and / or programming of code data.

[0124] In some embodiments, the test excitation signal includes one or a combination of more of the following: a reset signal, code length information, an incoming start address, code data, a data valid signal, and a transmission end flag, where:

[0125] The reset signal is used to reset the external clock and the FIFO module;

[0126] The code length information is used to count the transmitted code data and / or for data verification after the transmission of the code data ends;

[0127] The incoming start address is used to indicate the starting address for storing the code data;

[0128] The code data is stored starting from a specified address and in an address increment manner;

[0129] The data valid signal is used to indicate that the currently incoming code data is valid data;

[0130] The transmission end flag is used to indicate the end of the transmission of the code data and to indicate performing a CRC check on the code data and transmitting the check result externally.

[0131] In some embodiments, the method further includes: when valid code data is obtained, performing a CRC check calculation on the code data and the CRC initial value to obtain a CRC check result and temporarily storing it in a data register;

[0132] When the receiving end obtains the next valid code data, performing a CRC check calculation on the currently obtained code data and the CRC check result stored in the data register to obtain a new CRC check result;

[0133] When the transmission of the code data ends, compare the finally calculated CRC check result with the CRC reference value obtained externally. If the comparison is consistent, the alarm signal remains at a low level; if the comparison is inconsistent, the alarm signal is pulled high.

[0134] In some embodiments, encoding the test excitation signal after time domain conversion into a bus signal includes state transitions of a state machine, which include:

[0135] Idle state. When the bus module is reset and idle, the state machine is in the idle state and switches from the idle state to the bus request state when the FIFO module receives valid data;

[0136] Bus request state, used to initiate a bus receive request to the bus module, and switch to the start state after the bus module responds to the bus receive request, and unconditionally jump from the start state to the address and command transmission state;

[0137] Address and command transmission state, used to send the address and command included in the test excitation signal to the bus module, and jump to the data transmission state when the bus module is idle;

[0138] Data transmission state, used to transmit the code data included in the test excitation signal to the bus module. When the bus module is idle and the transmission of the code data has not ended, jump back to the address and command transmission state;

[0139] Check state, used to enter the state of performing CRC check on the code data when the transmission of the code data ends, and unconditionally jump to the idle state after the check of the code data ends.

[0140] In some embodiments, storing the bus signal to implement the download storage and / or programming of the code data, which includes: The test excitation signal containing the code data can be encoded into a bus signal and transmitted to the storage module for storage to implement the download storage of the code data in the storage module; and / or

[0141] The test excitation signal containing the code data is encoded into a bus signal and transmitted to the storage module to replace and store some of the code data in the storage module for programming the code data in the storage module.

[0142] For the parts of the method in the embodiments of the present invention that are not described in detail in the implementation process and beneficial effects, reference can be made to Figures 1 - 7 the relevant descriptions, which will not be elaborated here.

[0143] Those of ordinary skill in the art will realize that the units and algorithm steps described in the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of electronic hardware. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0144] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working process of the microprocessing chip described above can refer to the corresponding process in the foregoing method embodiments and will not be elaborated herein. The above is only the specific implementation manner of this application. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in this application should be covered by the protection scope of this application. The protection scope of this application shall be subject to the protection scope of the claims.

Claims

1. A microprocessor chip, characterized in that, the microprocessor chip is provided with a FIFO module, a state machine, a bus module and a storage module; wherein, the FIFO module is used to receive a test excitation signal based on an external clock and perform time-domain conversion on the test excitation signal; the state machine is used to encode the time-domain converted test excitation signal into a bus signal; the bus module is used to transmit the bus signal to the storage module to realize the download storage and / or programming of code data; the test excitation signal includes: an incoming start address and code data; the incoming start address is used to indicate the storage start address of the code data; the code data replaces and stores part of the code data in the storage module; the replacing and storing part of the code data in the storage module includes: encoding the test excitation signal containing the code data into a bus signal and transmitting it to the storage module to replace and store part of the code data in the storage module, so as to realize the programming modification of the code data in the storage module; performing CRC check on the code data and code length information passing through the chip IO port and across time domains; the FIFO module is an asynchronous FIFO for realizing the temporary storage and clock domain conversion of the code data; the FIFO module includes: a multi-bit code signal pin; the code data and the incoming start address share the multi-bit code signal pin time-division multiplexing.

2. The chip according to claim 1, characterized in that, the test excitation signal includes one or a combination of more of: a reset signal, code length information, a data valid signal, a transmission end flag, wherein: the reset signal is used to reset the external clock and the FIFO module; the code length information is used to count the transmitted code data and / or for data verification after the transmission of the code data; the data valid signal is used to indicate that the currently incoming code data is valid data; the transmission end flag is used to indicate the end of the transmission of the code data and for indicating to perform CRC check on the code data and transmit the check result to the outside.

3. The chip according to claim 1, characterized in that, the microprocessor chip is further provided with a check module; the check module includes a sending end and a receiving end, the sending end is used to receive the data transmitted by the IO port of the microprocessor chip, and the receiving end is connected to the read data port of the FIFO module; the check module is specifically used to perform CRC check calculation on the code data obtained by the receiving end and the CRC initial value, obtain the CRC check result and temporarily store it in the data register; when the receiving end obtains the next valid code data, perform CRC check calculation on the currently obtained code data and the CRC check result stored in the data register to obtain a new CRC check result; when the transmission of the code data ends, compare the finally calculated CRC check result with the CRC reference value obtained from the outside. If the comparison is consistent, the alarm signal remains low level; if the comparison is inconsistent, the alarm signal is pulled high.

4. The chip according to claim 1, wherein, the state machine includes: an idle state, in which the state machine is in an idle state when the bus module is reset and idle, and switches from the idle state to a bus request state when the FIFO module receives valid data; a bus request state, used to initiate a bus receive request to the bus module, and switches to a start state after the bus module responds to the bus receive request, and unconditionally jumps from the start state to an address and command transmission state; an address and command transmission state, used to send the address and command included in the test excitation signal to the bus module, and jumps to a data transmission state when the bus module is idle; a data transmission state, used to transmit the code data included in the test excitation signal to the bus module. When the bus module is idle and the transmission of the code data is not completed, it jumps back to the address and command transmission state; a verification state, used to enter a state of performing CRC verification on the code data when the transmission of the code data ends, and unconditionally jumps to the idle state after the verification of the code data ends.

5. A method for downloading code of a microprocessing chip, wherein, the method includes: receiving a test excitation signal based on an external clock, and performing time-domain conversion on the test excitation signal; encoding the time-domain converted test excitation signal into a bus signal; storing the bus signal to implement the download storage and / or programming of code data; the test excitation signal includes: an incoming start address and code data; the incoming start address is used to indicate the storage start address of the code data; the code data is used to replace and store part of the code data in the storage module; the replacing and storing part of the code data in the storage module includes: encoding the test excitation signal including the code data into a bus signal and transmitting it to the storage module to replace and store part of the code data in the storage module, so as to implement the programming modification of the code data in the storage module; performing CRC verification on the code data and the code length information passing through the chip IO port and across time domains; the incoming start address and the code data are obtained through the multi-bit code signal pins of the time-division multiplexing FIFO module.

6. The method according to claim 5, wherein, the test excitation signal includes a combination of one or more of a reset signal, code length information, a data valid signal, and a transmission end flag, wherein: the reset signal is used to reset the external clock and the FIFO module; the code length information is used to count the transmitted code data and / or to perform data verification after the transmission of the code data ends; the data valid signal is used to indicate that the currently incoming code data is valid data; the transmission end flag is used to indicate the end of the transmission of the code data, and is used to indicate performing CRC verification on the code data and transmitting the verification result to the outside.

7. The method according to claim 5, wherein, the method further includes: When valid code data is obtained, perform CRC check calculation on the code data and the CRC initial value, obtain the CRC check result and temporarily store it in the data register; When the receiving end obtains the next valid code data, perform CRC check calculation on the currently obtained code data and the CRC check result stored in the data register to obtain a new CRC check result; When the code data transmission ends, compare the finally calculated CRC check result with the CRC reference value obtained from the outside. If the comparison is consistent, the alarm signal remains low level; if the comparison is inconsistent, the alarm signal is pulled high.

8. The method according to claim 7, characterized in that, encoding the test excitation signal after time domain conversion into a bus signal includes state transitions of a state machine, which include: Idle state, when the bus module is reset and idle, the state machine is in the idle state, and when the FIFO module receives valid data, it switches from the idle state to the bus request state; Bus request state, used to initiate a bus receive request to the bus module, and switch to the start state after the bus module responds to the bus receive request, and unconditionally jump from the start state to the address and command transmission state; Address and command transmission state, used to send the address and command included in the test excitation signal to the bus module, and jump to the data transmission state when the bus module is idle; Data transmission state, used to transmit the code data included in the test excitation signal to the bus module, and when the bus module is idle and the transmission of the code data has not ended, jump back to the address and command transmission state; Check state, used to enter the state of performing CRC check on the code data when the code data transmission ends, and unconditionally jump to the idle state after the check of the code data is completed.

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