Semiconductor packaging structure and its circuit board

Abstract

This invention relates to a semiconductor packaging structure and its circuit board. The semiconductor packaging structure includes a chip, a circuit board, and a filler adhesive. The circuit board includes a carrier, a patterned metal layer, and a protective layer. The surface of the carrier includes a circuit placement area, a chip placement area, and a current-conducting unit placement area. The chip is disposed in the chip placement area and electrically connected to multiple circuits of the patterned metal layer. At least one current-conducting unit of the patterned metal layer is disposed in the current-conducting unit placement area. The current-conducting unit includes a cutout and multiple current-conducting grooves. Each current-conducting groove communicates with the cutout and is arranged radially. The current-conducting grooves guide the protective layer to flow toward the cutout. The cutout and the current-conducting grooves guide the filler adhesive to flow toward the protective layer, so that the filler adhesive covers the protective layer to increase the structural strength of the semiconductor packaging structure.

Description

Technical Field

[0001] This invention relates to a semiconductor packaging structure and its circuit board, particularly a semiconductor packaging structure and its circuit board with radially arranged channel guides for a protective layer and filler adhesive. Background Technology

[0002] Please see Figure 1 A conventional circuit board 10 includes a carrier board 11, a plurality of circuits 12, and a protective layer 13. The surface 11a of the carrier board 11 includes a circuit placement area 11b and a chip placement area 11c. The circuits 12 are disposed in the circuit placement area 11b, and the internal pins 12a of each circuit 12 are located in the chip placement area 11c. The protective layer 13 covers the circuits 12 and exposes the internal pins 12a. A chip 20 is disposed in the chip placement area 11c and electrically connected to the internal pins 12a. A filler 30 is filled between the chip 20 and the circuit board 10 to form a semiconductor package structure.

[0003] Please see Figure 1 and Figure 2 When the protective layer 13 is formed in the circuit setting area 11b to cover the circuit 12, the protective layer 13 may overflow insufficiently on the outer side of the corner of the chip setting area 11c. Similarly, when the filler 30 is filled between the chip 20 and the circuit board 10, the filler 30 may overflow insufficiently on the outer side of the corner of the chip setting area 11c. As a result, an area 11d is formed on the outer side of the corner of the chip setting area 11c between the protective layer 13 and the filler 30, exposing the surface 11a. When a peeling test is performed, this area 11d will cause the filler 30 to peel off the carrier board 11, thus affecting the structural strength of the semiconductor package structure. Furthermore, the filler 30 peeling off the carrier board 11 will also cause the inner pin 12a to break off from the circuit 12. Summary of the Invention

[0004] The main objective of this invention is to provide at least one flow guiding unit on the outer corner of the chip placement area of ​​the carrier board. The multiple flow guiding grooves of the flow guiding unit are arranged radially, and the flow guiding grooves are connected to the cutout portion of the flow guiding unit. The flow guiding grooves guide the protective layer covering multiple lines to flow toward the cutout portion, and guide the filler adhesive filled between the chip and the circuit board to flow from the corner toward the protective layer, so that the filler adhesive covers the protective layer located in the flow guiding groove.

[0005] A semiconductor packaging structure of the present invention includes a chip, a circuit board, and a filler adhesive. The circuit board includes a carrier, a patterned metal layer, and a protective layer. The carrier has a surface including a circuit placement area, a chip placement area, and a current-conducting unit placement area. The circuit placement area is located outside the chip placement area. A first boundary and a second boundary of the chip placement area intersect at a corner. A first straight line extends along the first boundary, and a second straight line extends along the second boundary. The current-conducting unit placement area is located between the first and second straight lines. The patterned metal layer has multiple circuits and at least one current-conducting unit. The circuits are disposed in the circuit placement area, and the internal pins of each circuit are located in the chip placement area. The current-conducting unit is disposed in the current-conducting unit placement area and includes a cutout portion and multiple current-conducting grooves. The cutouts are connected and arranged radially. The cutouts are located between the corner and the flow guide grooves, and the cutouts are adjacent to the corner. Each flow guide groove has a first flow guide and a second flow guide that are connected. The first flow guide is connected to the cutout and is located between the cutout and the second flow guide. The protective layer covers the circuit and fills each of the second flow guides. The protective layer exposes the internal pin, the cutout, and the first flow guide. The chip is disposed in the chip placement area and is electrically connected to the internal pin. The filler is filled between the chip and the circuit board, and the filler covers the cutout, the first flow guide, and the protective layer located in the flow guide unit placement area and the second flow guide. The protective layer and the filler form a first overlapping bonding layer in each of the second flow guides.

[0006] Preferably, the flow guiding unit includes a plurality of spacer ribs, each spacer rib being arranged radially from the cutout between adjacent flow guiding grooves. Each spacer rib has a first spacer portion and a second spacer portion. Each first spacer portion is located between adjacent first flow guiding portions, and each second spacer portion is located between adjacent second flow guiding portions. The protective layer covers the second spacer portion and exposes the first spacer portion.

[0007] Preferably, the filler adhesive covers the first spacer portion and the protective layer located on the second spacer portion, and the protective layer and the filler adhesive form a second overlapping bonding layer on each of the second spacer portions. The first overlapping bonding layer and the second overlapping bonding layer constitute the overlapping bonding layer of the protective layer and the filler adhesive.

[0008] Preferably, the protective layer filling the second guide portion forms a third guide portion, the third guide portion is connected to the first guide portion, and the filler adhesive covers the third guide portion.

[0009] Preferably, each of the first guide portions has a first width, and each of the second guide portions has a second width, wherein the first width is equal to the second width.

[0010] Preferably, each of the first guide portions has a first width, each of the second guide portions has a second width, and each of the third guide portions has a third width, wherein the third width is not greater than the first width.

[0011] Preferably, the first width is equal to the second width.

[0012] Preferably, each of the spacer ribs has a width that gradually increases from the first spacer portion toward the second spacer portion.

[0013] A semiconductor packaging circuit board according to the present invention includes a carrier board, a patterned metal layer, and a protective layer. The carrier board has a surface including a circuit placement area, a chip placement area, and a current-conducting unit placement area. The circuit placement area is located outside the chip placement area and is used for chip placement. A first boundary and a second boundary of the chip placement area intersect at a corner. A first straight line extends along the first boundary, and a second straight line extends along the second boundary. The current-conducting unit placement area is located between the first straight line and the second straight line. The patterned metal layer has a plurality of circuits and at least one current-conducting unit. The circuits are disposed in the circuit placement area, and each circuit is internally connected to... The pins are located in the chip mounting area, and each of the internal pins is used to electrically connect to the chip. The current guiding unit is disposed in the current guiding unit mounting area. The current guiding unit includes a cutout portion and a plurality of current guiding grooves. Each current guiding groove is connected to the cutout portion and is arranged radially. The cutout portion is located between the corner and the current guiding groove, and the cutout portion is adjacent to the corner. Each current guiding groove has a first current guiding portion and a second current guiding portion that are connected. The first current guiding portion is connected to the cutout portion and is located between the cutout portion and the second current guiding portion. The protective layer covers the circuit and fills each of the second current guiding portions. The protective layer exposes the internal pins, the cutout portion and the first current guiding portion.

[0014] Preferably, the flow guiding unit includes a plurality of spacer ribs, each spacer rib being arranged radially from the cutout between adjacent flow guiding grooves, each spacer rib having a first spacer portion and a second spacer portion, each first spacer portion being located between adjacent first flow guiding portions, each second spacer portion being located between adjacent second flow guiding portions, and the protective layer covering the second spacer portion and exposing the first spacer portion.

[0015] Preferably, the protective layer located on the second spacer and the first spacer are used to be covered by the filler adhesive.

[0016] Preferably, the protective layer filling the second guide portion forms a third guide portion, which is connected to the first guide portion and is used for covering the filler adhesive.

[0017] Preferably, each of the first guide portions has a first width, and each of the second guide portions has a second width, wherein the first width is equal to the second width.

[0018] Preferably, each of the first guide portions has a first width, each of the second guide portions has a second width, and each of the third guide portions has a third width, wherein the third width is not greater than the first width.

[0019] Preferably, the first width is equal to the second width.

[0020] Preferably, each of the spacer ribs has a width that gradually increases from the first spacer portion toward the second spacer portion.

[0021] The present invention guides the protective layer toward the first flow section and the cutout section by the second flow section of the radially arranged flow channel, and guides the filler adhesive from the corner toward the second flow section by the cutout section and the first flow section of the flow channel, so that the filler adhesive covers the protective layer, so that the filler adhesive and the protective layer are integrated, thereby increasing the structural strength of the semiconductor package structure and preventing the filler adhesive from peeling off the carrier board, which would cause the internal pins to break off from the circuit. Attached Figure Description

[0022] Figure 1 : A top view of a conventional semiconductor package structure.

[0023] Figure 2 : A cross-sectional view of a conventional semiconductor package structure.

[0024] Figure 3 : Top view of the circuit board of the present invention.

[0025] Figure 4 : A partial enlarged view of the flow guiding unit of the present invention.

[0026] Figure 5 : Top view of the circuit board of the present invention.

[0027] Figure 6 Cross-sectional view of the flow guiding unit of the present invention covered by a protective layer.

[0028] Figure 7 Along Figure 6 A cross-sectional view of the DD line.

[0029] Figure 8 : Top view of the semiconductor package structure of the present invention.

[0030] Figure 9 Cross-sectional view of the flow guiding unit of the present invention covered by a protective layer and filler adhesive.

[0031] Figure 10 Along Figure 9 A cross-sectional view of the EE line.

[0032] Figure 11 : A cross-sectional view of the semiconductor package structure of the present invention.

[0033] [Explanation of Key Component Symbols]

[0034] 10: Circuit board 11: Carrier board

[0035] 11a: Surface 11b: Circuit Setting Area

[0036] 11c: Chip setup area; 11d: Region

[0037] 12: Line 12a: Internal pin

[0038] 13: Protective layer 20: Chip

[0039] 30: Filler glue

[0040] 100: Chip; 200: Circuit board

[0041] 210: Carrier plate 211: Surface

[0042] 211a: Circuit setting area; 211b: Chip setting area

[0043] 211c: Flow guiding unit setting area; 220: Patterned metal layer

[0044] 221: Line 221a: Internal pin

[0045] 222: Flow guiding unit; 222a: Hollowed-out section

[0046] 222b: Flow guide channel; 222b1: First flow guide section

[0047] 222b2: Second guide section; 222b3: Third guide section

[0048] 222c: Spacer rib; 222c1: First spacer portion

[0049] 222c2: Second spacer portion; 230: Protective layer

[0050] 300: Filler A: First boundary

[0051] A1: First straight line; B: Second boundary line

[0052] B1: Second straight line; C: Corner

[0053] S: Overlapping bonding layer; S1: First overlapping bonding layer

[0054] S2: Second overlapping bonding layer; W: Width

[0055] W1: First width W2: Second width

[0056] W3: Third Width Detailed Implementation

[0057] Please see Figure 8 and Figure 11 A semiconductor packaging structure of the present invention includes a chip 100, a circuit board 200, and a filler adhesive 300. Please refer to [link to relevant documentation]. Figure 3 and Figure 5 The circuit board 200 includes a carrier board 210, a patterned metal layer 220, and a protective layer 230. The carrier board 210 has a surface 211, which includes a circuit placement area 211a, a chip placement area 211b, and a current-conducting unit placement area 211c. The circuit placement area 211a is located outside the chip placement area 211b. Please refer to [link to relevant documentation]. Figure 8 The chip setting area 211a is used for the chip 100 to set.

[0058] Please see Figure 3 and Figure 4 The first boundary A and the second boundary B of the chip setting area 211a intersect at corner C. A first straight line A1 extends along the first boundary A, and a second straight line B1 extends along the second boundary B. The current guiding unit setting area 211c is located between the first straight line A1 and the second straight line B1. The current guiding unit setting area 211c is adjacent to the line setting area 211a.

[0059] Please see Figure 3 and Figure 4 The patterned metal layer 220 has multiple lines 221 and at least one current-guiding unit 222. The lines 221 are disposed in the line setting area 211a, and the inner pins 221a of each line 221 are located in the chip setting area 211b. Each inner pin 221a is used to electrically connect to the chip 100. The current-guiding unit 222 is disposed in the current-guiding unit setting area 211c. The current-guiding unit 222 includes a cutout portion 222a and multiple current-guiding grooves 222b. Each current-guiding groove 222b communicates with the cutout portion 222a and is arranged radially. a is located between the corner C and the guide channel 222b, and the hollow portion 222a is adjacent to the corner C. Each guide channel 222b has a first guide portion 222b1 and a second guide portion 222b2 that are connected. The first guide portion 222b1 is connected to the hollow portion 222a and is located between the hollow portion 222a and the second guide portion 222b2. Each first guide portion 222b1 has a first width W1 and each second guide portion 222b2 has a second width W2. The first width W1 is substantially equal to the second width W2.

[0060] Please see Figure 3 and Figure 4 In this embodiment, the flow guiding unit 222 includes a plurality of spacer ribs 222c. Each spacer rib 222c is arranged radially from the hollow portion 222a between adjacent flow guiding grooves 222b. Each spacer rib 222c has a first spacer portion 222c1 and a second spacer portion 222c2. Each first spacer portion 222c1 is located between adjacent first flow guiding portions 222b1, and each second spacer portion 222c2 is located between adjacent second flow guiding portions 222b2. Each spacer rib 222c has a width W, which gradually increases from the first spacer portion 222c1 toward the second spacer portion 222c2.

[0061] Please see Figures 5 to 7 The protective layer 230 is formed on the carrier 210 by a screen printing process and covers the circuit 221. The material of the protective layer 230 is selected from solder mask, but is not limited to it. The uncured protective layer 230 is guided by the second flow guides 222b2 of the flow guide channels 222b to flow toward the first flow guides 222b1 and the cutouts 222a, and covers the second spacers 222c. The protective layer 230 also fills the second flow guides 222b2 of each flow guide channel 222b. Please refer to [link to relevant documentation]. Figure 5 The protective layer 230 exposes the inner pin 221a, the cutout portion 222a, the first guide portion 222b1, and the first spacer portion 222c1. Please refer to [link / reference]. Figure 5 and Figure 6 A third guide portion 222b3 is formed by filling the protective layer 230 in each of the second guide portions 222b2 in the direction from the second guide portion 222b2 toward the first guide portion 222b1. (See also...) Figure 4 , Figure 6 and Figure 7 The third guide section 222b3 is connected to the first guide section 222b1, and each of the third guide sections 222b3 has a third width W3, which is not greater than the first width W2.

[0062] Please see Figure 8 The chip 100 is located in the chip setting area 211b and is electrically connected to the internal pin 221a. Please refer to section [link to relevant documentation]. Figures 8 to 10In the coating process, the filler adhesive 300 is filled between the chip 100 and the circuit board 200. Before the filler adhesive 300 cures, the filler adhesive 300 is guided by the cutout portion 222a and the first guide portion 222b1 to flow from the corner C toward the second guide portion 222b2, so that the filler adhesive 300 covers the cutout portion 222a, the first guide portion 222b1, the first spacer portion 222c1, and the protective layer 230 located on the second guide portion 222b2 and the second spacer portion 222c2 in the guide unit setting area 211c. In this embodiment... The filler adhesive 300 covers the third flow guide 222b3 via the first flow guide 222b1. The protective layer 230 and the filler adhesive 300 in each of the second flow guides 222b2 form a first overlapping bonding layer S1. The protective layer 230 and the filler adhesive 300 on each of the second spacers 222c2 form a second overlapping bonding layer S2. The first overlapping bonding layer S1 and the second overlapping bonding layer S2 constitute the overlapping bonding layer S of the protective layer 230 and the filler adhesive 300, so that the filler adhesive 300 and the protective layer 230 are integrated into the flow guide unit setting area 211c outside the corner C.

[0063] Please see Figure 8 and Figure 11 The present invention guides the protective layer 230 toward the first flow guide 222b1 and the hollow portion 222a through the second flow guide portions 222b2 of the radially arranged flow guide channels 222b, and guides the filler adhesive 300 from the corner C toward the second flow guide portions 222b2 through the hollow portion 222a and the first flow guide portions 222b1 of the flow guide channels 222b, so that the filler adhesive 300 covers the hollow portion 222a, the first flow guide portion 222b1, the protective layer 230 located on the second flow guide portion 222b2, and the protective layer 230 located on the second spacer portion 222c2, so that the filler adhesive 300 and the protective layer 230 are bonded together. Therefore, a peel test is performed. During the test, the filler adhesive 300 can be prevented from being peeled off from the carrier board 210 by the cutout portion 222a, which would cause the inner pin 221a to break off from the circuit 221. Furthermore, since the filler adhesive 300 is bonded to the protective layer 230, the structural strength of the semiconductor package structure can be increased.

[0064] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A semiconductor package structure comprising: chip; Circuit board, comprising: A carrier board has a surface including a circuit setting area, a chip setting area and a current guiding unit setting area. The circuit setting area is located outside the chip setting area. A first boundary and a second boundary of the chip setting area intersect at a corner. A first straight line extends along the first boundary and a second straight line extends along the second boundary. The current guiding unit setting area is located between the first straight line and the second straight line. A patterned metal layer has multiple lines and at least one current-guiding unit. The lines are disposed in a line placement area, and the internal pins of each line are located in the chip placement area. The current-guiding unit is disposed in the current-guiding unit placement area. The current-guiding unit includes a cutout portion and multiple current-guiding grooves. Each current-guiding groove communicates with the cutout portion and is arranged radially. The cutout portion is located between a corner and the current-guiding grooves, and the cutout portion is adjacent to the corner. Each current-guiding groove has a first current-guiding portion and a second current-guiding portion that are connected. The first current-guiding portion communicates with the cutout portion and is located between the cutout portion and the second current-guiding portion. A protective layer covers the circuitry and fills each of the second current-conducting portions. This protective layer exposes the internal pins, the cutout portion, and the first current-conducting portion. The chip is disposed in the chip placement area and electrically connected to the internal pins. A filler adhesive is applied between the chip and the circuit board, and the filler adhesive covers the cutout portion, the first flow guide portion, and the protective layer located in the second flow guide portion of the flow guide unit setting area. The protective layer and the filler adhesive form a first overlapping bonding layer in each of the second flow guide portions.

2. The semiconductor package construction of claim 1, wherein, The flow guiding unit includes multiple spacer ribs, each spacer rib is arranged radially from the cutout between adjacent flow guiding grooves, each spacer rib has a first spacer portion and a second spacer portion, each first spacer portion is located between adjacent first flow guiding portions, each second spacer portion is located between adjacent second flow guiding portions, the protective layer covers the second spacer portion and exposes the first spacer portion.

3. The semiconductor package construction of claim 2, wherein, The filler adhesive covers the first spacer portion and the protective layer located on the second spacer portion. The protective layer and the filler adhesive form a second overlapping bonding layer on each of the second spacer portions. The first overlapping bonding layer and the second overlapping bonding layer constitute the overlapping bonding layer of the protective layer and the filler adhesive.

4. The semiconductor package structure according to claim 1 or 2, characterized by, The protective layer filling the second guide portion forms a third guide portion, which is connected to the first guide portion, and the filler adhesive covers the third guide portion.

5. The semiconductor package construction of claim 1, wherein, Each of the first guide portions has a first width, and each of the second guide portions has a second width, wherein the first width is equal to the second width.

6. The semiconductor package construction of claim 4, wherein, Each of the first guide portions has a first width, each of the second guide portions has a second width, and each of the third guide portions has a third width, wherein the third width is not greater than the first width.

7. The semiconductor packaging structure according to claim 6, characterized in that, The first width is equal to the second width.

8. The semiconductor packaging structure according to claim 2, characterized in that, Each of the spacer ribs has a width that gradually increases from the first spacer portion toward the second spacer portion.

9. A circuit board with a semiconductor package structure, characterized in that, Include: A carrier board has a surface including a circuit setting area, a chip setting area and a current guiding unit setting area. The circuit setting area is located outside the chip setting area. The chip setting area is used for chip setting. The first boundary and the second boundary of the chip setting area intersect at a corner. A first straight line extends along the first boundary and a second straight line extends along the second boundary. The current guiding unit setting area is located between the first straight line and the second straight line. A patterned metal layer has multiple lines and at least one current-guiding unit. The lines are disposed in the line placement area, and the internal pins of each line are located in the chip placement area. Each internal pin is used for electrical connection with the chip. The current-guiding unit is disposed in the current-guiding unit placement area. The current-guiding unit includes a cutout portion and multiple current-guiding grooves. Each current-guiding groove communicates with the cutout portion and is arranged radially. The cutout portion is located between a corner and the current-guiding groove, and the cutout portion is adjacent to the corner. Each current-guiding groove has a first current-guiding portion and a second current-guiding portion that communicate with the cutout portion and are located between the cutout portion and the second current-guiding portion. A protective layer covers the circuit and fills each of the second flow guides, the protective layer exposing the inner pin, the cutout, and the first flow guide.

10. The circuit board with the semiconductor package structure according to claim 9, characterized in that, The flow guiding unit includes multiple spacer ribs, each spacer rib is arranged radially from the cutout between adjacent flow guiding grooves, each spacer rib has a first spacer portion and a second spacer portion, each first spacer portion is located between adjacent first flow guiding portions, each second spacer portion is located between adjacent second flow guiding portions, and the protective layer covers the second spacer portion and exposes the first spacer portion.

11. The circuit board with the semiconductor package structure according to claim 10, characterized in that, The protective layer located on the second spacer and the first spacer are used for covering with filler adhesive.

12. The circuit board with a semiconductor package structure according to claim 9 or 10, characterized in that, The protective layer filled in the second guide portion forms a third guide portion, which is connected to the first guide portion and is used for covering with filler adhesive.

13. The circuit board with the semiconductor package structure according to claim 9, characterized in that, Each of the first guide portions has a first width, and each of the second guide portions has a second width, wherein the first width is equal to the second width.

14. The circuit board with the semiconductor package structure according to claim 11, characterized in that, The protective layer filling the second guide portion forms a third guide portion. Each of the first guide portions has a first width, each of the second guide portions has a second width, and each of the third guide portions has a third width, wherein the third width is not greater than the first width.

15. The circuit board with the semiconductor package structure according to claim 13, characterized in that, The first width is equal to the second width.

16. The circuit board with the semiconductor package structure according to claim 10, characterized in that, Each of the spacer ribs has a width that gradually increases from the first spacer portion toward the second spacer portion.

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