A noise cancellation based sample-and-hold circuit

Abstract

The present application relates to the field of analog integrated circuit technology, and particularly relates to a kind of sampling and holding circuit based on noise cancellation.The present application handles sampling noise by introducing noise cancellation technology, input signal is directly connected to the upper plate of C1, C1 samples during S1 switch is closed;The output end of operational amplifier is connected with the lower plate of C2 through S2 switch, C2 samples sampling noise during S2 switch is closed, C2 two ends are connected with C1 two ends through S3 switch, C1 and C2 share charge during S3 switch is closed;Dynamic operational amplifier output end is connected with latch at the same time, so as to use operational amplifier as the preamplifier of comparator.The present application effectively suppresses the deterioration of sampling noise under the condition of reducing sampling capacitor, and dynamic operational amplifier greatly reduces the power consumption and noise of sampling and holding after introducing operational amplifier, and C2=C3 can also be set to make the gain of dynamic operational amplifier in noise elimination stage and subsequent as comparator preamplifier be equal, further improve the precision of circuit.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, specifically to a sample-and-hold circuit based on noise cancellation, which can be used in medium- and low-speed, high-precision analog-to-digital converters. Background Technology

[0002] Like any ADC with a front-end S / H circuit, the sampling kT / C noise of a SAR ADC limits its SNR. To meet SNR requirements, the input capacitor must be large enough, which significantly increases circuit area and power consumption. Meanwhile, despite advancements in loop filter design in NS-SAR, achieving substantial suppression of quantization noise, existing NS-SAR solutions still face bottlenecks when pursuing higher resolutions: sampling kT / C noise and capacitor mismatch remain difficult to suppress and quickly become dominant factors in irrational behavior. While the size requirements for mismatch have been greatly relaxed with the development of various calibration and mismatch shaping techniques, kT / C noise remains a more fundamental bottleneck affecting capacitor size; each additional bit of SNR requires a fourfold increase in capacitance, impacting the need for large dynamic range and low oversampling rates. This not only generates significant switching power consumption in the CDAC and its drive buffer but also greatly complicates the design of the input and reference buffers.

[0003] To simplify the requirements of the ADC buffer, some researchers have suggested embedding a buffer within the SAR ADC loop. In this way, the S / H circuitry is separated and isolated from the feedback DAC, and isolated from the input by the buffer. The capacitance seen from the ADC input is only the input capacitance of the buffer, thus reducing the burden on the ADC input buffer. Furthermore, since the buffer is located within the SAR loop, its nonlinear distortions during the sampling and conversion stages cancel each other out; therefore, a simple source follower can be used as the buffer, reducing design complexity. However, the source follower buffer still requires driving a large sampling capacitor limited by kT / C noise, which consumes additional power and may reduce the ADC's power efficiency.

[0004] Since the root cause of this problem is the large input capacitance, there is a strong desire to find a way to reduce the capacitance size without causing significant degradation due to kT / C noise. Recently, a two-step ADC with only 120fF input capacitance has been developed, using kT / C noise-free continuous-time (CT) SAR as the first stage. Because there is no sampling operation, a small input capacitor can be used. However, it has several limitations: first, it cannot convert DC signals because its input is AC-coupled, limiting its application; second, the input signal frequency is limited to 1MHz to prevent large tracking errors from the CT SAR; finally, the CT SAR operation must be very fast, only 500ps per CT SAR cycle, and even with a reduced input capacitor size, the setup time in such a short period still places significant demands on the ADC's input buffer. Summary of the Invention

[0005] To address the aforementioned problems or shortcomings, this invention provides a sample-and-hold circuit based on noise cancellation. By introducing noise cancellation technology to process sampling noise, the degradation of sampling noise can be suppressed while reducing the sampling capacitance. This circuit can be used in medium- and low-speed, high-precision analog-to-digital converters.

[0006] A sample-and-hold circuit based on noise cancellation, which is a fully differential structure (see appendix). Figure 1 It includes a dynamic operational amplifier, four types of switches S1, S2, S3, and S4, three types of capacitors C1, C2, and C3, and a latch; among which, capacitors C1 and C2 are sampling capacitors, and C3 is the load capacitor for stabilizing the gain of the dynamic operational amplifier.

[0007] Its P terminal has the following configuration: the upper plate of capacitor C1 is connected to Vip via an S2 switch and to VDAC via an S3 switch; the lower plate of capacitor C1 is connected to one input terminal of the operational amplifier. The upper plate of capacitor C2 is grounded via an S2 switch; the lower plate of capacitor C2 is connected to one output terminal of the operational amplifier and one input terminal of the latch. The upper plate of capacitor C3 is grounded via an S4 switch; the lower plate of capacitor C3 is connected to one output terminal of the operational amplifier and one input terminal of the latch. The input terminal of the operational amplifier is also grounded via an S1 switch. Capacitors C1 and C2 are connected via two S3 switches, with their upper and lower plates respectively.

[0008] Its N-terminals are as follows: the upper plate of capacitor C1 is connected to Vin via an S2 switch and to VDAC via an S3 switch, and the lower plate of capacitor C1 is connected to the other input terminal of the operational amplifier; the upper plate of capacitor C2 is grounded via an S2 switch, and the lower plate of capacitor C2 is connected to the other output terminal of the operational amplifier and the other input terminal of the latch; the upper plate of capacitor C3 is grounded via an S4 switch, and the lower plate of capacitor C3 is connected to the other output terminal of the operational amplifier and the other input terminal of the latch; the corresponding operational amplifier input terminal is also grounded via an S1 switch, and capacitors C1 and C2 are connected by their upper and lower plates respectively through two S3 switches.

[0009] The above-mentioned sample-and-hold circuit based on noise cancellation has the following control logic:

[0010] For the P terminal: The first stage is the C1 capacitor sampling stage. At this time, switches S1 and S2 are closed, and switches S3 and S4 are open. Vip is connected to the upper plate of capacitor C1 through switch S2, and the lower plate of capacitor C1 is connected to ground through switch S1. The op-amp input is grounded. The upper plate of capacitor C2 is connected to ground through switch S2, and the lower plate of capacitor C2 is connected to the op-amp output. The op-amp output is connected to the latch input. The second stage is the C2 capacitor sampling stage. Switch S2 is closed, and switches S1, S3, and S4 are open. Vip is connected to the upper plate of capacitor C1 through switch S2, and C1... The lower plate of capacitor C2 is connected to the input terminal of the op-amp. The output terminal of the op-amp is connected to the lower plate of capacitor C2 through switch S2. The upper plate of capacitor C2 is connected to ground through switch S2. The output terminal of the op-amp is connected to the latch. The third stage is the noise cancellation stage. VDAC is the voltage of the upper plate of capacitor C2. At this time, switches S1 and S2 are open, and switches S3 and S4 are closed. VDAC is connected to the upper plates of capacitors C1 and C2 through switch S3. The lower plates of capacitors C1 and C2 are connected to the input terminal of the op-amp through switch S3. The lower plate of capacitor C3 is connected to the output terminal of the op-amp. The upper plate of capacitor C3 is connected to ground through switch S4.

[0011] For the N-terminal: The first stage is the sampling stage for capacitor C1. During this stage, switches S1 and S2 are closed, and switches S3 and S4 are open. Vin is connected to the upper plate of capacitor C1 through switch S2, and the lower plate of capacitor C1 is connected to ground through switch S1. The op-amp input is grounded. The upper plate of capacitor C2 is connected to ground through switch S2, and the lower plate of capacitor C2 is connected to the op-amp output. The op-amp output is connected to the latch input. The second stage is the sampling stage for capacitor C2. Switch S2 is closed, and switches S1, S3, and S4 are open. Vin is connected to the upper plate of capacitor C1 through switch S2. The lower plate is connected to the op-amp input terminal, and the op-amp output terminal is connected to the lower plate of capacitor C2 through switch S2. The upper plate of capacitor C2 is connected to ground through S2, and the op-amp output terminal is connected to the latch. The third stage is the noise cancellation stage. VDAC is the voltage of the upper plate of the capacitor array. At this time, switches S1 and S2 are open, and switches S3 and S4 are closed. VDAC is connected to the upper plates of capacitors C1 and C2 through switch S3. The lower plates of capacitors C1 and C2 are connected to the op-amp input terminal through switch S3. The lower plate of capacitor C3 is connected to the op-amp output terminal, and the upper plate of C3 is connected to ground through switch S4.

[0012] In this invention, the input signal is directly connected to the upper plate of capacitor C1, and the lower plate of capacitor C1 is connected to the input terminal of the dynamic operational amplifier and to ground through switch S1. During the period when switch S1 is closed, capacitor C1 performs sampling. The output terminal of the operational amplifier is connected to the lower plate of capacitor C2 through switch S2. During the period when switch S2 is closed, capacitor C2 samples the sampling noise. The two ends of capacitor C2 are connected to the two ends of capacitor C1 through switch S3. During the period when switch S3 is closed, capacitors C1 and C2 share charge. At the same time, the output terminal of the dynamic operational amplifier is connected to the latch, so the operational amplifier can be multiplexed as a preamplifier of the comparator.

[0013] In summary, this invention addresses sampling noise by introducing noise cancellation technology, thereby suppressing the deterioration of sampling noise while reducing the sampling capacitance. It can be used in medium- and low-speed, high-precision analog-to-digital converters. Attached Figure Description

[0014] Figure 1 This is the circuit diagram of the present invention.

[0015] Figure 2 This is the timing diagram corresponding to the present invention. Detailed Implementation

[0016] The working principle of the present invention will be further described in detail below with reference to the accompanying drawings.

[0017] This invention is an extension and optimization based on correlated double sampling technology, and the specific circuit structure is as follows: Figure 1 As shown, its working timing is as follows Figure 2 As shown.

[0018] This invention's noise cancellation-based sample-and-hold circuit consists of three operating stages:

[0019] (1) During the sampling stage of capacitor C1, switches S1 and S2 are closed, and the input signal Vin is sampled across capacitor C1. At the same time, the sampling noise Vns1 caused by the conduction resistance of switch S1 is also sampled across capacitor C1. At this time, the voltage across C1 can be described as Vin1 + Vns1. After switch S1 is opened, capacitor C1 is floating and the charge is conserved. The voltage difference across it is fixed as Vin1 + Vns1.

[0020] (2) During the sampling stage of capacitor C2, switch S1 is open and S2 is closed, and the dynamic operational amplifier starts to work. Let the input signal be Vin2, the sampling noise introduced by switch S2 be Vns2, and the gain of the operational amplifier be A. Then the voltage at the input terminal of the operational amplifier is Vin2-Vin1-Vns1, and the voltage at the output terminal is A(Vin2-Vin1-Vns1). At this time, capacitor C2 samples this voltage. When S2 is open, capacitor C2 is floating and the charge is conserved. Therefore, the voltage at both ends is fixed as A(Vin2-Vin1-Vns1)+Vns2.

[0021] (3) Noise cancellation stage: At this time, switches S1 and S2 are open, and S3 is closed. Capacitors C1 and C2 share charge. Let ΔV be the voltage difference across capacitors C1 and C2. The equation can be written as follows:

[0022] C1(Vin1+Vns1)+C2[A(Vin2-Vin1-Vns1)+Vns2]=(C1+C2)ΔV, we can obtain

[0023]

[0024] At this point, the signal seen at the op-amp input is VDAC-ΔV, with only ΔV containing a noise term. It can be seen that when C1 = AC2, the sampling noise introduced by switch S1 is eliminated, while the sampling noise introduced by switch S2 is... The inhibition of multiple times, that is The suppression is multiplied by 100%, thus achieving a significant reduction in sampling noise.

[0025] As can be seen from the above embodiments, the present invention uses noise cancellation technology to process sampling noise. The input signal is directly connected to the upper plate of capacitor C1, and the lower plate of capacitor C1 is connected to the input terminal of the dynamic operational amplifier and to ground through switch S1. During the period when switch S1 is closed, capacitor C1 samples. The output terminal of the operational amplifier is connected to the lower plate of capacitor C2 through switch S2. During the period when switch S2 is closed, capacitor C2 samples the sampling noise. The two ends of capacitor C2 are connected to the two ends of capacitor C1 through switch S3. During the period when switch S3 is closed, capacitors C1 and C2 share charge. At the same time, the output terminal of the dynamic operational amplifier is connected to the latch, so the operational amplifier can be multiplexed as a preamplifier of the comparator. Ultimately, this invention effectively suppresses the deterioration of sampling noise while reducing the sampling capacitor; and by using a dynamic operational amplifier, the power consumption and noise of the sampling protection after introducing the operational amplifier can be greatly reduced; secondly, the output of the dynamic operational amplifier is connected to capacitor C3 through switch S4, and as long as C2=C3, the gain of the dynamic operational amplifier is equal in the noise cancellation stage and when it is used as a preamplifier for the comparator, which further improves the accuracy of the circuit and can be used in medium and low speed high precision analog-to-digital converters.

Claims

1. A sample-and-hold circuit based on noise cancellation, characterized in that: It is a fully differential structure, including a dynamic operational amplifier, four types of switches S1, S2, S3 and S4, three types of capacitors C1, C2 and C3, and a latch; among them, capacitors C1 and C2 are sampling capacitors, and C3 is a load capacitor for stabilizing the gain of the dynamic operational amplifier. Its P terminal has the following configuration: the upper plate of capacitor C1 is connected to Vip via an S2 switch and to VDAC via an S3 switch; the lower plate of capacitor C1 is connected to one input terminal of the operational amplifier. The upper plate of capacitor C2 is grounded via an S2 switch; the lower plate of capacitor C2 is connected to one output terminal of the operational amplifier and one input terminal of the latch. The upper plate of capacitor C3 is grounded via an S4 switch; the lower plate of capacitor C3 is connected to one output terminal of the operational amplifier and one input terminal of the latch. The input terminal of the operational amplifier is also grounded via an S1 switch. Capacitors C1 and C2 are connected by their upper and lower plates respectively through two S3 switches. For the P terminal: The first stage is the C1 capacitor sampling stage. At this time, switches S1 and S2 are closed, and switches S3 and S4 are open. Vip is connected to the upper plate of capacitor C1 through switch S2, and the lower plate of capacitor C1 is connected to ground through switch S1. The op-amp input is grounded. The upper plate of capacitor C2 is connected to ground through switch S2, and the lower plate of capacitor C2 is connected to the op-amp output. The op-amp output is connected to the latch input. The second stage is the C2 capacitor sampling stage. Switch S2 is closed, and switches S1, S3, and S4 are open. Vip is connected to the upper plate of capacitor C1 through switch S2, and C1... The lower plate of capacitor C2 is connected to the input terminal of op-amp. The output terminal of op-amp is connected to the lower plate of capacitor C2 through switch S2. The upper plate of capacitor C2 is connected to ground through switch S2. The output terminal of op-amp is connected to latch. The third stage is the noise cancellation stage. VDAC is the voltage of the upper plate of capacitor. At this time, switches S1 and S2 are open, and switches S3 and S4 are closed. VDAC is connected to the upper plates of capacitors C1 and C2 through switch S3. The lower plates of capacitors C1 and C2 are connected to the input terminal of op-amp through switch S3. The lower plate of capacitor C3 is connected to the output terminal of op-amp. The upper plate of capacitor C3 is connected to ground through switch S4. The N and P terminals are symmetrically arranged.

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