Successive approximation analog-to-digital converter and conversion method thereof

Abstract

The application provides a successive approximation analog-digital converter and a conversion method thereof, the analog-digital converter comprising: a sequentially connected capacitor switch array, a comparator and a digital logic circuit; the capacitor switch array accepts an input analog signal, samples and converts the analog signal, and outputs a converted signal to the comparator for comparison; the comparator compares the converted signal, and outputs a comparison result to the digital logic circuit; the digital logic circuit outputs a feedback control signal to the capacitor switch array according to the comparison result, and outputs a digital signal, wherein the number of bits of the digital signal is N, and N is a positive integer; and the switches in the capacitor switch array are switched according to the feedback control signal to open and close. N The application can be applied to analog signals with common-mode voltage, and has simple structure and is easy to implement.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a successive approximation analog-to-digital converter and its conversion method. Background Technology

[0002] Due to advancements in manufacturing processes, successive approximation mode analog-to-digital converters (SAR ADCs) with their small size, low power consumption, and simple structure are widely used. In some applications, the performance of the SAR ADC is affected because the common-mode voltage of the input signal changes in real time. An improved structure has emerged, such as... Figure 1 As shown. By closing switch S1 and connecting the sampling capacitor in series, only the signal information is retained on the capacitor, unaffected by the common-mode voltage. During signal conversion, one end of each capacitor is set so that the comparator input sees a signal with a fixed common-mode voltage, thus stabilizing the SAR ADC performance. However, this improved structure is too complex and difficult to implement. Summary of the Invention

[0003] In view of the above-mentioned shortcomings of the existing technical solutions, the purpose of this invention is to provide a successive approximation analog-to-digital converter and its conversion method that are simple in structure and easy to implement.

[0004] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0005] A successive approximation analog-to-digital converter (ADC) includes: a capacitor switch array, a comparator, and a digital logic circuit connected in sequence. The capacitor switch array receives an input analog signal, samples and converts the analog signal, and outputs a converted signal to the comparator for comparison. The comparator compares the converted signal and outputs a comparison result to the digital logic circuit. The digital logic circuit outputs a feedback control signal to the capacitor switch array based on the comparison result and outputs a digital signal with N bits, where N is a positive integer. The switches in the capacitor switch array are switched open and closed according to the feedback control signal, wherein the number of capacitors is 2*2. N .

[0006] Furthermore, the capacitor switch array includes: a sampling capacitor group, a conversion capacitor group, and a sampling-conversion switching switch group connecting the two; during the sampling process, the sampling-conversion switching switch group is in an open state; during the conversion process, the sampling-conversion switching switch group is in a closed state.

[0007] Furthermore, the capacitor switch array also includes a pre-sampling switch group and a post-sampling switch group;

[0008] The sampling capacitor bank includes 2 N The capacitors are divided into 2 equal parts.N-1 One capacitor upsampling group and 2 N-1 One capacitor downsampling group; 2 N-1 The plates of each capacitor in the capacitor upsampling group are simultaneously connected to the first input terminal of the analog signal through the same presampling switch in the presampling switch group. N-1 Each capacitor in the capacitor upsampling group has its second plate connected to the second input terminal of the analog signal via a pre-sampling switch in the pre-sampling switch group, and is switched to either a high or low potential via a changeover switch; 2 N-1 Each capacitor in the capacitor downsampling group has its plates connected to the second input terminal of the analog signal simultaneously through the same presampling switch in the presampling switch group. N-1 The second plate of each capacitor in the capacitor downsampling group is connected to the first input terminal of the analog signal through a presampling switch in the presampling switch group, and is switched to high or low potential through a conversion switch.

[0009] The conversion capacitor bank includes 2 N One capacitor, divided into 2 N-2 One capacitor up-conversion group, 2 N-2 One capacitor down-conversion group, 2 N -3 One capacitor up-conversion group, 2 N-3 One capacitor down-conversion group, ..., and so on, ... 2 capacitor up-conversion groups, 2 capacitor down-conversion groups, 1 capacitor up-conversion group, 1 capacitor down-conversion group, and 1 capacitor up-conversion matching group, 1 capacitor down-conversion matching group; 2 N-2 One capacitor up-conversion group, 2 N-3 One capacitor up-conversion group, ..., and so on, ..., two capacitor up-conversion groups, one capacitor up-conversion group, and one capacitor up-conversion matching group, all the plates of each capacitor are simultaneously connected to the two capacitors through the same sampling conversion switching switch of the sampling conversion switching switch group. N-1 The plates of each capacitor in the sampling group are connected together and connected to the first input terminal of the comparator. N-2 One capacitor up-conversion group, 2 N-3 The plates of each capacitor in a capacitor up-conversion group, a capacitor up-conversion group, a capacitor up-conversion matching group, and a capacitor up-conversion matching group are respectively connected to a high potential or a low potential via a switching switch; 2 N-2 One capacitor down-conversion group, 2 N-3 The plates of each capacitor in a capacitor down-conversion group, a capacitor down-conversion group, a capacitor down-conversion group, and a capacitor down-conversion matching group are all simultaneously connected to the same sampling conversion switching switch of the sampling conversion switching switch group. N-1The plates of each capacitor in the capacitor sampling group are connected together and connected to the second input terminal of the comparator. N-2 One capacitor down-conversion group, 2 N-3 The plates of each capacitor in a capacitor down-conversion group, a capacitor down-conversion group, a capacitor down-conversion group, and a capacitor down-conversion matching group are respectively connected to a high potential or a low potential through a switching switch.

[0010] The post-sampling switch group includes a post-up-sampling switch and a post-down-sampling switch. One end of the post-up-sampling switch is connected to the first input terminal of the comparator, and the other end is connected to a low potential. One end of the post-down-sampling switch is connected to the second input terminal of the comparator, and the other end is connected to a low potential.

[0011] Furthermore, the 2 N-1 The capacitor upsampling groups are evenly divided into a first upsampling group capacitor and a second upsampling group capacitor, the 2 N-1 The capacitor downsampling groups are averaged into the first downsampling group capacitor and the second downsampling group capacitor.

[0012] Furthermore, the changeover switch includes: a high-position switch connected to a high potential and a low-position switch connected to a low potential; the high potential is a power source and the low potential is ground.

[0013] A conversion method for a successive approximation analog-to-digital converter, employing the analog-to-digital converter as described above, includes φ0, φ1, φ2, φ3, ..., φ within one conversion cycle T. N Sub-period, the conversion method includes:

[0014] During the φ0 sub-cycle, which is the sampling phase, all sampling conversion switching switches are open, all pre-sampling and post-sampling switching switches are closed, all switching switches connected to the sampling capacitor bank are open, and all switching switches connected to the conversion capacitor bank are connected to low potential.

[0015] In sub-cycle φ1, the first conversion of the conversion phase, all sampling conversion switching switches are closed, and both the pre-sampling and post-sampling switch groups are open. All switches connected to the capacitors of the first upsampling group are connected to high potential, and all switches connected to the capacitors of the second upsampling group are connected to low potential. All switches connected to the capacitors of the first downsampling group are connected to high potential, and all switches connected to the capacitors of the second downsampling group are connected to low potential. In the conversion capacitor group, 2... N-2 All the switching switches connected to the capacitor conversion group are connected to the high potential, 2 N-2All switches connected to the capacitor switching group below the current capacitor are connected to a high potential, while all switches connected to other capacitors are connected to a low potential. A comparator compares these switches, the digital logic circuit outputs the first bit of the digital circuit, and outputs a feedback control signal to the capacitor switch array; and thereafter until φ... N During the sub-cycle, the sampling conversion switching switch group is always fully closed, while the pre-sampling switch group and the post-sampling switch group are always fully open.

[0016] The φ2 sub-cycle is the second conversion stage. Based on the feedback control signal output from the φ1 sub-cycle, the switch is turned. If the voltage at the second input terminal of the comparator is greater than the voltage at the first input terminal, then the 2... N-1 All the switching switches connected to the sampling groups of the capacitors are connected to high potential. N-1 All the switching switches connected to the capacitor sampling group are connected to low potential, and vice versa. All the switching switches connected to the switching capacitor group are floating. The comparator compares them, the digital logic circuit outputs the second bit of the digital circuit, and outputs a feedback control signal to the capacitor switch array.

[0017] The φ3 sub-cycle is the third conversion stage. Based on the feedback control signal output from the φ2 sub-cycle, the switch is turned. If the voltage at the second input terminal of the comparator is greater than the voltage at the first input terminal, then the 2... N-2 All the switching switches connected to the capacitor conversion group are connected to the high potential, 2 N-2 All switching switches connected to the capacitor switching group are connected to the low potential, and vice versa. The switching switches connected to other capacitors remain unchanged from the previous sub-cycle. The comparator compares them, the digital logic circuit outputs the third bit of the digital circuit, and outputs a feedback control signal to the capacitor switch array.

[0018] Referring to the φ3 sub-period, and so on, until φ N Sub-cycle, which is the Nth transformation in the transformation phase, according to φ N-1 The feedback control signal output by the sub-cycle switches the changeover switches. If the voltage at the second input terminal of the comparator is greater than the voltage at the first input terminal, all changeover switches connected to the upper changeover group of the two capacitors are connected to the high potential, and all changeover switches connected to the lower changeover group of the two capacitors are connected to the low potential. Otherwise, they are interchanged. The changeover switches connected to other capacitors remain unchanged from the state of the previous sub-cycle. The comparator compares the values, and the digital logic circuit outputs the Nth bit of the digital circuit.

[0019] The successive approximation analog-to-digital converter and its conversion method described in this invention, during the signal sampling period, uses half of the capacitors in the capacitor switch array as a sampling capacitor group, and shorts the two ends of the other half of the capacitors to the same reference potential for discharge (in a specific embodiment of this invention, shorting to 0 potential), which can be temporarily referred to as the short-circuited capacitor group or the conversion capacitor group. After entering the conversion process, one end of the sampling capacitor group and the conversion capacitor group is shorted and connected to the input port of the comparator, and the other end of the sampling capacitor group and the conversion capacitor group are respectively connected to the reference high / low potential. This is equivalent to resetting the sampling signal capacitor, so that no matter how the common-mode voltage of the input signal changes, the common-mode voltage of the signal to be processed at the comparator input port is fixed at the midpoint between the reference high potential and the reference low potential. Therefore, this invention can be applied to analog signals with common-mode voltage. Moreover, this invention has a simple structure and is easy to implement. In addition, the successive approximation analog-to-digital converter described in this invention increases the amplitude of the signal change at each step during the conversion process (except for the first and last steps), reducing the error rate of the comparator during the conversion process. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of a conventional successive approximation analog-to-digital converter involved in the present invention;

[0022] Figure 2 This is a schematic diagram of the structure of a successive approximation analog-to-digital converter according to an embodiment of the present invention;

[0023] Figures 3a-3d This is a set of schematic diagrams illustrating the conversion process of a successive approximation analog-to-digital converter according to an embodiment of the present invention;

[0024] Figure 4 This is a schematic diagram of the conversion cycle of a successive approximation analog-to-digital converter according to an embodiment of the present invention. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] Please see Figure 2 As shown, one embodiment of the present invention provides a successive approximation analog-to-digital converter, comprising: a capacitor switch array, a comparator, and a digital logic circuit connected in sequence; the capacitor switch array receives an input analog signal, samples and converts the analog signal, and outputs a converted signal to the comparator for comparison; the comparator compares the converted signal and outputs a comparison result to the digital logic circuit; the digital logic circuit outputs a feedback control signal to the capacitor switch array based on the comparison result, and outputs a digital signal, wherein the digital signal has N bits, where N is a positive integer; the switches in the capacitor switch array are switched open and closed according to the feedback control signal, wherein the number of capacitors is 2*2. N .

[0027] The successive approximation analog-to-digital converter described in this invention is designed for differential analog signals with a resolution of N; for one input polarity, it requires 2 N There are 2 capacitors; since differential signals have two polarities, there are a total of 2*2 capacitors. N A capacitor. The capacitor switch array has two functions: first, to acquire analog input signals; and second, to realize the gradual change of signals at the connection ports of the capacitor and comparator under the control of different switch opening / closing.

[0028] Therefore, the capacitor switch array includes: a sampling capacitor group, a switching capacitor group, and a sampling-switching switching switch group connecting the two; during the sampling process, the sampling-switching switching switch group is in an open state; during the switching process, the sampling-switching switching switch group is in a closed state.

[0029] Furthermore, the capacitor switch array also includes a pre-sampling switch group and a post-sampling switch group. Each of the pre-sampling switch group and the post-sampling switch group contains a large and variable number of switches. The specific number depends mainly on the number of capacitors and the connection requirements. Since the switches in each "group" often perform the same operation simultaneously, this invention frequently uses the term "group" to refer to these switches.

[0030] The sampling capacitor bank includes 2 N The capacitors are divided into 2 equal parts. N-1 One capacitor upsampling group and 2 N-1 Two capacitor downsampling groups (together referred to as 2) N-1 (The same logic applies to other groups after sampling one capacitor group); 2 N-1 The plates of each capacitor in the capacitor upsampling group are simultaneously connected to the first input terminal of the analog signal through the same presampling switch in the presampling switch group. N-1Each capacitor in the capacitor upsampling group has its second plate connected to the second input terminal of the analog signal via a pre-sampling switch in the pre-sampling switch group, and is switched to either a high or low potential via a changeover switch; 2 N-1 Each capacitor in the capacitor downsampling group has its plates connected to the second input terminal of the analog signal simultaneously through the same presampling switch in the presampling switch group. N-1 Each capacitor in the capacitor downsampling group has its second plate connected to the first input terminal of the analog signal via a presampling switch in the presampling switch group, and is switched to either a high or low potential via a changeover switch. Among them, 2 N-1 Each capacitor upsampling group indicates that it contains 2 N-1 One capacitor, that is, these 2 N-1 2 capacitors form a "group"; N-1 The same applies to each capacitor downsampling group. Furthermore, for ease of description, this invention will be described according to... Figure 2 The orientation shown indicates that the 2nd position in the diagram is located at the top. N-1 One capacitor is defined as 2 N-1 The capacitor upsampling group is located at the bottom 2. N-1 One capacitor is defined as 2 N-1 The capacitor downsampling groups, in fact, can also be called the first sampling group, the second sampling group, or other names. That is, the terms "upper" and "lower" used here do not imply an absolute vertical relationship between the two, but are merely for ease of description and distinction. And 2 N-1 One capacitor upsampling group, 2 N-1 The connections between the capacitor-based downsampling group and the two input terminals of the input analog signal can be interchanged as needed. Meanwhile, Figure 2 The image only shows a schematic representation of four capacitors (top and bottom). The actual number of capacitors depends on the value of N. For example, if N is 4, then 2... N-1 One capacitor upsampling group and 2 N-1 Each capacitor sampling group consists of 8 capacitors.

[0031] The following description details the switching capacitor bank. Please refer to the above explanation for a thorough understanding of the subsequent description. The switching capacitor bank comprises 2... N One capacitor, divided into 2 N-2 One capacitor up-conversion group, 2 N-2 One capacitor down-conversion group, 2 N-3 One capacitor up-conversion group, 2 N-3 One capacitor down-conversion group, ..., and so on, ... 2 capacitor up-conversion groups, 2 capacitor down-conversion groups, 1 capacitor up-conversion group, 1 capacitor down-conversion group, and 1 capacitor up-conversion matching group, 1 capacitor down-conversion matching group; 2 N-2 One capacitor up-conversion group, 2 N-3One capacitor up-conversion group, ..., and so on, ..., two capacitor up-conversion groups, one capacitor up-conversion group, and one capacitor up-conversion matching group, all the plates of each capacitor are simultaneously connected to the two capacitors through the same sampling conversion switching switch of the sampling conversion switching switch group. N-1 The plates of each capacitor in the sampling group are connected together and connected to the first input terminal of the comparator. N-2 One capacitor up-conversion group, 2 N-3 The plates of each capacitor in a capacitor up-conversion group, a capacitor up-conversion group, a capacitor up-conversion matching group, and a capacitor up-conversion matching group are respectively connected to a high potential or a low potential via a switching switch; 2 N-2 One capacitor down-conversion group, 2 N-3 The plates of each capacitor in a capacitor down-conversion group, a capacitor down-conversion group, a capacitor down-conversion group, and a capacitor down-conversion matching group are all simultaneously connected to the same sampling conversion switching switch of the sampling conversion switching switch group. N-1 The plates of each capacitor in the capacitor sampling group are connected together and connected to the second input terminal of the comparator. N-2 One capacitor down-conversion group, 2 N-3 The capacitor plates of each capacitor in a down-conversion group, a 2-capacitor down-conversion group, a 1-capacitor down-conversion group, and a 1-capacitor down-conversion matching group are connected to either a high or low potential via a switching switch. Similarly, as mentioned before, 2 N -2 A capacitor upconversion group indicates that it contains 2 N-2 One capacitor is shown schematically in the diagram; 2 N-3 A capacitor upconversion group indicates that it contains 2 N-3 There is one capacitor, and only one capacitor is shown schematically in the diagram; similarly, there are other capacitors in the conversion group. The connections between each capacitor and the sampling capacitor group and the comparator can be interchanged as needed, as long as the corresponding relationships are maintained.

[0032] The post-sampling switch group includes a post-up sampling switch and a post-down sampling switch. One end of the post-up sampling switch is connected to the first input terminal of the comparator, and the other end is connected to a low potential. One end of the post-down sampling switch is connected to the second input terminal of the comparator, and the other end is connected to a low potential.

[0033] Furthermore, the 2 N-1 The capacitor upsampling groups are evenly divided into a first upsampling group capacitor and a second upsampling group capacitor, the 2 N-1The capacitor downsampling groups are averaged into a first downsampling group capacitor and a second downsampling group capacitor, that is, the first upsampling group capacitor, the second upsampling group capacitor, the first downsampling group capacitor, and the second downsampling group capacitor each contain 2 N-2 One capacitor.

[0034] In this invention, the switching switch includes: a high-position switch connected to a high potential and a low-position switch connected to a low potential; the high potential is a power source and the low potential is ground.

[0035] This invention also provides a conversion method for a successive approximation analog-to-digital converter, employing the analog-to-digital converter as described above, wherein within one conversion period T, φ0, φ1, φ2, φ3, ..., φ N Sub-period (e.g.) Figure 4 As shown), the conversion method includes:

[0036] During the φ0 sub-cycle, which is the sampling phase, all sampling conversion switching switches are open, while the pre-sampling and post-sampling switching switches are closed. All switches connected to the sampling capacitor bank are open, and all switches connected to the conversion capacitor bank are connected to a low potential. Figure 3a As shown;

[0037] The sampling capacitor bank is connected to the two ends of the input analog signal, vip and vin, respectively. Therefore, in one polarity, the voltage across the sampling capacitor bank is vip-vin, and in the other polarity, the voltage is vin-vip. Simultaneously, the plates of each capacitor in the switching capacitor bank disconnected by the sampling conversion switch are connected to ground, gnd. The total capacitance of the switching capacitor bank is the same as the capacitance of the sampling capacitor bank, equal to 2. N-1 C. Therefore, sampling capacitor group 2 corresponds to the two polarity input terminals. N-1 The signal charges stored on C can be represented by the following formulas:

[0038] (vip-vin)×2 N-1 C = 2ΔV × 2 N-1 C = Q p

[0039] (vin-vip)×2 N-1 C = -2ΔV × 2 N-1 C = Q n

[0040] In the input analog signal, the vip input signal is equal to the power supply Vdd, and the vin input signal is equal to the ground Gnd. Therefore, the above formula can be transformed into:

[0041] (vip-vin)×2 N-1 C = vdd × 2 N-1 C = Q p

[0042] (vin-vip)×2 N-1 C = -vdd × 2 N-1 C = Q n

[0043] Because during sampling, the two plates of each capacitor in the sampling capacitor bank are connected to the input signal, there is no common-mode voltage limitation.

[0044] In sub-cycle φ1, the first conversion of the conversion phase, all sampling conversion switching switches are closed, and both the pre-sampling and post-sampling switch groups are open. All switches connected to the capacitors of the first upsampling group are connected to high potential, and all switches connected to the capacitors of the second upsampling group are connected to low potential. All switches connected to the capacitors of the first downsampling group are connected to high potential, and all switches connected to the capacitors of the second downsampling group are connected to low potential. In the conversion capacitor group, 2... N-2 All the switching switches connected to the capacitor conversion group are connected to the high potential, 2 N-2 All switches connected to the capacitor switching group below the current capacitor are connected to a high potential, while all switches connected to other capacitors are connected to a low potential. A comparator compares these switches, the digital logic circuit outputs the first bit of the digital circuit, and outputs a feedback control signal to the capacitor switch array; and thereafter until φ... N During the sub-cycle, the sampling conversion switching group is always fully closed, while the pre-sampling switching group and the post-sampling switching group are always fully open. Figure 3b As shown;

[0045] Make up 2 N-1 Two groups of capacitor sampling groups N-2 The two plates of the capacitor are connected to the power supply Vdd and ground GND, respectively. Meanwhile, 2 N-2 The capacitor plates of the capacitor conversion group are connected to the power supply Vdd at two points. N - 3 The capacitors in one capacitor conversion group, two capacitor conversion groups, one capacitor conversion group, and one capacitor conversion matching group have their second plate grounded (gnd). This artificially creates an equivalent common-mode voltage (vdd / 2) on the first plate of the two capacitor groups of different polarities. The signal voltage on the first plate can be expressed by the following formula:

[0046]

[0047]

[0048] v ip -v in =2ΔV=vdd

[0049] It can be seen that regardless of the common-mode voltage of the input signal, since the signal acquired on the capacitor only has its differential information and no DC information, the capacitor switching array can generate an equivalent common-mode voltage during the conversion process.

[0050] The φ2 sub-cycle is the second conversion stage. Based on the feedback control signal output from the φ1 sub-cycle, the switch is turned. If the voltage at the second input terminal of the comparator is greater than the voltage at the first input terminal, then the 2... N-1 All the switching switches connected to the sampling groups of the capacitors are connected to high potential. N-1 All switches connected to the capacitor sampling group are connected to low potential, and vice versa. When these are interchanged, all switches connected to the capacitor group are floating. The comparator compares the signals, the digital logic circuit outputs the second bit of the digital circuit, and outputs a feedback control signal to the capacitor switch array. Figure 3c As shown;

[0051] The first comparator comparison output passes through a φ2 sub-cycle, for 2 N-1 In this specific embodiment, the switching of the capacitor plates connected to the two capacitors of the capacitor sampling group is adjusted by changing the 2 N - 1 All the switching switches connected to the sampling groups of the capacitors are connected to the power supply Vdd. N-1 All the switching switches connected to the capacitor sampling group are connected to ground (gnd), and simultaneously disconnected from 2 N-2 One capacitor conversion group, 2 N-3 The capacitor plates of one capacitor conversion group, two capacitor conversion groups, one capacitor conversion group, and one capacitor conversion matching group are connected to the power supply VDD / ground GND, making it a floating capacitor array, so that 2 N-1 The voltage at plate two of the capacitor in the capacitor sampling group has a new voltage value, which means that the input signal voltage of the comparator has been updated.

[0052] v ip =2ΔV=vdd

[0053] v in =0

[0054] v ip -v in =vdd

[0055] The comparator performs a second comparison based on the input voltage and outputs the result to the logic circuit.

[0056] The φ3 sub-cycle is the third conversion stage. Based on the feedback control signal output from the φ2 sub-cycle, the switch is turned. If the voltage at the second input terminal of the comparator is greater than the voltage at the first input terminal, then the 2... N-2All the switching switches connected to the capacitor conversion group are connected to the high potential, 2 N-2 All switches connected to the capacitor switching group are connected to low potential, and vice versa. Switches connected to other capacitors remain unchanged from the previous sub-cycle. The comparator compares the switches, the digital logic circuit outputs the third bit of the digital circuit, and outputs a feedback control signal to the capacitor switch array. Figure 3d As shown;

[0057] The comparison output of the second comparator passes through a φ3 sub-cycle, and is compared with 2. N-2 Adjusting the switch connecting the capacitor plates of the capacitor switching group to the second plate gives the voltage of the first plate a new value, thus updating the input signal voltage of the comparator. At this time, 2 N-3 The capacitors in one capacitor conversion group, two capacitor conversion groups, one capacitor conversion group, and one capacitor conversion matching group are still in a floating state.

[0058]

[0059]

[0060]

[0061] The comparator then performs a third comparison and outputs the result to the logic circuit.

[0062] Referring to the φ3 sub-period, and so on, until φ N Sub-cycle, which is the Nth transformation in the transformation phase, according to φ N-1 The feedback control signal output by the sub-cycle switches the changeover switches. If the voltage at the second input terminal of the comparator is greater than the voltage at the first input terminal, all changeover switches connected to the upper changeover group of the two capacitors are connected to the high potential, and all changeover switches connected to the lower changeover group of the two capacitors are connected to the low potential. Otherwise, they are interchanged. The changeover switches connected to other capacitors remain unchanged from the state of the previous sub-cycle. The comparator compares the values, and the digital logic circuit outputs the Nth bit of the digital circuit.

[0063] The process repeats with reference to the φ3 sub-cycle, and so on, until the control logic for the second plate of the capacitor in one capacitor switching group is determined. One switching cycle then ends. At this point, the differential input result of the comparator is 0.

[0064] The successive approximation analog-to-digital converter and its conversion method described in this invention, during the signal sampling period, uses half of the capacitors in the capacitor switch array as a sampling capacitor group, and shorts the two ends of the other half of the capacitors to the same reference potential for discharge (in a specific embodiment of this invention, shorting to 0 potential), which can be temporarily referred to as the short-circuited capacitor group or the conversion capacitor group. After entering the conversion process, one end of the sampling capacitor group and the conversion capacitor group is shorted and connected to the input port of the comparator, and the other end of the sampling capacitor group and the conversion capacitor group are connected to the reference high / low potential respectively. This is equivalent to resetting the sampling signal capacitor, so that no matter how the common-mode voltage of the input signal changes, the common-mode voltage of the signal to be processed at the comparator input port is fixed at the midpoint between the reference high potential and the reference low potential. Therefore, this invention can be applied to analog signals with common-mode voltage. Moreover, this invention has a simple structure and is easy to implement. In addition, the successive approximation analog-to-digital converter described in this invention also increases the amplitude of the signal change at each step during the conversion process (except for the first and last steps), reducing the error rate of the comparator during the conversion process.

[0065] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A successive approximation analog-to-digital converter, characterized in that, The analog-to-digital converter includes: a capacitor switch array, a comparator, and digital logic circuits connected in sequence; the number of capacitors in the capacitor switch array is 2*2. N N represents the number of bits in the digital signal output by the digital logic circuit, and N is a positive integer; the capacitor switch array includes: a sampling capacitor group, a conversion capacitor group, and a sampling-conversion switching switch group connecting the two; during sampling, the sampling-conversion switching switch group is in an open state; during conversion, the sampling-conversion switching switch group is in a closed state; the capacitor switch array also includes a pre-sampling switch group and a post-sampling switch group; The sampling capacitor bank includes 2 N The capacitors are divided into 2 equal parts. N-1 One capacitor upsampling group and 2 N-1 One capacitor downsampling group; 2 N-1 The plates of each capacitor in the capacitor upsampling group are simultaneously connected to the first input terminal of the analog signal through the same presampling switch in the presampling switch group. N-1 Each capacitor in the capacitor upsampling group has its second plate connected to the second input terminal of the analog signal via a pre-sampling switch in the pre-sampling switch group, and is switched to either a high or low potential via a changeover switch; 2 N-1 Each capacitor in the capacitor downsampling group has its plates connected to the second input terminal of the analog signal simultaneously through the same presampling switch in the presampling switch group. N-1 The second plate of each capacitor in the capacitor downsampling group is connected to the first input terminal of the analog signal through a presampling switch in the presampling switch group, and is switched to high or low potential through a conversion switch. The conversion capacitor bank includes 2 N The capacitors are divided into multiple capacitor up-conversion groups, multiple capacitor down-conversion groups, one capacitor up-conversion matching group, and one capacitor down-conversion matching group; the specific number of capacitors in each capacitor up-conversion group and each capacitor down-conversion group is 2 respectively. N-2 2 N-3 ...and so on, 2 1、 2 0 The plates of each capacitor in each capacitor up-conversion group and each capacitor up-conversion matching group are simultaneously connected to the two capacitors through the same sampling conversion switching switch of the sampling conversion switching switch group. N-1 The first plate of each capacitor in each capacitor up-sampling group is connected to the first input terminal of the comparator. The second plate of each capacitor in each capacitor up-conversion group and one capacitor up-conversion matching group is switched to a high potential or a low potential via a switching switch. The first plate of each capacitor in each capacitor down-conversion group and one capacitor down-conversion matching group is simultaneously connected to the two capacitors via the same sampling conversion switching switch group. N-1 The first plate of each capacitor in each capacitor downsampling group is connected to the second input terminal of the comparator. The second plate of each capacitor in each capacitor downconversion group and one capacitor downconversion matching group is connected to a high potential or a low potential switching switch respectively.

2. The successive approximation analog-to-digital converter according to claim 1, characterized in that, The post-sampling switch group includes a post-up-sampling switch and a post-down-sampling switch. One end of the post-up-sampling switch is connected to the first input terminal of the comparator, and the other end is connected to a low potential. One end of the post-down-sampling switch is connected to the second input terminal of the comparator, and the other end is connected to a low potential.

3. The successive approximation analog-to-digital converter according to claim 1, characterized in that, The 2 N-1 The capacitor upsampling groups are evenly divided into a first upsampling group capacitor and a second upsampling group capacitor, the 2 N-1 The capacitor downsampling groups are averaged into the first downsampling group capacitor and the second downsampling group capacitor.

4. The successive approximation analog-to-digital converter according to claim 1, characterized in that, The changeover switch includes: a high-position switch connected to a high potential and a low-position switch connected to a low potential; the high potential is a power source and the low potential is ground.

5. A conversion method for a successive approximation analog-to-digital converter, characterized in that, Using the analog-to-digital converter as described in any one of claims 1-4, within one conversion cycle T, φ0, φ1, φ2, φ3, ..., φ N Sub-period, the conversion method includes: During the φ0 sub-cycle, which is the sampling phase, all sampling conversion switching switches are open, all pre-sampling and post-sampling switching switches are closed, all switching switches connected to the sampling capacitor bank are open, and all switching switches connected to the conversion capacitor bank are connected to low potential. In sub-cycle φ1, the first conversion of the conversion phase, all sampling conversion switching switches are closed, and both the pre-sampling and post-sampling switch groups are open. All switches connected to the capacitors of the first upsampling group are connected to high potential, and all switches connected to the capacitors of the second upsampling group are connected to low potential. All switches connected to the capacitors of the first downsampling group are connected to high potential, and all switches connected to the capacitors of the second downsampling group are connected to low potential. In the conversion capacitor group, 2... N-2 All the switching switches connected to the capacitor conversion group are connected to the high potential, 2 N-2 All switches connected to the capacitor switching group below the current capacitor are connected to a high potential, while all switches connected to other capacitors are connected to a low potential. A comparator compares these switches, the digital logic circuit outputs the first bit of the digital circuit, and outputs a feedback control signal to the capacitor switch array; and thereafter until φ... N During the sub-cycle, the sampling conversion switching group is always fully closed, while the pre-sampling switching group and the post-sampling switching group are always fully open. The φ2 sub-cycle is the second conversion stage. Based on the feedback control signal output from the φ1 sub-cycle, the switch is turned. If the voltage at the second input terminal of the comparator is greater than the voltage at the first input terminal, then the 2... N-1 All the switching switches connected to the sampling groups of the capacitors are connected to high potential. N-1 All the switching switches connected to the capacitor sampling group are connected to low potential, and vice versa. All the switching switches connected to the switching capacitor group are floating. The comparator compares them, the digital logic circuit outputs the second bit of the digital circuit, and outputs a feedback control signal to the capacitor switch array. The φ3 sub-cycle is the third conversion stage. Based on the feedback control signal output from the φ2 sub-cycle, the switch is turned. If the voltage at the second input terminal of the comparator is greater than the voltage at the first input terminal, then the 2... N-2 All the switching switches connected to the capacitor conversion group are connected to the high potential, 2 N-2 All switching switches connected to the capacitor switching group are connected to the low potential, and vice versa. The switching switches connected to other capacitors remain unchanged from the previous sub-cycle. The comparator compares them, the digital logic circuit outputs the third bit of the digital circuit, and outputs a feedback control signal to the capacitor switch array. Referring to the φ3 sub-period, and so on, until φ N Sub-cycle, which is the Nth transformation in the transformation phase, according to φ N-1 The feedback control signal output by the sub-cycle switches the changeover switches. If the voltage at the second input terminal of the comparator is greater than the voltage at the first input terminal, all changeover switches connected to the upper changeover group of the two capacitors are connected to the high potential, and all changeover switches connected to the lower changeover group of the two capacitors are connected to the low potential. Otherwise, they are interchanged. The changeover switches connected to other capacitors remain unchanged from the state of the previous sub-cycle. The comparator compares the values, and the digital logic circuit outputs the Nth bit of the digital circuit.

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