A low-complexity concatenated DMF-DDC correlation peak extraction method for direct spread signals

Abstract

A direct spread signal low complexity cascade type DMF-DDC correlation peak extraction method, comprising the following steps: step 1: the intermediate frequency analog signal is sent to an analog-to-digital converter ADC for sampling, and an intermediate frequency spread digital signal after sampling is output; step 2: the signal is sent to a cascade type DMF-DDC module for processing, in which chip matching, DDC and chip matching are realized in sequence; step 3: low-pass filtering. The method can greatly reduce the complexity of hardware implementation and reduce the use of hardware resources on the basis of keeping the DS-SS signal correlation peak extraction efficiency unchanged.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic information technology, and particularly relates to a low-complexity cascade DMF-DDC correlation peak extraction method of DS-SS signal. BACKGROUND

[0002] DS-SS signal and DS / FH-SS signal have very strong anti-interference ability, and are widely used in modern military communication. A biggest feature of DS-SS signal is that low-rate information bits are multiplied with a specific high-rate pseudo-noise sequence, and the bandwidth of the multiplied signal is expanded many times compared with that before multiplication, so that the signal power spectrum is very low, and the signal can be hidden in noise to complete information transmission. At the receiving end, the same pseudo-noise sequence is used to multiply the DS-SS signal to complete the despreading of the DS-SS signal, and the correlation peak extraction is a key step to realize the despreading of the DS-SS signal.

[0003] There are generally two methods for extracting the correlation peak of DS-SS signal: one is to use a correlator to perform serial search, which has a simple idea and low hardware implementation complexity, but has a long synchronization capture time, and a tracking loop is needed to maintain and optimize the synchronization process. The other is to use a matched filter to realize parallel capture of the spread spectrum input data, which can realize synchronization within one PN code period, but the hardware complexity increases linearly with the PN code length.

[0004] According to the performance index requirement, the matched filter is used to realize the correlation peak extraction of DS-SS signal, and a low-complexity cascade DMF-DDC correlation peak extraction method of DS-SS signal is proposed to solve the problem of huge hardware resource consumption. SUMMARY

[0005] The present application aims at the problem of high implementation complexity of the existing intermediate frequency DMF, and proposes a low-complexity cascade DMF-DDC correlation peak extraction method of DS-SS signal. The method combines DMF and DCC together to design, divides the classical matched filtering process into PN chip matching and intra-chip matching two processes, thereby greatly reducing the hardware implementation complexity on the basis of keeping the efficiency of the correlation peak extraction of DS-SS signal unchanged. Thus, it is possible to realize real-time extraction of the correlation peak of five-channel DS-SS in a single FPGA.

[0006] The present application is realized by the following technical scheme:

[0007] A low-complexity cascade DMF-DDC correlation peak extraction method of direct spread signal, comprising the following steps:

[0008] Step 1: send the intermediate frequency analog signal into an analog-to-digital converter (ADC) for sampling, and output the sampled intermediate frequency spread spectrum digital signal;

[0009] Step 2: send the intermediate frequency spread spectrum digital signal into a cascaded DMF-DDC module for processing; the cascaded DMF-DDC is composed of three parts: the first part is chip matching, which realizes single sampling matching of the spread spectrum data; the second part is DDC processing, which realizes down-conversion operation of the output data after chip matching; and the third part is Chip matching, which respectively realizes accumulation summation of the in-phase and quadrature two-way data output by DDC.

[0010] Step 2.1: chip matching: specifically, the intermediate frequency spread spectrum data is first sequentially input into a shift register group with a length of NXM under the control of a sampling clock, and every M interval has a tap to multiply (XOR) with a local PN code, thereby completing single sampling chip matching.

[0011] Step 2.2: digital down-conversion processing: down-conversion operation of the output data after chip matching, specifically, multiplying the output data after chip matching with the local carrier of the in-phase and quadrature branches respectively, thereby completing the down-conversion operation of the chip output value, and outputting the baseband component and the second harmonic component;

[0012] Step 2.3: Chip matching: the in-phase and quadrature two-way digital down-conversion operation results are respectively sent into an M-order shift register, and the outputs of each register are added in parallel, thereby completing Chip matching;

[0013] Step 3: low-pass filtering: the correlation values of the in-phase and quadrature two branches output after Chip matching are respectively sent to a low-pass filter to filter out the second harmonic component generated by DDC, thereby completing matched filtering.

[0014] Compared with the prior art, the present application has the following advantages:

[0015] The present application combines DMF and DDC together for joint design, divides the classical matched filtering process into two cascaded processes of PN chip matching and Chip internal matching, greatly reduces the hardware implementation complexity on the basis of keeping the extraction efficiency of the DS-SS signal correlation peak unchanged. The feasibility of the present application is verified through theoretical analysis, computer simulation and FPGA implementation. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is the time domain waveform and spectrum diagram of the intermediate frequency spread spectrum digital signal of the cascaded DMF-DDC;

[0017] Figure 2 is the correlation value output waveform diagram after chip matching of the cascaded DMF-DDC.

[0018] Figure 3 Waveform diagram of the in-phase branch after matching of the cascaded DMF-DDC Chip;

[0019] Figure 4 Waveform diagram of the quadrature branch after matching of the cascaded DMF-DDC Chip;

[0020] Figure 5 Waveform diagram of the in-phase branch after low-pass filtering;

[0021] Figure 6 Waveform diagram of the quadrature branch after low-pass filtering;

[0022] Figure 7 Waveform diagram of the correlation value in the time domain after non-coherent processing;

[0023] Figure 8 Hardware resource consumption statistics diagram;

[0024] Figure 9 Total hardware resource consumption statistics diagram;

[0025] Figure 10 Chip matching structure block diagram;

[0026] Figure 11 DDC structure block diagram;

[0027] Figure 12 Chip matching structure block diagram;

[0028] Figure 13 Low-complexity cascaded DMF-DDC correlation peak extraction implementation block diagram;

[0029] Figure 14 Low-complexity cascaded DMF-DDC correlation peak extraction method flowchart for a direct spread signal. DETAILED DESCRIPTION

[0030] The technical solutions will be described clearly and completely below in conjunction with the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0031] Embodiment 1

[0032] A low-complexity cascaded DMF-DDC correlation peak extraction method for a direct spread signal includes the following steps:

[0033] Step 1: Send the intermediate-frequency analog signal into the analog-to-digital converter (ADC) for sampling. There is no specific model restriction for the ADC, and there are no special requirements. You can select the relevant ADC on the market according to your needs.

[0034] The output of the sampled intermediate-frequency spread-spectrum digital signal is:

[0035]

[0036] In formula (1): r(t) is the intermediate-frequency spread-spectrum digital signal; d(i) is the i-th information bit sent. If BPSK modulation is used, then d(i) = ±1; c j (j = 0, 1,..., N - 1) is the j-th chip of the spreading sequence; M is the number of samples per chip; N is the number of chips; g(t) is the modulation pulse used when each chip is transmitted. Ideally, it satisfies T c and T s are the chip period and bit period respectively.

[0037] Step 2: Send the intermediate-frequency spread-spectrum digital signal into the cascaded DMF-DDC module for processing; the cascaded DMF-DDC consists of three parts: the first part is chip matching, which realizes single-sampling matching of the spread-spectrum data; the second part is DDC processing, which realizes the down-conversion operation of the data output after chip matching; the third part is Chip matching, which realizes the accumulation and summation of the in-phase and quadrature two-way data output by the DDC respectively.

[0038] Step 2.1: Chip matching: Under the control of the sampling clock, the intermediate-frequency spread-spectrum data enters a shift register group with a length of N×M in sequence. The shift register group has a tap every M intervals, which are multiplied (XOR) with the local PN code respectively to complete the single-sampling chip matching; the specific expression is as follows:

[0039] In formula (2), corr pn (t) is the output value after chip matching; since the intermediate-frequency carrier is not removed, the output value after chip matching will contain carrier components;

[0040] Step 2.2: Digital down-conversion processing: The down-conversion operation of the data output after chip matching. Specifically, the output data after chip matching is multiplied with the local carriers of the in-phase and quadrature branches respectively, so as to complete the down-conversion operation of the chip output value and output the baseband component and the second harmonic component; the expression of the in-phase branch is as follows:

[0041]

[0042] The expression of the quadrature branch is as follows:

[0043]

[0044] In formula (3) and formula (4) corr is the in-phase branch output value after DDC; corr DDCQ (t) is the quadrature branch output value after DDC; cos(s′ m ), sin(s′ m )(m = 1, 2, …, M) are local in-phase and quadrature branch carriers, specifically and

[0045] Step 2.3: Chip matching: the in-phase and quadrature two-way digital down conversion operation results are respectively sent into an M-order shift register, the outputs of each level of the register are added in parallel, and then the Chip matching is completed;

[0046] Step 3: low-pass filtering: the correlation values of the in-phase and quadrature two branches output after Chip matching are respectively sent to a low-pass filter to filter out the second harmonic components generated by DDC, and the matched filtering is completed; the I-channel data expression output after low-pass filtering is respectively:

[0047]

[0048] The Q-channel data expression is respectively:

[0049]

[0050] In formula (5) and formula (6), corr chipI is the I-channel output value after low-pass filtering; corr chipQ is the Q-channel output value after low-pass filtering;

[0051] When the local carrier is synchronized with the intermediate frequency input carrier through the carrier tracking loop, formula (6) will be 0, and since the phase difference between the local carrier and the intermediate frequency input carrier is very small, cos(s m -s′ m ) in formula (5) can be equal to 1; the correlation peak time is extracted by comparing the modulus values of the two-way correlation values with a certain threshold, and the initial synchronization of the PN code is realized.

[0052] Embodiment 2

[0053] In order to easily illustrate the feasibility of the scheme from the principle, the following design example is obtained under the condition of high signal-to-noise ratio. In actual situations, the signal-to-noise ratio will be much lower than this condition.

[0054] Example design parameters: sampling bit width is 8 bits; number of channels is 5; information rate is 32 kbps; PN code length is 127, i.e., the spread spectrum chip rate is 4.064 Mcps; intermediate frequency carrier frequency is 24.384 MHz (exactly an integer multiple of the spread spectrum chip rate); signal-to-noise ratio is 30 dB; sampling rate is 20.32 Msps (the sampling rate is 5 times the chip rate and lower than the carrier frequency, which is undersampling).

[0055] like Figure 1 The figure shows the time-domain waveform and spectrum of the intermediate frequency (IF) spread spectrum digital signal of the DMF-DDC. According to the simulation parameters, after undersampling by 20.32 Msps, the spectrum of the IF spread spectrum data is equivalent to the spectrum of the IF spread spectrum signal with a carrier frequency of 4.064 MHz. Furthermore, since a chip interval is 6 times (an integer multiple) of the IF carrier period and 5 times the sampling rate, the IF carrier information carried by the 5 samples within a chip of the IF signal is periodic; that is, the carrier sample values ​​of the preceding and following chips are the same. This characteristic makes it possible to design cascaded DMF-DDCs.

[0056] Step 2 Simulation Results:

[0057] from Figure 2 As can be seen, when the local PN code is aligned with the PN code of the input spread spectrum data, the first part of the cascaded DMF-DDC will output a correlation peak (such as...). Figure 2 As shown in the upper half of the graph), due to the presence of an intermediate frequency carrier, the peak value exhibits a bipolar characteristic (e.g., Figure 2 (The lower half of the figure is shown).

[0058] Step 4 Simulation Results:

[0059] from Figure 3 and Figure 4 It can be seen that the polarity of the two correlation values ​​matched by DDC and Chip is basically unipolar, but there are still high-frequency components in the peak waveform, which need to be filtered out by a low-pass filter in subsequent processing. In addition, in the actual system, since there will definitely be a certain frequency deviation between the local carrier and the intermediate frequency carrier of DDC at the beginning, the frequency deviation is set to 2KHz in the simulation. This is reflected in the correlation values ​​of the in-phase and quadrature branches in the figure above, which modulate a carrier component.

[0060] Step 5 Simulation Results:

[0061] After low-pass filtering, the in-phase and quadrature branches remove the second harmonic component generated by the DDC, such as... Figure 5 and Figure 6 As shown: the high-frequency components in the peak waveform have been clearly filtered out.

[0062] likeFigure 7 As shown, the filtered in-phase and quadrature branch correlation values are used to extract the correlation peak. Since there is a frequency offset at the beginning, a non-coherent threshold control method is used to obtain the correlation peak, thereby achieving initial timing synchronization of the PN chip. As shown: the correlation peak after non-coherent processing is very obvious, thereby it is easier to extract the occurrence time of the correlation peak, thereby achieving accurate timing of the PN code.

[0063] Embodiment 3

[0064] Complexity comparison:

[0065] Table 1 FPGA resource consumption table when two schemes are used to realize one channel matched filtering

[0066]

[0067]

[0068] From the above table 1, Figure 8 and Figure 9 It can be seen that the classic intermediate frequency filtering + DDC scheme needs only one matching, but needs to consume a large number of shift registers and multipliers. Since the high-bit-width multiplier occupies a large resource in the FPGA, the hardware implementation complexity of the classic scheme is high. On the contrary, the proposed low-complexity cascaded DMF-DDC correlation peak extraction method for DS-SS signal divides the matched filtering into chip matching and Chip matching two parts, which are realized before and after DDC respectively. The proposed method avoids the excessive use of multipliers, thereby effectively reducing the implementation complexity.

[0069] The above detailed description of the embodiments of the application provided in the drawings is not intended to limit the scope of the claimed application, but only represents selected embodiments of the application.

Claims

1. A low complexity cascaded DMF-DDC correlation peak extraction method for a direct spread signal, characterized by: The method comprises the following steps: Step 1: The intermediate frequency analog signal is sent into an analog-to-digital converter (ADC) for sampling, and the sampled intermediate frequency spread spectrum digital signal is output as: In formula (1), r(t) is the intermediate frequency spread spectrum digital signal; d(i) is the i-th information bit sent, d(i) = ±1 if BPSK modulation is used; c j is the j-th chip of the spread spectrum sequence, j = 0, 1,..., N-1; M is the sampling number of each chip; N is the chip number; g(t) is the modulation pulse used when each chip is sent, which satisfies T c and T s respectively are the chip period and the bit period; s m is the instantaneous phase of the carrier; cos(s m ) is the carrier of the intermediate frequency spread spectrum signal; Step 2: sending the intermediate frequency spread spectrum digital signal into a cascade DMF-DDC module for processing; The cascade DMF-DDC is composed of three parts: the first part is chip matching, which realizes single-sampling matching of the spread spectrum data; the second part is DDC processing, which realizes down-conversion operation on the output data after chip matching; and the third part is Chip matching, which respectively realizes accumulation summation of the in-phase and quadrature two-way data output by the DDC; Step 2.1: chip matching: under the control of a sampling clock, the intermediate frequency spread spectrum data are sequentially input into a shift register group with a length of NXM, and every M intervals of the shift register group have a tap for multiplication operation with a local PN code, thereby completing single-sampling chip matching; the specific expression is as follows: instantaneous phase; TS is a bit period; cos(s m ) is a carrier of the intermediate frequency spread spectrum signal; corr pn (t) is a code matched output value; g s (t - iTs) is a modulation pulse used at the time of transmission of the i-th bit Step 2.2: digital down-conversion processing: down-conversion operation on the output data after chip matching, specifically, multiplication operation of the output data after chip matching with the in-phase and quadrature branch local carriers, thereby completing down-conversion operation on the chip output value, and outputting baseband components and second harmonic components; the expression of the in-phase branch is as follows: Down: corr (t) is the in-phase branch output value after DDC; corr DDCI (t) is the in-phase branch output value after DDC; corr DDCQ (t) is the in-phase branch output value after DDC; corr m (t) is the in-phase branch output value after DDC; corr m ) are local in-phase and quadrature branch carriers, specifically and ω' is the carrier angular frequency, is the initial phase, m = 1, 2, 3,..., M, m is the number of chips, and M is the number of samples per chip; Step 2.3: Chip matching: sending the in-phase and quadrature two-way digital down-conversion operation results into an M-order shift register, respectively, parallel adding the outputs of the registers, and then completing Chip matching; Step 3: low-pass filtering: sending the correlation values of the in-phase and quadrature two branches output after Chip matching to low-pass filters respectively to filter out the second harmonic components generated by the DDC, and completing matched filtering; the expression of the I-way data output after low-pass filtering is as follows: In formula (5) and formula (6), corr chipI is the I channel output value filtered by a low-pass filter; corr chipQ is the Q channel output value filtered by a low-pass filter; wherein: Δs m is the difference frequency component of the local carrier from the input carrier; sin(Δs m ) is the quadrature branch carrier.

2. The low complexity concatenated DMF-DDC correlation peak extraction method for a direct spread signal according to claim 1, characterized in that: When the local carrier is synchronized with the intermediate frequency input carrier by the carrier tracking loop, formula (6) will be 0, and since the phase difference between the local carrier and the intermediate frequency input carrier is very small, cos(s m -s′ m ) = 1; the sum of the modulus values of the two correlation values is compared with a certain threshold, thereby extracting the correlation peak time and achieving the initial synchronization of the PN code.

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