Display panel and display device

Abstract

A display panel and a display device, the display panel comprising a virtual gate line (G2) and a virtual conductive part (31) in a non-display area (BB), the virtual conductive part (31) is in the orthographic projection of the substrate within the orthographic projection of the virtual gate line (G2) in the substrate, the virtual conductive part (31) and the virtual gate line (G2) form an equivalent capacitance, by setting the RC load of the virtual gate line (G2) to match the RC load of the gate line (Gl) of the display area (AA), and taking the virtual gate line (G2) as the scan load of the second GOA unit (200) in the display panel which only provides a reset signal, so that the second GOA unit (200) and the first GOA unit (100) have a matched total load, thereby improving the display brightness unevenness.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] The display panel sequentially opens each row of scan lines and closes the scan lines of other rows under the drive of the gate drive signal provided by the gate drive circuit, thereby driving only the TFTs corresponding to the pixel units in that row to achieve line-by-line scanning. In related technologies, there is a problem of uneven display brightness caused by different loads on the gate drive signal.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display panel and display device.

[0005] According to one aspect of this disclosure, a display panel is provided, the display panel including a pixel driving circuit and a gate driving circuit, the pixel driving circuit being used to drive a light-emitting device to emit light, the pixel driving circuit including a driving transistor, the gate of the driving transistor being connected to a gate line; the gate driving circuit being used to provide a gate driving signal to the pixel driving circuit; the display panel further including: a substrate, the substrate including a display area and a non-display area located on one side of the display area; a second conductive layer located on one side of the substrate, the second conductive layer including: a plurality of gate lines located in the display area, the plurality of gate lines extending along the row direction and spaced apart in the column direction in their orthogonal projections on the substrate; a plurality of virtual gate lines located in the non-display area, the plurality of virtual gate lines extending along the row direction and spaced apart in the column direction in their orthogonal projections on the substrate; the display panel further including: virtual conductive portions located in the non-display area. The virtual conductive portion and the virtual gate line are located on different conductive layers, and the orthographic projection of the virtual conductive portion on the substrate is located within the orthographic projection of the virtual gate line on the substrate. The virtual conductive portion is used to form an equivalent capacitance with the virtual gate line. The RC load of the virtual gate line is matched with the RC load of the gate line. The gate driving circuit includes multiple first GOA units and multiple second GOA units. The first GOA units are correspondingly arranged with the gate line. The first GOA units are used to provide a gate driving signal to the nth row of gate lines and a reset signal to the (ni)th row of gate lines. The second GOA units are correspondingly arranged with the virtual gate lines. One second GOA unit is connected to one row of the virtual gate line and provides a reset signal to the (ni)th row of gate lines. n is a positive integer greater than or equal to 1 and less than or equal to N, i is a positive integer less than n, and N is the total number of rows of gate lines in the display area.

[0006] In an exemplary embodiment of this disclosure, the resistance value of the virtual gate line is matched with the resistance value of the gate line; the gate line and the conductive structure at the corresponding position form a first equivalent capacitance, the virtual conductive portion and the virtual gate line form a second equivalent capacitance, and the second equivalent capacitance is matched with the first equivalent capacitance.

[0007] In an exemplary embodiment of this disclosure, the virtual gate line includes a first side and a second side disposed opposite to each other in the column direction, and the virtual conductive portion includes a third side and a fourth side disposed opposite to each other in the column direction. The distance between the orthographic projection of the first side on the substrate and the orthographic projection of the second side on the substrate is L1, and the distance between the orthographic projection of the third side on the substrate and the orthographic projection of the fourth side on the substrate is L2. L1 / L2 is greater than or equal to 1 / 10 and less than or equal to 1.

[0008] In an exemplary embodiment of this disclosure, the virtual gate line has a first component and a second component, the width of the first component in the column direction being smaller than the width of the second component in the column direction; the virtual conductive portion includes a first sub-conductive portion and a second sub-conductive portion, the first sub-conductive portion being located within the orthographic projection of the first component on the substrate, and the second sub-conductive portion being located within the orthographic projection of the second component on the substrate.

[0009] In an exemplary embodiment of this disclosure, the first electrode of the driving transistor is connected to a data line, and the display panel further includes: a third conductive layer located on the side of the second conductive layer away from the substrate; the third conductive layer includes: a plurality of data lines extending along the column direction and spaced apart in the row direction in the orthographic projection of the substrate; one data line connects a first conductive portion and a virtual conductive portion in the same column; wherein the virtual gate line further includes a third component portion connected between the first component portion and the second component portion; the width of the third component portion in the column direction is smaller than the width of the first component portion in the column direction; the orthographic projection of the third component portion on the substrate intersects with the orthographic projection of the data line on the substrate, and the orthographic projections of the first component portion and the second component portion on the substrate are respectively located on both sides of the orthographic projection of the data line on the substrate.

[0010] In an exemplary embodiment of this disclosure, the first sub-conductive portion has a first extension length in the row direction when projected onto the substrate, and the second sub-conductive portion has a second extension length in the row direction when projected onto the substrate, wherein the first extension length is less than the second extension length.

[0011] In an exemplary embodiment of this disclosure, the first electrode of the driving transistor is connected to a data line, and the second electrode is connected to a pixel electrode. The display panel further includes: a third conductive layer located on the side of the second conductive layer away from the substrate; the third conductive layer includes: a plurality of first conductive portions located in the display area, the plurality of first conductive portions being arrayed in the row and column direction, the first conductive portions being used to form the first electrode of the driving transistor; a plurality of second conductive portions located in the display area, the second conductive portions corresponding one-to-one with the first conductive portions and electrically insulated from the first conductive portions, the second conductive portions being used to form the second electrode of the driving transistor; a plurality of data lines extending along the column direction and spaced apart in the row direction in the orthographic projection of the substrate, one data line connecting to the first conductive portions in the same column; and a fourth conductive layer located on the side of the third conductive layer away from the substrate; the fourth conductive layer includes: a plurality of pixel electrodes located in the display area, the plurality of pixel electrodes being spaced apart in the row and column direction, the pixel electrodes being located between the orthographic projections of adjacent data lines and adjacent gate lines in the orthographic projection of the substrate in the orthographic projection of the substrate, the pixel electrodes being connected to the second conductive portions through vias.

[0012] In an exemplary embodiment of this disclosure, the virtual conductive portion is located on the third conductive layer and connected to the data line. Virtual conductive portions in the same row are located on the same side of the data line to which they are connected. In any two adjacent rows of virtual conductive portions, the two virtual conductive portions connected to the same data line are located on opposite sides of the data line. The extension length of the virtual conductive portion in the row direction of its orthographic projection on the substrate is L3, and the spacing distance between the orthographic projections of adjacent data lines on the substrate in the row direction is L4. L3 / L4 is greater than or equal to 1 / 8 and less than or equal to 1 / 2.

[0013] In an exemplary embodiment of this disclosure, the virtual conductive portion is located on the third conductive layer and connected to the data line, the virtual conductive portions in the same row are located on the same side of the data line to which they are connected, and the virtual conductive portions in the same column are connected to the same side of the data line.

[0014] In an exemplary embodiment of this disclosure, the display panel further includes: a first conductive layer located between the second conductive layer and the substrate, the first conductive layer including: a plurality of common electrodes arranged in a row and column direction, wherein the orthographic projection of the common electrodes on the substrate overlaps with the orthographic projection of the pixel electrodes on the substrate; a semiconductor layer located on the side of the second conductive layer away from the substrate, the semiconductor layer including: a plurality of semiconductor structures, wherein the orthographic projection of the semiconductor structures on the substrate lies within the orthographic projection of the gate line on the substrate, the semiconductor structures being used to form the channel region of the driving transistor, and a portion of the structure of the gate line being used to form the gate of the driving transistor; the second conductive layer further includes: a common electrode line extending along the row direction, the common electrode line connecting each common electrode in the same row.

[0015] In an exemplary embodiment of this disclosure, the overlapping area of ​​the orthographic projection of the pixel electrode on the substrate and the orthographic projection of the common electrode on the substrate is S1, and the overlapping area of ​​the orthographic projection of the virtual conductive portion on the substrate and the orthographic projection of the virtual gate line on the substrate is S2, wherein S1 / S2 is greater than or equal to 1 / 10 and less than or equal to 1 / 2.

[0016] In an exemplary embodiment of this disclosure, the virtual conductive portion is located in the first conductive layer, the third conductive layer, or the fourth conductive layer.

[0017] In an exemplary embodiment of this disclosure, the first equivalent capacitance includes a first sub-equivalent capacitance between the gate line and the pixel electrode, a second sub-equivalent capacitance between the gate line and the common electrode line, a third sub-equivalent capacitance between the gate line and the data line, a fourth sub-equivalent capacitance between the gate line and the first conductive portion, and a fifth sub-equivalent capacitance between the gate and the second conductive portion.

[0018] In an exemplary embodiment of this disclosure, the spacing between adjacent gate lines projected onto the substrate in the column direction is L5, and the spacing between adjacent virtual gate lines projected onto the substrate in the column direction is L6, where L5 / L6 is less than or equal to 1 / 6.

[0019] In an exemplary embodiment of this disclosure, the orthographic projection pattern of the virtual gate line on the substrate is the same as the orthographic projection pattern of the gate line on the substrate.

[0020] This disclosure also provides a display device, including the display panel described in any embodiment of this disclosure.

[0021] The display panel provided in this disclosure solves the problem of uneven display brightness caused by different loads of GOA units by setting virtual grid lines and virtual conductive parts in the non-display area, forming an equivalent capacitance between the virtual conductive parts and the virtual grid lines, and matching the RC load of the virtual grid lines in the non-display area with that of the grid lines in the display area.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0024] Figure 1 This is a schematic diagram of the circuit structure of a pixel driving circuit according to one embodiment of the present disclosure;

[0025] Figure 2 This is a schematic diagram of the structure of a display panel according to one embodiment of the present disclosure;

[0026] Figure 3 for Figure 2 A schematic diagram of the structure of the second conductive layer in the middle;

[0027] Figure 4 for Figure 2 A schematic diagram of the structure of the third conductive layer in the middle;

[0028] Figure 5 for Figure 2 A schematic diagram of the structure of the first conductive layer in the middle;

[0029] Figure 6 for Figure 2 Schematic diagram of the middle semiconductor layer;

[0030] Figure 7 for Figure 2 Schematic diagram of the fourth conductive layer in the middle;

[0031] Figure 8 for Figure 2 Enlarged view of a portion of the BB region;

[0032] Figure 9 According to another embodiment of this disclosure Figure 2 Enlarged view of a portion of the BB region;

[0033] Figure 10 This is a schematic diagram of the structure of a virtual grid line and a virtual conductive part according to another embodiment of the present disclosure. Detailed Implementation

[0034] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. Matching reference numerals in the drawings denote matching or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0035] Figure 1 This is a schematic diagram of the circuit structure of a pixel driving circuit according to one embodiment of the present disclosure. The pixel driving circuit may include a driving transistor T, the gate of the driving transistor T is connected to the gate driving signal terminal Gate, the first terminal is connected to the data signal terminal Vdata, and the second terminal is connected to the pixel electrode Vcom.

[0036] Figure 2 This is a schematic diagram of the structure of a display panel according to one embodiment of the present disclosure. Figure 3 for Figure 2 A schematic diagram of the structure of the second conductive layer is shown below. Figure 2 , Figure 3As shown, the display panel provided in this exemplary embodiment may include a pixel driving circuit and a gate driving circuit. The pixel driving circuit is used to drive the light-emitting device to emit light. The pixel driving circuit includes a driving transistor T, and the gate of the driving transistor T is connected to a gate line G1. The gate driving circuit is used to provide a gate driving signal to the pixel driving circuit. The display panel may also include a substrate and a second conductive layer 2. The substrate may include a display area AA and a non-display area BB located on one side of the display area AA. The second conductive layer 2 is located on one side of the substrate. The second conductive layer 2 may include multiple gate lines G1 and multiple virtual gate lines G2. The multiple gate lines G1 are located in the display area AA. The projection of the multiple gate lines G1 onto the substrate extends along the row direction X and is spaced apart in the column direction Y. The multiple virtual gate lines G2 are located in the non-display area BB. The projection of the multiple virtual gate lines G2 onto the substrate extends along the row direction X and is spaced apart in the column direction Y. The display panel may also include a virtual conductive portion 31. The virtual conductive portion 31 is located in the non-display area BB. In the display area BB, the virtual conductive part 31 and the virtual gate line G2 are located on different conductive layers, and the orthographic projection of the virtual conductive part 31 on the substrate is located within the orthographic projection of the virtual gate line G2 on the substrate. The virtual conductive part 31 is used to form an equivalent capacitance with the virtual gate line G2. The RC load of the virtual gate line G2 is matched with the RC load of the gate line G1. The gate driving circuit includes multiple first GOA units 100 and multiple second GOA units 200. The first GOA units 100 are correspondingly arranged with the gate line G1. The first GOA units 100 are used to provide a gate driving signal to the nth row of gate lines G1 and a reset signal to the (ni)th row of gate lines G1. The second GOA units 200 are correspondingly arranged with the virtual gate line G2. One second GOA unit 200 is connected to one row of virtual gate lines G2 and provides a reset signal to the (ni)th row of gate lines G1. n is a positive integer greater than or equal to 1 and less than or equal to N, i is a positive integer less than n, and N is the total number of rows of gate lines G1 in the display area AA.

[0037] The display panel provided in this disclosure provides a virtual grid line G2 and a virtual conductive part 31 in the non-display area BB. The virtual conductive part 31 and the virtual grid line G2 form an equivalent capacitance, and the RC load of the virtual grid line G2 in the non-display area BB is matched with that of the grid line G1 in the display area AA. As a result, the load of the first GOA unit 100 is matched with the load of the second GOA unit 200, thereby solving the problem of uneven display brightness caused by different loads of the GOA units.

[0038] like Figure 2 As shown in this exemplary embodiment, the non-display area BB can be located on one side of the display area AA along the column direction Y. The extension length of the virtual gate line G2 in the row direction X can be the same as the extension length of the gate line G1 in the row direction X.

[0039] In this exemplary embodiment, gate line G1 and the corresponding conductive structure form a first equivalent capacitance, and virtual conductive portion 31 and virtual gate line G2 form a second equivalent capacitance. The RC load of virtual gate line G2 is the product of the resistance of virtual gate line G2 and the second equivalent capacitance, and the RC load of gate line G1 is the product of the resistance of gate line G1 and the first equivalent capacitance. Matching the RC load of virtual gate line G2 with the RC load of gate line G1 can be understood as the resistance of virtual gate line G2 being the same as the resistance of gate line G1 and the second equivalent capacitance being the same as the first equivalent capacitance. Alternatively, it can be that the resistance of virtual gate line G2, the second equivalent capacitance and the resistance of gate line G1 are correspondingly matched, and the product of the resistance of virtual gate line G2 and the second equivalent capacitance is the same as the product of the resistance of gate line G1 and the first equivalent capacitance.

[0040] In this exemplary embodiment, matching the resistance value of virtual gate line G2 with the resistance value of gate line G1 can be understood as the ratio of the resistance of virtual gate line G2 to the resistance of gate line G1 being within a set tolerance range. For example, the tolerance range can be 0.7 to 1.3. Therefore, when the ratio of the resistance of virtual gate line G2 to the resistance of gate line G1 is greater than or equal to 0.7 and less than or equal to 1.3, the resistance value of virtual gate line G2 is considered to match the resistance value of gate line G1. Similarly, matching the second equivalent capacitance with the first equivalent capacitance can be understood as the ratio of the second equivalent capacitance to the first equivalent capacitance being within a set tolerance range. For example, the tolerance range can be 0.7 to 1.3. Therefore, when the ratio of the second equivalent capacitance to the first equivalent capacitance is greater than or equal to 0.7 and less than or equal to 1.3, the second equivalent capacitance is considered to match the first equivalent capacitance. It should be understood that the tolerance range of the capacitor may be different from the tolerance range of the resistor.

[0041] In this exemplary embodiment, the gate line G1 and the corresponding conductive structure form a first equivalent capacitance. This first equivalent capacitance may include the equivalent capacitance formed by the gate line G1 and other conductive structures X in the same conductive layer, as well as the equivalent capacitance formed by the gate line G1 and conductive structures in other conductive layers. Specifically, the equivalent capacitance between the gate line G1 and other structures in the same conductive layer refers to the equivalent capacitance between the gate line G1 and other conductive structures adjacent to the gate line G1 in the second conductive layer 2. The equivalent capacitance between the gate line G1 and other conductive structures in other conductive layers refers to the equivalent capacitance between the gate line G1 and the conductive structures whose orthographic projections on the substrate intersect or are adjacent to the orthographic projection of the gate line G1 on the substrate. It should be understood that the adjacency of structure A and structure B in this exemplary embodiment can be understood as all or part of structure A's orthographic projection on the substrate and structure B's orthographic projection on the substrate being located within the same pixel unit.

[0042] It is understandable that in the gate driving circuit, the subsequent GOA unit provides a gate driving signal to the pixel driving circuit of its own row while also providing a reset signal to the pixel row driven by the previous GOA unit. Therefore, the last or last few GOA units are only used to provide a reset signal. This last or last few GOA units that only provide a reset signal are the second GOA unit 200 described in this exemplary embodiment. It can be seen that the second GOA unit 200 only has a reset load and no scan load, resulting in a stronger driving capability than other GOA units (i.e., the first GOA unit 100), causing the display brightness of the last or last few rows of pixel units to differ from the display brightness of other rows of pixel units.

[0043] In this exemplary embodiment, by additionally providing a virtual gate line G2 and a virtual conductive portion 31 in the non-display area BB, the resistance value of the virtual gate line G2 matches the resistance value of the gate of the normal pixel row, and the second equivalent capacitance formed by the virtual gate line G2 and the virtual conductive portion 31 matches the first equivalent capacitance formed by the gate line G1 of the normal pixel row. By connecting the second GOA unit 200 to the virtual gate line G2, the second GOA unit 200 can have a reset load of the normal pixel row as well as a scan load equivalent to the normal pixel row, thereby making the driving capability of the second GOA unit 200 the same as that of the first GOA unit 100, thereby solving the problem that the display brightness of the pixel row reset by the second GOA unit 200 is different from the display brightness of other row pixel units.

[0044] It should be understood that, in this exemplary embodiment, the number of second GOA units 200 and the number of pixel rows reset by the second GOA units 200 are the same as the number of pixel rows between a pixel row driven by a first GOA unit 100 and the reset pixel rows. For example, if i is 1, meaning a first GOA unit 100 provides a gate drive signal to the pixel driving circuit of the current row and a reset signal to the pixel driving circuit of the previous row, then the number of second GOA units 200 is 1, meaning a GOA unit provides a reset signal to the last row of pixel driving circuits in the display area AA; if i is 8, meaning a first GOA unit 100 provides a gate drive signal to the pixel driving circuit of the current row and a reset signal to the 8th row of pixel driving circuits located before the current pixel row, then the number of second GOA units 200 is 8, meaning 8 second GOA units 200 respectively provide reset signals to the last 8 rows of pixel driving circuits in the display area AA.

[0045] The display panel provided in this exemplary embodiment can be an LCD display panel, which can be applied to high PPI, high-load products such as large-size 8k displays. This disclosure only uses a schematic diagram of an LCD display panel for illustrative purposes. It should be understood that the display panel can also be an OLED display panel. By setting a load matching structure in the non-display area of ​​the OLED display panel as the scanning load for the GOA unit that only provides a reset signal, and only performing load matching of resistors and capacitors, the GOA unit that only provides a reset signal can have a load that matches other GOA units. This can also improve the display uniformity of the OLED display panel and reduce the space occupied by the load.

[0046] like Figure 3 As shown in this exemplary embodiment, the second conductive layer 2 includes a gate line G1 located in the display area AA and a virtual gate line G2 located in the non-display area BB. The gate line G1 in the display area AA is used to provide... Figure 1 The gate drive signal terminal Gate is connected to the first GOA unit 100 via gate line G1. The first GOA unit 100 provides a gate drive signal to the gate line G1, controlling the semiconductor structure 32 located in the semiconductor layer 3 to turn on or off, thereby controlling the on / off state of the drive transistor T. The virtual gate line G2 is connected to the second GOA unit 200, serving as the scan load of the second GOA unit 200, so that the second GOA unit 200 has a total load that matches that of the first GOA unit 100.

[0047] like Figure 3 As shown in this exemplary embodiment, the second conductive layer 2 may further include multiple common electrode lines COM located in the display area AA. The multiple common electrode lines COM extend along the row direction X and are spaced apart in the column direction Y in the orthogonal projection of the substrate. The common electrode lines COM are not connected to the gate line G1. The common electrode lines COM are connected to each isolated common electrode 11 of the first conductive layer 1 and provide voltage signals to each common electrode 11.

[0048] It should be understood that, in this exemplary embodiment, for a structure A to extend along the direction B means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip shape. The main part extends along the direction B, and the length of the main part extending along the direction B is greater than the length of the secondary part extending along other directions.

[0049] like Figure 2As shown in this exemplary embodiment, the display panel may further include a first conductive layer 1, a semiconductor layer 3, a third conductive layer 4, and a fourth conductive layer 5. The first conductive layer 1, the second conductive layer 2, the semiconductor layer 3, the third conductive layer 4, and the fourth conductive layer 5 are sequentially stacked on one side of the substrate. An insulating layer may be provided between the functional layers; for example, an insulating layer may be provided between the third conductive layer 4 and the fourth conductive layer 5. In this exemplary embodiment, the virtual conductive portion 31 may be located in the first conductive layer 1, the third conductive layer 4, or the fourth conductive layer 5. This disclosure only exemplifies the case where the virtual conductive portion 31 is located in the third conductive layer 4. Figure 4 for Figure 2 A schematic diagram of the structure of the third conductive layer in the middle. Figure 5 for Figure 2 A schematic diagram of the structure of the first conductive layer. Figure 6 for Figure 2 A schematic diagram of the structure of the middle semiconductor layer. Figure 7 for Figure 2 A schematic diagram of the structure of the fourth conductive layer.

[0050] like Figure 5 As shown in this exemplary embodiment, the first conductive layer 1 may include a plurality of common electrodes 11 located in the display area AA, and the plurality of common electrodes 11 are arrayed in the row and column direction. The orthographic projection of the common electrode line COM in the second conductive layer 2 onto the substrate may be located on the orthographic projection of the common electrode 11 onto the substrate. An insulating layer may not be provided between the second conductive layer 2 and the first conductive layer 1, so that the common electrode line COM is connected to each common electrode 11 of the first conductive layer 1. Furthermore, the common electrode 11 is not connected to the gate line G1 of the second conductive layer 2, and the orthographic projection of the common electrode 11 onto the substrate is located between the orthographic projections of adjacent gate lines G1 onto the substrate.

[0051] like Figure 6 As shown in this exemplary embodiment, the semiconductor layer 3 includes a plurality of semiconductor structures 32 arrayed in the row and column direction. The semiconductor structures 32 are located in the display area AA and are used to form the channel region of the driving transistor T. The orthogonal projection of the semiconductor structure 32 onto the substrate lies within the orthogonal projection of the gate line G1 onto the substrate. A portion of the structure of the gate line G1 forms the gate of the driving transistor T, providing a gate drive signal and a reset signal to the gate of the driving transistor T. It is understood that an insulating layer may be disposed between the semiconductor layer 3 and the second conductive layer 2.

[0052] like Figure 4As shown in this exemplary embodiment, the third conductive layer 4 may include a plurality of first conductive portions 41, a plurality of second conductive portions 42, and a plurality of data lines Data. The first conductive portions 41 and second conductive portions 42 are both located in the display area AA. The plurality of first conductive portions 41 are arrayed in the row and column direction, and the first conductive portions 41 are used to form the first electrode of the driving transistor T. The plurality of second conductive portions 42 are disposed one-to-one with the plurality of first conductive portions 41 and are electrically insulated from the first conductive portions 41. The second conductive portions 42 are used to form the second electrode of the driving transistor T. The data lines Data are used to form... Figure 1 The data signal terminal Vdata has multiple data lines Data whose projections on the substrate extend along the column direction Y and are spaced apart in the row direction X. Each data line Data connects to the first conductive portion 41 in the same column to provide a data signal to the first conductive portion 41, i.e., the first electrode of the driving transistor T. The second conductive portion 42 can be connected to the pixel electrode located in the fourth conductive layer 5 through vias, so that the second electrode of the driving transistor T is connected to the pixel electrode. The projection of the data line Data on the substrate can be located between the projections of adjacent common electrodes 11 on the substrate. The third conductive layer 4 can also have a bridging portion, which can be connected to the common electrode 11 of the first conductive layer 1 through vias, so that adjacent common electrodes 11 in the column direction Y are connected through the bridging portion, so that the common electrodes 11 form a grid structure. In addition, the third conductive layer 4 can also have other structures, such as a support structure. Furthermore, in this exemplary embodiment, the virtual conductive portion 31 can be located in the third conductive layer 4 and connected to the data line Data. The distribution relationship of the virtual conductive portion 31 relative to the data line Data can be found in the description of the following embodiments, and will not be elaborated here.

[0053] like Figure 7 As shown, in this exemplary embodiment, the fourth conductive layer 5 may include a plurality of pixel electrodes 51 located in the display area AA. The plurality of pixel electrodes 51 are spaced apart in the row and column direction. As described above, the pixel electrodes 51 can be connected to the second conductive portion 42 located in the third conductive layer 4 through vias to provide a voltage signal to the second electrode of the driving transistor T. Figure 7 , Figure 4 As shown in this exemplary embodiment, the pixel electrode 51 can be disposed one-to-one with the common electrode 11, and the orthographic projection of the pixel electrode 51 on the substrate overlaps with the orthographic projection of the common electrode 11 on the substrate. The basic orthographic projection of the pixel electrode 51 is located between the orthographic projections of two adjacent data lines Data on the substrate and between the orthographic projections of two adjacent gate lines G1 on the substrate. It should be understood that in other exemplary embodiments, the pixel electrode 51 may also have other structures, and this disclosure is not limited thereto.

[0054] Based on the above analysis, it can be understood that the first equivalent capacitance described in this exemplary embodiment may include the equivalent capacitance Cgc between the gate line G1 and the common electrode line COM, the equivalent capacitance between the gate line G1 and the first conductive portion 41 (i.e., the equivalent capacitance Cgd between the gate line G1 and the first electrode of the driving transistor T), the equivalent capacitance between the gate line G1 and the second conductive portion 42 (i.e., the equivalent capacitance Cgs between the gate line G1 and the second electrode of the driving transistor T), the equivalent capacitance Cgdx between the gate line G1 and the data line Data, and the equivalent capacitance Cpg between the gate line G1 and the pixel electrode 51. It should be understood that when the film layer structure of the display panel changes,

[0055] Furthermore, as can be seen from the above analysis, the non-display area BB in this exemplary embodiment is only used for load matching of the gate lines, and the non-display area BB only has a virtual gate line G2 in the second conductive layer 2 and a virtual conductive part 31 in the third conductive layer 4. The non-display area BB no longer has TFT, ITO and other structures. By matching the resistance and capacitance of the virtual gate line G2 with the resistance and capacitance of the gate lines of the display area AA, the structure of the non-display area BB can be simplified, and because of the simplified structure, the space occupied by the non-display area BB used for load matching can be minimized as much as possible.

[0056] As described in the above embodiments, the virtual conductive part 31 may be located in the first conductive layer 1, the third conductive layer 4, or the fourth conductive layer 5. This disclosure will further introduce the structure of the virtual gate line G2 and the virtual conductive part 31 by taking the virtual conductive part 31 located in the third conductive layer 4 as an example in conjunction with the accompanying drawings.

[0057] Figure 8 for Figure 2 A magnified view of a portion of the BB region, as shown below. Figure 8 As shown in this exemplary embodiment, the virtual conductive parts 31 can be alternately connected to both sides of the data line Data. Specifically, the virtual conductive parts 31 in the same row are located on the same side of the data line Data to which they are connected, and in any two adjacent rows of virtual conductive parts 31, the two virtual conductive parts 31 connected to the same data line Data are located on both sides of the data line Data. This means that for each data line Data, the virtual conductive parts 31 connected to it are alternately distributed on both sides of the data line Data.

[0058] Figure 9 According to another embodiment of this disclosure Figure 2 A magnified view of a portion of the BB region, as shown below. Figure 9As shown, the virtual conductive part 31 can be located on the same side of the data line Data. Specifically, the virtual conductive parts 31 in the same row are located on the same side of the data line Data to which they are connected, and the virtual conductive parts 31 in the same column are connected to the same side of the data line Data. Virtual conductive parts 31 connected to the same data line Data will not generate parasitic capacitance. However, because the signals of two adjacent data lines Data are different, parasitic capacitance is easily generated if the two are close to each other. By setting the virtual conductive parts 31 on the same side of the data line Data, the virtual conductive parts 31 in adjacent columns are spaced far apart, thus avoiding the formation of parasitic capacitance between virtual conductive parts 31 in different columns.

[0059] like Figure 8 As shown in this exemplary embodiment, the virtual gate line G2 may include a first component 331 and a second component 332. The width of the first component 331 in the column direction Y, projected onto the substrate, is smaller than the width of the second component 332 in the column direction Y, projected onto the substrate. The virtual conductive portion 31 may include a first sub-conductive portion and a second sub-conductive portion. The projection of the first sub-conductive portion onto the substrate is located within the projection of the first component 331 onto the substrate, and the projection of the second sub-conductive portion onto the substrate is located within the projection of the second component 332 onto the substrate. This is equivalent to the virtual gate line G2 overlapping with the virtual conductive portion 31 at the widened position, forming a second equivalent capacitance. The projection of the first sub-conductive portion onto the substrate has a first extension length in the row direction X, and the projection of the second sub-conductive portion onto the substrate has a second extension length in the row direction X. The first extension length is smaller than the second extension length. By overlapping the main part of the virtual conductive part 31 with the virtual gate line G2 at the widened position of the virtual gate line G2 to form a second equivalent capacitance, the extension length of the virtual conductive part 31 in the row direction X can be minimized.

[0060] like Figure 8 As shown in this exemplary embodiment, the virtual gate line G2 may further include a third component 333, and the width of the orthographic projection of the third component 333 onto the substrate in the column direction Y is smaller than the width of the orthographic projection of the first component 331 onto the substrate in the column direction Y. That is, the third component 333 is the narrowest position of the virtual gate line G2 in the column direction Y. The orthographic projection of the data line Data in the fourth conductive layer 5 onto the substrate may overlap with the orthographic projection of the third component 333 onto the substrate. By overlapping the data line Data at the narrowest position of the virtual gate line G2, the parasitic capacitance formed by the virtual gate line G2 and the data line Data can be reduced.

[0061] In this exemplary embodiment, when the virtual conductive part 31 is as follows: Figure 8When the virtual conductive portions 31 are distributed on both sides of the data lines Data as shown, the length of the virtual conductive portions 31 in the row direction X can be set to reduce parasitic capacitance. For example, the extension length of the virtual conductive portions 31 projected onto the substrate in the row direction X is L3, and the spacing between adjacent data lines Data projected onto the substrate in the row direction X is L4. L3 / L4 can be set to be greater than or equal to 1 / 8 and less than or equal to 1 / 2, for example, 1 / 8, 1 / 4, 3 / 8, 1 / 2, etc. Because the data signals of two adjacent virtual conductive portions 31 in the row direction X are different, by setting the ratio of the extension length of the virtual conductive portions 31 in the row direction X to the spacing between adjacent data lines Data within the above-mentioned ratio range, parasitic capacitance can be avoided due to the virtual conductive portions 31 in adjacent rows being too close, or at least the parasitic capacitance generated by both can be reduced. When the virtual conductive portions 31 are as shown... Figure 9 When the virtual conductive parts 31 are distributed on the same side of the data line Data, since the virtual conductive parts 31 do not form parasitic capacitance with the virtual conductive parts 31 of other columns, the extension length of the virtual conductive parts 31 in the row direction X can be increased, thereby reducing the width of the virtual conductive parts 31 in the column direction Y to a certain extent, and correspondingly reducing the width of the virtual gate line G2 in the column direction Y, which is beneficial to reducing the distance between adjacent virtual gate lines G2. This is equivalent to compressing the space occupied by the virtual gate line G2 and the virtual conductive parts 31 in the column direction Y, which is beneficial to improving the screen ratio of the display area.

[0062] like Figure 8 As shown in this exemplary embodiment, the virtual gate line G2 may include a first side k1 and a second side k2 disposed opposite to each other in the column direction Y. The virtual conductive part 31 includes a third side k3 and a fourth side k4 disposed opposite to each other in the column direction Y. The distance between the orthographic projection of the first side k1 on the substrate and the orthographic projection of the second side k2 on the substrate is L1, and the distance between the orthographic projection of the third side k3 on the substrate and the orthographic projection of the fourth side k4 on the substrate is L2. L1 / L2 is greater than or equal to 1 / 10 and less than or equal to 1, for example, it can be 1 / 10, 1 / 5, 3 / 10, 2 / 5, 1 / 2, 3 / 5, 7 / 10, 4 / 5, 9 / 10, 1, etc. When L1 / L2 is 1, it means that the width of the virtual conductive part 31 in the column direction Y is the same as the width of the virtual gate line G2 in the column direction Y at the corresponding position. Obviously, while ensuring that the overlapping capacitance matches the first equivalent capacitance of the display area AA, widening the width of the virtual conductive part 31 in the column direction Y helps to reduce the extension length of the virtual conductive part 31 in the row direction X. Figure 8When the virtual conductive portion 31 is distributed on both sides of the data line Data, the structure with a smaller extension length of the virtual conductive portion 31 in the row direction X is beneficial to reducing the parasitic capacitance generated between the virtual conductive portion 31 and adjacent virtual conductive portions 31. When L1 / L2 decreases, it is equivalent to the orthographic projection of the virtual conductive portion 31 on the substrate being located within the orthographic projection of the virtual gate line G2 on the substrate. At this time, it is beneficial to reduce the width of the virtual gate line G2 and the virtual conductive portion 31 in the column direction Y, thereby reducing the display space occupied by the virtual gate line G2 and the virtual conductive portion 31 in the column direction Y. The virtual conductive portion 31 can be as follows Figure 9 As shown, the data lines are distributed on the same side of the Data line, which improves the utilization of the display area AA without increasing parasitic capacitance.

[0063] like Figure 3 As shown in this exemplary embodiment, the spacing between adjacent gate lines G1 in the display area AA, projected onto the substrate in the column direction Y, is L5. The spacing between adjacent virtual gate lines G2 in the non-display area BB, projected onto the substrate in the column direction Y, is L6. L5 / L6 is less than or equal to 1 / 6. For example, L5 / L6 can be 1 / 15, 1 / 10, 2 / 15, 1 / 6, etc. By setting the ratio of the spacing between the virtual gate lines G2 in the non-display area BB and the spacing between the gate lines G1 in the display area AA within the above-mentioned ratio range, the space occupied by the non-display area BB in the column direction Y can be sufficiently compressed, which is beneficial to improving the utilization rate of the display area AA.

[0064] like Figure 2 As shown in this exemplary embodiment, the overlapping area of ​​the orthographic projection of the pixel electrode 51 onto the substrate and the orthographic projection of the common electrode 11 onto the substrate is S1, and the overlapping area of ​​the orthographic projection of the virtual conductive portion 31 onto the substrate and the orthographic projection of the virtual gate line G2 onto the substrate is S2. S1 / S2 is greater than or equal to 1 / 10 and less than or equal to 1 / 2, for example, it can be 1 / 10, 1 / 5, 3 / 10, 2 / 5, 1 / 2, etc. By setting the overlapping area of ​​the virtual conductive portion 31 and the virtual gate line G2 within the above ratio range, the second equivalent capacitance formed by the virtual gate line G2 and the virtual conductive portion 31 is matched with the first equivalent capacitance formed by the gate line G1 of the display area AA and the metal structure at the corresponding position.

[0065] It should be understood that, in other exemplary embodiments, the virtual gate line G2 may have, in addition to having Figure 8 Besides the structure shown, other structures are also possible. For example, it can be a regular graphic, such as... Figure 10 As shown, the orthographic projection of the virtual gate line G2 onto the substrate can be rectangular. Furthermore, it is understood that the virtual conductive portion 31 can also have other structures; for example, the orthographic projection of the virtual conductive portion 31 onto the substrate can be as follows: Figure 9The shape is rectangular, and it satisfies the requirement that the orthographic projection of the virtual conductive part 31 on the substrate is located within the orthographic projection of the virtual gate line G2 on the substrate.

[0066] Furthermore, this disclosure also provides a display device that includes the display panel described in any of the above embodiments of this disclosure. Therefore, the display device also includes the beneficial effects described in any of the above embodiments.

[0067] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the generality of this disclosure and include, but are not disclosed herein, common knowledge or customary techniques in the art. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

Claims

1. A display panel, wherein, The display panel includes a pixel driving circuit and a gate driving circuit. The pixel driving circuit is used to drive the light-emitting device to emit light. The pixel driving circuit includes a driving transistor, and the gate of the driving transistor is connected to a gate line. The gate driving circuit is used to provide a gate driving signal to the pixel driving circuit. The display panel also includes: A substrate, the substrate including a display area and a non-display area located on one side of the display area; The second conductive layer is located on one side of the substrate, and the second conductive layer includes: Multiple gate lines are located in the display area, and the orthographic projection of the multiple gate lines on the substrate extends along the row direction and is spaced apart in the column direction; Multiple virtual grid lines are located in the non-display area, and the projection of the multiple virtual grid lines on the substrate extends along the row direction and is spaced apart in the column direction; The display panel also includes: A virtual conductive portion is located in the non-display area. The virtual conductive portion and the virtual gate line are located in different conductive layers, and the orthographic projection of the virtual conductive portion on the substrate is located within the orthographic projection of the virtual gate line on the substrate. The virtual conductive portion is used to form an equivalent capacitance with the virtual gate line. Wherein, the RC load of the virtual gate line is matched with the RC load of the gate line; The gate drive circuit includes a plurality of first GOA units and a plurality of second GOA units. The first GOA units are configured to correspond to the gate lines. The first GOA units are used to provide a gate drive signal to the nth row of gate lines and a reset signal to the (ni)th row of gate lines. The second GOA unit is configured in correspondence with the virtual grid line. One second GOA unit is connected to one row of the virtual grid line and provides a reset signal to the (Ni)th row of grid lines, where n is a positive integer greater than or equal to 1 and less than or equal to N, i is a positive integer less than n, and N is the total number of rows of grid lines in the display area. The resistance value of the virtual gate line is matched with the resistance value of the gate line; The gate line and the corresponding conductive structure form a first equivalent capacitance, the virtual conductive part and the virtual gate line form a second equivalent capacitance, and the second equivalent capacitance matches the first equivalent capacitance; The virtual gate line includes a first side and a second side arranged opposite to each other in the column direction. The virtual conductive part includes a third side and a fourth side arranged opposite to each other in the column direction. The distance between the orthographic projection of the first side on the substrate and the orthographic projection of the second side on the substrate is L1. The distance between the orthographic projection of the third side on the substrate and the orthographic projection of the fourth side on the substrate is L2. L1 / L2 is greater than or equal to 1 / 10 and less than or equal to 1.

2. The display panel according to claim 1, wherein, The virtual grid line has a first component and a second component, wherein the width of the first component in the column direction is smaller than the width of the second component in the column direction; The virtual conductive portion includes a first sub-conductive portion and a second sub-conductive portion. The first sub-conductive portion is projected onto the substrate within the projection of the first component onto the substrate, and the second sub-conductive portion is projected onto the substrate within the projection of the second component onto the substrate.

3. The display panel according to claim 2, wherein, The first electrode of the driving transistor is connected to the data line, and the display panel further includes: A third conductive layer is located on the side of the second conductive layer opposite to the substrate, and the third conductive layer includes: Multiple data lines extend along the column direction and are spaced apart in the row direction in the orthographic projection of the substrate, and one of the data lines connects the first conductive part and the virtual conductive part in the same column; The virtual grid line further includes a third component, which is connected between the first component and the second component, and the width of the third component in the column direction is smaller than the width of the first component in the column direction. The orthographic projection of the third component on the substrate intersects with the orthographic projection of the data line on the substrate, and the orthographic projections of the first component on the substrate and the second component on the substrate are respectively located on both sides of the orthographic projection of the data line on the substrate.

4. The display panel according to claim 2, wherein, The first sub-conductive portion has a first extension length in the row direction when projected onto the substrate, and the second sub-conductive portion has a second extension length in the row direction when projected onto the substrate, wherein the first extension length is less than the second extension length.

5. The display panel according to claim 1, wherein, The first electrode of the driving transistor is connected to the data line, and the second electrode is connected to the pixel electrode. The display panel also includes: A third conductive layer is located on the side of the second conductive layer opposite to the substrate, and the third conductive layer includes: A plurality of first conductive portions are located in the display area, and the plurality of first conductive portions are arranged in an array in the row and column direction. The first conductive portions are used to form the first pole of the driving transistor. A plurality of second conductive portions are located in the display area. Each second conductive portion corresponds to a first conductive portion and is electrically insulated from the first conductive portion. The second conductive portions are used to form the second electrode of the driving transistor. Multiple data lines extend along the column direction and are spaced apart in the row direction in the orthographic projection of the substrate, and one of the data lines connects to the first conductive part of the same column; A fourth conductive layer is located on the side of the third conductive layer opposite to the substrate, and the fourth conductive layer includes: Multiple pixel electrodes are located in the display area, and the multiple pixel electrodes are distributed at intervals in the row and column direction. The orthographic projection of the pixel electrode on the substrate is located between the orthographic projections of the adjacent data lines on the substrate and between the orthographic projections of the adjacent gate lines on the substrate. The pixel electrode is connected to the second conductive part through a via.

6. The display panel according to claim 5, wherein, The virtual conductive part is located in the third conductive layer and connected to the data line. The virtual conductive parts in the same row are located on the same side of the data line to which they are connected. In any two adjacent rows of virtual conductive parts, the two virtual conductive parts connected to the same data line are located on both sides of the data line. The extension length of the virtual conductive part in the row direction of the orthographic projection on the substrate is L3, and the spacing distance between the orthographic projections of adjacent data lines on the substrate in the row direction is L4, where L3 / L4 is greater than or equal to 1 / 8 and less than or equal to 1 / 2.

7. The display panel according to claim 5, wherein, The virtual conductive part is located on the third conductive layer and connected to the data line. Virtual conductive parts in the same row are located on the same side of the data line to which they are connected, and virtual conductive parts in the same column are connected to the same side of the data line.

8. The display panel according to claim 5, wherein, The display panel also includes: A first conductive layer is located between the second conductive layer and the substrate, and the first conductive layer includes: Multiple common electrodes are arranged in an array in the row and column direction, and the orthographic projection of the common electrodes on the substrate overlaps with the orthographic projection of the pixel electrodes on the substrate. A semiconductor layer, located on the side of the second conductive layer opposite to the substrate, the semiconductor layer comprising: Multiple semiconductor structures, wherein the orthographic projection of the semiconductor structure on the substrate is located within the orthographic projection of the gate line on the substrate, the semiconductor structure is used to form the channel region of the driving transistor, and a portion of the structure of the gate line is used to form the gate of the driving transistor; The second conductive layer further includes: A common electrode line extends along the row direction, and the common electrode line connects each common electrode in the same row.

9. The display panel according to claim 8, wherein, The overlapping area of ​​the orthographic projection of the pixel electrode on the substrate and the orthographic projection of the common electrode on the substrate is S1, and the overlapping area of ​​the orthographic projection of the virtual conductive part on the substrate and the orthographic projection of the virtual gate line on the substrate is S2. S1 / S2 is greater than or equal to 1 / 10 and less than or equal to 1 / 2.

10. The display panel according to claim 8, wherein, The virtual conductive part is located in the first conductive layer, the third conductive layer, or the fourth conductive layer.

11. The display panel according to claim 8, wherein, The first equivalent capacitance includes a first sub-equivalent capacitance between the gate line and the pixel electrode, a second sub-equivalent capacitance between the gate line and the common electrode line, a third sub-equivalent capacitance between the gate line and the data line, a fourth sub-equivalent capacitance between the gate line and the first conductive portion, and a fifth sub-equivalent capacitance between the gate and the second conductive portion.

12. The display panel according to claim 1, wherein, The spacing between adjacent gate lines projected onto the substrate in the column direction is L5, and the spacing between adjacent virtual gate lines projected onto the substrate in the column direction is L6, where L5 / L6 is less than or equal to 1 / 6.

13. The display panel according to claim 1, wherein, The orthographic projection of the virtual grid line onto the substrate is the same as the orthographic projection of the grid line onto the substrate.

14. A display device, wherein, Includes the display panel as described in any one of claims 1-13.

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