Method of driving a scan circuit, scan circuit and display device

Abstract

A method of driving a scan circuit includes providing N first clock signals in a time sequence to (k*N) stages of the scan circuit, respectively. The (k*N) stages include M groups. Each of the M groups includes one or more stages of the scan circuit. Each of the N first clock signals includes a first level component and a second level component. A difference between a starting point of the first level component of an nth first clock signal and a starting point of an nth data enable signal of the N data enable signals with respect to the N data enable signals is equal to t m1 . Values of t m1 of the first clock signals provided to different ones of the M groups are different.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to a method for driving a scanning circuit, a scanning circuit, and a display device. Background Technology

[0002] Image display devices include drivers for controlling the display of an image in each of a plurality of pixels. The driver is a transistor-based circuit that includes gate drive circuitry and data drive circuitry. The gate drive circuitry consists of multiple shift register units cascaded together. Each shift register unit outputs a gate drive signal to one of a plurality of gate lines. The gate drive signal from the gate drive circuitry scans through the gate lines line by line to control the transistors in each row to be in an on / off state. The gate drive circuitry can be integrated into a gate-on-array (GOA) circuitry, which can be directly formed in the array substrate of the display panel. Summary of the Invention

[0003] In one aspect, this disclosure provides a method for driving a scanning circuit, comprising: providing N first clock signals sequentially to (k*N) stages of the scanning circuit, the (k*N) stages comprising M groups, each of the M groups comprising one or more stages of the scanning circuit, wherein N, k, and M are integers; N≥2, k≥1; M≥2; wherein each of the N first clock signals comprises a first level component and a second level component following the first level component; the m-th group of the M groups is configured to receive a first clock signal before the (m+1)-th group of the M groups receives a first clock signal, 1≤m≤(M-1); the difference between the starting point of the first level component of the n-th first clock signal and the starting point of the n-th data enable signal among the N data enable signals is equal to t. m1 ; providing the first clock signal t to different groups in the M groups m1 The values ​​are different; and the N data enable signals are signals provided to a timing controller, which is coupled to the scan circuit and configured to control the timing of data output.

[0004] Optionally, the t of the first clock signal provided to different groups in the M groups m1 The value gradually increases group by group.

[0005] Optionally, t is provided to the first clock signal of the m-th group among the M groups. m1 The value is less than t of the first clock signal provided to the (m+1)th group in the M groups. m1 The value of t; and the first clock signal t provided to the same group in the M groups. m1 The values ​​are the same.

[0006] Optionally, the difference between the starting point of the first level component of the nth first clock signal and the starting point of the nth first reference period out of the N first reference periods is equal to t. mA The durations of the N first reference periods are the same; the Nth first reference period of the N first reference periods overlaps with the Nth period of the N first clock signals; at least a first period of the N first clock signals does not overlap with a portion of the first first reference period of the N first reference periods; and t is provided to the first clock signals of different groups in the M groups. mA The values ​​are different.

[0007] Optionally, t is provided to the first clock signal of the m-th group among the M groups. m1 The value is greater than t of the first clock signal provided to the (m+1)th group in the M groups. mA The value of is 1≤m≤(M-1).

[0008] Optionally, t is provided to the first clock signal of the same group in the M groups. mA The values ​​are the same.

[0009] Optionally, the method further includes outputting (k*N) output control signals from the (k*N) stages of the scanning circuit, wherein the starting points of the (k*N) output control signals are equally spaced.

[0010] Optionally, the duty cycle of the first clock signal provided to the M groups is the same.

[0011] Optionally, the duty cycle of the first clock signal provided to the M groups is gradually increased group by group.

[0012] Optionally, the method further includes providing N second clock signals sequentially to (k*N) stages of the scanning circuit; wherein each of the N second clock signals includes a third level component and a fourth level component following the third level component; the m-th group of the M groups is configured to receive the second clock signal before the (m+1)-th group of the M groups receives the second clock signal; the difference between the starting point of the third level component of the n-th second clock signal and the starting point of the n-th data enable signal among the N data enable signals is equal to t. m2 ; and t, which provides a second clock signal to different groups in the M groups. m2 The values ​​are different.

[0013] Optionally, a second clock signal t is provided to different groups in the M groups. m2 The value gradually increases group by group.

[0014] Optionally, a second clock signal t is provided to the m-th group of the M groups. m2 The value is less than t of the second clock signal provided to the (m+1)th group in the M groups. m2 The value of t; and the second clock signal t provided to the same group in the M groups. m2 The values ​​are the same.

[0015] Optionally, the difference between the starting point of the third level component of the nth second clock signal and the starting point of the nth second reference period out of the N second reference periods is equal to t. mB The durations of the N second reference periods are the same; the Nth second reference period of the N second reference periods overlaps with the Nth period of the N second clock signals; at least a first period of the N second clock signals does not overlap with a portion of the first second reference period of the N second reference periods; and t is provided to the second clock signals of different groups in the M groups. mB The values ​​are different.

[0016] Optionally, a second clock signal t is provided to the m-th group of the M groups. mB The value is greater than t of the second clock signal provided to the (m+1)th group in the M groups. m2 The value of is 1≤m≤(M-1).

[0017] Optionally, a second clock signal t is provided to the same group in the M groups. mB The values ​​are the same.

[0018] Optionally, the method further includes providing an integrated circuit; wherein the (m+1)th group of the M groups is closer to the integrated circuit than the mth group of the M groups, 1≤m≤(M-1).

[0019] Optionally, the method further includes: providing a first clock signal line; and providing a modulation circuit configured to convert an original first clock signal transmitted by the first clock signal line into N first clock signals respectively provided to the (k*N) stages in time sequence; wherein the modulation circuit includes: a first transistor; a first resistor; a second resistor; a first capacitor; and a transistor; wherein a first electrode of the first transistor is coupled to the first clock signal line and a first terminal of the first resistor; a second electrode of the first transistor is coupled to the transistor; a second terminal of the first resistor is coupled to the first electrode of the first capacitor and a first terminal of the second resistor; the gate of the first transistor is coupled to the second terminal of the second resistor; and the output terminal of the transistor is coupled to the (k*N) stages; wherein the method further includes providing the N first clock signals to the (k*N) stages in time sequence through the modulation circuit; wherein the method further includes gradually increasing the resistance value of the first resistor, thereby gradually increasing the t of the first clock signals provided to the M groups group by group. m1 The value of .

[0020] In another aspect, this disclosure provides a scanning circuit, comprising: (k*N) stages; a first clock signal line; and a modulation circuit configured to convert an original first clock signal transmitted by the first clock signal line into N first clock signals provided sequentially to the (k*N) stages; wherein the (k*N) stages comprise M groups, each of the M groups comprising one or more stages of the scanning circuit, N, k, and M being integers; N≥2, k≥1; M≥2; each of the N first clock signals comprises a first level component and a second level component following the first level component; the m-th group of the M groups is configured to receive the first clock signal before the (m+1)-th group of the M groups receives the first clock signal, 1≤m≤(M-1); the difference between the starting point of the first level component of the n-th first clock signal and the starting point of the n-th data enable signal among the N data enable signals is equal to t. m1 ; providing the first clock signal t to different groups in the M groups m1 The values ​​are different; and the N data enable signals are signals provided to a timing controller, which is coupled to the scan circuit and configured to control the timing of data output.

[0021] Optionally, the modulation circuit includes: a first transistor; a first resistor; a second resistor; a first capacitor; and a transistor; wherein, the first electrode of the first transistor is coupled to the first clock signal line and the first terminal of the first resistor; the second electrode of the first transistor is coupled to the transistor; the second terminal of the first resistor is coupled to the first electrode of the first capacitor and the first terminal of the second resistor; the gate of the first transistor is coupled to the second terminal of the second resistor; and the output terminal of the transistor is coupled to the (k*N) stages.

[0022] Optionally, the scanning circuit further includes a second clock signal line; wherein the modulation circuit is further configured to convert the original second clock signal transmitted by the second clock signal line into N second clock signals provided sequentially to the (k*N) levels; each of the N second clock signals includes a third level component and a fourth level component following the third level component; the m-th group of the M groups is configured to receive the second clock signal before the (m+1)-th group of the M groups receives the second clock signal; the difference between the starting point of the third level component of the n-th second clock signal and the starting point of the n-th data enable signal among the N data enable signals is equal to t. m2 ; and t, which provides a second clock signal to different groups in the M groups. m2 The values ​​are different.

[0023] Optionally, the modulation circuit includes: a first transistor; a first resistor; a second resistor; a first capacitor; a second transistor; a third resistor; a fourth resistor; a second capacitor; and a transistor; wherein, the first electrode of the first transistor is coupled to the first clock signal line and the first terminal of the first resistor; the second electrode of the first transistor is coupled to the transistor; the second terminal of the first resistor is coupled to the first electrode of the first capacitor and the first terminal of the second resistor; the gate of the first transistor is coupled to the second terminal of the second resistor; the first electrode of the second transistor is coupled to the second clock signal line and the first terminal of the third resistor; the second electrode of the second transistor is coupled to the transistor; the second terminal of the third resistor is coupled to the first electrode of the second capacitor and the first terminal of the fourth resistor; the gate of the second transistor is coupled to the second terminal of the fourth resistor; and the output terminal of the transistor is coupled to the (k*N) stages.

[0024] In another aspect, this disclosure provides a display device including a scanning circuit described herein or manufactured by the methods described herein, and an integrated circuit connected to a first clock signal line. Attached Figure Description

[0025] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0026] Figure 1 This is a schematic diagram showing the delay of the resistors and capacitors in the clock signal line of the relevant scanning circuit.

[0027] Figure 2 This is a schematic diagram illustrating the delay of the control signal in the relevant scanning circuit.

[0028] Figure 3A This is a plan view of a display panel according to some embodiments of the present disclosure.

[0029] Figure 3B This is a schematic diagram of a display device according to some embodiments of the present disclosure.

[0030] Figure 4 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0031] Figure 5 This illustrates the reduction in data charging duration due to delays in the control signal within the relevant scanning circuit.

[0032] Figure 6 This shows the brightness variation caused by the delay of the control signal in the relevant scanning circuit.

[0033] Figure 7 This shows the change in ΔE5 due to the delay of the control signal in the relevant scanning circuit.

[0034] Figure 8 This is a schematic diagram illustrating the delay of the control signal in the relevant scanning circuit.

[0035] Figure 9 This is a schematic diagram illustrating a method for driving a scanning circuit according to some embodiments of the present disclosure.

[0036] Figure 10 This is a schematic diagram showing M groups of multiple stages of a scanning circuit according to some embodiments of the present disclosure.

[0037] Figure 11 The waveform of one of N first clock signals according to some embodiments of the present disclosure is shown.

[0038] Figure 12 The waveform of one of the N second clock signals according to some embodiments of the present disclosure is shown.

[0039] Figure 13The period of N first clock signals according to some embodiments of the present disclosure is shown.

[0040] Figure 14 The period of N second clock signals according to some embodiments of the present disclosure is shown.

[0041] Figure 15 The period of the first clock signal provided to the m-th group of M groups is shown in some embodiments of this disclosure.

[0042] Figure 16 The period of the second clock signal provided to the m-th group of M groups is shown in some embodiments of this disclosure.

[0043] Figure 17 The phase shifts between N first clock signals and N data enable signals are shown in some embodiments according to this disclosure.

[0044] Figure 18 The phase shift between N second clock signals and N data enable signals is shown in some embodiments according to this disclosure.

[0045] Figure 19 The phase shift of a first clock signal relative to a first reference clock signal or a data enable signal is shown in some embodiments of the present disclosure.

[0046] Figure 20 The phase shift of the second clock signal relative to a second reference clock signal or a data enable signal is shown in some embodiments of the present disclosure.

[0047] Figure 21 The present disclosure illustrates N first reference periods relative to N first clock signals in some embodiments.

[0048] Figure 22 The phase shift between N first clock signals and N first reference periods is shown in some embodiments of the present disclosure.

[0049] Figure 23 The present disclosure illustrates N second reference cycles relative to N second clock signals in some embodiments.

[0050] Figure 24 The phase shift between N second clock signals and N second reference periods is shown in some embodiments according to this disclosure.

[0051] Figure 25 This is a circuit diagram illustrating the structure of a modulation circuit according to some embodiments of the present disclosure.

[0052] Figure 26 This is a circuit diagram of a scanning unit according to some embodiments of the present disclosure.

[0053] Figure 27 It is shown Figure 26 The timing diagram of the operation of this scanning unit is shown in the figure.

[0054] Figure 28 This is a circuit diagram of a scanning unit according to some embodiments of the present disclosure. Detailed Implementation

[0055] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0056] Resistance-capacitance delay occurs in display panels due to the presence of resistance and parasitic capacitance in the signal lines. This delay is particularly significant when the signal transmission distance in the signal lines becomes longer. The inventors of this disclosure have discovered that control signals (e.g., gate scan signals) output from the scan circuit to control signals (e.g., gate scan signals) output from the scan circuit to control signals (e.g., gate scan signals) output from the scan circuit to control signals (e.g., gate scan signals) output from the scan circuit to the multi-row sub-pixels closer to the integrated circuit have a longer delay. The inventors of this disclosure have discovered that this is at least in part due to the resistance-capacitance delay in the signal lines that transmit signals (e.g., clock signals) from the integrated circuit to the multiple stages of the scan circuit.

[0057] Figure 1 This is a schematic diagram illustrating the resistor-capacitor delay in the clock signal line of the relevant scanning circuit. (Refer to...) Figure 1 , Figure 1 The left side shows the waveform of the clock signal transmitted by the clock signal line CSL. The clock signal line CSL is connected to the integrated circuit IC. The clock signal transmitted to multiple stages of the scan circuit closer to the integrated circuit IC has little or no resistance-capacitance delay. As the transmission distance increases, the clock signal transmitted to multiple stages of the scan circuit farther from the integrated circuit IC has a larger resistance-capacitance delay.

[0058] Figure 2 This is a schematic diagram illustrating the delay of the control signals in the relevant scanning circuit. (Reference) Figure 2The diagram illustrates the actual control signal ACS' and the reference control signal RCS. The actual control signal ACS' represents the delayed control signal actually generated, at least in part, due to the delay caused by the resistors and capacitors in the clock signal line CSL. The reference control signal RCS represents the assumed control signal without delay. For control signals output to multi-row sub-pixels closer to the integrated circuit IC, little or no delay is observed because the waveforms of the actual control signal ACS' and the reference control signal RCS almost overlap each other. For control signals output to multi-row sub-pixels farther from the integrated circuit IC, a more significant delay is observed because the waveforms of the actual control signal ACS' and the reference control signal RCS partially do not overlap each other.

[0059] In some embodiments, the scanning circuitry is configured to provide control signals to multiple rows of sub-pixels in the display panel. Examples of control signals include gate scan signals, reset control signals, and emission control signals. In one example, the control signals are output to the pixel driving circuitry of the LED display panel. Figure 3A This is a plan view of a display panel according to some embodiments of this disclosure. (Refer to...) Figure 3A The array substrate comprises an array of sub-pixels Sp. Each sub-pixel includes electronic components, such as a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes multiple gate lines GL, multiple data lines DL, and multiple high-voltage signal lines Vdd. The emission of light from each sub-pixel is driven by the corresponding pixel driving circuit PDC. In one example, a high-voltage signal is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element via a corresponding high-voltage signal line among the multiple high-voltage signal lines Vdd; a low-voltage signal is input to the cathode of the light-emitting element. The voltage difference between the high-voltage signal (e.g., the VDD signal) and the low-voltage signal (e.g., the VSS signal) is the driving voltage ΔV, which drives the light-emitting element to emit light.

[0060] Various suitable pixel driving circuits can be used in this array substrate. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each pixel driving circuit in the plurality of pixel driving circuits is a 7T1C driving circuit. Various suitable light-emitting elements can be used in this array substrate. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and microLEDs. Optionally, the light-emitting element is a microLED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0061] Figure 3B This is a schematic diagram of a display device according to some embodiments of the present disclosure. (Refer to...) Figure 3BThe display device includes a timing controller TC, a scan driver SD, a data driver DD, a light emission control driver LECD, and a display panel DP. The timing controller TC receives synchronization signals and video signals R, G, and B from the system interface. Synchronization signals may include, for example, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a master clock signal MCLK, and a data enable signal DE. The video signals R, G, and B include brightness information for each of a plurality of sub-pixels PX. The data enable signal DE is configured to control the timing of data output from the data lines.

[0062] The timing controller TC generates the first drive control signal CONT1, the second drive control signal CONT2, the third drive control signal CONT3, the first switch control signal SW1, the second switch control signal SW2, and the digital image signal DAT based on the video signals R, G, B, the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, the data enable signal DE, and the master clock signal MCLK. The timing controller TC also divides the video signals R, G, and B in frames based on the vertical synchronization signal Vsync, and in data lines based on the horizontal synchronization signal Hsync, to generate the digital image signal DAT. The timing controller TC transmits the digital image signal DAT and the second drive control signal CONT2 to the data driver DD.

[0063] The timing controller TC can be implemented in various suitable ways (e.g., using dedicated hardware) to perform the various functions discussed herein. A “processor” is an example of a timing controller that uses one or more microprocessors, which can be programmed using software (e.g., microcode) to perform the various functions discussed herein. The timing controller TC can be implemented with or without a processor, and can also be implemented as a combination of dedicated hardware performing some functions and processors (e.g., one or more programmed microprocessors and associated circuitry) performing other functions. Examples of controller components that can be used in various embodiments of this disclosure include (but are not limited to) conventional microprocessors, application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs).

[0064] like Figure 3B As shown, in some embodiments, the display panel DP includes a plurality of sub-pixels Sp, which are essentially arranged in a matrix. In this embodiment, the plurality of sub-pixels Sp may include light-emitting elements such as organic light-emitting diodes and associated pixel driving circuitry.

[0065] In the display panel DP, multiple essentially parallel scan lines S1, S2, ..., SK-1 and SK extend in the row direction, multiple essentially parallel light emission control lines EM1, EM2, ..., EMK-1 and EMK extend in the row direction, and multiple essentially parallel data lines D1, D2, D3, D4, ..., DM-1 and DM extend in the column direction. Scan lines S1 to SK, light emission control lines EM1 to EMK, and data lines D1 to DM are coupled to multiple sub-pixels Sp. When the light emission control signal on the light emission control line is active, a row of sub-pixels connected to the light emission control line can emit light.

[0066] The scan driver SD is coupled to scan lines S1 to SK and generates multiple scan signals according to the first drive control signal CONT1. The scan driver SD can sequentially apply the scan signals to scan lines S1 to SK. In some embodiments, the scan driver SD can be integrally formed with the display panel DP as a gate-on-array (GOA) driver.

[0067] The luminous emission control driver (LECD) is coupled to luminous emission control lines EM1 to EMK and generates multiple luminous emission control signals according to the third drive control signal CONT3. The LECD can sequentially apply the luminous emission control signals to the luminous emission control lines EM1 to EMK. In some embodiments, the LECD can be integrally formed with the display panel (DP) as a GOA (Glass Outer Aspect).

[0068] The data driver DD samples and holds the digital image signal DAT according to the second drive control signal CONT2, and generates multiple analog data signals based on the digital image signal DAT. In some exemplary embodiments, the data driver DD may include a shift register, a latch, a digital-to-analog converter, and a buffer. The shift register can output latch pulses to the latch. The latch can temporarily store and output the digital image signal DAT, and can output the digital image signal DAT to the digital-to-analog converter. The digital-to-analog converter can generate analog data signals based on the digital image signal DAT, and output the analog data signals to the buffer.

[0069] Figure 4 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 4In some embodiments, each pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a corresponding reset control signal line rstN in the current stage of a plurality of reset control signal lines, a source connected to a corresponding reset signal line Vint in the current stage of a plurality of first reset signal lines, and a drain connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding gate line in a plurality of gate lines GL, a source connected to a corresponding data line in a plurality of data lines DL, and a drain connected to the source of the driving transistor Td; and a third transistor T3 having a gate connected to a corresponding gate line, a first capacitor electrode Ce1 connected to the storage capacitor Cst, and a gate of the driving transistor Td. The transistor has a source electrode and a drain electrode connected to the drain electrode of the driving transistor Td; a fourth transistor T4, which has a gate electrode connected to a corresponding light-emitting control signal line in a plurality of light-emitting control signal lines em, a source electrode connected to a corresponding voltage supply line in a plurality of voltage supply lines Vdd, and a drain electrode connected to the source electrode of the driving transistor Td and the drain electrode of the second transistor T2; a fifth transistor T5, which has a gate electrode connected to a corresponding light-emitting control signal line, a source electrode connected to the drain electrode of the driving transistor Td and the third transistor T3, and a drain electrode connected to the anode electrode of the light-emitting element LE; and a sixth transistor T6, which has a gate electrode connected to a corresponding reset control signal line rst(N+1) in the next adjacent stage of a plurality of reset control signal lines, a source electrode connected to a corresponding reset signal line Vint in the current stage of a plurality of second reset signal lines, and a drain electrode connected to the drain electrode of the fifth transistor and the anode electrode of the light-emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the source electrode of the fourth transistor T4.

[0070] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the source of the third transistor T3. The second node N2 is connected to the drain of the fourth transistor T4, the drain of the second transistor T2, and the source of the driving transistor Td. The third node N3 is connected to the drain of the driving transistor Td, the drain of the third transistor T3, and the source of the fifth transistor T5. The fourth node N4 is connected to the drain of the fifth transistor T5, the drain of the sixth transistor T6, and the anode of the light-emitting element LE.

[0071] In one example, the scan circuit is a gate scan signal scan circuit configured to provide gate scan signals to multiple gate lines GL. In another example, the scan circuit is a light emission control signal scan circuit configured to provide light emission control signals to multiple light emission control signal lines em. In yet another example, the scan circuit is a reset control signal scan circuit configured to provide reset control signals to multiple reset control signal lines (e.g., rstN and rst(N+1)).

[0072] Figure 5 This illustrates the reduction in data charging duration due to control signal delays in the relevant scan circuitry. (Refer to...) Figure 5 As the transmission distance *d* increases, the clock signals transmitted to multiple stages of the scanning circuit farther from the integrated circuit have a large resistance-capacitance delay, and the control signals provided to multiple stages of the scanning circuit farther from the integrated circuit also have a large delay. The data charging duration of the pixel driving circuit corresponding to the sub-pixel farther from the integrated circuit decreases by, for example, a value δ, while the data charging duration of the pixel driving circuit corresponding to the sub-pixel closer to the integrated circuit is reduced to a minimum or not reduced at all.

[0073] Because the data charging duration of the pixel driving circuit corresponding to the sub-pixel farther from the integrated circuit is reduced, reference Figure 4 The voltage level charged to node N1 also decreases, resulting in a decrease in Vgs of the driving transistor Td and an increase in the driving current. The increased driving current leads to an increase in brightness in sub-pixels farther from the integrated circuit. Figure 6 This illustrates the brightness variation caused by the delay in the control signal within the relevant scanning circuitry. The display panel is configured to display an image, wherein data signals of the same level are provided to all sub-pixels of the display panel. The signal transmission distance in the clock signal line is represented by "d". (Example: ...) Figure 6 As shown, the display area farther from the integrated circuit (corresponding to a larger value of the signal transmission distance d) has a higher brightness, while the display area closer to the integrated circuit (corresponding to a smaller value of the signal transmission distance d) has a lower brightness.

[0074] Figure 7 This illustrates the ΔE5 variation caused by the delay of the control signal in the relevant scanning circuitry. The display panel is configured to display an image, where data signals of the same level are provided to all sub-pixels of the display panel. The signal transmission distance in the clock signal line is represented by "d". The ΔE5 value represents the difference between the displayed color of the input data signal and the original color standard. A lower ΔE5 value indicates higher accuracy, while a higher ΔE5 value indicates lower accuracy. Figure 7As shown, the display area farther from the integrated circuit (corresponding to a larger value of the signal transmission distance d) has a larger ΔE5 value compared to the display area closer to the integrated circuit (corresponding to a smaller value of the signal transmission distance d).

[0075] Figure 8 This is a schematic diagram illustrating the delay of the control signals in the relevant scanning circuit. (Refer to...) Figure 8 The diagram shows the waveforms of the start signal SSTV, data enable signal DE, first clock signal SCK, and second clock signal SCB. The period of the data enable signal DE is constant. Optionally, both the first clock signal SCK and the second clock signal SCB can have two horizontal cycles (2H) and have a gate on level during different horizontal cycles. Optionally, the second clock signal SCB can be set to be a signal offset from the first clock signal SCK by half a cycle (i.e., one horizontal period (1H)). In one example, the first clock signal SCK is transmitted to multiple stages of the scan circuit via a first clock signal line connected to the integrated circuit, the second clock signal SCB is transmitted to multiple stages of the scan circuit via a second clock signal line connected to the integrated circuit, and the start signal SSTV is transmitted to multiple stages of the scan circuit via a start signal line connected to the integrated circuit. The waveforms of the output signals from the multiple stages of the scan circuit are also shown. Figure 8 As shown in the diagram. For example, OUT_1 is the output signal from the first stage of the scan circuit furthest from the integrated circuit, OUT_2 is the output signal from the first stage of the scan circuit second furthest from the integrated circuit, OUT_N-1 is the output signal from the first stage of the scan circuit second closest to the integrated circuit, and OUT_N is the output signal from the first stage of the scan circuit closest to the integrated circuit.

[0076] exist Figure 8 The diagram illustrates the actual control signal ACS' and the reference control signal RCS. The actual control signal ACS' represents the delayed control signal actually generated, at least in part, due to the delay caused by the resistors and capacitors in the clock signal line CSL. The reference control signal RCS represents the assumed control signal without delay. For control signals output to multiple rows of sub-pixels close to the integrated circuit (e.g., output from multiple stages of a scan circuit close to the integrated circuit), little or no delay is observed because the waveforms of the actual control signal ACS' and the reference control signal RCS almost overlap each other. For control signals output to multiple rows of sub-pixels farther from the integrated circuit IC (e.g., output from multiple stages of a scan circuit farther from the integrated circuit IC), a more significant delay is observed because the waveforms of the actual control signal ACS' and the reference control signal RCS partially do not overlap each other.

[0077] Therefore, this disclosure particularly provides a method for driving a scanning circuit, a scanning circuit, and a display device, which substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides a method for driving a scanning circuit. In some embodiments, the method includes: providing N first clock signals sequentially to (k*N) stages of the scanning circuit, the (k*N) stages comprising M groups, each of the M groups comprising one or more stages of the scanning circuit, where N, k, and M are integers; N≥2, k≥1; M≥2. Optionally, each of the N first clock signals includes a first level component and a second level component following the first level component. Optionally, the m-th group of the M groups is configured to receive the first clock signal before the (m+1)-th group of the M groups is configured to receive the first clock signal, 1≤m≤(M-1). Optionally, the difference between the starting point of the first level component of the n-th first clock signal and the starting point of the n-th data enable signal among the N data enable signals is equal to t. m1 Optionally, t is provided to the first clock signal of different groups in the M groups. m1 The values ​​are different. Optionally, the N data enable signals are signals provided to a timing controller, which is coupled to the scan circuit and configured to control the timing of data output.

[0078] Figure 9 This is a schematic diagram illustrating a method for driving a scanning circuit according to some embodiments of the present disclosure. (Refer to...) Figure 9 The method includes providing N first clock signals SCK to (k*N) stages of the scanning circuit in chronological order. Optionally, N is an integer greater than or equal to 2. Optionally, k is an integer greater than or equal to 1 (e.g., 1, 2, 3, 4, 5, or 6). Figure 9 In one example shown, k = 2.

[0079] refer to Figure 9 In some embodiments, the method further includes providing N second clock signals SCB to (k*N) stages of the scanning circuit in chronological order. Optionally, N is an integer greater than or equal to 2, and optionally, k is an integer greater than or equal to 1 (e.g., 1, 2, 3, 4, 5, or 6). Figure 9 In one example shown, k = 2.

[0080] In some embodiments, the (k*N) stages comprise M groups. Each of the M groups comprises one or more stages of the scanning circuit. Optionally, M is an integer greater than or equal to 2. Figure 10 This is a schematic diagram illustrating M groups of multiple stages of a scanning circuit according to some embodiments of the present disclosure. (See reference...) Figure 10The multiple stages of the scanning circuit can be grouped into M groups, including G1, G2, G3, ..., G(M-1) and GM. Correspondingly, the multiple rows of sub-pixels RS in the display area can also be grouped into M groups of multiple rows of sub-pixels, such as... Figure 10 As shown. In one example, each of the M groups of multiple levels comprises a single level of the scan circuit. In another example, each group of multi-row subpixels comprises a single row of subpixels. In yet another example, each of the M groups of multiple levels comprises multiple levels of the scan circuit. In yet another example, each group of multi-row subpixels comprises multiple rows of subpixels. In one example, M = 16. In yet another example, M is a multiple of 16.

[0081] In some embodiments, the (m+1)th group of the M groups is closer to the integrated circuit than the mth group of the M groups, where 1 ≤ m ≤ (M-1). In one example, the first group of the M groups is the first group to receive clock signals in chronological order, and the Mth group is the last group to receive clock signals in chronological order; the mth group of the M groups receives clock signals before the (m+1)th group of the M groups receives clock signals. In another example, the Mth group of the M groups is the first group to receive clock signals in chronological order, and the first group of the M groups is the last group to receive clock signals in chronological order; the (m+1)th group of the M groups receives clock signals before the mth group of the M groups receives clock signals.

[0082] Reference Figure 9 The N actual first clock signals generated according to this method are represented as ACK, and N data enable signals DE are also shown. The N data enable signals DE can be understood as repetitive clock signals, each with the same duration. Figure 9 As shown, at least some of the N actual first clock signals ACK are generated, and the at least some actual first clock signals ACK have a phase shift relative to the corresponding data enable signal DE among the N data enable signals DE.

[0083] Reference Figure 9 The N actual second clock signals generated according to this method are represented as ACB, and N data enable signals DE are also shown. The N data enable signals DE can be understood as repetitive clock signals, each with the same duration. Figure 9 As shown, at least some of the N actual second clock signals ACB are generated, and these at least some actual second clock signals ACB have a phase shift relative to the corresponding data enable signal DE among the N data enable signals DE.

[0084] Reference Figure 9The N actual first clock signals generated according to this method are represented as ACK, and the N first reference clock signals are represented as RCK. The N first reference clock signals RCK can be understood as repetitive clock signals, each with the same period. Figure 9 As shown, at least some of N actual first clock signals ACK are generated, each having a phase shift relative to a corresponding first reference clock signal RCK among the N first reference clock signals RCK. Optionally, at least some of the N actual first clock signals ACK have the same period. In one example, the N actual first clock signals ACK have the same period. In some embodiments, at least the Nth (e.g., the last) actual first clock signal among the N actual first clock signals ACK completely overlaps with the Nth (e.g., the last) first reference clock signal among the N first reference clock signals RCK. In some embodiments, at least the first actual first clock signal among the N actual first clock signals ACK partially does not overlap with the first first reference clock signal among the N first reference clock signals RCK.

[0085] Reference Figure 9 The N actual second clock signals generated according to this method are denoted as ACB, and the N second reference clock signals are denoted as RCB. The N second reference clock signals RCB can be understood as repetitive clock signals, each with the same period. Figure 9 As shown, at least some of N actual second clock signals ACB are generated, each having a phase shift relative to a corresponding second reference clock signal RCB among N second reference clock signals RCB. Optionally, at least some of the N actual second clock signals ACB have the same period. In one example, the N actual second clock signals ACB have the same period. In some embodiments, at least the Nth (e.g., the last) actual second clock signal among the N actual second clock signals ACB completely overlaps with the Nth (e.g., the last) second reference clock signal among the N second reference clock signals RCB. In some embodiments, at least the first actual second clock signal among the N actual second clock signals ACB partially does not overlap with the first second reference clock signal among the N second reference clock signals RCB.

[0086] refer to Figure 9 The diagram illustrates the actual control signal ACS and the reference control signal RCS. The actual control signal ACS represents the control signal actually generated using a clock signal modulated by phase shift based on the method according to this disclosure. The reference control signal RCS represents the assumed control signal without delay, for example, without delay at least in part due to resistance and capacitance delay in the clock signal line. Figure 9 As shown, the actual control signal ACS and the reference control signal RCS substantially overlap each other. For example, the actual control signal ACS and the reference control signal RCS deviate from each other by less than 10%, such as less than 9%, less than 8%, less than 7%, less than 6%, less than 5%, less than 4%, less than 3%, less than 2%, less than 1%, less than 0.5%, less than 0.4%, less than 0.3%, less than 0.2%, and less than 0.1%. In one example, the actual control signal ACS and the reference control signal RCS completely overlap each other.

[0087] Compared to Figure 8 The driving method shown, Figure 9 The driving method shown avoids the problem of control signal delay. For example... Figure 9 As shown, for control signals output to multiple rows of sub-pixels far from the integrated circuit IC, minimal or no delay is observed because the waveforms of the actual control signal ACS and the reference control signal RCS almost overlap. For control signals output to multiple rows of sub-pixels closer to the integrated circuit IC, minimal or no delay is observed because the waveforms of the actual control signal ACS and the reference control signal RCS almost overlap. Throughout the entire display panel, minimal or no delay is observed in control signals output to any row or group of multiple rows of sub-pixels, regardless of the signal transmission distance in the clock signal line or the proximity to the integrated circuit.

[0088] In some embodiments, the method further includes outputting (k*N) output control signals from (k*N) stages of the scanning circuit, respectively. Optionally, the starting points of the (k*N) output control signals are equally spaced, for example, deviating from each other by less than 10%, such as less than 9%, less than 8%, less than 7%, less than 6%, less than 5%, less than 4%, less than 3%, less than 2%, less than 1%, less than 0.5%, less than 0.4%, less than 0.3%, less than 0.2%, and less than 0.1%.

[0089] As a result, a substantially uniform data charging duration (e.g., deviations of less than 10%, e.g., less than 9%, less than 8%, less than 7%, less than 6%, less than 5%, less than 4%, less than 3%, less than 2%, less than 1%, less than 0.5%, less than 0.4%, less than 0.3%, less than 0.2%, less than 0.1%) can be achieved across the entire display panel when the same level of data signal is provided to all sub-pixels. When data signals of the same level are provided to all sub-pixels in the display panel, a substantially uniform ΔE5 value can be achieved throughout the display panel (e.g., deviations from each other by less than 10%, e.g., less than 9%, less than 8%, less than 7%, less than 6%, less than 5%, less than 4%, less than 3%, less than 2%, less than 1%, less than 0.5%, less than 0.4%, less than 0.3%, less than 0.2%, less than 0.1%).

[0090] Figure 11 The waveform of one of N first clock signals according to some embodiments of the present disclosure is shown. (Refer to...) Figure 11 In some embodiments, each of the N first clock signals includes a first level component C1 and a second level component C2 following the first level component C1. In one example, the first level component C1 is a low voltage level component, and the second level component C2 is a high voltage level component. In another example, the first level component C1 is a high voltage level component, and the second level component C2 is a low voltage level component.

[0091] Figure 12 The waveform of one of N second clock signals according to some embodiments of the present disclosure is shown. (Reference) Figure 12 In some embodiments, each of the N second clock signals includes a third level component C3 and a fourth level component C4 following the third level component C3. In one example, the third level component C3 is a high voltage level component, and the fourth level component C4 is a low voltage level component. In another example, the third level component C3 is a low voltage level component, and the fourth level component C4 is a high voltage level component.

[0092] Figure 13 The period of N first clock signals according to some embodiments of this disclosure is shown. (See reference...) Figure 13The periods of the N first clock signals SCK (including D1, D2, D3, ..., D(N-1), DN) provided to the M groups are the same.

[0093] Figure 14 The period of N second clock signals according to some embodiments of this disclosure is shown. (Reference) Figure 14 The periods of the N second clock signals SCB (including D1', D2', D3', ..., D(N-1)', DN') provided to the M groups are the same.

[0094] Figure 15 This illustrates the period of a first clock signal provided to the m-th group of M groups according to some embodiments of this disclosure. (Refer to...) Figure 15 In addition to providing a first clock signal to the level directly adjacent to the (m+1)th group among the M groups, the first clock signal provided to the mth group among the M groups has the same period d1. The first clock signal provided to the level directly adjacent to the (m+1)th group among the M groups has a period d1'. Optionally, d1 and d1' are different from each other. In one example, d1' > d1. In another example, d1' < d1.

[0095] Figure 16 This illustrates the period of a second clock signal provided to the m-th group of M groups according to some embodiments of the present disclosure. (Refer to...) Figure 16 In addition to providing a second clock signal to the level directly adjacent to the (m+1)th group among the M groups, the second clock signal provided to the mth group among the M groups has the same period d2. The second clock signal provided to the level directly adjacent to the (m+1)th group among the M groups has a period d2'. Optionally, d2 and d2' are different from each other. In one example, d2' > d2. In another example, d2' < d2.

[0096] As used herein, the term "period" refers to the sum of the durations of the high-level component and the low-level component. In the context of the first clock signal, the term "period" refers to the sum of the durations of the first and second-level components. In the context of the second clock signal, the term "period" refers to the sum of the durations of the third and fourth-level components.

[0097] Figure 17 The diagram illustrates the phase shift between N first clock signals and N data enable signals according to some embodiments of this disclosure. (Refer to...) Figure 17 The difference between the starting point spt1 of the first level component of the nth first clock signal and the starting point spt2 of the nth data enable signal among the N data enable signals DE is equal to t.m1 In some embodiments, t is provided to the first clock signal of different groups in M ​​groups. m1 The values ​​are different. In some embodiments, the N data enable signals DE have the same period Pde.

[0098] In some embodiments, t is provided to the first clock signal of different groups in M ​​groups. m1 The value increases gradually group-by-group. Optionally, the first clock signal t is provided to the m-th group out of the M groups. m1 The value is less than t of the first clock signal provided to the (m+1)th group in the M groups. m1 The value of t is 1 ≤ m ≤ (M-1). Optionally, the first clock signal t is provided to the same group in the M groups. m1 The values ​​are the same.

[0099] In some embodiments, the starting point is the falling edge of the signal. For example, in the context of a first clock signal, the starting point spt1 is the falling edge of the first level component.

[0100] In some embodiments, the starting point is the rising edge of the signal. For example, in the context of data enable signals, the starting point spt2 of the nth data enable signal among N data enable signals DE is the rising edge of the nth data enable signal.

[0101] Figure 18 The diagram illustrates the phase shift between N second clock signals and N data enable signals according to some embodiments of this disclosure. (Refer to...) Figure 18 The difference between the starting point spt3 of the first level component of the nth second clock signal and the starting point spt2 of the nth data enable signal among the N data enable signals DE is equal to t. m2 In some embodiments, a second clock signal t is provided to different groups in M ​​groups. m2 The values ​​are different. In some embodiments, the N data enable signals DE have the same period Pde.

[0102] In some embodiments, t is provided to different groups in M ​​groups. m2 The value of is gradually increased group by group. Optionally, the second clock signal t is provided to the m-th group in the M groups. m2 The value is less than t of the second clock signal provided to the (m+1)th group in the M groups. m2 The value of t is 1 ≤ m ≤ (M-1). Optionally, a second clock signal t is provided to the same group in the M groups. m2 The values ​​are the same.

[0103] In some embodiments, the starting point is the rising edge of the signal. For example, in the context of a second clock signal, the starting point spt3 is the rising edge of the third level component.

[0104] In some embodiments, the starting point is the rising edge of the signal. For example, in the context of data enable signals, the starting point spt2 of the nth data enable signal among N data enable signals DE is the rising edge of the nth data enable signal.

[0105] refer to Figure 9 In some embodiments, the start signal is shifted to be in phase with at least one of a first clock signal or a second clock signal.

[0106] Phase shifting of a clock signal can be achieved by changing the duty cycle of the clock signal or by maintaining the duty cycle of the clock signal. In some embodiments, the duty cycle of the first clock signals provided to the M groups is the same. In some embodiments, the duty cycle of the first clock signals provided to the M groups gradually decreases or increases group by group. In some embodiments, the duty cycle of the second clock signals provided to the M groups is the same. In some embodiments, the duty cycle of the second clock signals provided to the M groups gradually decreases or increases group by group.

[0107] Figure 19 The diagram illustrates the phase shift of a first clock signal relative to a first reference clock signal or a data enable signal according to some embodiments of the present disclosure. Reference Figure 19 The phase shift of the first clock signal can be achieved by maintaining the duty cycle of the first clock signal (represented by SCK1) relative to the first reference clock signal (represented by RCK); or by changing the duty cycle of the first clock signal (represented by SCK2) relative to the first reference clock signal (represented by RCK). In some embodiments, N data enable signals DE have the same period Pde; N first reference clock signals RCK have the same period RP1; N first clock signals SCK1 or N first clock signals SCK2 have the same period Pck. Optionally, RP1 and Pck are the same. Optionally, Pde, RP1, and Pck are the same.

[0108] In some embodiments, the duty cycle of the first clock signal provided to the M groups is the same (see, for example, SCK1). Optionally, the duty cycle of the first clock signal provided to the M groups is the same as the duty cycle of the first reference clock signal RCK.

[0109] In some embodiments, the duty cycle of the first clock signal provided to the M groups gradually decreases group by group (see, for example, SCK2).

[0110] In some embodiments, the duty cycle of the first clock signal provided to the M groups is gradually increased group by group. Figure 19 In the example shown, the duty cycle of the first clock signal provided to the m-th group of the M groups is less than the duty cycle of the first clock signal provided to the (m+1)-th group of the M groups, 1≤m≤(M-1). The duty cycle of the first clock signal provided to the first group of the M groups is the smallest, and the duty cycle of the first clock signal provided to the last group of the M groups is the largest. In one example, the duty cycle of the first clock signal provided to the last group of the M groups is the same as the duty cycle of the first reference clock signal RCK.

[0111] Figure 20 The diagram illustrates the phase shift of a second clock signal relative to a second reference clock signal or a data enable signal according to some embodiments of the present disclosure. Reference Figure 20 The phase shift of the second clock signal can be achieved by maintaining the duty cycle of the second clock signal (represented by SCB1) relative to the second reference clock signal (represented by RCB); or by changing the duty cycle of the second clock signal (represented by SCB2) relative to the second reference clock signal (represented by RCB). In some embodiments, N data enable signals DE have the same period Pde; N second reference clock signals RCB have the same period RP2; N second clock signals SCB1 or N second clock signals SCB2 have the same period Pcb. Optionally, RP2 and Pcb are the same. Optionally, Pde, RP2, and Pcb are the same.

[0112] In some embodiments, the duty cycle of the second clock signals provided to the M groups is the same (see, for example, SCB1). Optionally, the duty cycle of the second clock signals provided to the M groups is the same as the duty cycle of the second reference clock signal RCB.

[0113] In some embodiments, the duty cycle of the second clock signal provided to the M groups is gradually decreased group by group (see, for example, SCB2).

[0114] In some embodiments, the duty cycle of the second clock signals provided to the M groups is gradually increased group by group. Figure 20 In the example shown, the duty cycle of the second clock signal provided to the m-th group of the M groups is less than the duty cycle of the second clock signal provided to the (m+1)-th group of the M groups, where 1 ≤ m ≤ (M-1). The duty cycle of the second clock signal provided to the first group of the M groups is the smallest, and the duty cycle of the second clock signal provided to the last group of the M groups is the largest. In one example, the duty cycle of the second clock signal provided to the last group of the M groups is the same as the duty cycle of the second reference clock signal RCB.

[0115] Figure 21A schematic diagram is shown showing N first reference periods relative to N first clock signals according to some embodiments of the present disclosure. See also Figure 21 N first reference periods RP1 represent the generated first reference clock signal without phase shift described in this disclosure (e.g., Figure 9 The RCK in the equation assumes a repeating period. The duration of the N first reference periods RP1 is the same. Figure 22 The diagram illustrates the phase shift between N first clock signals and N first reference periods according to some embodiments of the present disclosure. (Refer to...) Figure 21 and Figure 22 The Nth first reference period in the N first reference periods RP1 completely overlaps with the Nth period of the N first clock signals SCK. At least the first period of the N first clock signals SCK does not partially overlap with the first first reference period in the N first reference periods RP1, such as... Figure 21 and Figure 22 As shown.

[0116] In some embodiments, the difference between the starting point spt1 of the first level component of the nth first clock signal and the starting point sptA of the nth first reference period among the N first reference periods RP1 is equal to t. mA In some embodiments, t is provided to the first clock signal of different groups in M ​​groups. mA The values ​​are different.

[0117] In some embodiments, t is provided to the first clock signal of different groups in M ​​groups. mA The value of gradually decreases group by group. Optionally, t is provided to the first clock signal of the m-th group in the M groups. mA The value is greater than t of the first clock signal provided to the (m+1)th group in the M groups. mA The value of t is 1 ≤ m ≤ (M-1). Optionally, the first clock signal t is provided to the same group in the M groups. mA The values ​​are the same.

[0118] In some embodiments, the starting point is the falling edge of the signal. For example, in the context of a first clock signal, the starting point spt1 is the falling edge of the first level component.

[0119] Figure 23 This illustrates N second reference periods relative to N second clock signals according to some embodiments of the present disclosure. See also... Figure 23 N second reference periods RP2 represent the generated, phase-shift-free second reference clock signal described in this disclosure (e.g., Figure 9 The RCB in the equation assumes a repeating period. The duration of the N second reference periods RP2 is the same. Figure 24 The diagram illustrates the phase shift between N second clock signals and N second reference periods according to some embodiments of the present disclosure. (Refer to...) Figure 23 and Figure 24 The Nth second reference period in the N second reference periods RP2 completely overlaps with the Nth period of the N second clock signals SCB. At least the first period of the N second clock signals SCB does not overlap with a portion of the first second reference period in the N second reference periods RP2, such as... Figure 23 and Figure 24 As shown.

[0120] In some embodiments, the difference between the starting point spt3 of the first level component of the nth second clock signal and the starting point sptB of the nth second reference period in the N second reference periods RP2 is equal to t. mB In some embodiments, a second clock signal t is provided to different groups in M ​​groups. mB The values ​​are different.

[0121] In some embodiments, t is provided to different groups in M ​​groups. mB The value of gradually decreases group by group. Optionally, t is provided to the second clock signal of the m-th group in the M groups. mB The value is greater than t of the second clock signal provided to the (m+1)th group in the M groups. mB The value of t is 1 ≤ m ≤ (M-1). Optionally, a second clock signal t is provided to the same group in the M groups. mB The values ​​are the same.

[0122] In some embodiments, the starting point is the rising edge of the signal. For example, in the context of a second clock signal, the starting point spt3 is the rising edge of the third level component.

[0123] refer to Figure 9 In some embodiments, the start signal is shifted to be in phase with at least one of a first clock signal or a second clock signal.

[0124] Phase shifting of a clock signal can be achieved by changing the duty cycle of the clock signal or by maintaining the duty cycle of the clock signal. In some embodiments, the duty cycle of the first clock signals provided to the M groups is the same. In some embodiments, the duty cycle of the first clock signals provided to the M groups gradually decreases or increases group by group. In some embodiments, the duty cycle of the second clock signals provided to the M groups is the same. In some embodiments, the duty cycle of the second clock signals provided to the M groups gradually decreases or increases group by group.

[0125] In some embodiments, the method further includes providing a first clock signal line; and providing modulation circuitry that couples the first clock signal line to (k*N) stages. Figure 25 This is a circuit diagram illustrating the structure of a modulation circuit according to some embodiments of the present disclosure. (Refer to...) Figure 25 The first clock signal line CK is coupled to the modulation circuit MC, which is configured to convert the original first clock signal OCK transmitted by the first clock signal line CK into N first clock signals provided in time sequence to (k*N) levels.

[0126] In some embodiments, the method further includes providing a second clock signal line CB. The second clock signal line CB is coupled to a modulation circuit MC, which is configured to convert the original second clock signal OCB transmitted by the second clock signal line CB into N second clock signals provided sequentially to (k*N) levels.

[0127] In some embodiments, the modulation circuit MC includes a first transistor T1; a first resistor R1; a second resistor R2; a first capacitor C1; and a transistor T. The first electrode of the first transistor T1 is coupled to a first clock signal line CK and the first terminal of the first resistor R1. The second electrode of the first transistor T1 is coupled to the transistor T. The second terminal of the first resistor R1 is coupled to the first electrode of the first capacitor C1 and the first terminal of the second resistor R2. The gate of the first transistor T1 is coupled to the second terminal of the second resistor R2. The output terminal of the transistor T is coupled to (k*N) stages.

[0128] In some embodiments, the method further includes providing N first clock signals to (k*N) stages in a time-sequential manner via a modulation circuit MC. In some embodiments, the method further includes gradually increasing the resistance value of the first resistor R1, thereby gradually increasing the t of the first clock signals provided to the M groups group by group. m1 The value of t, where t m1 This is the difference between the starting point spt1 of the first level component of the nth first clock signal and the starting point spt2 of the nth data enable signal among the N data enable signals DE. The larger the resistance value of the first resistor R1, the longer the time it takes for the transistor to conduct, and the longer the t of the first clock signal... m1 The larger the value of R1, the faster the transistor conducts, and the longer the t-value of the first clock signal. m1 The smaller the value, the better. As a result, the t value provided to the first clock signal of the M groups... m1 The value gradually increases group by group.

[0129] In some embodiments, the modulation circuit MC includes a second transistor T2; a third resistor R3; a fourth resistor R4; a second capacitor C2; and a transistor T. The first electrode of the second transistor T2 is coupled to the second clock signal line CB and the first terminal of the third resistor R3. The second electrode of the second transistor T2 is coupled to the transistor T. The second terminal of the third resistor R3 is coupled to the first electrode of the second capacitor C2 and the first terminal of the fourth resistor R4. The gate of the second transistor T2 is coupled to the second terminal of the fourth resistor R4. The output terminal of the transistor T is coupled to (k*N) stages.

[0130] In some embodiments, the method further includes providing N second clock signals sequentially to (k*N) stages via a modulation circuit MC. In some embodiments, the method further includes gradually increasing the resistance value of a third resistor R3, thereby gradually increasing the t of the second clock signals provided to the M groups group by group. m2 The value of t, where t m2 This is the difference between the starting point spt3 of the first level component of the nth second clock signal and the starting point spt2 of the nth data enable signal among the N data enable signals DE. The larger the resistance value of the third resistor R3, the longer the transistor takes to conduct, and the longer the t of the second clock signal... m2 The larger the value of the second clock signal, the faster the transistor conducts, and the faster the second clock signal t is turned on. The smaller the resistance value of the third resistor R3, the faster the transistor conducts. m2 The smaller the value, the better. As a result, the t value provided to the M groups... m2 The value gradually increases group by group.

[0131] In another aspect, this disclosure provides a scanning circuit. In some embodiments, the scanning circuit includes (k*N) stages; a first clock signal line; and a modulation circuit configured to convert an original first clock signal transmitted by the first clock signal line into N first clock signals provided sequentially to the (k*N) stages. Optionally, the (k*N) stages include M groups, each of the M groups comprising one or more stages of the scanning circuit, where N, k, and M are integers; N≥2, k≥1; M≥2. Optionally, each of the N first clock signals includes a first level component and a second level component following the first level component. Optionally, the m-th group of the M groups is configured to receive the first clock signal before the (m+1)-th group of the M groups is configured to receive the first clock signal, 1≤m≤(M-1). Optionally, the difference between the starting point of the first level component of the n-th first clock signal and the starting point of the n-th data enable signal among the N data enable signals is equal to t. m1 Optionally, t is provided to the first clock signal of different groups in the M groups. m1The values ​​are different. Optionally, the N data enable signals are signals provided to a timing controller, which is coupled to the scan circuit and configured to control the timing of data output.

[0132] Reference Figure 25 In some embodiments, the modulation circuit MC includes a first transistor T1; a first resistor R1; a second resistor R2; a first capacitor C1; and a transistor T. The first electrode of the first transistor T1 is coupled to a first clock signal line CK and the first terminal of the first resistor R1. The second electrode of the first transistor T1 is coupled to the transistor T. The second terminal of the first resistor R1 is coupled to the first electrode of the first capacitor C1 and the first terminal of the second resistor R2. The gate of the first transistor T1 is coupled to the second terminal of the second resistor R2. The output terminal of the transistor T is coupled to (k*N) stages.

[0133] In some embodiments, the scanning circuit further includes a second clock signal line. Optionally, the modulation circuit MC is further configured to convert the original second clock signal transmitted by the second clock signal line into N second clock signals provided sequentially to the (k*N) levels. Optionally, each of the N second clock signals includes a third level component and a fourth level component following the third level component. Optionally, the m-th group of the M groups is configured to receive the second clock signal before the (m+1)-th group of the M groups is configured to receive the second clock signal. Optionally, the difference between the starting point of the third level component of the n-th second clock signal and the starting point of the n-th data enable signal among the N data enable signals is equal to t. m2 Optionally, a second clock signal t is provided to different groups among the M groups. m2 The values ​​are different.

[0134] In some embodiments, the modulation circuit MC includes a second transistor T2; a third resistor R3; a fourth resistor R4; a second capacitor C2; and a transistor T. The first electrode of the second transistor T2 is coupled to the second clock signal line CB and the first terminal of the third resistor R3. The second electrode of the second transistor T2 is coupled to the transistor T. The second terminal of the third resistor R3 is coupled to the first electrode of the second capacitor C2 and the first terminal of the fourth resistor R4. The gate of the second transistor T2 is coupled to the second terminal of the fourth resistor R4. The output terminal of the transistor T is coupled to (k*N) stages.

[0135] Various suitable structures for multiple stages of the scanning circuit can be implemented in this scanning circuit. Figure 26 This is a circuit diagram of a scanning unit according to some embodiments of this disclosure. (See reference...) Figure 26In some embodiments, each scanning unit includes an input sub-circuit ISC, an output sub-circuit OSC, a first processing sub-circuit PSC1, a second processing sub-circuit PSC2, a third processing sub-circuit PSC3, a first stabilizing sub-circuit SSC1, and a second stabilizing sub-circuit SSC2.

[0136] In some embodiments, the output sub-circuit OSC is configured to provide a first power supply VGH or a second power supply VGL to the output terminal TM4 in response to the voltages of the fourth node N4 and the first node N1. Optionally, the output sub-circuit OSC includes a ninth transistor T9 and a tenth transistor T10.

[0137] The ninth transistor T9 is coupled between the first power supply VGH and the output terminal TM4. The gate of the ninth transistor T9 is coupled to the fourth node N4. The ninth transistor T9 can be turned on or off according to the voltage of the fourth node N4. Optionally, when the ninth transistor T9 is turned on, the voltage of the first power supply VGH is provided to the output terminal TM4, and the voltage of the first power supply VGH (in...) Figure 26 The signal marked OUTc can be transmitted to the nth gate line and used as a gate drive signal with a gate on level.

[0138] The tenth transistor T10 is coupled between the output terminal TM4 and the second power supply VGL. The gate of the tenth transistor T10 is coupled to the first node N1. The tenth transistor T10 can be turned on or off according to the voltage of the first node N1. Optionally, when the tenth transistor T10 is turned on, the voltage of the second power supply VGL is provided to the output terminal TM4, and the voltage of the second power supply VGL (in the...) Figure 26 The signal marked OUTc can be provided to the nth gate line and used as a gate drive signal with a gate cutoff level. In one example, when the gate drive signal has a gate cutoff level, it can be understood that no gate drive signal is provided.

[0139] In some embodiments, the input sub-circuit ISC is configured to control the voltages of the first node N1 and the fifth node N5 in response to signals provided to the first input terminal TM1 and the second input terminal TM2, respectively. Optionally, the input sub-circuit ISC includes a first transistor T1.

[0140] The first transistor T1 is coupled between the first input terminal TM1 and the fifth node N5. The gate of the first transistor T1 is coupled to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the first transistor T1 is turned on to electrically couple the first input terminal TM1 to the fifth node N5.

[0141] In some embodiments, the first processing sub-circuit PSC1 is configured to control the voltage of the fourth node N4 in response to the voltages of the first node N1 and the fifth node N5. Optionally, the first processing sub-circuit PSC1 includes an eighth transistor T8 and a second capacitor C2.

[0142] The eighth transistor T8 is coupled between the first power supply VGH and the fourth node N4. The gate of the eighth transistor T8 is coupled to the fifth node N5. The eighth transistor T8 can be turned on or off depending on the voltage of the fifth node N5. Optionally, when the eighth transistor T8 is turned on, the voltage of the first power supply VGH can be supplied to the fourth node N4.

[0143] The second capacitor C2 is coupled between the first power supply VGH and the fourth node N4. Optionally, the second capacitor C2 is configured to charge the voltage to be applied to the fourth node N4. Optionally, the second capacitor C2 is configured to stably maintain the voltage of the fourth node N4.

[0144] In some embodiments, the second processing sub-circuit PSC2 is coupled to the sixth node N6 and configured to control the voltage of the fourth node N4 in response to a signal input to the third input terminal TM3. Optionally, the second processing sub-circuit PSC2 includes a sixth transistor T6, a seventh transistor T7, and a first capacitor C1.

[0145] The first terminal of the first capacitor C1 is coupled to the sixth node N6, and the second terminal of the first capacitor C1 is coupled to the third node N3, which is the common node between the sixth transistor T6 and the seventh transistor T7.

[0146] The sixth transistor T6 is coupled between the third node N3 and the sixth node N6. The gate of the sixth transistor T6 is coupled to the sixth node N6. The sixth transistor T6 can be turned on according to the voltage of the sixth node N6, so that the voltage corresponding to the second clock signal CB provided to the third input terminal TM3 can be applied to the third node N3.

[0147] The seventh transistor T7 is coupled between the fourth node N4 and the third node N3. The gate of the seventh transistor T7 is coupled to the third input terminal TM3. The seventh transistor T7 can be turned on in response to the second clock signal CB provided to the third input terminal TM3, thus applying the voltage of the first power supply VGH to the third node N3.

[0148] In some embodiments, the third processing sub-circuit PSC3 is configured to control the voltage of the second node N2. Optionally, the third processing sub-circuit PSC3 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a third capacitor C3.

[0149] The first electrode of the third capacitor C3 is coupled to the first node N1, and the second electrode of the third capacitor C3 is coupled to the seventh node N7. The seventh node N7 is the common node between the fourth transistor T4 and the fifth transistor T5.

[0150] The fifth transistor T5 is coupled between the first power supply VGH and the seventh node N7. The gate of the fifth transistor T5 is coupled to the second node N2. The fifth transistor T5 can be turned on or off according to the voltage of the second node N2.

[0151] The fourth transistor T4 is coupled between the seventh node N7 and the third input terminal TM3. The gate of the fourth transistor T4 is coupled to the first node N1. The fourth transistor T4 can be turned on or off according to the voltage of the first node N1.

[0152] The second transistor T2 is coupled between the second node N2 and the second input terminal TM2. The gate of the second transistor T2 is coupled to the fifth node N5.

[0153] The third transistor T3 is coupled between the second node N2 and the second power supply VGL. The gate of the third transistor T3 is coupled to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the third transistor T3 can be turned on, so that the voltage of the second power supply VGL can be provided to the second node N2.

[0154] In some embodiments, a first stabilizing subcircuit SSC1 is coupled between a second processing subcircuit PSC2 and a third processing subcircuit PSC3. Optionally, the first stabilizing subcircuit SSC1 is configured to limit the voltage drop width of the second node N2. Optionally, the first stabilizing subcircuit SSC1 includes an eleventh transistor T11.

[0155] The eleventh transistor T11 is coupled between the second node N2 and the sixth node N6. The gate of the eleventh transistor T11 is coupled to the second power supply VGL. Since the second power supply VGL has a gate on-level voltage, the eleventh transistor T11 can always remain on. Therefore, the second node N2 and the sixth node N6 can be maintained at the same voltage and operate as essentially the same node.

[0156] In some embodiments, the second stabilizing sub-circuit SSC2 is connected between the first node N1 and the fifth node N5. Optionally, the second stabilizing sub-circuit SSC2 is configured to limit the voltage drop width of the first node N1. Optionally, the second stabilizing sub-circuit SSC2 includes a twelfth transistor T12.

[0157] The twelfth transistor T12 is coupled between the first node N1 and the fifth node N5. The gate of the twelfth transistor T12 is coupled to the second power supply VGL. Since the second power supply VGL has a gate on-level voltage, the twelfth transistor T12 can always remain on. Therefore, the first node N1 and the fifth node N5 can be maintained at the same voltage and operate as essentially the same node.

[0158] In some embodiments, each of the first transistor T1 to the twelfth transistor T12 may be formed of a p-type transistor. In some embodiments, the gate on-state voltage of the first transistor T1 to the twelfth transistor T12 may be set to a low level, while its gate off-state voltage may be set to a high level.

[0159] Figure 27 It is shown Figure 26 The timing diagram shows the operation of the first-level scan unit. (Refer to...) Figure 27 The first clock signal CK and the second clock signal CB each have two horizontal cycles (2H) and have a gate on level during different horizontal cycles. Optionally, the second clock signal CB can be set to a signal offset from the first clock signal CK by half a cycle (i.e., one horizontal cycle (1H)).

[0160] In some embodiments, when clock signals CK and CB are provided, the second input terminal TM2 and the third input terminal TM3 can be set to a low level, i.e., the voltage of the second power supply VGL. When clock signals CK and CB are not provided, the second input terminal TM2 and the third input terminal TM3 can be set to a high level, i.e., the voltage of the first power supply VGH.

[0161] In some embodiments, when a start signal STV or an output signal Outp from the output terminal of a previous scan unit (e.g., a previous scan unit in the same stage or a previous scan unit in the previous stage) is provided, the first input terminal TM1 can be set to a high level, i.e., the voltage of the first power supply VGH. When the start signal STV or the output signal Outp from the output terminal of a previous scan unit is not provided, the first input terminal TM1 can be set to a low level, i.e., the voltage of the second power supply VGL.

[0162] In some embodiments, the start signal STV provided to the first input terminal TM1 or the output signal Outp from the output terminal of the previous scan unit may be configured to overlap with the first clock signal CK provided to the second input terminal TM2 at least once. Optionally, the width of the start signal STV or the output signal Outp from the output terminal of the previous scan unit may be greater than the width of the first clock signal CK, and may be provided, for example, during four horizontal cycles (4H). In this case, the output signal provided to the first input terminal TM1 of the next stage may also overlap with the second clock signal CB provided to the second input terminal TM2 of the next stage at least once.

[0163] In some embodiments, during the first cycle t1, the first clock signal CK is provided to the second input terminal TM2. The first transistor T1 and the third transistor T3 are turned on. Furthermore, during the first cycle t1, the second clock signal CB is not provided to the third input terminal TM3, and the seventh transistor T7 is turned off.

[0164] In some embodiments, when the first transistor T1 is turned on, the first input terminal TM1 is electrically coupled to the fifth node N5. The twelfth transistor T12 remains turned on, and the first input terminal TM1 is electrically coupled to the first node N1 through the fifth node N5.

[0165] In some embodiments, during the first cycle t1, the start signal STV provided to the first input terminal TM1 or the output signal Outp from the output terminal of the previous scan unit is at a low level, and a low voltage (e.g., the voltage of the second power supply VGL) can be applied to the fifth node N5 and the first node N1. When the fifth node N5 and the first node N1 are set to a low voltage, the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned on.

[0166] In some embodiments, when the fourth transistor T4 is turned on, the third input terminal TM3 is electrically coupled to the seventh node N7. During the first cycle t1, the second clock signal CB is not provided to the third input terminal TM3, and a high voltage can be provided to the seventh node N7. The third capacitor C3 is configured to charge to the voltage corresponding to the on-state of the fourth transistor T4.

[0167] In some embodiments, when the fourth transistor T4 is turned on, the fifth transistor T5 is connected as a diode between the second node N2 and the first power supply VGH. When the fifth transistor T5 is turned on during the first cycle t1, the voltage of the first power supply VGH is not transmitted to the second node N2, and the voltage of the second node N2 remains at the voltage of the previous state, such as a high voltage. The eleventh transistor T11 remains on, and the high voltage of the second node N2 is applied to the sixth node N6, setting the sixth node N6 to a high voltage. The second transistor T2 and the sixth transistor T6 are turned off.

[0168] In some embodiments, when the eighth transistor T8 is turned on, the voltage of the first power supply VGH is provided to the fourth node N4. The ninth transistor T9 is turned off.

[0169] In some embodiments, when the tenth transistor T10 is turned on, the voltage of the second power supply VGL is provided to the output terminal TM4. During the first cycle t1, the gate drive signal is not provided to the nth gate line.

[0170] In some embodiments, during the second cycle t2, the supply of the first clock signal CK to the second input terminal TM2 is interrupted. The first transistor T1 and the fifth transistor T5 are turned off. The fourth node N4 and the first node N1 maintain the voltage of the previous cycle through the second capacitor C2 and the third capacitor C3. Since the fourth node N4 remains at a high voltage, the ninth transistor T9 remains off. Since the first node N1 remains at a low voltage, the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 remain on.

[0171] In some embodiments, during the second period t2, a second clock signal CB is provided to the third input terminal TM3. The seventh transistor T7 is turned on by the second clock signal CB provided to the third input terminal TM3. When the seventh transistor T7 is turned on, the fourth node N4 and the third node N3 are electrically coupled to each other. The third node N3 is set to a high voltage.

[0172] In some embodiments, during the second period t2, the second clock signal CB is provided to the seventh node N7 via the turned-on fourth transistor T4. A low voltage is provided to the seventh node N7. Through the coupling of the third capacitor C3, the voltage of the first node N1 is maintained at a voltage lower than the second power supply VGL (second-order low voltage).

[0173] In some embodiments, during the third cycle t3, the supply of the second clock signal CB to the third input terminal TM3 is interrupted. When the supply of the second clock signal CB is interrupted, the seventh transistor T7 is turned off.

[0174] In some embodiments, during the third cycle t3, the start signal STV or the output signal Outp from the output of the previous scan unit is provided to the first input terminal TM1, and the first clock signal CK is provided to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the first transistor T1 and the third transistor T3 are turned on.

[0175] In some embodiments, when the first transistor T1 is turned on, the first input terminal TM1 and the fifth node N5 are electrically coupled to each other. The twelfth transistor T12 remains on, and the first input terminal TM1 is electrically coupled to the first node N1 through the fifth node N5. The fifth node N5 and the first node N1 are set to a high voltage by a start signal STV provided to the first input terminal TM1 or an output signal Outp from the output terminal of the previous scan unit. When the fifth node N5 and the first node N1 are set to a high voltage, the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned off.

[0176] In some embodiments, when the third transistor T3 is turned on, a low voltage of the second power supply VGL is applied to the second node N2, causing the second node N2 and the sixth node N6 to be set to a low voltage. The fifth transistor T5 and the sixth transistor T6 can then be turned on.

[0177] In some embodiments, when the fifth transistor T5 is turned on, the voltage of the first power supply VGH is applied to the seventh node N7. The seventh node N7 remains at a high voltage. Since the fourth transistor T4 remains off, the voltage of the second clock signal CB, which is to be applied to the third input terminal TM3, is not transmitted to the seventh node N7. Since both the seventh node N7 and the first node N1, i.e., the opposite end of the third capacitor C3, remain at a high voltage, the third capacitor C3 is neither charged nor discharged. A current path is formed from the first power supply VGH through the fifth transistor T5 to the first node N1, and the high voltage of the first power supply VGH is transmitted to the first node N1. The voltage of the first node N1 remains stably at a high level.

[0178] In some embodiments, when the sixth transistor T6 is turned on, the third input terminal TM3 is electrically coupled to the third node N3. Since the second clock signal CB is not provided to the third input terminal TM3 during the third cycle t3, the third node N3 remains at a high voltage. Since the seventh transistor T7 remains off, the voltage of the third node N3 does not affect the voltage of the fourth node N4. The first capacitor C1 is configured to store a voltage corresponding to the on-level of the sixth transistor T6.

[0179] In some embodiments, during the fourth cycle t4, the second clock signal CB may be provided to the third input terminal TM3. When the second clock signal CB is provided to the third input terminal TM3, the seventh transistor T7 is turned on.

[0180] In some embodiments, when the seventh transistor T7 is turned on, the fourth node N4 and the third node N3 are electrically coupled to each other. A low voltage of the second clock signal CB, provided to the third input terminal TM3, is provided to the third node N3 and the fourth node N4 via the sixth transistor T6, which remains on. When a low voltage is provided to the fourth node N4, the ninth transistor T9 is turned on.

[0181] In some embodiments, when the ninth transistor T9 is turned on, the voltage of the first power supply VGH is provided to the output terminal TM4. The voltage of the first power supply VGH provided to the output terminal TM4 is provided to the nth gate line as a gate drive signal.

[0182] In some embodiments, during the fifth cycle t5, the supply of the second clock signal CB to the third input terminal TM3 is interrupted. When the supply of the second clock signal CB is interrupted, the seventh transistor T7 is turned off. The fourth node N4 is stably maintained at a high voltage through the second capacitor C2. The ninth transistor T9 remains on, and the voltage of the first power supply VGH is provided to the nth gate line as a gate drive signal.

[0183] Although the supply of the second clock signal CB is interrupted during the fifth cycle t5, the fourth transistor T4 remains off. Therefore, the voltage of the second clock signal CB is not supplied to the seventh node N7 and does not affect the voltage of the first node N1.

[0184] As described above, in some embodiments, during the supply of the gate drive signal, the fourth transistor T4 remains off to prevent voltage variations of the second clock signal CB from affecting the first node N1, thereby allowing the first node N1 to be stably maintained at a high voltage. Furthermore, in some embodiments, during the supply of the gate drive signal, the third capacitor C3 is prevented from charging or discharging. The third capacitor C3 does not perform charging or discharging operations at any time except when the voltage of the first node N1 is set low through the coupling of the third capacitor C3. Therefore, in some embodiments, the third capacitor C3 does not act as a load during the supply of the gate drive signal. This reduces power consumption and ensures reliable output of the gate drive signal.

[0185] Figure 28 This is a circuit diagram of a scanning unit according to some embodiments of the present disclosure. Figure 28 The scanning unit in Figure 27The difference in the scanning unit lies in that the first processing sub-circuit PSC1 further includes a thirteenth transistor T13. The thirteenth transistor T13 is coupled between the first power supply VGH and the fifth node N5. The gate of the thirteenth transistor T13 is coupled to the signal terminal NCX. The thirteenth transistor T13 can be turned on or off depending on the voltage at the signal terminal NCX. Optionally, when the thirteenth transistor T13 is turned on, the voltage of the first power supply VGH can be provided to the fifth node N5.

[0186] In another aspect, the present invention provides a display device including a scanning circuit described herein or manufactured by the methods described herein, and a display panel having a plurality of light-emitting elements. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a quantum dot display device.

[0187] The scanning circuit described in this disclosure can be used to generate various suitable control signals for sub-pixels in a display panel. In one example, the scanning circuit described in this disclosure is a light emission control signal generation circuit configured to generate light emission control signals for sub-pixels in a display panel. In another example, the scanning circuit described in this disclosure is a gate scan signal generation circuit configured to generate gate scan signals for sub-pixels in a display panel. In yet another example, the scanning circuit described in this disclosure is a reset control signal generation circuit configured to generate reset control signals for sub-pixels in a display panel.

[0188] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. A method for driving a scanning circuit, comprising: N first clock signals are provided to (k*N) stages of the scanning circuit in chronological order. The (k*N) stages include M groups, and each of the M groups includes one or more stages of the scanning circuit. N, k, and M are integers; N≥2, k≥1; M≥2. Each of the N first clock signals includes a first level component and a second level component following the first level component; The m-th group of the M groups is configured to receive the first clock signal before the (m+1)-th group of the M groups receives the first clock signal, where 1≤m≤(M-1); The difference between the starting point of the first level component of the nth first clock signal and the starting point of the nth data enable signal among the N data enable signals is equal to t. m1 ; The first clock signal t provided to different groups in the M groups m1 The values ​​are different; and The N data enable signals are signals provided to the timing controller, which is coupled to the scanning circuit and configured to control the timing of data output. The difference between the starting point of the first level component of the nth first clock signal and the starting point of the nth first reference period out of the N first reference periods is equal to t. mA ; The durations of the N first reference periods are the same; The Nth first reference period of the N first reference periods overlaps with the Nth period of the N first clock signals; At least a first period of the N first clock signals does not overlap with a first reference period portion of the N first reference periods; and The first clock signal t provided to different groups in the M groups mA The values ​​are different.

2. The method according to claim 1, wherein, The t that provides the first clock signal to different groups in the M groups m1 The value gradually increases group by group.

3. The method according to claim 1, wherein, The first clock signal t provided to the m-th group of the M groups m1 The value is less than t of the first clock signal provided to the (m+1)th group in the M groups. m1 The value; and The first clock signal t provided to the same group in the M groups m1 The values ​​are the same.

4. The method according to claim 1, wherein, The first clock signal t provided to the m-th group of the M groups mA The value is greater than t of the first clock signal provided to the (m+1)th group in the M groups. mA The value of is 1≤m≤(M-1).

5. The method according to claim 1, wherein, The first clock signal t provided to the same group in the M groups mA The values ​​are the same.

6. The method according to any one of claims 1 to 5, further comprising outputting (k*N) output control signals from the (k*N) stages of the scanning circuit respectively; in, The starting points of the (k*N) output control signals are equally spaced.

7. The method according to any one of claims 1 to 6, wherein, The duty cycle of the first clock signal provided to the M groups is the same.

8. The method according to any one of claims 1 to 7, wherein, The duty cycle of the first clock signal provided to the M groups gradually increases group by group.

9. The method according to any one of claims 1 to 8, further comprising providing N second clock signals to (k*N) stages of the scanning circuit in chronological order; in, Each of the N second clock signals includes a third level component and a fourth level component following the third level component; The m-th group of the M groups is configured to receive the second clock signal before the (m+1)-th group of the M groups receives the second clock signal; The difference between the starting point of the third level component of the nth second clock signal and the starting point of the nth data enable signal among the N data enable signals is equal to t. m2 ;as well as The second clock signal t is provided to different groups in the M groups. m2 The values ​​are different.

10. The method according to claim 9, wherein, The second clock signal t is provided to different groups in the M groups. m2 The value gradually increases group by group.

11. The method according to claim 9, wherein, The second clock signal t provided to the m-th group of the M groups m2 The value is less than t of the second clock signal provided to the (m+1)th group in the M groups. m2 The value; and The second clock signal t provided to the same group in the M groups m2 The values ​​are the same.

12. The method according to any one of claims 9 to 11, wherein, The difference between the starting point of the third level component of the nth second clock signal and the starting point of the nth second reference period out of the N second reference periods is equal to t. mB ; The durations of the N second reference periods are the same; The Nth second reference period of the N second reference periods overlaps with the Nth period of the N second clock signals; At least a first period of the N second clock signals does not overlap with a portion of the first second reference period of the N second reference periods; as well as The second clock signal t is provided to different groups in the M groups. mB The values ​​are different.

13. The method according to claim 12, wherein, The second clock signal t provided to the m-th group of the M groups mB The value is greater than t of the second clock signal provided to the (m+1)th group in the M groups. m2 The value of is 1≤m≤(M-1).

14. The method according to claim 12, wherein, The second clock signal t provided to the same group in the M groups mB The values ​​are the same.

15. The method according to any one of claims 1 to 14, further comprising providing an integrated circuit; in, The (m+1)th group of the M groups is closer to the integrated circuit than the mth group of the M groups, 1≤m≤(M-1).

16. The method according to any one of claims 1 to 15, further comprising: Provide the first clock signal line; as well as A modulation circuit is provided, the modulation circuit being configured to convert an original first clock signal transmitted by the first clock signal line into N first clock signals respectively provided in time sequence to the (k*N) levels; The modulation circuit includes: First transistor; First resistor; Second resistor; The first capacitor; and triode; The first electrode of the first transistor is coupled to the first clock signal line and the first end of the first resistor; The second electrode of the first transistor is coupled to the transistor; The second end of the first resistor is coupled to the first electrode of the first capacitor and the first end of the second resistor; The gate of the first transistor is coupled to the second terminal of the second resistor; and The output terminal of the transistor is coupled to the (k*N) stages; The method further includes providing N first clock signals to the (k*N) stages in chronological order through the modulation circuit; The method further includes gradually increasing the resistance value of the first resistor, thereby gradually increasing the t of the first clock signal provided to the M groups one by one. m1 The value of .

17. A scanning circuit, comprising: (k*N) levels; First clock signal line; as well as A modulation circuit is configured to convert the original first clock signal transmitted by the first clock signal line into N first clock signals provided sequentially to the (k*N) levels. Wherein, the (k*N) levels include M groups, and each of the M groups includes one or more levels of the scanning circuit, where N, k, and M are integers; N≥2, k≥1; M≥2; Each of the N first clock signals includes a first level component and a second level component following the first level component; The m-th group of the M groups is configured to receive the first clock signal before the (m+1)-th group of the M groups receives the first clock signal, where 1≤m≤(M-1); The difference between the starting point of the first level component of the nth first clock signal and the starting point of the nth data enable signal among the N data enable signals is equal to t. m1 ; The first clock signal t provided to different groups in the M groups m1 The values ​​are different; and The N data enable signals are signals provided to the timing controller, which is coupled to the scanning circuit and configured to control the timing of data output. The difference between the starting point of the first level component of the nth first clock signal and the starting point of the nth first reference period out of the N first reference periods is equal to t. mA ; The durations of the N first reference periods are the same; The Nth first reference period of the N first reference periods overlaps with the Nth period of the N first clock signals; At least a first period of the N first clock signals does not overlap with a first reference period portion of the N first reference periods; and The first clock signal t provided to different groups in the M groups mA The values ​​are different.

18. The scanning circuit according to claim 17, wherein, The modulation circuit includes: First transistor; First resistor; Second resistor; The first capacitor; and triode; The first electrode of the first transistor is coupled to the first clock signal line and the first end of the first resistor; The second electrode of the first transistor is coupled to the transistor; The second end of the first resistor is coupled to the first electrode of the first capacitor and the first end of the second resistor; The gate of the first transistor is coupled to the second terminal of the second resistor; and The output terminal of the transistor is coupled to the (k*N) stages.

19. The scanning circuit according to claim 17, further comprising a second clock signal line; in, The modulation circuit is further configured to convert the original second clock signal transmitted by the second clock signal line into N second clock signals provided sequentially to the (k*N) levels; Each of the N second clock signals includes a third level component and a fourth level component following the third level component; The m-th group of the M groups is configured to receive the second clock signal before the (m+1)-th group of the M groups receives the second clock signal; The difference between the starting point of the third level component of the nth second clock signal and the starting point of the nth data enable signal among the N data enable signals is equal to t. m2 ;as well as The second clock signal t is provided to different groups in the M groups. m2 The values ​​are different.

20. The scanning circuit according to claim 19, wherein, The modulation circuit includes: First transistor; First resistor; Second resistor; First capacitor; Second transistor; Third resistor; Fourth resistor; The second capacitor; and triode; The first electrode of the first transistor is coupled to the first clock signal line and the first end of the first resistor; The second electrode of the first transistor is coupled to the transistor; The second end of the first resistor is coupled to the first electrode of the first capacitor and the first end of the second resistor; The gate of the first transistor is coupled to the second terminal of the second resistor; The first electrode of the second transistor is coupled to the second clock signal line and the first terminal of the third resistor; The second electrode of the second transistor is coupled to the transistor. The second end of the third resistor is coupled to the first electrode of the second capacitor and the first end of the fourth resistor; The gate of the second transistor is coupled to the second terminal of the fourth resistor; and The output terminal of the transistor is coupled to the (k*N) stages.

21. A display device comprising a scanning circuit according to any one of claims 17 to 20, and an integrated circuit connected to the first clock signal line.

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