Display panel and display device

Abstract

A display panel (10). The display panel (10) comprises a plurality of pixel driving circuits (D), a plurality of pads (130), a plurality of first data lines (141) and at least one data lead (150). The plurality of pixel driving circuits (D) are disposed in a display area (AA), the plurality of pixel driving circuits (D) form a plurality of circuit columns (120) distributed along a first direction, the circuit column (120) comprises at least two pixel driving circuits (D) distributed along a second direction. The plurality of pads (130) are located on one side of the display area (AA) along the second direction. The plurality of first data lines (141) are disposed in the display area (AA), and the first data line (141) is coupled with at least two pixel driving circuits (D) in the circuit column (120). The data lead (150) is coupled with the first data line (141) and at least one pad (130). Wherein the plurality of circuit columns (120) form a plurality of circuit groups (DG) distributed along the first direction, the circuit group (DG) comprises at least one circuit column (120), and the data lead (150) is disposed between two adjacent circuit groups (DG).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] To provide users with a better user experience, full-screen displays, narrow bezels, and high resolutions will become the future development trend for display products, especially mobile phones. Summary of the Invention

[0003] On one hand, a display panel is provided. The display panel includes multiple pixel driving circuits, multiple pads, multiple first data lines, and at least one data lead. The multiple pixel driving circuits are disposed in a display area, forming multiple circuit columns distributed along a first direction. Each circuit column includes at least two pixel driving circuits distributed along a second direction, the second direction intersecting the first direction. The multiple pads are disposed in a non-display area and located on one side of the display area along the second direction. The multiple first data lines are disposed in the display area, extending along the second direction and coupled to at least two pixel driving circuits in the circuit columns. The data lead is coupled to the first data lines, extending from the display area to the non-display area, and is coupled to at least one pad. The multiple circuit columns form multiple circuit groups distributed along the first direction, each circuit group including at least one circuit column, and the data lead is disposed between two adjacent circuit groups.

[0004] In some embodiments, at least one data lead includes at least one first data lead, wherein the portion of the first data lead located in the display area is disposed on the same layer as the first data line.

[0005] In some embodiments, at least one data lead includes at least one second data lead, wherein the portion of the second data lead located in the display area is disposed on a different layer from the first data lead.

[0006] In some embodiments, at least one data lead may be multiple data leads, and the multiple data leads may include at least one first data lead, wherein the portion of the first data lead located in the display area is disposed on the same layer as the first data line. In the thickness direction of the display panel, the first data lead and the second data lead do not overlap.

[0007] In some embodiments, the display panel further includes a plurality of first signal lines. The plurality of first signal lines are disposed in the display area, extending along a first direction, and each first signal line includes a plurality of first line segments and at least one second line segment. A second data lead is disposed on the same layer as the first line segments in the portion of the display area, and is disposed between two adjacent first line segments. Two adjacent first line segments in the first direction are coupled together by a second line segment, which is disposed on a different layer than the first line segments.

[0008] In some embodiments, the display panel further includes at least one connecting line disposed in the display area, the connecting line extending along a first direction. The connecting line couples a first data line to a data lead, and the connecting line and a second data lead are disposed on the same layer in the portion of the display area.

[0009] In some embodiments, the display panel further includes at least one connecting line. The at least one connecting line is disposed in the display area and extends along a first direction. The first data line is coupled to a data lead via the connecting line.

[0010] In some embodiments, the display panel further includes a plurality of signal lines. The plurality of signal lines are disposed in the display area and extend along a first direction. The plurality of signal lines form a plurality of signal line groups distributed along a second direction, and each signal line group includes at least one signal line. Connecting lines are disposed on the same layer as at least a portion of the signal lines and are disposed between two adjacent signal line groups.

[0011] In some embodiments, in a plurality of signal line groups, the distance between any two adjacent signal line groups is approximately the same.

[0012] In some embodiments, the display panel further includes a plurality of light-emitting devices coupled to a pixel driving circuit. The plurality of first data lines include a plurality of different-color data lines, each coupled to at least two light-emitting devices emitting different colors. The portions of all data leads coupled to the plurality of different-color data lines are arranged on the same layer as the display area.

[0013] In some embodiments, the display panel further includes at least one second data line extending from the display area to the non-display area along a second direction and coupled to at least one pad.

[0014] In some embodiments, at least one data lead may be multiple data leads, which form multiple lead groups distributed along a first direction. Each data lead in a lead group is disposed between two identical circuit groups. In the display area, the distance between any two adjacent lead groups is approximately the same.

[0015] On the other hand, a display device is provided. The display device includes a display panel as described in any of the above embodiments.

[0016] On the other hand, a method for manufacturing a display panel is provided. The method includes: forming a plurality of pixel driving circuits, a plurality of pads, a plurality of first data lines, and at least one data lead on a substrate; the plurality of pixel driving circuits forming a plurality of circuit columns distributed along a first direction, each circuit column including at least two pixel driving circuits distributed along a second direction, the first and second directions intersecting; the plurality of pads located on one side of the plurality of pixel driving circuits along the second direction; the first data lines extending along the second direction and coupled to at least two pixel driving circuits in the circuit columns; the data lead extending along the second direction and coupled to the first data lines and at least one pad; the plurality of circuit columns forming a plurality of circuit groups distributed along the first direction, each circuit group including at least one circuit column; and the data lead disposed between two adjacent circuit groups. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0018] Figure 1 This is a structural diagram of a display panel based on related technologies;

[0019] Figure 2 This is a structural diagram of a display device according to some embodiments;

[0020] Figure 3 and Figure 4 This is a structural diagram of a display panel according to some embodiments;

[0021] Figure 5 This is the equivalent circuit diagram of the pixel driving circuit;

[0022] Figure 6 A top view of a plurality of pixel driving circuits in a display panel according to some embodiments;

[0023] Figures 7-9 This is a partial enlarged view of a display panel according to some embodiments;

[0024] Figure 10 for Figure 1 A magnified view of a portion of region U2 in the display panel of the related technology;

[0025] Figure 11 This is a top view of a display panel according to some embodiments;

[0026] Figure 12 for Figure 11 A magnified view of a portion of the display panel;

[0027] Figure 13 for Figure 7 A magnified view of a portion of area U3 in the display panel;

[0028] Figure 14 for Figure 8 A magnified view of a portion of area U4 in the display panel;

[0029] Figure 15 This is a partial enlarged view of the display area of ​​a display panel according to some embodiments. Detailed Implementation

[0030] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0031] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0032] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0033] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0034] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0035] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0036] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0037] As used herein, “approximately” or “about” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0038] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0039] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0040] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0041] See Figure 1 In related technologies, a display panel DP may have a display area AA', and the display panel DP may also have a fan-out area FA', a bending area BA', and a bonding area PA' located on one side of the display area AA' (e.g., on one side of the display area AA' along the negative Y-axis). Exemplarily, the fan-out area FA', the bending area BA', and the bonding area PA' may be arranged sequentially.

[0042] The display panel DP may also include multiple data lines DB, multiple data leads DL, and multiple pads P. Multiple (e.g., all) data lines DB are located in the display area AA'. A data line DB (e.g., each data line DB) can be configured to write data signals to the pixel driving circuitry. Multiple pads P can be located in the bonding area PA'. A data line DB located in the display area AA' can be coupled to at least one pad P located in the bonding area PA' via a data lead. Specifically, a data lead DL (e.g., each data lead DL) is coupled to a data line DB, and the data lead DL can also extend from the fan-out area FA' to the bend area BA' and the bonding area PA', and be coupled to at least one (e.g., one; or, multiple) pad P located in the bonding area PA'. Further, a pad P (e.g., each pad P) can be configured to be coupled to data driving circuitry (e.g., a source driver). In this way, the electrical signals (including data signals) output by the data driving circuit can be written into the pixel driving circuit through one or more pads P, data leads DL and data lines DB.

[0043] See also Figure 1The portion of the display panel DP located in the bending area BA' can be bent, thereby bending the portion of the display panel DP located in the bonding area PA' to the back of the display panel DP, i.e., the side of the display panel DP facing the non-display surface. Based on the above, the height h1 of the fan-out area FA' (e.g., the dimension of the fan-out area FA' along the Y-axis) can affect the size k1 of the bottom bezel of the display panel DP (e.g., the bezel of the display panel DP at one end along the negative Y-axis). The larger the height h1 of the fan-out area FA', the larger the size k1 of the bottom bezel of the display panel DP.

[0044] Regarding the height of the fan-out area FA', since the dimension d1 of the bonding area PA' with multiple pads P along the first direction (e.g., parallel to the X-axis) is smaller than the dimension d2 of the display area AA' with multiple data lines DB along the first direction, multiple data leads DL can be arranged in a fan shape in the fan-out area FA'. This results in a greater number of diagonal traces (e.g., portions of data leads DL extending in directions not parallel to the Y-axis) in the fan-out area FA', especially at the corner CR' of the lower bezel of the display panel DP, leading to a larger height h1 in the fan-out area FA', and consequently a larger bezel size for the display panel DP.

[0045] The bezel size of a display panel (DP) can be reduced by decreasing the number of data lines (DB). Because the number of DBs is reduced, the number of diagonal traces in the fan-out area (FA') can be reduced, thus decreasing the bezel size of the DP. However, reducing the number of DBs may lead to a reduction in the number of light-emitting devices in the DP, i.e., a reduction in the DP's resolution. How to reduce the bezel size of a display panel while maintaining its resolution is a pressing problem that needs to be solved.

[0046] To address the aforementioned problems, embodiments of this disclosure provide a display panel and a method for manufacturing the same, as well as a display device.

[0047] Figure 2 This is a structural diagram of a display device according to some embodiments. See also... Figure 2 Display device 1 is a product with image display function (including still images or moving images, where moving images can be video). For example, display device 1 can be any of the following: monitor, television set, billboard, digital photo frame, laser printer with display function, telephone, mobile phone, personal digital assistant (PDA), digital camera, portable camcorder, viewfinder, navigator, vehicle, large wall surface, home appliance, information query equipment (such as business query equipment in e-government, banking, hospitals, power, etc.), monitor, etc.

[0048] The display device 1 includes a display panel 10. The display panel 10 can be configured to display an image. The structure of the display panel 10 will be described in detail below. The display device 1 may also include a drive control circuit 20 coupled to the display panel 10. The drive control circuit 20 is configured to provide an electrical signal to the display panel 10, and in response to the electrical signal, the display panel 10 can display an image.

[0049] See also Figure 2 The drive control circuit 20 may include a data drive circuit 210 (also known as a source driver IC), which is configured to provide a data drive signal (also known as a data signal) to the display panel 10.

[0050] The drive control circuit 20 may also include a timing control circuit 220 (also called a timing controller, or TCON) coupled to the data drive circuit 210.

[0051] In some embodiments, the drive control circuit 20 may further include a scan drive circuit 110. In other embodiments, the scan drive circuit 110 may be integrated into the display panel 10, or the display panel 10 may include the scan drive circuit 110. Since the scan drive circuit 110 is disposed in the display panel 10, the scan drive circuit 110 may also be referred to as GOA (Gate Driver on Array, a scan drive circuit disposed on an array substrate).

[0052] The timing control circuit 220 can be coupled to the data driving circuit 210 and also to the scan driving circuit 110.

[0053] The timing control circuit 220 can be configured to receive display signals, such as power signals, video image signals, communication signals (e.g., signals corresponding to the IIC communication protocol), and mode control signals (e.g., mode control signals corresponding to test mode or normal display mode). The video image signals are, for example, MIPI (Mobile Industry Processor Interface) signals or LVDS (Low-Voltage Differential Signaling) signals. The video image signals can include image data and timing control signals. Image data can include, for example, pixel data of multiple sub-pixels, such as RGB data. Timing control signals include, for example, a data enable signal (DE), a horizontal synchronization signal (Hsync, HS), and a vertical synchronization signal (Vsync, VS).

[0054] The timing control circuit 220 can also be configured to output a first control signal and image data to the data driving circuit 210 and a second control signal to the scan driving circuit 110 in response to the display signal. The first control signal is configured to control the operating timing of the data driving circuit 210, and the second control signal is configured to control the operating timing of the scan driving circuit 110.

[0055] The data driving circuit 210 can be configured to convert received image data into data signals for a plurality of light-emitting devices E (described below) in the display panel 10, and output the data signals to the pixel driving circuits D (described below) coupled to the corresponding light-emitting devices E according to the operating timing determined by the first control signal. The scan driving circuit 110 is configured to output scan signals to the plurality of pixel driving circuits D according to the operating timing determined by the second control signal.

[0056] Some embodiments of this disclosure also provide a display panel. This display panel can be used as the display panel in any of the display devices provided in the above embodiments. Of course, this display panel can also be applied to other display devices, and the embodiments of this disclosure do not limit this application.

[0057] Figure 3 and Figure 4 This is a structural diagram of a display panel according to some embodiments. It should be noted that, for clarity of the drawings, Figure 3 The image shows multiple pixel driving circuits, multiple light-emitting devices, and multiple data lines in the display panel, but omits many data leads. Furthermore, Figure 3 The specific structure of the non-display area is omitted. Figure 4The image shows multiple data lines and multiple data leads in the display panel, while omitting multiple pixel drive circuits and multiple light-emitting devices.

[0058] See Figure 3 and Figure 4 The display panel 10 can be one of OLED (Organic Light Emitting Diode) display panel, QLED (Quantum Dot Light Emitting Diodes) display panel, or microLED (including MiniLED or MicroLED, where LED is a light-emitting diode) display panel.

[0059] See also Figure 3 and Figure 4 The display panel 10 has a display area AA. The portion of the display panel 10 located in the display area AA can display an image. The display panel 10 also has a non-display area SA. The non-display area SA can be located at least on one side of the display area AA (e.g., one side; or, around all sides, including the top, bottom, left, and right sides). See also Figure 4 In some embodiments, the non-display area SA of the display panel 10 may include a bonding area PA. The non-display area SA of the display panel 10 may also include a fan-out area FA and a bending area BA. The fan-out area FA, bending area BA, and bonding area PA may be located on one side of the display area AA (e.g., on one side of the display area AA along the negative Y-axis). Furthermore, the fan-out area FA, bending area BA, and bonding area PA may be arranged sequentially; for example, the fan-out area FA, bending area BA, and bonding area PA may be arranged sequentially along the negative Y-axis.

[0060] See Figure 3 The display panel 10 may include multiple light-emitting devices E. Multiple (e.g., all) light-emitting devices E may be disposed in the display area AA. The light-emitting devices E may emit light, for example, red light, green light, blue light, or white light. By emitting light through the multiple light-emitting devices E disposed in the display area AA, the portion of the display panel 10 located in the display area AA can display an image. The light-emitting devices E may be one of organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), or light-emitting diodes (LEDs).

[0061] See also Figure 3The display panel 10 may further include multiple pixel driving circuits D. Multiple (e.g., all) pixel driving circuits D are disposed in the display area AA. A pixel driving circuit D (e.g., each pixel driving circuit D) may be coupled to a light-emitting device E. The pixel driving circuit D may be configured to provide an electrical signal (e.g., driving voltage or driving current) to the light-emitting device E coupled to it in response to received scan signals and data signals (e.g., scan signals output from a scan driving circuit and data signals output from a data driving circuit), thereby driving the light-emitting device E to emit light, thus enabling the display panel 10 to display an image.

[0062] Pixel driving circuit D may include multiple transistors and at least one (e.g., one; or multiple) capacitor. For example, pixel driving circuit D may have a structure such as "2T1C", "6T1C", "7T1C", "6T2C", or "7T2C". Here, "T" represents a transistor, such as a thin-film transistor. The number preceding "T" indicates the number of transistors. "C" represents a capacitor, and the number preceding "C" indicates the number of capacitors. The pixel driving circuit D will be described below using a "7T1C" structure as an example. Understandably, when pixel driving circuit D has other structures, the structure, function, and connection relationships of the components (e.g., transistors or capacitors) in pixel driving circuit D can be similar to those of the 7T1C structure pixel driving circuit D, as described in the following description.

[0063] In some embodiments, all transistors in the pixel driving circuit D are LTPS (Low Temperature Poly-Silicon) transistors. The active layer of the LTPS transistor may be made of polycrystalline silicon. In other embodiments, one or more (e.g., two) transistors in the pixel driving circuit D are oxide transistors, and the active layer of the oxide transistor may be made of oxide, such as IGZO (Indium Gallium Zinc Oxide). When the pixel driving circuit D includes at least one LTPS transistor and at least one oxide transistor, the pixel driving circuit D may also be referred to as an LTPO (Low-Temperature Polycrystalline Oxide) type pixel driving circuit.

[0064] Figure 5 This is the equivalent circuit diagram of the pixel driving circuit. Figure 6 This is a top view of a plurality of pixel driving circuits in a display panel according to some embodiments. It should be noted that... Figure 6 Only multiple conductor pattern layers are shown, while other film layers, such as the active layer, are omitted.

[0065] See Figure 5 The pixel driving circuit D can be a 7T1C structure, that is, the pixel driving circuit D can include 7 transistors, such as the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7. The pixel driving circuit D can also include 1 capacitor C.

[0066] For example, the operation of the pixel driving circuit D may include the following three stages:

[0067] In the first stage, in response to the first scan signal GA1, the first transistor T1 is turned on, thereby writing the first reset signal Vint1 into the gate of the third transistor T3. This resets the gate of the third transistor T3. Furthermore, in the first stage, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can all be turned off.

[0068] In the second stage, in response to the second scan signal GA2, the fourth transistor T4 is turned on. And in response to the third scan signal GA3, the second transistor T2 is turned on. Through the fourth transistor T4 and the second transistor T2, the data signal DA can be written to the gate of the third transistor T3, making the gate voltage of the third transistor T3 VDA + Vth, where VDA is the voltage of the data signal DA, and Vth is the threshold voltage of the third transistor T3. Furthermore, in the second stage, the first transistor T1, the fifth transistor T5, and the sixth transistor T6 can all be turned off.

[0069] In some embodiments, in the second stage, the seventh transistor T7 may also be turned on in response to the fourth scan signal GA4, thereby writing the second reset signal Vint2 into the light-emitting device E. This resets the light-emitting device E. In some possible implementations, the gates of the fourth transistor T4 and the seventh transistor T7 may be connected in series, so that both the fourth transistor T4 and the seventh transistor T7 can be turned on in the second stage, allowing the data signal DA to be written into the gate of the third transistor T3, and also resetting the light-emitting device E. In other embodiments, the step of writing the second reset signal Vint2 into the light-emitting device E may be performed in the first stage. For example, the gates of the first transistor T1 and the seventh transistor T7 may be connected in series, so that both the first transistor T1 and the seventh transistor T7 can be turned on in the first stage, allowing both the third transistor T3 and the light-emitting device E to be reset in the first stage.

[0070] In the third stage, in response to the fifth scan signal GA5, the fifth transistor T5 is turned on. Through the fifth transistor T5, the power supply voltage signal VDD can be written to the first terminal (e.g., the source) of the third transistor T3, making the voltage at the first terminal of the third transistor T3 VDD. In response to the voltage VDD at its first terminal and the gate voltage VDA+Vth, the third transistor T3 can generate a drive current flowing through its first and second terminals (e.g., the drain). Furthermore, in response to the sixth scan signal GA6, the sixth transistor T6 is turned on. Through the sixth transistor T6, the drive current generated by the third transistor T3 can flow into the light-emitting device E to drive it to emit light. Additionally, in the third stage, the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 can all be turned off.

[0071] See Figure 5 and Figure 6 The display panel may include an active layer (not shown) and multiple conductor pattern layers, such as a first conductor pattern layer 160 and a second conductor pattern layer 170. The active layer and the multiple conductor pattern layers may form one or more of the aforementioned pixel driving circuits D.

[0072] In addition, see also Figure 5 and Figure 6 In order to write the electrical signals described above into the pixel driving circuit D, the conductor pattern layer may further include one or more signal lines. A signal line may be configured to write one or more of the aforementioned electrical signals (e.g., data signal DA, first scan signal GA1, second scan signal GA2, third scan signal GA3, fourth scan signal GA4, fifth scan signal GA5, sixth scan signal GA6, first reset signal Vint1, second reset signal Vint2, and power supply voltage signal VDD) into the pixel driving circuit D. Those skilled in the art will understand that when multiple electrical signals are written into the pixel driving circuit D by a single signal line, these multiple electrical signals may be the same.

[0073] See also Figure 5 and Figure 6For example, the first conductor pattern layer 160 may include multiple first data lines 141. The first data lines 141 may be coupled to a fourth transistor T4 in the pixel driving circuit D. The first data lines 141 may be configured to write a data signal DA to the pixel driving circuit D. The first conductor pattern layer 160 may also include multiple power supply voltage signal lines 161. The first power supply voltage signal lines 161 may be coupled to a fifth transistor T5 in the pixel driving circuit D. The first power supply voltage signal lines 161 may be configured to write a power supply voltage signal VDD to the pixel driving circuit D. Furthermore, the first conductor pattern layer 160 may also include one or more connection patterns CP. The connection pattern CP may be part of the pixel driving circuit D. The connection pattern CP may be configured to couple two elements in the pixel driving circuit D (e.g., transistors or capacitors). The connection pattern CP may also be configured to couple the pixel driving circuit D to other elements besides the pixel driving circuit D, for example, to couple the pixel driving circuit D to a light-emitting device E.

[0074] For example, see also Figure 5 and Figure 6 The second conductor pattern layer 170 may include multiple reset signal lines 171. The reset signal lines 171 may be coupled to a seventh transistor T7 in the pixel driving circuit D. The reset signal lines 171 may be configured to write a second reset signal Vint2 to the pixel driving circuit D. Furthermore, similar to the first conductor pattern layer 160, the second conductor pattern layer 170 may also include one or more connection patterns CP.

[0075] Based on the above, a pixel driving circuit D can be the smallest unit capable of implementing the functions described above, such as... Figure 6 As shown. See also Figure 6 Those skilled in the art will understand that the pixel driving circuit D is coupled to one or more signal lines. For example, a signal line may contact the pixel driving circuit to achieve mutual coupling. Therefore, as the position of the pixel driving circuit D changes, the position of one or more signal lines coupled to the pixel driving circuit D will also change accordingly. Based on this, a portion of a signal line can be configured to define the boundary of the pixel driving circuit D. For example, the position where a signal line contacts the pixel driving circuit can be configured to define the boundary of the pixel driving circuit. For example, a portion of the first data line 141 coupled to the pixel driving circuit D1 can serve as the left boundary D1a of the pixel driving circuit D1 (e.g., the boundary of the pixel driving circuit D1 along the negative X-axis direction). As another example, a portion of the first data line 141 coupled to the pixel driving circuit D2 can serve as the right boundary D2b of the pixel driving circuit D2 (e.g., the boundary of the pixel driving circuit D2 along the positive X-axis direction).

[0076] See Figure 3 and Figure 6 In the display panel 10, a plurality of pixel driving circuits D can be formed into a plurality of circuit columns 120 distributed along a first direction (e.g., parallel to the X-axis direction). A circuit column 120 (e.g., each circuit column 120) includes at least two pixel driving circuits D distributed along a second direction (e.g., parallel to the Y-axis direction). Exemplarily, in the display panel 10, the plurality of pixel driving circuits D can be arranged in an array. It should be noted that the first and second directions intersect; for example, the first direction is perpendicular to the second direction. The first direction (e.g., parallel to the X-axis direction) and the second direction (e.g., parallel to the Y-axis direction) can be parallel to the extension direction of the display panel 10.

[0077] See Figure 4 The display panel 10 includes a plurality of pads 130. The plurality of pads 130 are disposed in a non-display area SA. Furthermore, the plurality of (e.g., all) pads 130 may be located on one side of the display area AA along a second direction (e.g., parallel to the Y-axis direction). Exemplarily, a bonding area PA may be located on one side of the display area AA along the second direction, for example, along the negative Y-axis direction, and the plurality of (e.g., all) pads 130 may be located within the bonding area PA.

[0078] A pad 130 (e.g., each pad 130) can be configured to be coupled to data drive control circuitry (i.e., a source driver). Exemplarily, the pad 130 can be coupled to the data drive control circuitry via anisotropic conductive adhesive.

[0079] See Figure 3 and Figure 4 The display panel 10 also includes a plurality of first data lines 141. The plurality of (e.g., all) first data lines 141 are disposed in the display area AA. A first data line 141 (e.g., each first data line 141) extends along a second direction (e.g., parallel to the Y-axis direction) and is coupled to at least two pixel driving circuits D in a circuit array 120. Exemplarily, a first data line 141 may be coupled to two pixel driving circuits D in a circuit array 120. Also exemplaryly, a first data line 141 may be coupled to all pixel driving circuits D in a circuit array 120.

[0080] See Figure 4The display panel 10 also includes at least one (e.g., one; or multiple) data lead 150. A data lead 150 (e.g., each data lead 150) is coupled to a first data line 141. A data lead 150 (e.g., each data lead 150) extends from the display area AA to the non-display area SA. Furthermore, the data lead 150 is coupled to at least one (e.g., one; or multiple) pad 130. Thus, a first data line 141 can be coupled to at least one pad 130 via a single data lead 150. Exemplarily, a data lead 150 may include a first portion and a second portion coupled to each other, wherein the first portion is located in the display area AA. The first portion may be a straight line extending in a second direction. The second portion is located in the non-display area. The second portion may be coupled to at least one pad 130.

[0081] See Figure 3 and Figure 4 Referring to the above description, a pad 130 can be configured to be coupled to a data driving circuit. Furthermore, a data lead 150 is coupled to at least one pad 130, and this data lead 150 is also coupled to a first data line 141. The first data line 141 is coupled to at least two pixel driving circuits in a circuit array 120. Based on this, at least two (e.g., all) pixel driving circuits D in a circuit array 120 can be coupled to the data driving circuit via the first data line and the data lead, such that data signals output by the data driving circuit can be written to at least two (e.g., all) pixel driving circuits D in the circuit array 120. In response to this data signal, a plurality of light-emitting devices E coupled to the at least two pixel driving circuits D can emit light, enabling the display panel 10 to display an image.

[0082] Figures 7-9 This is a partial enlarged view of a display panel according to some embodiments, showing the locations of data leads and pixel driving circuitry. It should be noted that, for the sake of simplicity in the accompanying drawings, Figures 7-9 The light-emitting device and the specific structure of the pixel driving circuit are omitted. Only the relative positions of the pixel driving circuit and the data leads are shown.

[0083] See Figures 7-9In the display panel 10, multiple circuit columns 120 form multiple circuit groups DG distributed along a first direction (e.g., parallel to the X-axis direction). A circuit group DG (e.g., each circuit group DG) includes at least one (e.g., one; or multiple) circuit columns 120. Furthermore, a data lead 150 is disposed between two adjacent circuit groups DG. Alternatively, a data lead 150 can be disposed between two adjacent pixel driving circuits D, which belong to two adjacent circuit groups DG respectively. It should be noted that two adjacent circuit groups DG can mean that there are no other circuit groups DG between these two circuit groups DG. Similarly, two adjacent pixel driving circuits D can mean that there are no other pixel driving circuits D between these two pixel driving circuits D.

[0084] The embodiments of this disclosure do not limit the number of data leads 150 provided between two adjacent circuit groups DG. Exemplarily, one data lead 150 is provided between two adjacent circuit groups DG. Also exemplaryly, multiple data leads 150 are provided between two adjacent circuit groups DG.

[0085] Figure 10 for Figure 1 The image shows a partial enlarged view of region U2 in the display panel of the related technology. It should be noted that... Figures 7-9 The structure of region U1 in a display panel according to some embodiments is shown, wherein region U1 is provided with eight pixel driving circuits. For comparison, Figure 8 The structure of region U2 in the display panel of the related technology is shown, and region U2 is also provided with 8 pixel driving circuits.

[0086] See Figures 7-9In the display panel provided in the embodiments of this disclosure, since a data lead 150 (e.g., each data lead 150) is disposed between two adjacent circuit groups DG, under the premise that the dimensions t1 of region U1 along the first direction (e.g., parallel to the X-axis direction) and t2 of region U2 along the first direction are the same, in the display panel according to the embodiments of this disclosure, the dimension r1 of a pixel driving circuit D (e.g., each pixel driving circuit D) along the first direction can be smaller than the dimension r2 of a pixel driving circuit D' along the first direction in the related art. Thus, in the display panel provided in the embodiments of this disclosure, without increasing the display panel size or reducing the number of pixel driving circuits, a certain space can be provided between two adjacent circuit groups DG by reducing the dimension of the pixel driving circuit D in the first direction. This space can be used to arrange one or more data leads 150. It is understood that since there is a certain space between two adjacent circuit groups DG, one or more of the plurality of conductor pattern layers also have a certain space at their respective positions, and data leads can be disposed in the corresponding spaces of the one or more conductor pattern layers. In this way, without increasing the size of the display panel or reducing the number of pixel driving circuits, at least one (e.g., one; or multiple) data lead 150 can be set in the display area AA.

[0087] Further, see Figure 1 and Figure 4 A data lead 150 can be closer to the center line 10c of the display panel 10 than the first data line 141 coupled to it. The center line 10c is the center line of the display panel along a first direction (e.g., parallel to the X-axis). Thus, provided the number of data leads 150 in the display panel 10 is the same as the number of data leads DL in the display panel DP, the tilt angle o1 (e.g., the angle between the extension direction of the tilted line and the negative direction of the Y-axis) of the oblique trace in the fan-out area FA of the display panel 10 (e.g., the portion of the second part of the data lead 150 located in the fan-out area FA and whose extension direction is not parallel to the Y-axis) can be smaller than the tilt angle o2 of the oblique trace in the fan-out area FA' of the display panel DP. Thus, the height h2 of the fan-out area FA in the display panel 10 can be smaller than the height h1 of the fan-out area FA' in the display panel DP, thereby making the size k2 of the frame of the display panel 10 (i.e., the frame with the fan-out area) smaller than the size k1 of the frame of the display panel DP. Based on the above, in the display panel provided in the embodiments of this disclosure, without reducing the number of pixel driving circuits, at least one (e.g., one; or multiple) data lead 150 can be provided in the display area AA, and the bezel size of the display panel can be reduced without increasing the size of the display panel or reducing the resolution of the display panel.

[0088] See Figures 7-9 In some embodiments, at least one (e.g., one; or multiple) data lead 150 includes at least one (e.g., one; or multiple) first data lead 151. A portion 151a of a first data lead 151 (e.g., each first data lead 151) located in the display area AA (i.e., the first portion of the first data lead 151) is disposed on the same layer as the first data line.

[0089] For example, when the display panel includes a data lead 150 and the data lead 150 includes a first data lead 151, the data lead 150 is the first data lead 151. Alternatively, the portion of the data lead 150 located in the display area AA is disposed on the same layer as the first data line. As another example, when the display panel includes multiple data leads 150 and the multiple data leads 150 include a first data lead 151, one of the multiple data leads 150 is the first data lead 151. Alternatively, the portion of the multiple data leads 150 located in the display area AA is disposed on the same layer as the first data line. As yet another example, when the display panel includes multiple data leads 150 and the multiple data leads 150 include multiple first data leads 151, multiple (e.g., some; or all) of the multiple data leads 150 are first data leads 151. Alternatively, it can be said that the portion of each of the data leads 150 located in the display area AA is set on the same layer as the first data line.

[0090] See Figures 6-9 In some possible implementations, the portion 151a of the first data lead 151 located in the display area AA and the first data line 141 are both located in the first conductor pattern layer 160.

[0091] See also Figures 6-9 Referring to the above description, the first data line 141 is located in the display area AA and extends along the second direction. Furthermore, the portion 151a of the first data lead 151 located in the display area AA, i.e., the first portion 151a of the first data lead 151, can also extend along the second direction. That is, the first portion 151a of the first data lead 151 and the first data line 141 can extend in the same direction. Therefore, the portion 151a of the first data lead 151 located in the display area AA can be disposed on the same layer as the first data line 141. In this way, compared to one or more first data leads 151 being separately disposed on other pattern layers (e.g., pattern layers in the display panel other than multiple conductor pattern layers used to form multiple pixel driving circuits and conductor pattern layers containing one or more signal lines), the display panel can include fewer pattern layers, allowing for a smaller display panel thickness, which is beneficial for the thinning and lightening of the display panel and display device.

[0092] See Figures 7-9 In some embodiments, at least one (e.g., one; or multiple) data lead 150 includes at least one (e.g., one; or multiple) second data lead 152. A portion 152a of a second data lead 152 (e.g., each second data lead 152) located in the display area AA (i.e., the first portion 152a of the second data lead 152) is disposed on a different layer from the first data line.

[0093] For example, when the display panel includes a data lead 150 and the data lead 150 includes a second data lead 152, the data lead 150 is the second data lead 152. Alternatively, the portion of the data lead 150 located in the display area AA is disposed on a different layer from the first data line. As another example, when the display panel includes multiple data leads 150 and the multiple data leads 150 include a second data lead 152, one of the multiple data leads 150 is the second data lead 152. Alternatively, the portion of the multiple data leads 150 located in the display area AA is disposed on a different layer from the first data line. As yet another example, when the display panel includes multiple data leads 150 and the multiple data leads 150 include multiple second data leads 152, multiple (e.g., some; or all) of the multiple data leads 150 are second data leads 152. Alternatively, it can be said that the portion of each of the data leads 150 located in the display area AA is set on a different layer from the first data line.

[0094] Since the portion 152a of the second data lead 152 located in the display area AA is on a different layer than the first data line, the influence of the second data lead 152 on the first data line 141 can be reduced, and the problem of signal crosstalk between the two signal lines can be improved.

[0095] See Figure 6 , Figure 8 and Figure 9 In some possible implementations, the first data line 141 is located in the first conductor pattern layer 160. The portion 152a of the second data lead 152 located in the display area AA is located in the second conductor pattern layer 170. In this way, compared to one or more second data leads 152 being separately disposed on other pattern layers (e.g., pattern layers in the display panel other than multiple conductor pattern layers used to form multiple pixel driving circuits and conductor pattern layers containing one or more signal lines), the display panel can include fewer pattern layers, making the thickness of the display panel smaller, which is beneficial for the thinning of the display panel and the display device.

[0096] See Figure 8 and Figure 9In some embodiments, the display panel includes multiple data leads 150. Each data lead 150 includes at least one first data lead 151. A portion 151a of a first data lead 151 (e.g., each first data lead 151) located in the display area AA is disposed on the same layer as the first data line. The multiple data leads 150 also include at least one second data lead 152. A portion 152a of a second data lead 152 (e.g., each second data lead 152) located in the display area AA is disposed on a different layer from the first data line. A portion 151a of a first data lead 151 (e.g., each first data lead 151) located in the display area AA and a portion 152a of a second data lead 152 located in the display area AA are disposed on different layers. Thus, given a fixed distance between two adjacent circuit groups CG, more data leads can be arranged in the corresponding spaces of the two conductor pattern layers.

[0097] Furthermore, in some possible implementations, in the thickness direction of the display panel (e.g., parallel to the Z-axis), a first data lead 151 (e.g., each first data lead 151) does not overlap with a second data lead 152. This reduces signal crosstalk between the first data lead 151 and the second data lead 152, improving the display effect of the display panel. Understandably, since a first data lead 151 (e.g., each first data lead 151) does not overlap with a second data lead 152, correspondingly, the portion 151a of the first data lead 151 located in the display area AA also does not overlap with the portion 152a of the second data lead 152 located in the display area AA.

[0098] Figure 11 This is a top view of a display panel according to some embodiments, showing multiple pixel driving circuits and multiple data leads located in the display area. See also Figure 11 In some embodiments, the display panel 10 includes at least one data lead 150, which includes at least one second data lead 152. The display panel 10 also includes multiple first signal lines 171. Multiple (e.g., all) first signal lines 171 are disposed in the display area. Exemplarily, the first signal lines 171 may be connected to a seventh transistor in the pixel driving circuit D. Figure 5 The first signal line 171 can be configured to write a second reset signal to the pixel driving circuit D. In this case, the first signal line 171 can also be referred to as a reset signal line. A first signal line 171 (e.g., each first signal line 171) extends along a first direction (e.g., parallel to the X-axis direction). Exemplarily, a first signal line 171 (e.g., each first signal line 171) extends along the first direction and is coupled to a plurality of pixel driving circuits D distributed along the first direction.

[0099] Figure 12 for Figure 11 A magnified view of a portion of the display panel. It should be noted that, for clarity, the accompanying image... Figure 12 Only the first signal line and data lead are shown, while other patterns are omitted.

[0100] See Figure 12 A first signal line 171 (e.g., each first signal line 171) includes a plurality of first segments 171a and at least one (e.g., one; or multiple) second segments 171b. A portion 152a of a second data lead (e.g., each second data lead) located in the display area (i.e., the first portion of the second data lead) is disposed on the same layer as the first segments 171a. Exemplarily, both the portion 152a of the second data lead in the display area and the first segments 171a are located in the second conductor pattern layer 170. Furthermore, the portion 152a of a second data lead (e.g., each second data lead) located in the display area is disposed between two adjacent first segments 171a. It should be noted that two adjacent first segments 171a can mean that there are no other first segments 171a between these two first segments 171a.

[0101] See also Figure 12 Furthermore, two adjacent first line segments 171a in the first direction (e.g., parallel to the X-axis) are coupled by a second line segment 171b, and the second line segment 171b is disposed on a different layer than the first line segment 171a. Alternatively, the second line segment 171b is disposed on a different layer than the first portion 152a of one or more second data leads located between the two first line segments 171a. In this way, the first portion 152a of the second data lead extending along the second direction (e.g., parallel to the Y-axis) and the first signal line 171 extending along the first direction may not be in contact, and they can be disposed on the same layer without short-circuiting the portion 152a of the second data lead located in the display area and the first line segment 171a of the first signal line 171.

[0102] See Figure 11 and Figure 12In some possible implementations, a first portion 152a of a first line segment 171a (e.g., each first line segment 171a) and a second data lead (e.g., each second data lead) may be included in the second conductor pattern layer 170, while a second line segment 171b (e.g., each second line segment 171b) may be included in the third conductor pattern layer 180. It should be noted that the third conductor pattern layer 180 may be a conductor pattern layer. The third conductor pattern layer 180 may include multiple signal lines and may also include one or more connection patterns. For example, the third conductor pattern layer 180 may include multiple signal lines extending along a first direction (e.g., parallel to the X-axis direction), which are configured, for example, to transmit a first scan signal (i.e., a first scan signal). Figure 5 The first scan signal GA1) or the third scan signal (i.e. Figure 5 The third scan signal GA3 in the display panel. For example, the third conductor pattern layer 180, the second conductor pattern layer 170 and the first conductor pattern layer 160 can be arranged sequentially along the thickness direction of the display panel (e.g., parallel to the Z-axis direction).

[0103] See Figures 7-9 Given that the dimension of the display panel 10 along the first direction (e.g., parallel to the X-axis) is fixed, and the dimension r1 of the pixel driving circuit D along the first direction is fixed, the multiple pixel driving circuits D can be arranged in various ways in the display panel. In different arrangements, the number of data leads 150 between two adjacent circuit groups DG can be different. The following will describe in detail the arrangement of the multiple pixel driving circuits D and the corresponding number of data leads 150.

[0104] Figure 13 for Figure 7 A magnified view of a portion of area U3 in the display panel. Figure 14 for Figure 8 A magnified view of area U4 in the display panel.

[0105] First, it's important to note that in the manufacturing process of display panels, such as the fabrication of data leads, the distance between two patterns on the same layer must be considered. The minimum distance between two patterns on the same layer should be greater than or equal to a critical value. Too close a distance between two patterns on the same layer can lead to signal crosstalk. Furthermore, considering the precision of the manufacturing process, a certain distance is also required between two patterns on the same layer; otherwise, due to manufacturing errors, short circuits between the two patterns may occur.

[0106] It should be noted that in this document, "multiple patterns set on the same layer" means that multiple patterns belong to the same pattern layer, that is, multiple patterns are formed through the same patterning process. Here, the patterning process refers to a process capable of forming multiple patterns simultaneously. For example, the patterning process can be vapor deposition or printing. Exemplarily, the patterning process can include: first forming a thin film using a film deposition process, and then patterning the thin film to form a pattern layer containing multiple patterns. The patterning process can include processes such as coating photoresist, exposure, development, and etching. It should be noted that the multiple patterns can be at least partially connected or spaced apart from each other. Furthermore, the multiple patterns may have different thicknesses (e.g., the dimension of the pattern along the thickness direction of the display panel).

[0107] See Figure 13 For ease of explanation, in this document, the minimum allowable distance between two adjacent patterns arranged on the same layer is denoted as W1, meaning the distance between two adjacent patterns arranged on the same layer should be greater than or equal to W1. It should be noted that adjacent patterns can mean that there are no other patterns between these two patterns in the same pattern layer. The width of the first data lead 151 (e.g., the dimension of the first data lead 151 along its width direction, where the width direction of the first portion 151a of the first data lead is perpendicular to its extension direction, and for example, parallel to the X-axis direction) is denoted as W2. The width of the first portion 152a of the second data lead (e.g., the dimension of the first portion 152a of the second data lead along its width direction, where the width direction of the second data lead 152 is perpendicular to its extension direction, and for example, parallel to the X-axis direction) can be the same as the width of the first portion 151a of the first data lead. The width of the first part 152a of the second data lead can also be denoted as W2.

[0108] In some embodiments, see Figure 7 and Figure 13 Referring to the above description, a circuit group DG (e.g., each circuit group DG) includes a circuit column 120. There is a certain space between two adjacent circuit groups DG, or in other words, there is a certain space between two adjacent circuit columns 120. At least one (e.g., one; or multiple) data lead 150 can be disposed in this space. It should be noted that two adjacent circuit columns can mean that there are no other circuit columns between these two circuit columns.

[0109] The minimum distance between two adjacent circuit columns 120 that allows the placement of a data lead is denoted as W3 (hereinafter referred to as the first distance). To place a data lead 150 between two adjacent circuit columns 120, W3 = W2 + 2W1 is required. It should be noted that the minimum distance between two adjacent circuit columns 120 that allows the placement of a data lead 150 can mean: in a conductor pattern layer containing at least one data lead 150 (e.g., a first conductor pattern layer containing one or more first data leads, or a second conductor pattern layer containing one or more second data leads), the minimum distance between two patterns corresponding to two adjacent circuit columns 120 and adjacent to the data lead 150. Here, a pattern corresponding to a circuit column 120 can mean: the pattern is part of one or more pixel driving circuits D in the circuit column 120, for example, the pattern is configured to couple multiple elements in a pixel driving circuit D in the circuit column. The correspondence between a pattern and a circuit array 120 can also mean that the pattern is coupled to one or more pixel driving circuits D in the circuit array 120. For example, the pattern is configured to write electrical signals to one or more pixel driving circuits D in the circuit array 120; for example, the pattern is a signal line, such as a first data line or a power supply voltage signal line. As another example, the pattern is configured to couple one or more pixel driving circuits D in the circuit array 120 to other components; for example, the pattern is configured to couple a pixel driving circuit D to a light-emitting device E.

[0110] In other embodiments, see Figure 8 , Figure 9 and Figure 14 A circuit group DG (e.g., each circuit group DG) includes multiple circuit columns 120. See, for example, [link to example]. Figure 8 and Figure 14 A circuit group DG comprises two circuit columns 120. See also, by example, […]. Figure 9 A circuit group DG includes four circuit columns 120.

[0111] Will Figure 8 and Figure 14 and Figure 7 and Figure 13In contrast, given a fixed dimension of the display panel along the first direction and a fixed dimension r1 of the pixel driving circuit D along the first direction, when a circuit group DG includes two circuit columns 120, the distance between two adjacent circuit groups DG is 2W3 (hereinafter referred to as the second distance). The second distance allows for the setting of M1 (M1≥2) data leads, but the actual number set is N1, where N1≤M1. The second distance can refer to the distance between two patterns corresponding to two adjacent circuit columns 120 and adjacent to N data leads 150 in a conductor pattern layer containing multiple data leads 150 (e.g., a first conductor pattern layer containing multiple first data leads arranged in the same layer, or a second conductor pattern layer containing multiple second data leads arranged in the same layer). Two adjacent circuit columns 120 refer to two circuit columns 120 belonging to the two adjacent circuit groups DG and being close to each other.

[0112] Referring to the above explanation, since one data lead can be placed in a space of size W3, two data leads arranged in the same layer can be placed in a space of size 2W3. For example, two first data leads 151 can be placed in the corresponding space of the first conductor pattern layer 160. Since W3 = W2 + 2W1, after placing two data leads arranged in the same layer in a space of size 2W3, the remaining space size can be 2W3 - (2W2 + 3W1) = 2(W2 + 2W1) - (2W2 + 3W1) = W1. One or more data leads can be placed in this space of size W1. For example, more first data leads can be placed in the corresponding space of the first conductor pattern layer. For another example, one or more second data leads can be placed in the corresponding space of the second conductor pattern layer. Based on the above, it can also be said that for the area corresponding to the four circuit columns, when a circuit group DG includes two circuit columns 120, more than four data leads can be placed in this area.

[0113] Similarly, Figure 9 and Figure 7 and Figure 13In contrast, given a fixed dimension of the display panel along the first direction and a fixed dimension r1 of the pixel driving circuit D along the first direction, when a circuit group DG includes four circuit columns 120, the distance between two adjacent circuit groups DG is 4W3 (hereinafter referred to as the third distance). The third distance allows for the setting of M2 (M2≥4) data leads. Of course, the actual number set is N2, where N2≤M2. The third distance can be similar to the second distance described above, and can be referred to the relevant explanation above, which will not be repeated here. Based on the above, 5 data leads arranged in the same layer can be set in a space of size 4W3. Since W3=W2+2W1, after setting 5 data leads arranged in the same layer in a space of size 4W3, the remaining space is 4W3-(5W2+6W1)=4(W2+2W1)-(5W2+6W1)=2W1-W2. One or more data leads can be set in the space of size 2W1-W2. For example, more first data leads can be set in the corresponding space of the first conductor pattern layer. Similarly, one or more second data leads can be set in the corresponding space of the second conductor pattern layer. In other words, for the area corresponding to the four circuit columns, in the case where a circuit group DG includes four circuit columns 120, more than five (e.g., six; or even seven) data leads 150 can be set in that area.

[0114] Understandably, when a circuit group DG includes more (e.g., more than or equal to 5) circuit columns 120, given that the size of the display panel along the first direction is fixed and the size of the pixel driving circuit along the first direction is fixed, more data leads can be provided between two adjacent circuit groups DG, that is, more data leads can be provided in the display panel.

[0115] See Figure 4 In some embodiments, along a first direction (e.g., parallel to the X-axis), the length q1 of the portion of the data lead 150 located in the display area AA first increases and then decreases. Specifically, the length q1 of the first portion of the data lead 150 (e.g., each data lead 150) located in the display area AA can be the dimension of the first portion along a second direction (e.g., parallel to the Y-axis). This results in a more uniform distribution of the multiple data leads 150, improving the structural stability of the display panel.

[0116] See Figure 3 ,as well as Figures 7-9In some embodiments, the display panel further includes multiple light-emitting devices E, one of which is coupled to a pixel driving circuit D. Multiple first data lines 141 include multiple different-color data lines. Alternatively, multiple of the multiple first data lines 141 may be different-color data lines. A different-color data line (e.g., each different-color data line) extends along a second direction (e.g., parallel to the Y direction) and is coupled to at least two pixel driving circuits D in a circuit array 120. Furthermore, a different-color data line (e.g., each different-color data line) is coupled to at least two light-emitting devices E with different emission colors. All data leads 150 coupled to the multiple (e.g., all) different-color data lines are disposed on the same layer. Exemplarily, all data leads 150 coupled to the multiple (e.g., all) different-color data lines are first data leads 151, all contained within the first conductor pattern layer 160.

[0117] When the same electrical signal is written to two data lines, and these two data lines are arranged on the same layer, the difference in electrical load on these two data lines (e.g., caused by parasitic capacitance in the pixel driving circuit) can be smaller, thus reducing the difference in electrical signals output by these two data lines to the pixel driving circuit D. Based on this, when multiple (e.g., all) data lines are arranged on the same layer, the display effect of the display panel can be improved. Furthermore, since the different-color data lines are coupled to at least two light-emitting devices E with different emission colors, the frequency of change of the electrical signals transmitted on the different-color data lines may be larger. Based on this, since all data lines 150 coupled to multiple (e.g., all) different-color data lines are arranged on the same layer, the display effect of the display panel can be further improved.

[0118] See Figure 3 In some embodiments, the display panel further includes at least one (e.g., one; or, multiple) second data line 142. A second data line 142 (e.g., each second data line 142) extends along a second direction (e.g., parallel to the Y-axis) from the display area AA to the non-display area SA and is coupled to at least one (e.g., one; or, multiple) pad P. For example, a second data line 142 extends along the second direction from the display area AA to the fan-out area FA, the bend area BA, and the bonding area PA, and is coupled to at least one pad P located in the bonding area PA. The second data line 142 can be coupled to at least one pad P without connecting lines and data leads; therefore, since the display includes at least one second data line 142, the structure of the display panel can be simpler, and the yield of the display panel can be improved.

[0119] See Figures 7-9In some embodiments, the display panel includes multiple data leads 150. The multiple data leads 150 form multiple lead groups LG distributed along a first direction (e.g., parallel to the X-axis direction), with each data lead 150 in a lead group LG (e.g., each lead group LG) disposed between two identical circuit groups DG. Alternatively, a lead group LG can be disposed between two adjacent circuit groups DG. In the display area, the distance q1 between any two adjacent lead groups LG is approximately the same. It should be noted that two adjacent lead groups LG can mean that there are no other lead groups LG between these two lead groups LG. Exemplarily, in the display area, the distance q1 between two adjacent lead groups LG can be the minimum distance between two data leads 150 belonging to these two lead groups LG and being close to each other. Since the distance q1 between any two adjacent lead groups LG in the display area is approximately the same, the number of circuit columns 120 in each circuit group DG of the display panel can be the same.

[0120] Since the distance q1 between any two adjacent lead groups LG is approximately the same in the multiple lead groups LG, the structure of the display panel can be relatively uniform. For example, the dimensions of each of the multiple circuit groups DG along a first direction (e.g., parallel to the X-axis) can be approximately the same, thus ensuring a more uniform structure for the display panel and improving its structural stability.

[0121] Figure 15 This is a partial enlarged view of the display area of ​​a display panel according to some embodiments, showing the relative positions of the connecting lines, data leads, and first signal lines. It should be noted that, for the sake of simplicity, the accompanying drawings... Figure 15 The diagram only shows multiple connection lines, multiple data leads, and multiple first signal lines, while other structures are omitted.

[0122] See Figure 4 and Figure 15 In some embodiments, the display panel further includes at least one (e.g., one; or multiple) connecting line 172. A connecting line 172 (e.g., each connecting line 172) is disposed in the display area AA. A connecting line 172 (e.g., each connecting line 172) extends along a first direction (e.g., parallel to the X-axis direction). Through the connecting line 172, the first data line 141 is coupled to the data lead 150. Exemplarily, a connecting line 172 may be coupled to the first data line 141, and the connecting line 172 may also be coupled to the first data lead 151 or the second data lead 152, so that through the connecting line 172, a first data lead 141 can be coupled to a first data lead 151 or a second data lead 152.

[0123] See also Figure 4 and Figure 15 In some embodiments, the display panel further includes at least one connecting line 172, and the display panel also includes multiple signal lines disposed in the display area AA. One signal line (e.g., each signal line) extends along a first direction (e.g., parallel to the X-axis direction). Exemplarily, one signal line (e.g., each signal line) is a first signal line 171. Of course, the signal line can also be other types of signal lines, and the embodiments of this disclosure are not limited thereto, as long as the signal line is disposed in the display area AA and extends along the first direction. Hereinafter, the example of the first signal line will be used for illustration.

[0124] Furthermore, multiple signal lines (e.g., multiple first signal lines 171) form multiple signal line groups SG distributed along a second direction (e.g., parallel to the Y-axis direction), and each signal line group SG includes at least one (e.g., one; or multiple) signal line. A connecting line 172 (e.g., each connecting line 172) is disposed on the same layer as at least a portion (e.g., part; or or all) of the signal line, and is disposed between two adjacent signal line groups SG. It should be noted that the adjacent positions of two signal line groups SG can mean that there are no other signal line groups SG between these two signal line groups SG. For example, when the signal line is a first signal line 171, a connecting line 172 is disposed on the same layer as the first segment 171a of the first signal line. For example, both the connecting line 172 and the first segment 171a of the first signal line are included in the second conductor pattern layer 170.

[0125] Since a connecting line 172 extends along a first direction and a signal line also extends along the first direction, the connecting line 172 can be disposed on the same layer as at least a portion of a signal line and disposed between two adjacent signal line groups SG. Thus, compared to one or more connecting lines 172 being disposed separately on other pattern layers (e.g., pattern layers in the display panel other than multiple conductor pattern layers used to form multiple pixel driving circuits and conductor pattern layers containing one or more signal lines), the display panel can include fewer pattern layers, resulting in a smaller display panel thickness, which is beneficial for the thinning of the display panel and the display device. Furthermore, similar to data leads, by reducing the dimension of at least a portion (e.g., part; or even all) of the pixel driving circuit along the second direction (e.g., parallel to the Y-axis direction), a certain space can be provided between two adjacent signal line groups SG, which can be used to accommodate one or more connecting lines 172. In this way, multiple connecting lines 172 can be disposed in the display area AA without increasing the display panel size or reducing the number of pixel driving circuits D.

[0126] See also Figure 15In some embodiments, a signal line group SG (e.g., each signal line group SG) includes multiple signal lines; for example, a signal line group SG includes two signal lines. Alternatively, in other embodiments, a signal line group SG (e.g., each signal line group SG) includes one signal line. Similar to data leads, when a signal line group SG (e.g., each signal line group SG) includes multiple signal lines, more connecting lines can be provided in the display panel.

[0127] See also Figure 15 In some embodiments, the distance q2 between any two adjacent signal line groups SG is approximately the same. For example, the distance q2 between two adjacent signal line groups SG can be the minimum distance between two adjacent signal lines belonging to those two signal line groups SG. Since the distance q2 between any two adjacent signal line groups SG is approximately the same, the structure of the display panel can be more uniform, thus improving the structural stability of the display panel.

[0128] Some embodiments of this disclosure also provide a method for manufacturing a display panel. This method can be used to manufacture the display panel provided in any of the above embodiments. The method for manufacturing the display panel includes: forming a plurality of pixel driving circuits, a plurality of pads, a plurality of first data lines, and at least one data lead on a substrate.

[0129] The circuits consist of multiple pixel driving circuits forming multiple circuit columns distributed along a first direction. Each circuit column includes at least two pixel driving circuits distributed along a second direction, which intersect. Multiple pads are located on one side of the multiple pixel driving circuits along the second direction. A first data line extends along the second direction and is coupled to at least two pixel driving circuits in the circuit column. Data leads extend along the second direction and are coupled to the first data line and at least one pad. The multiple circuit columns form multiple circuit groups distributed along the first direction. Each circuit group includes at least one circuit column, and data leads are positioned between two adjacent circuit groups. For a detailed description of the above structure, please refer to the relevant description above; further details will not be repeated here.

[0130] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel having a display area and a non-display area, the display panel comprising: Multiple pixel driving circuits are disposed in the display area, the multiple pixel driving circuits forming multiple circuit columns distributed along a first direction, the circuit columns including at least two pixel driving circuits distributed along a second direction, the second direction intersecting the first direction; Multiple pads are disposed in the non-display area and located on one side of the display area along the second direction; Multiple first data lines are disposed in the display area, the first data lines extend along the second direction and are coupled to at least two pixel driving circuits in the circuit column; At least one data lead is coupled to the first data line, the data lead extends from the display area to the non-display area, and is coupled to at least one pad; The at least one data lead includes at least one second data lead, wherein the portion of the second data lead located in the display area is disposed on a different layer from the first data lead; Multiple first signal lines are disposed in the display area, the first signal lines extend along the first direction, and the first signal lines include multiple first line segments and at least one second line segment; The portion of the second data lead located in the display area is disposed on the same layer as the first line segment, and is disposed between two adjacent first line segments; Two first line segments that are adjacent in the first direction are coupled by the second line segment, and the second line segment and the first line segment are disposed in different layers; The plurality of circuit columns form a plurality of circuit groups distributed along the first direction, each circuit group including at least one circuit column, and the data leads are disposed between two adjacent circuit groups.

2. The display panel according to claim 1, wherein, The at least one data lead includes at least one first data lead, wherein the portion of the first data lead located in the display area is disposed on the same layer as the first data line.

3. The display panel according to claim 1, wherein, The at least one data lead can be multiple data leads, and the multiple data leads further include at least one first data lead, wherein the portion of the first data lead located in the display area is disposed on the same layer as the first data line; In the thickness direction of the display panel, the first data lead and the second data lead do not overlap.

4. The display panel according to claim 1, further comprising: At least one connecting line is disposed in the display area, and the connecting line extends along the first direction; The first data line is coupled to the data lead via the connecting line, and the connecting line and the second data lead are located on the same layer in the display area.

5. The display panel according to claim 1, further comprising: At least one connecting line is disposed in the display area, and the connecting line extends along the first direction; The first data line is coupled to the data lead via the connecting line.

6. The display panel according to claim 5, further comprising: Multiple signal lines are disposed in the display area, and the signal lines extend along the first direction; The multiple signal lines form multiple signal line groups distributed along the second direction, and each signal line group includes at least one signal line. The connecting line is disposed on the same layer as at least a portion of the signal line, and is disposed between two adjacent signal line groups.

7. The display panel according to claim 6, wherein, In the plurality of signal line groups, the distance between any two adjacent signal line groups is approximately the same.

8. The display panel according to claim 1, further comprising: Multiple light-emitting devices, wherein the light-emitting devices are coupled to the pixel driving circuit; The plurality of first data lines include a plurality of different colored data lines, and the different colored data lines are coupled to at least two light-emitting devices with different light-emitting colors; All data leads coupled to the multiple different colored data lines are partially located on the same layer as the display area.

9. The display panel according to claim 1, further comprising: At least one second data line extends from the display area to the non-display area along the second direction and is coupled to at least one pad.

10. The display panel according to claim 1, wherein, The at least one data lead is multiple data leads, which form multiple lead groups distributed along the first direction, and each data lead in the lead group is disposed between the same two circuit groups. In the display area, among the plurality of lead groups, the distance between any two adjacent lead groups is approximately the same.

11. A display device comprising the display panel as described in any one of claims 1 to 10.

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