Self-refresh of memory unit

Abstract

This application relates to self-refresh of a memory cell. A controller coupled with a memory cell can be configured to apply a first voltage to a control gate of a first transistor, where the first voltage activates the first transistor to selectively couple terminals of the first transistor to each other based on a charge stored on a gap gate. The controller can be configured to apply a current to a bit line, where a second voltage of the bit line is based on the current and the charge stored on the gap gate. The controller can be configured to apply a third voltage to a gate of a second transistor to couple the bit line with the gap gate of the first transistor based on applying the first voltage to the control gate of the first transistor and applying the current to the bit line.

Description

[0001] Cross-reference

[0002] This patent application is a national stage application of International Patent Application No. PCT / US2022 / 072326, entitled “SELF-REFRESH OF MEMORY CELL,” to CARMAN et al., filed May 13, 2022, which claims priority to U.S. Patent Application No. 17 / 338,453, entitled “SELF-REFRESH OF MEMORY CELL,” to CARMAN, filed June 3, 2021, each of which is assigned to its assignee and the entire contents of each of which are hereby expressly incorporated by reference herein. TECHNICAL FIELD

[0003] The technical field relates to self-refresh of memory cells. BACKGROUND

[0004] Memory devices are widely used in electronic systems to store information. Information is stored by programming memory cells within the memory device to various states. For example, binary memory cells can be programmed to one of two supported states, typically represented by a logic 1 or a logic 0. In some examples, a single memory cell can support more than two states, any of which can be stored. To access stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write or program a state in the memory device.

[0005] There are a variety of types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self- selecting memory, chalcogenide memory technology, and others. Memory cells can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can maintain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices (e.g., DRAM) can lose their stored state when disconnected from an external power source. SUMMARY

[0006] A memory device is described. The memory device can include a memory cell comprising a first transistor comprising a control gate and an interstitial gate, wherein a first terminal of the first transistor is coupled with a bit line, and a second transistor, wherein a first terminal of the second transistor is coupled with the bit line and a second terminal of the second transistor is coupled with the interstitial gate of the first transistor, and a controller coupled with the memory cell and configured to apply a first voltage to the control gate of the first transistor, wherein the first voltage activates the first transistor to selectively couple the first terminal of the first transistor with a second terminal of the first transistor based at least in part on a charge stored on the interstitial gate, apply a current to the bit line, wherein a second voltage of the bit line is based at least in part on the current applied to the bit line and the charge stored on the interstitial gate of the first transistor, and apply a third voltage to a gate of the second transistor to couple the bit line with the interstitial gate of the first transistor based at least in part on applying the first voltage to the control gate of the first transistor and applying the current to the bit line.

[0007] An apparatus is described. The apparatus can include a memory array comprising a first word line coupled with a first transistor of a first memory cell and a second transistor of a second memory cell, a second word line coupled with a third transistor of the first memory cell and a fourth transistor of the second memory cell, a first bit line coupled with the first memory cell, and a second bit line coupled with the second memory cell, and a controller coupled with the memory array and configured to perform an access operation on the first memory cell, wherein performing the access operation comprises activating the first transistor via the first word line, apply a current to the second bit line based at least in part on performing the access operation on the first memory cell, wherein a voltage of the second bit line is based at least in part on the current and a charge stored at an interstitial gate of the second transistor, and activate the third transistor and the fourth transistor via the second word line, wherein activating the fourth transistor recovers the charge stored at the interstitial gate of the second transistor.

[0008] A method is described. The method can include applying a first voltage to a control gate of a first transistor of a memory cell, wherein the first voltage activates the first transistor to selectively couple a first terminal of the first transistor with a second terminal of the first transistor based at least in part on a charge stored at a gap fill gate of the first transistor, and wherein the first terminal of the first transistor is coupled with a bit line; applying a current to the bit line, wherein a second voltage of the bit line is based at least in part on the applying the current to the bit line and the charge stored on the gap fill gate of the first transistor; and applying a third voltage to a gate of a second transistor of the memory cell to couple the bit line with the gap fill gate of the first transistor based at least in part on the applying the first voltage to the control gate of the first transistor and the applying the current to the bit line, wherein a first terminal of the second transistor is coupled with the bit line and a second terminal of the second transistor is coupled with the gap fill gate of the first transistor.

[0009] Another method is described. The method can include performing an access operation on a first memory cell of a memory array, wherein performing the access operation comprises activating a first transistor of the first memory cell via a first word line coupled with the first transistor, wherein the first memory cell is coupled with a first bit line; applying a current to a second bit line coupled with a second memory cell based at least in part on performing the access operation on the first memory cell, wherein a voltage of the second bit line is based at least in part on the current and a charge stored at a gap fill gate of a second transistor of the second memory cell; activating a third transistor of the first memory cell and a fourth transistor of the second memory cell via a second word line coupled with the third transistor and the fourth transistor; and restoring the charge stored at the gap fill gate of the second transistor based at least in part on activating the fourth transistor.

[0010] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium can include instructions that, when executed by a processor of an electronic device, cause the electronic device to: apply a first voltage to a control gate of a first transistor of a memory cell, wherein the first voltage activates the first transistor to selectively couple a first terminal of the first transistor with a second terminal of the first transistor based at least in part on a charge stored at a gap fill gate of the first transistor, and wherein the first terminal of the first transistor is coupled with a bit line; apply a current to the bit line, wherein a second voltage of the bit line is based at least in part on the application of the current to the bit line and the charge stored on the gap fill gate of the first transistor; and apply a third voltage to a gate of a second transistor of the memory cell to couple the bit line with the gap fill gate of the first transistor based at least in part on the application of the first voltage to the control gate of the first transistor and the application of the current to the bit line, wherein a first terminal of the second transistor is coupled with the bit line and a second terminal of the second transistor is coupled with the gap fill gate of the first transistor. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 An example of a system that supports self-refresh of a memory cell is described in accordance with examples as disclosed herein.

[0012] Figure 2 An example of a memory die that supports self-refresh of a memory cell is described in accordance with examples as disclosed herein.

[0013] Figure 3 An example of a circuit that supports self-refresh of a memory cell is described in accordance with examples as disclosed herein.

[0014] Figure 4 An example of a timing diagram that supports self-refresh of a memory cell is described in accordance with examples as disclosed herein.

[0015] Figure 5 An example of a circuit that supports self-refresh of a memory cell is described in accordance with examples as disclosed herein.

[0016] Figure 6 An example of a timing diagram that supports self-refresh of a memory cell is described in accordance with examples as disclosed herein.

[0017] Figure 7 A block diagram of a memory device that supports self-refresh of a memory cell is shown in accordance with examples as disclosed herein.

[0018] Figure 8 and 9A flow diagram illustrating one or more methods of supporting self-refresh of memory cells in accordance with examples as disclosed herein is shown. DETAILED DESCRIPTION

[0019] A memory array of a memory device can include a set of memory cells. Each of the set of memory cells can include a first transistor (e.g., a p-type transistor, such as a p-channel metal-oxide-semiconductor (PMOS)) coupled with a first word line and a second transistor (e.g., an n-type transistor, such as an n-channel MOS (NMOS)) coupled with a second word line. The second transistor of each memory cell can be configured to selectively couple a respective bit line with an interstitial gate (e.g., a floating gate) of the first transistor and the first transistor can be configured to selectively couple the bit line with a ground reference of the memory array. The interstitial gate can be configured to store a charge representative of a state of the memory cell.

[0020] In some examples, a memory device can access a first memory cell of a set of memory cells. Accessing the first memory cell can include selecting a first word line, a second word line, and a bit line associated with the first memory cell. After accessing the first memory cell, the memory device can restore a charge stored at the first memory cell. To access and restore charges stored at each memory cell coupled with the first word line and the second word line, the memory device can have a sense amplifier associated with each bit line. With no sense amplifier on a bit line to sense a charge on an unselected (e.g., for a given access operation) memory cell, selecting the first word line and the second word line can overwrite the charge stored at the unselected memory cell. Thus, to support access operations to a subset of memory cells coupled with the first word line and the second word line, the memory device can have a sense amplifier per bit line and a bit line driver. However, it can be desirable to support access operations to a subset of memory cells coupled with the first word line and the second word line without the area consumed by the sense amplifier per bit line and the bit line driver.

[0021] The techniques described herein can enable memory cells that do not have their bit lines selected for an access procedure (e.g., a read or write) to recover charge according to a procedure that can be referred to as self-refresh (e.g., without a dedicated sense amplifier or bit line driver for the bit line). For example, a memory device can apply a current to a bit line of one of the other memory cells and can activate a respective first transistor to pull down a voltage of the bit line (e.g., if a charge at a gap fill gate of the respective first transistor activates the first transistor or maintains the first transistor in an on state) or can enable a current to increase a voltage on the bit line (e.g., if a charge at a gap fill gate of the respective first transistor deactivates the first transistor or maintains the first transistor in an off state). Once a voltage is generated on the bit line, a second transistor can be activated to recover sensed charge on the gap fill gate. In some examples, one or more aspects of the techniques described herein can additionally or alternatively be applied in examples where a memory cell’s contents are not read.

[0022] Features of the disclosure are first described in the context of a system and die as described with reference to Figure 1 and 2 Features of the disclosure are described in the context of a circuit and timing diagram as described with reference to Figures 3 to 6 Features of the disclosure are further illustrated and described with reference to device diagrams and flowcharts related to self-refresh of memory cells, as described with reference to Figures 7 to 9 Features of the disclosure are further illustrated and described with reference to device diagrams and flowcharts related to self-refresh of memory cells, as described with reference to

[0023] Figure 1 An example of a system 100 that supports self-refresh of memory cells according to examples as disclosed herein is illustrated. The system 100 can include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 and the memory device 110. The system 100 can include one or more memory devices 110, but aspects of the one or more memory devices 110 can be described in the context of a single memory device (e.g., the memory device 110).

[0024] The system 100 can include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, the system 100 can illustrate aspects of a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an internet-connected device, a vehicle controller, or the like. The memory device 110 can be a component of the system that is operable to store data for one or more other components of the system 100.

[0025] At least portions of system 100 can be an instance of a host device 105. Host device 105 can be an instance of a processor or other circuitry within a device that uses memory to perform processes, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, a system on a chip (SoC), or some other fixed or portable electronic device, among other examples. In some examples, host device 105 can refer to hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 120. In some examples, external memory controller 120 can be referred to as a host or host device 105.

[0026] Memory device 110 can be a standalone device or component that is operable to provide physical memory addresses / space that can be used or referenced by system 100. In some examples, memory device 110 can be configured to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 can be operable to support one or more of: a modulation scheme used to modulate signals; various pin configurations used to transfer signals; various form factors of physical packaging of host device 105 and memory device 110; clock signaling and synchronization between host device 105 and memory device 110; timing conventions; or other factors.

[0027] Memory device 110 can be operable to store data for components of host device 105. In some examples, memory device 110 can act as an auxiliary or dependent device of host device 105 (e.g., responding to and executing commands provided by host device 105 through external memory controller 120). Such commands can include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0028] Host device 105 can include one or more of external memory controller 120, processor 125, basic input / output system (BIOS) component 130, or other components (e.g., one or more peripheral components or one or more input / output controllers). Components of host device 105 can be coupled to each other using bus 135.

[0029] The processor 125 can be operable to provide control or other functionality for at least portions of the system 100 or at least portions of the host device 105. The processor 125 can be a general -purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field -programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, the processor 125 can be a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC, among other examples. In some examples, the external memory controller 120 can be implemented by or be part of the processor 125.

[0030] The BIOS component 130 can be a software component that includes a BIOS operating as firmware, which can initialize and run various hardware components of the system 100 or the host device 105. The BIOS component 130 can also manage data flow between the processor 125 and the various components of the system 100 or the host device 105. The BIOS component 130 can include a program or software stored in one or more of read-only memory (ROM), flash memory, or other nonvolatile memory.

[0031] In some examples, the system 100 or the host device 105 can include various peripheral components. The peripheral components can be any input or output device, or an interface for such devices, which can be integrated to or with the system 100 or the host device 105. Examples can include one or more of a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a universal serial bus (USB) controller, a serial or parallel port, or a peripheral card slot (such as a peripheral component interconnect (PCI) or a dedicated graphics port). The peripheral components can be other components understood by one of ordinary skill in the art to be interface devices.

[0032] In some examples, the system 100 or the host device 105 can include an I / O controller. The I / O controller can manage data communication between the processor 125 and peripheral components, input devices, or output devices. The I / O controller can manage interface devices that are not integrated to or with the system 100 or the host device 105. In some examples, the I / O controller can represent a physical connection or port to an external peripheral component.

[0033] In some examples, system 100 or host device 105 can include an input component, an output component, or both. An input component can represent a device or signal external to system 100 that provides information, signals, or data to system 100 or its components. In some examples, an input component can include a user interface or an interface to or between other devices. In some examples, an input component can be an interface device that interfaces with system 100 via one or more peripheral components or can be managed by an I / O controller. An output component can represent a device or signal external to system 100 that is operable to receive output from system 100 or any of its components. Examples of output components can include a display, an audio speaker, a printing device, another processor on a printed circuit board, and other output components. In some examples, an output can be an interface device that interfaces with system 100 via one or more peripheral components or can be managed by an I / O controller.

[0034] Memory device 110 can include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) can include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 can be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more segments), where each memory cell is operable to store at least one data bit. A memory device 110 that includes two or more memory dies 160 can be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package.

[0035] Memory die 160 can be an example of one two-dimensional (2D) array of memory cells or can be an example of one three-dimensional (3D) array of memory cells. A 2D memory die 160 can include a single memory array 170. A 3D memory die 160 can include two or more memory arrays 170 that can be stacked on top of one another or positioned adjacent to one another (e.g., relative to a substrate). In some examples, a memory array 170 in a 3D memory die 160 can be referred to as a tier, a layer, a level, or a die. A 3D memory die 160 can include any number of stacked memory arrays 170 (e.g., two high, three high, four high, five high, six high, seven high, eight high). In some 3D memory dies 160, different tiers can share at least one common access line such that some tiers can share one or more of a word line, a digit line, or a plate line.

[0036] The device memory controller 155 can include circuitry, logic, or components operable to control operations of the memory device 110. The device memory controller 155 can include hardware, firmware, or instructions that enable the memory device 110 to perform various operations and can be operable to receive, transmit, or execute commands, data, or control information related to components of the memory device 110. The device memory controller 155 can be operable to communicate with one or more of the external memory controller 120, the one or more memory dies 160, or the processor 125. In some examples, the device memory controller 155 can control operations of the memory device 110 described herein in connection with the local memory controller 165 of the memory die 160.

[0037] In some examples, the memory device 110 can receive data or commands, or both, from the host device 105. For example, the memory device 110 can receive a write command instructing the memory device 110 to store data for the host device 105 or a read command instructing the memory device 110 to provide data stored in the memory die 160 to the host device 105.

[0038] The local memory controller 165 (e.g., local to the memory die 160) can include circuitry, logic, or components operable to control operations of the memory die 160. In some examples, the local memory controller 165 can be operable to communicate (e.g., receive or transmit data or commands, or both) with the device memory controller 155. In some examples, the memory device 110 can not include the device memory controller 155 and the local memory controller 165, or the external memory controller 120 can perform various functions described herein. As such, the local memory controller 165 can be operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or a combination thereof. Examples of components that can be included in the device memory controller 155 or the local memory controller 165, or both, can include receivers for receiving signals (e.g., from the external memory controller 120), transmitters for transmitting signals (e.g., to the external memory controller 120), decoders for decoding or demodulating received signals, encoders for encoding or modulating signals to be transmitted, or various other circuitry or controllers operable to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

[0039] The external memory controller 120 can be operable to enable transfer of one or more of information, data, or commands between components of the system 100 or host device 105 (e.g., the processor 125) and the memory device 110. The external memory controller 120 can translate or interpret communications exchanged between components of the host device 105 and the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or host device 105, or their functions described herein, can be implemented by the processor 125. For example, the external memory controller 120 can be hardware, firmware, or software, or some combination thereof, implemented by the processor 125 or other components of the system 100 or host device 105. Although the external memory controller 120 is depicted as being external to the memory device 110, in some examples, the external memory controller 120 or its functions described herein can be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165), or vice versa.

[0040] Components of the host device 105 can exchange information with the memory device 110 using one or more channels 115. The channels 115 can be operable to support communications between the external memory controller 120 and the memory device 110. Each channel 115 can be an example of a transmission medium that carries information between the host device 105 and the memory device. Each channel 115 can include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of the system 100. A signal path can be an example of an electrically conductive path that is operable to carry a signal. For example, a channel 115 can include a first terminal that includes one or more pins or pads at the host device 105 and one or more pins or pads at the memory device 110. A pin can be an example of an electrically conductive input or output point of a device of the system 100, and a pin can be operable to act as part of a channel.

[0041] The channels 115 (and associated signal paths and terminals) can be dedicated to transferring one or more types of information. For example, the channels 115 can include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some examples, signaling can be transferred via the channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., a signal level) of a signal can be registered for each clock cycle (e.g., on a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal can be registered for each clock cycle (e.g., on both a rising edge and a falling edge of a clock signal).

[0042] In some examples, the CA channel 186 can be operable to communicate commands between the host device 105 and the memory device 110, including control information (e.g., address information) associated with the commands. For example, a command carried by the CA channel 186 can include a read command with an address of desired data. In some examples, the CA channel 186 can include any number of signal paths (e.g., eight or nine signal paths) to decode one or more of the address or command data.

[0043] In some examples, the clock signal channel 188 can be operable to communicate one or more clock signals between the host device 105 and the memory device 110. Each clock signal can be operable to oscillate between a high state and a low state, and can support coordination (e.g., real-time) between actions of the host device 105 and the memory device 110. In some examples, the clock signal can be single-ended. In some examples, the clock signal can provide a timing reference for command and addressing operations of the memory device 110, or other system-wide operations of the memory device 110. Thus, the clock signal can be referred to as a control clock signal, a command clock signal, or a system clock signal. The system clock signal can be generated by a system clock that can include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors).

[0044] In some examples, the data channel 190 can be operable to communicate one or more of data or control information between the host device 105 and the memory device 110. For example, the data channel 190 can communicate information to be written to the memory device 110 (e.g., bidirectional) or information read from the memory device 110.

[0045] The channel 115 can include any number of signal paths, including a single signal path. In some examples, the channel 115 can include multiple individual signal paths. For example, the channel can be x4 (e.g., including four signal paths), x8 (e.g., including eight signal paths), x16 (including sixteen signal paths), etc.

[0046] In some examples, one or more other channels 192 can include one or more error detection code (EDC) channels. The EDC channels can be operable to communicate error detection signals, such as a sum check code, to improve system reliability. The EDC channels can include any number of signal paths.

[0047] The signals communicated via the channel 115 can be modulated using one or more different modulation schemes. In some examples, the signals communicated between the host device 105 and the memory device 110 can be modulated using a binary symbol (or binary level) modulation scheme. A binary symbol modulation scheme can be an example of an M-ary modulation scheme, where M equals 2. Each symbol of a binary symbol modulation scheme can be operable to represent one digital data bit (e.g., a symbol can represent a logic 1 or a logic 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return-to-zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and / or others.

[0048] In some examples, the signals communicated between the host device 105 and the memory device 110 can be modulated using a multi-symbol (or multi-level) modulation scheme. A multi-symbol modulation scheme can be an example of an M-ary modulation scheme, where M is greater than or equal to 3. Each symbol of a multi-symbol modulation scheme can be operable to represent more than one digital data bit (e.g., a symbol can represent a logic 00, a logic 01, a logic 10, or a logic 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM3, PAM4, PAM8, etc., quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and / or others. A multi-symbol signal (e.g., a PAM3 signal or a PAM4 signal) can be a signal modulated using a modulation scheme that includes at least three levels to encode more than one information bit. Multi-symbol modulation schemes and symbols can alternatively be referred to as non-binary, multi-bit, or higher order modulation schemes and symbols.

[0049] The memory array 170 of the memory device 110 can include a set of memory cells. Each of the set of memory cells can include a first transistor (e.g., a p-type transistor, such as a p-channel metal-oxide-semiconductor (PMOS)) coupled with a first word line and a second transistor (e.g., an n-type transistor, such as an n-channel MOS (NMOS)) coupled with a second word line. The second transistor of each memory cell can be configured to selectively couple a respective bit line with an interstitial gate (e.g., a floating gate) of the first transistor and the first transistor can be configured to selectively couple the bit line with a ground reference of the memory array. The interstitial gate can be configured to store a charge representative of a state of the memory cell.

[0050] In some examples, memory device 110 can access a first memory cell of a group of memory cells. Accessing the first memory cell can include selecting a first word line, a second word line, and a bit line associated with the first memory cell. After accessing the first memory cell, memory device 110 can restore a charge stored at the first memory cell. To access and restore a charge stored at each memory cell coupled with the first word line and the second word line, memory device 110 can have a sense amplifier associated with each bit line. With no sense amplifier on a bit line to sense a charge on an unselected (e.g., for a given access operation) memory cell, selecting the first word line and the second word line can overwrite a charge stored at the unselected memory cell. Thus, to support access operations to a subset of memory cells coupled with the first word line and the second word line, memory device 110 can have a sense amplifier per bit line and a bit line driver. However, it can be desirable to support access operations to a subset of memory cells coupled with the first word line and the second word line without the area consumed by a sense amplifier per bit line and a bit line driver.

[0051] The techniques described herein can enable a memory cell that has its bit line unselected for an access procedure (e.g., a read or a write) to restore a charge according to a procedure that can be referred to as self-refresh (e.g., without a dedicated sense amplifier or bit line driver for the bit line). For example, memory device 110 can apply a current to a bit line of one of the other memory cells and can activate a respective first transistor to pull down a voltage of the bit line (e.g., if a charge at an interstitial gate of the respective first transistor activates the first transistor or maintains the first transistor in an on state) or can enable a current to increase a voltage on the bit line (e.g., if a charge at an interstitial gate of the respective first transistor deactivates the first transistor or maintains the first transistor in an off state). Once a voltage is generated on the bit line, a second transistor can be activated to restore a sensed charge on the interstitial gate. In some examples, one or more aspects of the techniques described herein can additionally or alternatively be applied in examples where a memory cell’s contents are not read.

[0052] Figure 2 An example of a memory die 200 is described in accordance with examples as disclosed herein. Memory die 200 can be a reference to memory die 110 of FIG. 1. Figure 1An example of a memory die 160 is described. In some examples, the memory die 200 can be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory die 200 can include one or more memory cells 205, which can each be programmed to store different logical states (e.g., a programmed state of a set of two or more possible states). For example, the memory cells 205 can be operable to store one bit of information (e.g., a logical 0 or a logical 1) at a time. In some examples, the memory cells 205 (e.g., multi-level memory cells) can be operable to store more than one bit of information (e.g., logical 00, logical 01, logical 10, or logical 11) at a time.

[0053] The memory die 200 can include one or more access lines (e.g., one or more word lines 210-a and 210-b and one or more digit lines 215) arranged in a pattern (e.g., a grid-like pattern). The access lines can be conductive lines coupled with the memory cells 205 and can be used to perform access operations on the memory cells 205. In some examples, the word lines 210-a and 210-b can be referred to as row lines. In some examples, the digit lines 215 can be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, or bit lines, or the like, can be interchangeable without loss of understanding or operation. The memory cells 205 can be located at intersections of the word lines 210-a and 210-b and the digit lines 215.

[0054] The memory cells 205 can store electrical charges representing programmable states in an interstitial gate (e.g., a floating gate) of the first transistor 270. The memory cells 205 can include the first transistor 270 and the second transistor 265. In some examples, the first transistor 270 and the second transistor 265 can be of different or complementary types (e.g., the first transistor 270 can be a PMOS transistor and the second transistor 265 can be an NMOS transistor, or vice versa). A first terminal (e.g., a source or a drain) of the first transistor 270 can be coupled with a ground reference of the memory die 200 and a second terminal (e.g., a source or a drain) of the first transistor 270 can be coupled with the digit line 215. A first terminal (e.g., a source or a drain) of the second transistor 265 can be coupled with the interstitial gate (e.g., the floating gate) of the first transistor 270 and a second terminal (e.g., a source or a drain) of the second transistor 265 can be coupled with the digit line 215. Further, a third terminal (e.g., a gate) of the first transistor 270 can be coupled with the word line 210-b and a third terminal (e.g., a gate) of the second transistor 265 can be coupled with the word line 210-a.

[0055] Operations such as reads and writes can be performed on memory cells 205 by activating or selecting an access line, such as one or more of word lines 210-a, 210-b, or digit lines 215. A single memory cell 205 can be accessed at the intersection of word lines 210-a, 210-b, and digit lines 215 by biasing them, such as applying a voltage to word lines 210-a, 210-b, or digit lines 215. The intersection of word lines 210-a, 210-b, and digit lines 215 in two-dimensional or three-dimensional configurations can be referred to as an address of a memory cell 205.

[0056] Accessing memory cells 205 can be controlled by row decoders 220-a, 220-b, or column decoder 225. For example, row decoder 220-a can receive a row address from local memory controller 260 and can activate word lines 210-a based on the received row address. Also, row decoder 220-b can receive a row address from local memory controller 260 and can activate word lines 210-b based on the received row address. Column decoder 225 can receive a column address from local memory controller 260 and can activate digit lines 215 based on the received column address.

[0057] Selecting or deselecting a memory cell 205 can be accomplished by activating or deactivating first transistor 270 and / or second transistor 265. For example, digit line 215 can be isolated from a ground reference when first transistor 270 is deactivated and can be coupled to a ground reference when first transistor 270 is activated. In some examples, whether first transistor 270 is activated or deactivated can be based on a state stored by the interstitial gate of first transistor 270. For example, if the control gate is in a first state (e.g., a high state, a state associated with a higher voltage), first transistor 270 can remain deactivated (e.g., isolate the ground reference from digit line 215) regardless of the charge stored at the interstitial gate of first transistor 270. However, if the control gate is in a lower state (e.g., a lower state, a state associated with a lower voltage), first transistor 270 can be activated depending on the charge stored at the interstitial gate. For example, if the interstitial gate stores a first amount of charge associated with a first logic state, first transistor 270 can be activated when the control gate is in the low state. However, if the interstitial gate of first transistor 270 stores a second amount of charge associated with a second logic state, first transistor can be deactivated when the control gate is in the low state. Also, in some examples, the interstitial gate of first transistor 270 can be isolated from digit line 215 when second transistor 265 is deactivated and can be coupled to digit line 215 when second transistor 265 is activated.

[0058] The word line 210-a or 210-b can be an electrically conductive line in electronic communication with the memory cell 205 that is used to perform access operations on the memory cell 205. In some architectures, the word line 210-a can be coupled with the gate of the second transistor 265 of the memory cell 205 and can be operable to control the second transistor 265 of the memory cell 205. Further, the word line 210-b can be coupled with the gate of the first transistor 270 of the memory cell 205 and can be operable to control the first transistor 270 of the memory cell 205.

[0059] The digit line 215 can be an electrically conductive line that connects the memory cell 205 with a sense component 245. In some architectures, the memory cell 205 can be selectively coupled with the digit line 215 during a portion of an access operation. In some architectures, the memory cell 205 can be coupled with the digit line 215.

[0060] The sense component 245 can be operable to detect a state (e.g., charge) stored at the gap fill gate of the first transistor 270 of the memory cell 205 and determine a logic state of the memory cell 205 based on the stored state. The sense component 245 can include one or more sense amplifiers to amplify or otherwise convert a signal resulting from accessing the memory cell 205. In some cases, the sense component 245 can compare a signal detected from the memory cell 205 to a reference 250 (e.g., a reference voltage). Alternatively, the sense component 245 can use a single-ended (e.g., non-differential) amplifier or sensing circuit to amplify or latch a logic state corresponding to the memory cell 205. The detected logic state of the memory cell 205 can be provided as an output of the sense component 245 (e.g., to the input / output 255) and can indicate the detected logic state to another component of a memory device including the memory die 200.

[0061] The local memory controller 260 can control access of the memory cell 205 through various components (e.g., the row decoder 220, the column decoder 225, the sense component 245). The local memory controller 260 can be a reference Figure 1An example of a local memory controller 165 is described. In some examples, one or more of the row decoder 220, the column decoder 225, and the sense component 245 can be co-located with the local memory controller 260. The local memory controller 260 can be operable to receive one or more of commands or data from one or more different memory controllers (e.g., the external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), translate the commands or data (or both) into information that can be used by the memory die 200, perform one or more operations on the memory die 200, and pass data from the memory die 200 to the host device 105 based on performing the one or more operations. The local memory controller 260 can generate row signals and column address signals to activate a target word line 210 and a target digit line 215. The local memory controller 260 can also generate and control various voltages or currents used during operation of the memory die 200. In general, the amplitudes, shapes, or durations of the applied voltages or currents discussed herein can vary and can differ for the various operations discussed in operating the memory die 200.

[0062] The local memory controller 260 can be operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations can include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. The local memory controller 260 can be operable to perform other access operations not listed here or other operations related to operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0063] The local memory controller 260 can be operable to perform a write operation (e.g., a program operation) on one or more memory cells 205 of the memory die 200. During the write operation, the memory cells 205 of the memory die 200 can be programmed to store a desired logic state. The local memory controller 260 can identify a target memory cell 205 on which to perform the write operation. The local memory controller 260 can identify a target word line 210-a and a target digit line 215 coupled with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 260 can activate the target word line 210-a and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215-a) to access the target memory cell 205. The local memory controller 260 can apply a particular signal (e.g., a write pulse) to the digit line 215 during the write operation to store a particular state (e.g., a charge) at the first transistor 270. The pulse used as part of the write operation can include one or more voltage levels for a duration of time.

[0064] The local memory controller 260 can be operable to perform a read operation (e.g., a sense operation) on one or more memory cells 205 of the memory die 200. During a read operation, a logical state stored in a memory cell 205 of the memory die 200 can be determined. The local memory controller 260 can identify a target memory cell 205 on which a read operation is to be performed. The local memory controller 260 can identify a target word line 210-b and a target digit line 215 coupled with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 260 can activate the target word line 210-b and the target digit line 215 (e.g., apply a voltage to the word line 210-b or the digit line 215) to access the target memory cell 205. The target memory cell 205 can transfer a signal to the sense component 245 in response to the biasing of the access line. The sense component 245 can amplify the signal. The local memory controller 260 can activate the sense component 245 (e.g., latch the sense component) and thereby compare the signal received from the memory cell 205 to the reference 250. Based on the comparison, the sense component 245 can determine the logical state stored on the memory cell 205.

[0065] In some examples, the memory die 200 can access a first memory cell 205 of a group of memory cells 205. Accessing the first memory cell 205 can include selecting a word line 210-a or a word line 210-b and a bit line 215 associated with the first memory cell 205. After accessing the first memory cell 205, the memory die 200 can restore a charge stored at the first memory cell 205. To access and restore a charge stored at each memory cell coupled with the word line 210-a and the word line 210-b, a memory device can have a sense amplifier associated with each digit line 215. In the absence of a sense amplifier on a digit line to sense a charge on an unselected (e.g., for a given access operation) memory cell, selecting the word line 210-a and the word line 210-b can overwrite a charge stored at the unselected memory cell. Thus, to support access operations to a subset of memory cells coupled with the word line 210-a and the word line 210-b, a memory device can have a sense amplifier and a driver per digit line. However, it can be desirable to support access operations to a subset of memory cells coupled with the word line 210-a and the word line 210-b without the area consumed by a sense amplifier and a driver per digit line.

[0066] The disclosure describes techniques for refreshing the gap gate (e.g., the floating node) of the first transistor 270 of the memory cell 205. For example, the local memory controller 260 can activate the digit line 215 (e.g., apply a current to the digit line 215) and can activate the word line 210-b. If the gap gate of the first transistor 270 stores a first amount of charge, the first transistor 270 can activate and can pull down the voltage of the digit line 215. However, if the gap gate of the first transistor 270 stores a second amount of charge, the first transistor 270 can be deactivated or remain in a deactivated state, which can enable the voltage on the digit line 215 to increase or remain. Once the voltage is generated on the digit line 215, the local memory controller 260 can activate the word line 210-a. Activating the word line 210-a can activate the second transistor 265 and can restore the sensed charge at the gap gate of the first transistor 270. In some examples, a subset of memory cells with less or at most all memory cells of a row can be refreshed at the same time. Further, the techniques described herein can be used when the memory die 200 is to perform an activate command (e.g., page open), a read command, or a write command.

[0067] In some examples, by performing a method as described herein, the sense component 245 can include an amount of sense amplifiers for each row that is equal to the number of selected memory cells 205 on the row. For example, if each row has N memory cells 205 and digit lines 215 and the interface to the memory device has a width or burst size M, the sense component 245 can include M sense amplifiers that can be selectively coupled with M digit lines of the N digit lines. Thus, instead of having one sense amplifier per digit line 215 (for example), the sense component 245 can have one sense amplifier per group of digit lines 215 (e.g., per group of N / M digit lines 215). That is, a sense amplifier can be used to perform an access operation on M memory cells 205 of the N memory cells 205 in a row while N-M memory cells 205 of the row perform a self-refresh operation without being coupled to a sense amplifier. Having fewer sense amplifiers can reduce the power of the memory die 200, which can improve the efficiency of the memory die 200 and / or can increase the battery life of the memory die 200. Further, reducing the number of sense amplifiers can reduce the number of control signals used to perform access operations.

[0068] Figure 3 An example of a circuit 300 that supports self-refresh of memory cells is described in accordance with examples as disclosed herein. In some examples, the circuit 300 can implement one or more features of the memory die 200. For example, the word line 305-a can be an example of the word line 210-a as described with reference to Figure 2 The word line 305-b can be an example of the word line 210-b as described with reference to Figure 2The example word line 210-b described; the digit lines 310-a, 310-b, and 310-c can be as described with reference to Figure 2 The example digit line 215 described; the second transistors 320-a, 320-b, and 320-c can be as described with reference to Figure 2 The example second transistor 265 described; and the first transistors 325-a, 325-b, and 325-c can be as described with reference to Figure 2 The example first transistor 270 described. In some examples, the second transistor 320-a and the first transistor 325-a can correspond to a first memory cell of a row of a memory array, the second transistor 320-b and the first transistor 325-b can correspond to a second memory cell of the row of the memory array, and the second transistor 320-c and the first transistor 325-c can correspond to a third memory cell of the row of the memory array. In some examples, a digit line can also be referred to as a bit line.

[0069] The word line 305-a can be coupled with a gate of the second transistor 320-a, a gate of the second transistor 320-b, and a gate of the second transistor 320-c. The word line 305-b can be coupled with a gate of the first transistor 325-a, a gate of the first transistor 325-b, and a gate of the first transistor 325-c. The gate of the first transistor 325 coupled to the word line 305-b can also be referred to as a control gate, and activation of the control gate can enable the spacers gate to control activation or deactivation of the first transistor 325. A first terminal (e.g., source or drain) of the first transistor 325-a can be coupled with a ground reference 330-a; a first terminal (e.g., source or drain) of the first transistor 325-b can be coupled with a ground reference 330-b; and a first terminal (e.g., source or drain) of the first transistor 325-c can be coupled with a ground reference 330-c. In some examples, the ground references 330-a, 330-b, and 330-c can correspond to the same ground reference. A first terminal (e.g., source or drain) of the second transistor 320-a can be coupled with the spacer gate of the first transistor 325-a; a first terminal (e.g., source or drain) of the second transistor 320-b can be coupled with the spacer gate of the first transistor 325-b; and a first terminal (e.g., source or drain) of the second transistor 320-c can be coupled with the spacer gate of the first transistor 325-c. A second terminal (e.g., the other of source or drain) of the first transistor 325-a and a second terminal (e.g., the other of source or drain) of the second transistor 320-a can be coupled with the digit line 310-a; a second terminal (e.g., the other of source or drain) of the first transistor 325-b and a second terminal (e.g., the other of source or drain) of the second transistor 320-b can be coupled with the digit line 310-b; and a second terminal (e.g., the other of source or drain) of the first transistor 325-c and a second terminal (e.g., the other of source or drain) of the second transistor 320-c can be coupled with the digit line 310-c.

[0070] The digital line 310-a can be coupled with a third transistor 335-a, the digital line 310-b can be coupled with a third transistor 335-b, and the digital line 310-c can be coupled with a third transistor 335-c. Further, the digital line 310-a can be coupled with a switching component 340-a, the digital line 310-b can be coupled with a switching component 340-b, and the digital line 310-c can be coupled with a switching component 340-c. Each of the switching components 340-a, 340-b, and 340-c can be coupled with a sense amplifier 345. In some examples, each of the switching components 340-a, 340-b, and 340-c can be an example of a fourth transistor. In some such examples, a first terminal (e.g., one of a source or a drain) of each fourth transistor can be coupled with a respective digital line and a second terminal (e.g., the other of the source or the drain) can be coupled with the sense amplifier 345.

[0071] The first transistor 325-a can be configured to selectively couple the digital line 310-a with a ground reference 330-a; the first transistor 325-b can be configured to selectively couple the digital line 310-b with a ground reference 330-b; and the first transistor 325-c can be configured to selectively couple the digital line 310-c with a ground reference 330-c. The second transistor 320-a can be configured to selectively couple the digital line 310-a with a gate of the first transistor 325-a; the second transistor 320-b can be configured to selectively couple the digital line 310-b with a gate of the first transistor 325-b; and the second transistor 320-c can be configured to selectively couple the digital line 310-c with a gate of the first transistor 325-c. The third transistor 335-a can be configured to selectively couple the digital line 310-a with a current source; the third transistor 335-b can be configured to selectively couple the digital line 310-b with a current source; and the third transistor 335-c can be configured to selectively couple the digital line 310-c with a current source (e.g., via a pull-up enable (PUE) signal PUE[0], PUE[l], or PUE[2]). Alternatively, the third transistor 335 can operate as a current source, where a reference voltage on a gate of the third transistor 335 (e.g., PUE[0], PUE[l], or PUE[2]) can set a current supplied by the third transistor 335. In some examples, the third transistor 335 can be a PMOS transistor. The switching component 340-a can be configured to selectively couple the digital line 310-a with the sense amplifier 345; the switching component 340-b can be configured to selectively couple the digital line 310-b with the sense amplifier 345; and the switching component 340-c can be configured to selectively couple the digital line 310-c with the sense amplifier 345.

[0072] In some examples, a self-refresh (e.g., self-recovery) operation can be performed at one or more of the memory cells (e.g., without performing an access operation through a sense amplifier). For example, digit line 310-b can be charged high and then can be discharged through first transistor 325-b. The discharge of digit line 310-b can depend on the voltage of the gap fill gate of first transistor 325-b and the discharge time. After discharging digit line 310-b, second transistor 320-b can be activated and can charge the gap fill gate of first transistor 325-b to the voltage of digit line 310-b. In examples where the charge at the gap fill gate causes first transistor 325-b to activate, the gap fill gate can draw current from digit line 310-b at least until the current between the source and drain of first transistor 325-b matches the current provided to digit line 310-b through third transistor 335-b (e.g., which can act as a current source). For example, the voltage of the gap fill gate of first transistor 325-b can modify the equilibrium voltage of digit line 310-b to balance the current. In some such examples, second transistor 320-b can be deactivated and, as a result, the gap fill gate of first transistor 325-b can remain set by the previous access operation. Although some transient effects (e.g., from digit line coupling of activating word line 305) can occur, these effects can cancel out. In some examples, the current between the source and drain of third transistor 335-b can be represented as and the current between the first and second terminals of first transistor 325 can be where V fg may be the voltage of the gap fill gate. In some examples, I pull_up = I pmos In examples where second transistor 320 is deactivated, V fg may not be charged but can be used to balance current. Thus, for example, transient effects of digit line or bit line coupling can cancel out.

[0073] Figure 4 An example of a timing diagram 400 to support self-refresh of a memory cell according to examples as disclosed herein is illustrated. For example, timing diagram 400 can be an example of signaling to support a self-refresh operation at a memory cell of circuit 300.

[0074] Word line signaling 405 (NMOS word line (NWL)) can correspond to the voltage on word line 305-a and word line signaling 410 (PMOS word line (PWL)) can correspond to the voltage on word line 305-b. Pull-up enable (PUE) signaling 415 can correspond to the voltage at the gate of the third transistor 335 (e.g., one or more of third transistors 335-a, 335-b, and 335-c), or to an enable circuit for enabling the third transistor 335 to supply current. Selected digit line (SDL) signaling 420 can correspond to the voltage on the digit line 310 selected during an access operation (e.g., a read or write operation). For example, the access operation can be a read operation and selected digit line signaling 420-a can correspond to the voltage on the selected digit line 310 when the gap gate of the respective first transistor 325 stores a first state (e.g., a logic'1 ') and selected digit line signaling 420-b can correspond to the voltage on the selected digit line 310 when the gap gate of the respective first transistor 325 stores a second state (e.g., a logic '0'). Unselected digit line (UDL) signaling 425 can correspond to the voltage on the digit line 310 that is not selected during the access operation. Unselected digit line signaling 425-a can correspond to the voltage on the unselected digit line 310 when the gap gate of the respective first transistor 325 stores the first state and unselected digit line signaling 425-b can correspond to the voltage on the unselected digit line 310 when the gap gate of the respective first transistor 325 stores the second state. Cell float node (CFN) signaling 430-a and 430-b can each correspond to the voltage at the gap gate of the first transistor 325. For example, cell float node signaling 430-a can correspond to the voltage at the gap gate when the gap gate of the first transistor 325 stores the first state and cell float node signaling 430-b can correspond to the voltage at the gap gate when the gap gate of the first transistor 325 stores the second state.

[0075] Between 435-a and 435-d, the circuit 300 can perform an access operation. Performing the access operation can include the circuit 300 performing an activation operation (e.g., between 435-a and 435-b), a read or write operation (e.g., between 435-b and 435-c), and a pre-charge operation (between 435-c and 435-d).

[0076] At 435-a, the word line signaling 410 can transition from a high voltage to a low voltage (e.g., from an idle voltage to a read voltage). The transition from a high voltage to a low voltage can activate (e.g., turn on) each first transistor 325 (e.g., first transistors 325-a, 325-b, and 325-c) coupled with the word line 305-b. At 435-a or after (e.g., and before 435-b), the selected digit line signaling 420 can transition from a low voltage to a high voltage (e.g., can transition to a read voltage). For example, if the digit line 310-a is the selected digit line, the voltage on the digit line 310-a can transition from a low voltage to a higher or intermediate voltage. The change in the selected digit line signaling 420 between 435-a and 435-b can be sensed by the sense amplifier 345 and the result can be stored as a logic 0 or 1 in the sense amplifier 345. The sense charge can include coupling the sense amplifier 345 with the digit line 310-a via the switching component 340-a. While the switching component 340-a is configured to couple the sense amplifier 345 and the digit line 310-a, the switching component 340-b can be configured to isolate the digit line 310-b from the sense amplifier 345 and the switching component 340-c can be configured to isolate the digit line 310-c from the sense amplifier 345.

[0077] Between 435-b and 435-c, the circuit 300 can determine to perform a read or write to the data stored in the sense amplifier 345 coupled to the selected digit line. For example, if the command is a read operation, the circuit 300 and / or the local memory controller 260 can read the data stored in the sense amplifier 345 during the sensing operation and can output the data (e.g., using an input / output, such as the input / output 255 as described herein (e.g., with reference to FIG. 2)). If the command is a write operation, the circuit 300 and / or the local memory controller 260 can write a logic 0 to the sense amplifier 345 in place of the logic 0 or 1 stored during the sensing operation. Alternatively, during the write operation, the circuit 300 and / or the local memory controller 260 can write a logic 1 to the sense amplifier 345 in place of the logic 0 or 1 previously stored during the sensing operation. Figure 2

[0078] At 435-c or after (e.g., during a pre-charge operation), the pull-up enable signaling 415 can transition from a low voltage to a high voltage. The pull-up enable signaling 415 transitioning to a high voltage can activate the third transistors 335 of the unselected digit lines 310 (e.g., digit lines 310-b and 310-c). Further, in some examples, the pull-up enable signaling 415 can also activate the third transistors 335 of the selected digit line 310 (e.g., digit line 310-a). Activating the one or more third transistors 335 can enable current to be applied to the respective digit line 310 coupled with each of the one or more third transistors 335.​

[0079] Timing diagram 400 can illustrate a read operation on a first memory cell including first transistor 325-a and second transistor 320-a. At or after 435-a, sense amplifier 345 can detect the state of the interstitial gate of first transistor 325-a. If the interstitial gate of first transistor 325-a stores a first state, sense amplifier 345 can detect the first state and can transition selected digit line 310 to a higher voltage according to selected digit line signaling 420-a. However, if the interstitial gate of first transistor 325-a stores a second state, sense amplifier 345 can detect the second state and can transition selected digit line 310 to a lower voltage according to selected digit line signaling 420-b. Further, at or after 435-c, if the first transistor 325 of unselected digit line 310 (e.g., the interstitial gate of first transistor 325-b or first transistor 325-c) stores a first state, the unselected digit line 310 can transition to a higher voltage as illustrated by unselected digit line signaling 425-a because current can be supplied via third transistor 335 and the first transistor can be deactivated, allowing the selected digit line 310 to charge to a higher voltage. However, if the interstitial gate of first transistor 325 of unselected digit line 310 stores a second state, the unselected digit line 310 can remain or transition to a lower voltage because the first transistor 325 can sink current supplied via the third transistor to a ground reference 330, thus preventing the digit line 310 from charging as illustrated by unselected digit line signaling 425-b.

[0080] After the voltages on the selected and unselected digit lines 310 transition according to the applied current and the state stored at the interstitial gate of the respective first transistor 325, pull-up enable signaling 415 can transition from a high voltage to a low voltage. The pull-up enable signaling 415 transitioning to a low voltage can deactivate the third transistor 335 that was previously activated by the pull-up enable signaling transitioning to a high voltage. In some examples, a first transistor 325 storing a first state can have a higher floating gate voltage and thus can sink less read current from its digit line 310 compared to a first transistor 325 storing a second state.

[0081] After the pull-up enable signaling 415 transitions back to the low voltage, the word line signaling 410 can transition from the low voltage back to the high voltage. The transition to the high voltage can deactivate the first transistors 325 (e.g., the first transistors 325-a, 325-b, and 325-c) coupled with the word line 305-b. Further, after the pull-up enable signaling transitions back to the low voltage, the word line signaling 405 can transition from the low voltage to the high voltage. The transition from the low voltage to the high voltage can activate (e.g., turn on) each of the second transistors 320 (e.g., the second transistors 320-a, 320-b, and 320-c) coupled with the word line 305-a. Activating the second transistors 320 can enable the interstitial gates of the respective first transistors 325 to be charged by the respective digit lines 310. For example, if the interstitial gates of the first transistors 325 store the first state, the charge stored at the interstitial gates can be recovered according to the cell floating node signaling 430-a. However, if the interstitial gates of the first transistors 325 store the second state, the charge stored at the interstitial gates can be recovered according to the cell floating node signaling 430-b.

[0082] In some examples, the pull-up enable signaling 415 can not transition back to the low voltage until after the word line signaling 405 transitions from the low voltage to the high voltage and back to the low voltage. In such examples, after the word line signaling 405 transitions back to the low voltage, the pull-up enable signaling 415 can transition from the high voltage to the low voltage. Additionally or alternatively, the word line signaling 410 can not transition back to the high voltage until after the word line signaling 405 transitions from the low voltage to the high voltage and back to the low voltage. In such examples, after the word line signaling transitions back to the low voltage, the word line signaling 410 can transition from the low voltage to the high voltage. Avoiding the transition of the pull-up enable signaling 415 back to the low voltage and / or avoiding the transition of the word line signaling 410 back to the high voltage until after the word line signaling 405 transitions back to the low voltage can enable the digit lines 310 associated with the signaling to be actively driven (e.g., relative to enabling the digit lines 310 to float) when the second transistors 320 coupled with the digit lines 310 are activated.

[0083] After the charge has been recovered at the interstitial gates of the respective first transistors 325, the word line signaling 405 can transition from the high voltage to the low voltage. The transition from the high voltage to the low voltage can deactivate each of the second transistors 320 (e.g., the second transistors 320-a, 320-b, and 320-c) coupled with the word line 305-a, thus capturing the charge on the interstitial gates of the first transistors 325 transferred or supplied during the word line signaling 405 when at the high voltage.

[0084] At 435-d or after, if the gap fill gate of the first transistor 325 of the selected digit line 310 stores the first state, the selected digit line signaling 420-a can transition to a low voltage (e.g., the voltage of the selected digit line signaling 420 before or at 435-a). Further, at 435-d or after, if the gap fill gate of the first transistor 325 of the unselected digit line 310 stores the first state, the unselected digit line signaling 425-a can transition to a low voltage (e.g., the voltage of the unselected digit line signaling 425 before or at 435-a).

[0085] In some examples, the circuit 300 can perform the methods described herein without performing access operations to the memory cells using sense amplifiers. For example, during the duration between 435-b and 435-c, the circuit 300 can refrain from performing access operations to the unselected cells. Instead, 435-b and 435-c can occur simultaneously (e.g., the duration between 435-b and 435-c can equal 0). In some examples where access operations are not performed, the SDL signaling 420 can not represent one or more digit lines 310 (digit lines 310-a, 310-b, and / or 310-c) (or any of them) and / or the UDL signaling 425 can represent one or more (or all) digit lines 310 (e.g., digit lines 310-a, 310-b, and / or 310-c). That is, access operations can be performed to a first subset of memory cells of a row of memory cells while self-refresh operations can be performed to a second subset of memory cells of the row of memory cells. Instead, self-refresh operations can be performed to all of the memory cells of a row of memory cells (e.g., no access operations are performed or no sense amplifiers are used to read or write any of the memory cells of the row).

[0086] In some examples, restoring charge at the gap fill gate of a selected digit line 310 as described herein can have one or more advantages. For example, the method of restoring charge at the gap fill gate of the first transistor 325 of a selected digit line 310 as described herein can include coupling the selected digit line 310 with a sense amplifier 345. Other methods can include using a sense amplifier 345 for each digit line 310. Thus, the method described herein can enable the circuit 300 to include a smaller number of sense amplifiers 345 (e.g., one sense amplifier 345 for a group of digit lines) than other methods (e.g., the circuit 300 can have fewer sense amplifiers 345 than digit lines 310). Additionally or alternatively, the method described herein can enable a selected digit line 310 to restore charge at the gap fill gate of the first transistor 325 during an access operation. Thus, the method described herein can prevent the gap fill gate from losing charge or prolong the amount of time it takes for the gap fill gate to lose charge beyond a threshold amount. For example, a self-refresh operation can be performed on all memory cells of a row during a refresh operation. Further, the method described herein can enable a DRAM memory cell that can not be able to perform self-restoration or self-refresh to be replaced with another type of memory cell (e.g., a memory cell 205 as described with reference to Figure 2 FIG. 1) that can be able to perform self-restoration or self-refresh.

[0087] Figure 5 An example of a circuit 500 that supports self-refresh of memory cells according to examples as disclosed herein is described. In some examples, the circuit 500 can be implemented by one or more aspects of the circuit 300. For example, the word line 505 can be an example of the word line 305-a as described with reference to Figure 3 FIG. 1; the word line 510 can be an example of the word line 305-b as described with reference to Figure 3 FIG. 1; the digit lines 515-a, 515-b, 515-c, and 515-d can be examples of the digit line 310 as described with reference to Figure 3 FIG. 1; the first transistor 530 can be an example of the first transistor 325 as described with reference to Figure 3 FIG. 1; the second transistor 525 can be an example of the second transistor 320 as described with reference to Figure 3 FIG. 1; the ground reference 535 can be an example of the ground reference 330 as described with reference to Figure 3 FIG. 1; the third transistor 520-a, 520-b, and 520-c can be examples of the third transistor 335 as described with reference to Figure 3 FIG. 1; or any combination thereof. In some examples, the circuit 500 can be an example of a multi-level memory array.

[0088] Circuit 500 can include multiple levels of a memory array. For example, digit line 515-a can be coupled with memory cells of a first level; digit line 515-b can be coupled with memory cells of a second level; digit line 515-c can be coupled with memory cells of a third level; and digit line 515-d can be coupled with memory cells of a fourth level. Each memory cell can include a respective first transistor 530, a respective second transistor 525, and a respective ground reference 535. Word line 505 can be coupled with the gate of one first transistor 530 of each of digit lines 515-a, 515-b, 515-c, and 515-d. Further, word line 510 can be coupled with the gate of one second transistor 525 of each of digit lines 515-a, 515-b, 515-c, and 515-d.

[0089] A first terminal (e.g., one of a source or a drain) of each respective first transistor 530 can be coupled with a respective ground reference 535 and a second terminal (e.g., the other of the source or the drain) can be coupled with a respective digit line 515. A first terminal (e.g., one of a source or a drain) of each respective second transistor 525 can be coupled with the gap gate of a respective first transistor 530 and a second terminal (e.g., the other of the source or the drain) can be coupled with a respective digit line 515. Each digit line 515 can be coupled with a third transistor 520. For example, in the present example, digit lines 515-a, 515-b, 515-c, and 515-d can be coupled with third transistor 520-a. In some examples, multiplexers can exist between digit lines 515-a, 515-b, 515-c, and 515-d and third transistor 520-a.

[0090] Each first transistor 530 can be configured to selectively couple a respective ground reference 535 with a respective digit line 515. Further, each first transistor 530 can be configured to store a state of a memory cell including the first transistor 530 at the gap gate of the first transistor 530. Each second transistor 525 can be configured to selectively couple the gap gate of a respective first transistor 530 with a respective digit line 515. Each third transistor 520 can be a current source or can be configured to couple one or more digit lines 515 (e.g., digit lines 515-a, 515-b, 515-c, and 515-d) with a current source (e.g., a DC current source). If present, each multiplexer between a third transistor 520 and a respective group of digit lines 515 can be configured to selectively couple the third transistor 520 with one of the respective group of digit lines 515 and isolate the third transistor 520 from remaining digit lines 515 of the group of digit lines 515.

[0091] In some examples, having word lines 505 and 510 coupled with memory cells of multiple levels can have one or more advantages. For example, a smaller number of word line drivers can be used for word lines 505 and 510 and socket routing can be performed in a less complex manner compared to having separate word lines 505 and 510 for each level. Driving word lines 505 and / or 510 for multiple levels can enable memory cells coupled with word lines 505 and / or 510 to be written back together. A method without self-restore as described herein can include a sense amplifier per digit line per level. However, a method without self-restore as described herein can use fewer sense amplifiers. In some examples, self-restore as described herein can be used to refresh unselected bits on selected word lines 505 and / or 510 of selected levels. Additionally or alternatively, with word lines 505 and 510 shared between levels, bits on unselected levels can be refreshed during access operations to selected levels. In some such examples, circuit 500 can employ a digit line level selection.

[0092] Figure 6 An example of a timing diagram 600 to support self-refresh of memory cells is illustrated in accordance with examples as disclosed herein. For example, timing diagram 600 can be an example of signaling to support self-refresh operations at memory cells of circuit 500.

[0093] Word line (NMOS word line (NWL)) signaling 605 can correspond to a voltage on word line 505 and word line signaling 610 (PMOS word line (PWL) signaling) can correspond to a voltage on word line 510. Third level select signaling 615 (level select 2 (DSL2)) can correspond to a voltage associated with a selected level and selected digit line signaling 620 (selected digit line (SDL)) can correspond to a voltage on digit line 515 of a selected level (e.g., for a read operation). Selected digit line signaling 620-a can correspond to a voltage on selected digit line 515 when an interstitial gate of a respective first transistor 530 stores a first state and selected digit line signaling 620-b can correspond to a voltage on selected digit line 515 when an interstitial gate of a respective first transistor 530 stores a second state. Pull-up enable signaling 625 (pull-up enable (PUE)) can correspond to a voltage at a gate of third transistor 520 (e.g., third transistors 520-a, 520-b, and / or 520-c) or can correspond to an enable circuit for enabling one or more third transistors 520 to supply current.

[0094] The first level select signaling 630 (bit line level select 0 (BDS0)) corresponds to a voltage associated with the first level (e.g., a voltage that enables a current source coupled with the third transistor 520 to couple with a digit line 515 of the first level when high) and the unselected digit line signaling 635 (unselected digit line 0 (UDL0)) can correspond to a voltage on an unselected digit line 515 (e.g., digit line 515-a) of the first level. The second level select signaling 640 (bit line level select 1 (BDS1)) corresponds to a voltage associated with the second level (e.g., a voltage that enables a current source coupled with the third transistor 520 to couple with a digit line 515 of the second level when high) and the unselected digit line signaling 645 (unselected digit line 1 (UDL1)) can correspond to a voltage on an unselected digit line 515 (e.g., digit line 515-b) of the second level. The third level select signaling 650 (bit line level select 2 (BDS2)) corresponds to a voltage associated with the third level (e.g., a voltage that enables a current source coupled with the third transistor 520 to couple with a digit line 515 of the third level when high) and the unselected digit line signaling 655 (unselected digit line 2 (UDL2)) can correspond to a voltage on an unselected digit line 515 (e.g., digit line 515-c) of the third level. The fourth level select signaling 660 (bit line level select 3 (BDS3)) corresponds to a voltage associated with the fourth level (e.g., a voltage that enables a current source coupled with the third transistor 520 to couple with a digit line 515 of the fourth level when high) and the unselected digit line signaling 665 (unselected digit line 3 (UDL3)) can correspond to a voltage on an unselected digit line 515 (e.g., digit line 515-d) of the fourth level. Each of the unselected digit line signaling 635-a, 645-a, 655-a, and 665-a can correspond to a voltage on a respective unselected digit line 515 when the first state is stored by the gate first transistor 530 and each of the unselected digit line signaling 635-b, 645-b, 655-b, and 665-b can correspond to a voltage on a respective unselected digit line 515 when the second state is stored by the gate first transistor 530.

[0095] The cell floating node signaling 670-a and 670-b (cell floating node (CFN)) can each correspond to a voltage at the gate of the first transistor 530. For example, the cell floating node signaling 670-a can correspond to a voltage at the gate when the first state is stored by the gate of the first transistor 530 and the cell floating node signaling 670-b can correspond to a voltage at the gate when the second state is stored by the gate of the first transistor 530.

[0096] Between 675-a and 675-d, the circuit 500 can perform an access operation. Performing an access operation can include the circuit 500 performing an activation operation (e.g., between 675-a and 675-b), a read or write operation (e.g., between 675-b and 675-c), and a precharge operation (between 675-c and 675-d).

[0097] At 675-a, the word line signaling 610 can transition from a high voltage to a low voltage (e.g., from an idle voltage to a read voltage). Transitioning from a high voltage to a low voltage can activate (e.g., turn on) each first transistor 530 coupled with the word line 510. At or after 675-a (e.g., and before 675-b), the selected digit line signaling 620 can transition from a low voltage to a high voltage (e.g., can transition to a read voltage). For example, if the digit line 515-c is the selected digit line, the voltage on the digit line 515-c can transition from a low voltage to a higher voltage or an intermediate voltage. Further, at or after 675-a (e.g., substantially contemporaneous with the selected digit line signaling 620 transitioning to a high voltage), the third level select signaling 615 can transition from a low voltage to a high voltage.

[0098] Between 675-b and 675-c, the circuit 500 and / or the local memory controller 260 can determine to perform a read or write to a sense amplifier coupled to the selected digit line (e.g., the sense amplifier 345 as described with reference to FIG. 3). For example, if the command is a write operation, the circuit 500 and / or the local memory controller 260 can write data to the sense amplifier (e.g., the sense amplifier 345 as described with reference to FIG. 3). At or after 675-c, the sense amplifier can write a charge to the gap fill gate of the first transistor 530 of the selected digit line 515. Figure 3 Figure 3 Between 675-b and 675-c, the circuit 500 and / or the local memory controller 260 can determine to perform a read or write to a sense amplifier coupled to the selected digit line (e.g., the sense amplifier 345 as described with reference to FIG. 3). For example, if the command is a write operation, the circuit 500 and / or the local memory controller 260 can write data to the sense amplifier (e.g., the sense amplifier 345 as described with reference to FIG. 3). At or after 675-c, the sense amplifier can write a charge to the gap fill gate of the first transistor 530 of the selected digit line 515.

[0099] At or after 675-c, the pull-up enable signaling 625 can transition from a low voltage to a high voltage. The pull-up enable signaling 625 transitioning to a high voltage can activate one or more of the third transistors 520-a, 520-b, and 520-c. Activating the one or more third transistors 520 can enable current to be applied to the respective digit line 515 coupled with each of the one or more third transistors 520. At or after 675-c, the third level select signaling 615 can transition from a high voltage to a low voltage.

[0100] ​Timing diagram 600 can illustrate a read operation on a memory cell including a respective first transistor 530 and a respective second transistor 525. At or after 675-a, a sense amplifier coupled with the memory cell can detect a state of the gapfill gate of the respective first transistor 530. If the gapfill gate of the respective first transistor 530 stores a first state, the sense amplifier can detect the first state and can transition the selected digit line 515 to a higher voltage according to selected digit line signaling 620-a. However, if the gapfill gate of the respective first transistor 530 stores a second state, the sense amplifier can detect the second state and can transition the selected digit line 310 to a lower voltage according to selected digit line signaling 620-b.

[0101] Furthermore, at or after 675-c, the first level select signaling 630 can transition from a low voltage to a high voltage. Furthermore, at or after 675-c, if the gapfill gate of the first transistor 530 of an unselected digit line 515 (e.g., digit line 515-a) of the first level stores the first state, the unselected digit line 515 can transition to a higher voltage (e.g., a write voltage) as illustrated by unselected digit line signaling 635-a, because current can be supplied via the respective third transistor 520 and the first transistor 530 can be deactivated, allowing the respective unselected digit line 515 to charge to the higher voltage. However, if the gapfill gate of the first transistor 530 of the unselected digit line 515 stores the second state, the unselected digit line 515 can remain at or transition to a lower voltage (e.g., the voltage of unselected digit line signaling 635 prior to 675-a) as illustrated by unselected digit line signaling 635-b, because the first transistor 530 can sink current supplied via the third transistor 520 to the respective ground reference, thus preventing the unselected digit line 515 from charging. After the unselected digit line 515 transitions to the higher voltage or the lower voltage, the first level select signaling 630 can transition from the high voltage to the low voltage.

[0102] After the first tier select signaling 630 transitions from low voltage to high voltage (e.g., and before the first tier select signaling 630 transitions back to low voltage), the second tier select signaling 640 can transition from low voltage to high voltage. Further, upon or after the second tier select signaling 640 transitions to high voltage, if the first transistor 530 of the unselected digit line 515 of the second tier (e.g., digit line 515-b) has its gap fill gate storing the first state, then the unselected digit line 515 can transition to a higher voltage (e.g., a write voltage) as dictated by unselected digit line signaling 645-a, because current can be supplied via the respective third transistor 520 and the first transistor 530 can be deactivated, allowing the respective unselected digit line 515 to charge to the higher voltage. However, if the first transistor 530 of the unselected digit line 515 has its gap fill gate storing the second state, then the unselected digit line 515 can remain at or transition to a lower voltage (e.g., the voltage of the unselected digit line signaling 645 prior to 675-a) as dictated by unselected digit line signaling 645-b, because the first transistor 530 can sink current supplied via the third transistor 520 to the respective ground reference, thus preventing the unselected digit line 515 from charging. After the unselected digit line 515 transitions to the higher voltage or the lower voltage, the second tier select signaling 640 can transition from high voltage to low voltage.

[0103] After the second tier select signaling 640 transitions from low voltage to high voltage (e.g., and before the second tier select signaling 640 transitions back to low voltage), the third tier select signaling 650 can transition from low voltage to high voltage. Further, upon or after the third tier select signaling 650 transitions to high voltage, if the first transistor 530 of the unselected digit line 515 of the third tier (e.g., digit line 515-c) has its gap fill gate storing the first state, then the unselected digit line 515 can transition to a higher voltage (e.g., a write voltage) as dictated by unselected digit line signaling 655-a, because current can be supplied via the respective third transistor 520 and the first transistor 530 can be deactivated, allowing the respective unselected digit line 515 to charge to the higher voltage. However, if the first transistor 530 of the unselected digit line 515 has its gap fill gate storing the second state, then the unselected digit line 515 can remain at or transition to a lower voltage (e.g., the voltage of the unselected digit line signaling 655 prior to 675-a) as dictated by unselected digit line signaling 655-b, because the first transistor 530 can sink current supplied via the third transistor 520 to the respective ground reference, thus preventing the unselected digit line 515 from charging. After the unselected digit line 515 transitions to the higher voltage or the lower voltage, the third tier select signaling 650 can transition from high voltage to low voltage.

[0104] After the third level select signaling 650 transitions from low voltage to high voltage (e.g., and before the third level select signaling 650 transitions back to low voltage), the fourth level select signaling 660 can transition from low voltage to high voltage. Further, at or after the fourth level select signaling 660 transitions to high voltage, if the first transistor 530 of the unselected digit line 515 of the fourth level (e.g., digit line 515-d) has a gap fill gate storing a first state, then the unselected digit line 515 can transition to a higher voltage (e.g., a write voltage) as indicated by unselected digit line signaling 665-a, because current can be supplied via the respective third transistor 520 and the first transistor 530 can be deactivated, allowing the respective unselected digit line 515 to charge to the higher voltage. However, if the first transistor 530 of the unselected digit line 515 has a gap fill gate storing a second state, then the unselected digit line 515 can remain at or transition to a lower voltage (e.g., the voltage of the unselected digit line signaling 665 before 675-a) as indicated by unselected digit line signaling 665-b, because the first transistor 530 can sink current supplied via the third transistor 520 to the respective ground reference, thus preventing the unselected digit line 515 from charging. After the unselected digit line 515 transitions to the higher voltage or the lower voltage, the fourth level select signaling 660 can transition from high voltage to low voltage.

[0105] After the voltages on the selected and unselected digit lines 515 of each level (e.g., each of the first level, the second level, the third level, and the fourth level) transition according to the applied current and the state stored at the gap fill gate of the respective first transistor 530, the pull-up enable signaling 625 can transition from high voltage to low voltage. The pull-up enable signaling 625 transitioning to low voltage can deactivate one or more of the third transistors 520-a, 520-b, and 520-c previously activated by the pull-up enable signaling transitioning to high voltage.

[0106] After the pull-up enable signaling 625 transitions back to low voltage, the word line signaling 610 can transition back from low voltage to high voltage. Transitioning to high voltage can deactivate the first transistors 530 coupled with the word line 510. Further, after the pull-up enable signaling transitions back to low voltage, the word line signaling 605 can transition from low voltage to high voltage. Transitioning from low voltage to high voltage can activate (e.g., turn on) each second transistor 525 coupled with the word line 505. Activating the second transistors 525 can enable the gap fill gate of the respective first transistor 530 to be charged by the respective digit line 515. For example, if the gap fill gate of the first transistor 530 stores a first state, then the charge stored at the gap fill gate can be recovered according to the cell floating node signaling 670-a. However, if the gap fill gate of the first transistor 530 stores a second state, then the charge stored at the gap fill gate can be recovered according to the cell floating node signaling 670-b.

[0107] In some examples, the pull-up enable signaling 625 can not transition back to the low voltage until after the word line signaling 605 transitions from the low voltage to the high voltage and back to the low voltage. In such examples, after the word line signaling 605 transitions back to the low voltage, the pull-up enable signaling 625 can transition from the high voltage to the low voltage. Additionally or alternatively, the word line signaling 610 can not transition back to the high voltage until after the word line signaling 605 transitions from the low voltage to the high voltage and back to the low voltage. In such examples, after the word line signaling transitions back to the low voltage, the word line signaling 610 can transition from the low voltage to the high voltage. Avoiding transitioning the pull-up enable signaling 625 back to the low voltage and / or avoiding transitioning the word line signaling 610 back to the high voltage until after the word line signaling 610 transitions back to the low voltage can enable the digit line 515 associated with the signaling to be actively driven (e.g., relative to enabling the digit line 515 to float) when the second transistor 525 coupled with the digit line 515 is activated.

[0108] After the charge has been restored at the gate of the respective first transistor 530, the word line signaling 605 can transition from the high voltage to the low voltage. Transitioning from the high voltage to the low voltage can deactivate each of the second transistors 525 coupled with the word line 505, thus freeing the charge on the gate of the first transistor 530 that was transferred or supplied during the time the word line signaling 605 was at the high voltage.

[0109] At 675-d or after, if the gate of the first transistor 530 of the selected digit line 515 stores the first state, the selected digit line signaling 620-a can transition to the low voltage (e.g., the voltage of the selected digit line signaling 620 before or at 675-a). Also, at 675-d or after, if the gate of the first transistor 530 of the unselected digit line 515 of the first tier, the second tier, the third tier, or the fourth tier stores the first state, the unselected digit line signaling 635-a, 645-a, 655-a, or 665-a, respectively, can transition to the low voltage (e.g., the voltage of the unselected digit line signaling 635, 645, 655, or 665, respectively, before or at 675-a).

[0110] In some examples, the circuit 500 can perform the methods described herein without performing access operations. For example, during the duration between 675-b and 675-c, the circuit 500 can refrain from performing access operations. Instead, 675-b and 675-c can occur simultaneously (e.g., the duration between 675-b and 675-c can equal 0). In some examples where access operations are not performed, the source of the SDL signaling 620 can be isolated from each digit line 515 and / or the source of the UDL signaling (e.g., unselected digit line signaling 635, 645, 655, 665) can be coupled with each digit line 515 (e.g., there can be no selected digit line 515, each digit line 515 can be an unselected digit line 515). Further, in some such examples, the source of the third level select signaling 615 can be isolated from the third level and / or the source of the third level select signaling 650 can be coupled with the third level.

[0111] Figure 7 A block diagram 700 of a memory device 720 that supports self-refresh of memory cells according to examples as disclosed herein is shown. The memory device 720 can be an example of aspects of a memory device as described with reference to Figures 1 to 6 Examples of aspects of a memory device are described. The memory device 720, or various components thereof, can be examples of means for performing various aspects of self-refresh of memory cells as described herein. For example, the memory device 720 can include a transistor activation component 725, a current application component 730, an access operation component 735, a charge recovery component 740, a latching component 745, or any combination thereof. Each of these components can communicate, directly or indirectly, with one another (e.g., via one or more buses).

[0112] The transistor activation component 725 can be configured as or otherwise support a means for applying a first voltage to a control gate of a first transistor of a memory cell, where the first voltage activates the first transistor to selectively couple a first terminal of the first transistor with a second terminal of the first transistor based at least in part on a charge stored at an interstitial gate of the first transistor, and where the first terminal of the first transistor is coupled with a bit line. The current application component 730 can be configured as or otherwise support a means for applying a current to the bit line, where a second voltage of the bit line is based at least in part on the application of the current to the bit line and the charge stored on the interstitial gate of the first transistor. In some examples, the transistor activation component 725 can be configured as or otherwise support a means for applying a third voltage to a gate of a second transistor of the memory cell to couple the bit line with the interstitial gate of the first transistor based at least in part on the application of the first voltage to the control gate of the first transistor and the application of the current to the bit line, where a first terminal of the second transistor is coupled with the bit line and a second terminal of the second transistor is coupled with the interstitial gate of the first transistor.

[0113] In some examples, the current application component 730 can be configured as or otherwise support a means for stopping the application of the current to the bit line prior to the application of the third voltage to the gate of the second transistor, where the second voltage of the bit line is based at least in part on the stopping of the application of the current.

[0114] In some examples, the transistor activation component 725 can be configured as or otherwise support a means for applying a fourth voltage to the control gate of the first transistor prior to the application of the third voltage to the gate of the second transistor, where the fourth voltage deactivates the first transistor to isolate a first terminal of the first transistor from a second terminal of the first transistor.

[0115] In some examples, the charge restoration component 740 can be configured as or otherwise support a means for restoring the charge at the interstitial gate of the first transistor based at least in part on the activation of the second transistor.

[0116] In some examples, the transistor activation component 725 can be configured as or otherwise support a means for applying a fifth voltage to the gate of the second transistor, where the fifth voltage deactivates the second transistor to isolate the bit line from an interstitial gate of the second transistor, and where the charge at the interstitial gate of the first transistor is restored based at least in part on the deactivation of the second transistor.

[0117] In some examples, the first transistor includes a P-channel metal oxide semiconductor. In some examples, the second transistor includes an N-channel metal oxide semiconductor.

[0118] In some examples, the second terminal of the first transistor is coupled with a ground of a memory array including the memory cell.

[0119] The access operation component 735 can be configured as or otherwise support a means for performing an access operation on a first memory cell of a memory array, where performing the access operation includes activating a first transistor via a first word line coupled with the first transistor, where the first memory cell is coupled with a first bit line. In some examples, the current application component 730 can be configured as or otherwise support a means for applying a current to a second bit line coupled with a second memory cell based at least in part on performing the access operation on the first memory cell, where a voltage of the second bit line is based at least in part on the current and a charge stored at an interstitial gate of a second transistor of the second memory cell. In some examples, the transistor activation component 725 can be configured as or otherwise support a means for activating a third transistor of the first memory cell and a fourth transistor of the second memory cell via a second word line coupled with the third transistor and the fourth transistor. The charge restoration component 740 can be configured as or otherwise support a means for restoring the charge stored at the interstitial gate of the second transistor based at least in part on activating the fourth transistor.

[0120] In some examples, the current application component 730 can be configured as or otherwise support a means for ceasing to apply the current to the second bit line prior to activating the fourth transistor, where the voltage of the second bit line is based at least in part on ceasing to apply the current.

[0121] In some examples, the transistor activation component 725 can be configured as or otherwise support a means for activating the second transistor prior to applying the current to the second bit line, where the voltage of the second bit line is based at least in part on activating the second transistor prior to applying the current.

[0122] In some examples, the current application component 730 can be configured as or otherwise support a means for ceasing to apply the current to the second bit line. In some examples, the transistor activation component 725 can be configured as or otherwise support a means for deactivating the second transistor after ceasing to apply the current to the second bit line, where a charge is restored at the interstitial gate of the second transistor based at least in part on deactivating the second transistor after ceasing to apply the current to the second bit line.

[0123] In some examples, the second transistor is deactivated prior to activating the fourth transistor. In some examples, a charge is restored at the interstitial gate of the second transistor based at least in part on deactivating the second transistor prior to activating the fourth transistor.

[0124] In some examples, the transistor activation component 725 can be configured as or otherwise support a means for deactivating the fourth transistor after activating the fourth transistor, where the charge is restored at the gate-last of the second transistor based at least in part on deactivating the fourth transistor after activating the fourth transistor.

[0125] In some examples, the current application component 730 can be configured as or otherwise support a means for applying a current to the first bit line based at least in part on performing an access operation on the first memory cell, where a voltage of the first bit line is based at least in part on the current and the charge stored at the gate-last of the first transistor. In some examples, the latching component 745 can be configured as or otherwise support a means for latching a representation of the voltage of the first bit line at a sense amplifier, where the first bit line and the second bit line are coupled with the sense amplifier via respective selection components.

[0126] In some examples, the first transistor and the second transistor each include a p-type transistor. In some examples, the third transistor and the fourth transistor each include an n-type transistor.

[0127] Figure 8 A flow diagram illustrating a method 800 of supporting self-refresh of a memory cell in accordance with examples as disclosed herein is shown. The operations of method 800 can be implemented by a memory device or its components as described herein. For example, the operations of method 800 can be performed by a memory device as described with reference to Figures 1 to 7 The operations of method 800 can be performed by a memory device as described with reference to FIGS. 1-6. In some examples, a memory device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0128] At 805, the method can include applying a first voltage to a control gate of a first transistor of a memory cell, where the first voltage activates the first transistor to selectively couple a first terminal of the first transistor with a second terminal of the first transistor based at least in part on a charge stored at a gate-last of the first transistor, and where the first terminal of the first transistor is coupled with a bit line. The operations of 805 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of 805 can be performed by a transistor activation component 725 as described with reference to Figure 7 FIGS. 1-6.

[0129] At 810, the method can include applying a current to a bit line, where a second voltage of the bit line is based at least in part on applying the current to the bit line and a charge stored on a gap fill gate of a first transistor. The operations of 810 can be performed according to the examples as disclosed herein. In some examples, aspects of the operations of 810 can be performed by a current application component 730 as described with reference to Figure 7 FIG. 7.

[0130] At 815, the method can include applying a third voltage to a gate of a second transistor of a memory cell to couple the bit line with a gap fill gate of the first transistor based at least in part on applying a first voltage to a control gate of the first transistor and applying a current to the bit line, where a first terminal of the second transistor is coupled with the bit line and a second terminal of the second transistor is coupled with the gap fill gate of the first transistor. The operations of 815 can be performed according to the examples as disclosed herein. In some examples, aspects of the operations of 815 can be performed by a transistor activation component 725 as described with reference to Figure 7

[0131] In some examples, an apparatus as described herein can perform a method or methods, such as method 800. The apparatus can include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for applying a first voltage to a control gate of a first transistor of a memory cell, where the first voltage activates the first transistor to selectively couple a first terminal of the first transistor with a second terminal of the first transistor based at least in part on a charge stored at a gap fill gate of the first transistor, and where the first terminal of the first transistor is coupled with a bit line; applying a current to the bit line, where a second voltage of the bit line is based at least in part on applying the current to the bit line and the charge stored on the gap fill gate of the first transistor; and applying a third voltage to a gate of a second transistor of the memory cell to couple the bit line with the gap fill gate of the first transistor based at least in part on applying the first voltage to the control gate of the first transistor and applying the current to the bit line, where a first terminal of the second transistor is coupled with the bit line and a second terminal of the second transistor is coupled with the gap fill gate of the first transistor.

[0132] Some examples of the method 800 and apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for stopping applying a current to a bit line prior to applying a third voltage to a gate of a second transistor, where a second voltage of the bit line can be based at least in part on stopping applying the current.

[0133] ​Some examples of the method 800 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for applying a fourth voltage to a control gate of the first transistor prior to applying the third voltage to the gate of the second transistor, where the fourth voltage deactivates the first transistor to isolate a first terminal of the first transistor from a second terminal of the first transistor.

[0134] Some examples of the method 800 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for restoring charge at the gap gate of the first transistor based at least in part on activating the second transistor.

[0135] Some examples of the method 800 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for applying a fifth voltage to the gate of the second transistor, where the fifth voltage deactivates the second transistor to isolate a bit line from a gap gate of the second transistor, and where charge at the gap gate of the first transistor can be restored based at least in part on deactivating the second transistor.

[0136] In some examples of the method 800 and the apparatus described herein, the first transistor includes a P-channel metal oxide semiconductor, and the second transistor includes an N-channel metal oxide semiconductor.

[0137] In some examples of the method 800 and the apparatus described herein, the second terminal of the first transistor can be coupled with a ground of a memory array including the memory cell.

[0138] Figure 9 A flow chart illustrating a method 900 of supporting self-refresh of a memory cell is shown, in accordance with examples as disclosed herein. The operations of method 900 can be implemented by a memory device or its components as described herein. For example, the operations of method 900 can be performed by a memory device as described with reference to Figures 1 to 7 The operations of method 900 can be performed by a memory device as described with reference to FIGS. 1-6. In some examples, a memory device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0139] At 905, the method can include performing an access operation on a first memory cell of a memory array, where performing the access operation includes activating a first transistor of the first memory cell via a first word line coupled with the first transistor, where the first memory cell is coupled with a first bit line. The operations of 905 can be performed according to the examples as disclosed herein. In some examples, aspects of the operations of 905 can be performed by an access operation component 735 as described with reference to Figure 7 At 905, the method can include performing an access operation on a first memory cell of a memory array, where performing the access operation includes activating a first transistor of the first memory cell via a first word line coupled with the first transistor, where the first memory cell is coupled with a first bit line. The operations of 905 can be performed according to the examples as disclosed herein. In some examples, aspects of the operations of 905 can be performed by an access operation component 735 as described with reference to

[0140] At 910, the method can include applying a current to a second bit line coupled with a second memory cell based at least in part on performing an access operation on a first memory cell, where a voltage of the second bit line is based at least in part on the current and a charge stored at a gap gate of a second transistor of the second memory cell. The operations of 910 can be performed according to and in accordance with examples as disclosed herein. In some examples, aspects of the operations of 910 can be performed by a current application component 730 as described with reference to Figure 7 At 915, the method can include activating a third transistor of the first memory cell and a fourth transistor of the second memory cell via a second word line coupled with the third transistor and the fourth transistor. The operations of 915 can be performed according to and in accordance with examples as disclosed herein. In some examples, aspects of the operations of 915 can be performed by a transistor activation component 725 as described with reference to

[0141] At 915, the method can include activating a third transistor of the first memory cell and a fourth transistor of the second memory cell via a second word line coupled with the third transistor and the fourth transistor. The operations of 915 can be performed according to and in accordance with examples as disclosed herein. In some examples, aspects of the operations of 915 can be performed by a transistor activation component 725 as described with reference to Figure 7 At 920, the method can include restoring the charge stored at the gap gate of the second transistor based at least in part on activating the fourth transistor. The operations of 920 can be performed according to and in accordance with examples as disclosed herein. In some examples, aspects of the operations of 920 can be performed by a charge restoration component 740 as described with reference to

[0142] At 920, the method can include restoring the charge stored at the gap gate of the second transistor based at least in part on activating the fourth transistor. The operations of 920 can be performed according to and in accordance with examples as disclosed herein. In some examples, aspects of the operations of 920 can be performed by a charge restoration component 740 as described with reference to Figure 7 In some examples, an apparatus as described herein can perform one or more methods, such as method 900. The apparatus can include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing an access operation on a first memory cell of a memory array, where performing the access operation includes activating a first transistor of the first memory cell via a first word line coupled with the first transistor, where the first memory cell is coupled with a first bit line; applying a current to a second bit line coupled with a second memory cell based at least in part on performing the access operation on the first memory cell, where a voltage of the second bit line is based at least in part on the current and a charge stored at a gap gate of a second transistor of the second memory cell; activating a third transistor of the first memory cell and a fourth transistor of the second memory cell via a second word line coupled with the third transistor and the fourth transistor; and restoring the charge stored at the gap gate of the second transistor based at least in part on activating the fourth transistor.

[0143] In some examples, an apparatus as described herein can perform one or more methods, such as method 900. The apparatus can include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing an access operation on a first memory cell of a memory array, where performing the access operation includes activating a first transistor of the first memory cell via a first word line coupled with the first transistor, where the first memory cell is coupled with a first bit line; applying a current to a second bit line coupled with a second memory cell based at least in part on performing the access operation on the first memory cell, where a voltage of the second bit line is based at least in part on the current and a charge stored at a gap gate of a second transistor of the second memory cell; activating a third transistor of the first memory cell and a fourth transistor of the second memory cell via a second word line coupled with the third transistor and the fourth transistor; and restoring the charge stored at the gap gate of the second transistor based at least in part on activating the fourth transistor.

[0144] Some examples of the method 900 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for stopping applying a current to a second bit line prior to activating a fourth transistor, where a voltage of the second bit line can be based at least in part on stopping applying the current.

[0145] Some examples of the method 900 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for activating a second transistor prior to applying a current to a second bit line, where a voltage of the second bit line can be based at least in part on activating the second transistor prior to applying the current.

[0146] Some examples of the method 900 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for stopping applying a current to a second bit line and deactivating a second transistor after stopping applying the current to the second bit line, where a charge at a grain boundary gate of the second transistor can be recovered based at least in part on deactivating the second transistor after stopping applying the current to the second bit line.

[0147] In some examples of the method 900 and the apparatus described herein, a second transistor can be deactivated prior to a fourth transistor being activated, and a charge at a grain boundary gate of the second transistor can be recovered based at least in part on deactivating the second transistor prior to the fourth transistor being activated.

[0148] Some examples of the method 900 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for deactivating a fourth transistor after activating the fourth transistor, where a charge at a grain boundary gate of a second transistor can be recovered based at least in part on deactivating the fourth transistor after activating the fourth transistor.

[0149] Some examples of the method 900 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for applying a current to a first bit line based at least in part on performing an access operation on a first memory cell, where a voltage of the first bit line can be based at least in part on the current and a charge stored at a grain boundary gate of a first transistor; and latching a representation of the voltage of the first bit line at a sense amplifier, where the first bit line and a second bit line can be coupled with the sense amplifier via respective selection components.

[0150] In some examples of the method 900 and the apparatus described herein, the first transistor and the second transistor each include a p-type transistor, and the third transistor and the fourth transistor each include an n-type transistor.

[0151] It should be noted that the methods described herein describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Further, portions from two or more methods can be combined.

[0152] An apparatus is described. The apparatus can include a memory cell including a first transistor including a control gate and a gap fill gate, wherein a first terminal of the first transistor is coupled with a bit line, a second transistor, wherein a first terminal of the second transistor is coupled with the bit line and a second terminal of the second transistor is coupled with the gap fill gate of the first transistor, and a controller coupled with the memory cell. The controller can be configured to apply a first voltage to the control gate of the first transistor, wherein the first voltage activates the first transistor to selectively couple the first terminal of the first transistor with a second terminal of the first transistor based at least in part on a charge stored on the gap fill gate, apply a current to the bit line, wherein a second voltage of the bit line is based at least in part on applying the current to the bit line and the charge stored on the gap fill gate of the first transistor, and apply a third voltage to a gate of the second transistor to couple the bit line with the gap fill gate of the first transistor based at least in part on applying the first voltage to the control gate of the first transistor and applying the current to the bit line.

[0153] In some examples, the controller can be further configured to stop applying the current to the bit line prior to applying the third voltage to the gate of the second transistor, wherein a second voltage of the bit line can be based at least in part on stopping the application of the current.

[0154] In some examples, the controller can be further configured to apply a fourth voltage to a control gate of a first transistor prior to applying the third voltage to the gate of the second transistor, wherein the fourth voltage deactivates the first transistor to isolate a first terminal of the first transistor from a second terminal of the first transistor.

[0155] In some examples of an apparatus, the charge at the gap fill gate of the first transistor can be restored based at least in part on activating the second transistor.

[0156] In some examples, the controller can be further configured to apply a fifth voltage to a gate of the second transistor, wherein the fifth voltage deactivates the second transistor to isolate the bit line from a gap fill gate of the second transistor, and wherein the charge at the gap fill gate of the first transistor can be restored based at least in part on deactivating the second transistor.

[0157] In some examples of the apparatus, the first transistor includes a P-channel metal oxide semiconductor and the second transistor includes an N-channel metal oxide semiconductor.

[0158] In some examples of the apparatus, the second terminal of the first transistor can be coupled with a ground of the memory device.

[0159] Another apparatus is described. The apparatus can include a memory array including a first word line coupled with a first transistor of a first memory cell and a second transistor of a second memory cell, a second word line coupled with a third transistor of the first memory cell and a fourth transistor of the second memory cell, a first bit line coupled with the first memory cell, a second bit line coupled with the second memory cell, and a controller coupled with the memory array. The controller is configured to perform an access operation on the first memory cell, where performing the access operation includes activating the first transistor via the first word line, applying a current to the second bit line based at least in part on performing the access operation on the first memory cell, where a voltage of the second bit line is based at least in part on the current and a charge stored at a gap fill gate of the second transistor, and activating the third transistor and the fourth transistor via the second word line, where activating the fourth transistor recovers the charge stored at the gap fill gate of the second transistor.

[0160] In some examples, the controller can be further configured to stop applying a current to a second bit line prior to activating the fourth transistor, where a voltage of the second bit line can be based at least in part on stopping the application of the current.

[0161] In some examples, the controller can be further configured to activate a second transistor prior to applying a current to a second bit line, where a voltage of the second bit line can be based at least in part on activating the second transistor prior to the application of the current.

[0162] In some examples, the controller can be further configured to stop applying a current to the second bit line and deactivate the second transistor after stopping the application of the current to the second bit line, where a charge can be recovered at a gap fill gate of the second transistor based at least in part on deactivating the second transistor after stopping the application of the current to the second bit line.

[0163] In some examples of the apparatus, the second transistor can be deactivated prior to the fourth transistor being activatable, and a charge can be recovered at the gap fill gate of the second transistor based at least in part on deactivating the second transistor prior to the fourth transistor being activatable.

[0164] In some examples, the controller can be further configured to deactivate the fourth transistor after activating the fourth transistor, wherein the charge at the gap gate of the second transistor can be restored based at least in part on deactivating the fourth transistor after activating the fourth transistor.

[0165] In some examples, the controller can be further configured to apply a current to a first bit line based at least in part on performing an access operation on a first memory cell, wherein a voltage of the first bit line can be based at least in part on the current and a charge stored at a gap gate of the first transistor and a representation of the voltage of the first bit line is latched at a sense amplifier, wherein the first bit line and a second bit line can be coupled with the sense amplifier via respective selection components.

[0166] In some examples, the apparatus can include a set of bit lines including a first bit line and a second bit line and a set of sense amplifiers, wherein each bit line of the set of bit lines can be coupled with a sense amplifier of the set of sense amplifiers via a respective switching component, and wherein a total amount of bit lines of the set of bit lines can be greater than a total amount of sense amplifiers of the set of sense amplifiers.

[0167] In some examples of an apparatus, the first transistor and the second transistor each include a p-type transistor, and the third transistor and the fourth transistor each include an n-type transistor.

[0168] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields, or particles, optical fields, or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, such signals can represent a bus of signals, where buses can have a variety of bit widths.

[0169] The terms "in electronic communication," "electrically conductive contact," "connected," and "coupled" can refer to a relationship between components in which the components support the flow of signals between the components. Components are considered to be in electronic communication with each other (or in electrically conductive contact with each other or connected to each other or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. The conductive path between components that are in electronic communication with each other (or in electrically conductive contact with each other or connected to each other or coupled to each other) at any given time can be an open or closed circuit based on the operation of the device that includes the connected components. The conductive path between connected components can be a direct conductive path between the components, or the conductive path between connected components can be an indirect conductive path that can include intervening components (such as switches, transistors, or other components). In some examples, the flow of signals between connected components can be interrupted for a period of time, for example, using one or more intervening components (such as switches or transistors).

[0170] The term "coupled" refers to the state of moving from an open circuit relationship between components (in which signals cannot currently pass between the components through a conductive path) to a closed circuit relationship between the components (in which signals can pass between the components through a conductive path). When a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components through a conductive path in which signals were not previously allowed to flow.

[0171] The term "isolated" refers to a relationship between components in which signals cannot currently flow between the components. Components are isolated from each other if there is an open circuit between them. For example, two components that are separated from each other by a switch positioned between the components are isolated from each other when the switch is open. When a controller isolates two components, the controller brings about a change that prevents signals from flowing between the components using a conductive path in which signals were previously permitted to flow.

[0172] The term "layer" or "layer stage" as used herein refers to a layer or sheet of a geometric structure (e.g., with respect to a substrate). Each layer or layer stage can have three dimensions (e.g., height, width, and depth) and can cover at least a portion of a surface. For example, a layer or layer stage can be a three-dimensional structure in which two dimensions are greater than a third dimension, such as a thin film. Layers or layer stages can include different elements, components, and / or materials. In some examples, one layer or layer stage can be composed of two or more sub-layers or sub-layer stages.

[0173] As used herein, the term "substantially" means that the modified characteristic (e.g., the verb or adjective modified by the term substantially) need not be absolute but is close enough to the intended characteristic to achieve the advantage.

[0174] As used herein, the term "electrode" can refer to an electrical conductor and, in some instances, can be used as an electrical contact to a memory cell or other component of a memory array. Electrodes can include traces, wires, conductive lines, conductive layers, or the like that provide a conductive path between elements or components of the memory array.

[0175] The devices discussed herein, including memory arrays, can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species, including (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0176] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0177] The descriptions set forth herein, together with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description," and not "preferred" or "superior to other instances." The detailed description includes specific details used to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0178] In the drawings, like reference numerals can be used to denote similar components throughout the several views. Additionally, various components of the same type can be distinguished by following the convention of placing the primary reference number in the hundreds column and a differentiation digit in the tens column. For example, 205 can be used to denote a component that differs from 205A, 205B, and 205C, in which the primary reference number is 205, and the differentiation digit is 'A', 'B', and 'C', respectively. If only the primary reference number is used in the specification, the description is applicable to any one of the comparable components having the same primary reference number irrespective of the differentiation digit.

[0179] The functions described herein can be implemented in hardware, software, or any combination thereof. If implemented in software, the functions can be stored on or transmitted over a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

[0180] The various illustrative blocks and modules described in connection with the disclosure herein can be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other configuration).

[0181] As used herein, including in the claims, "or" as used in a list of items prefaced by "at least one of" indicates a disjunctive list such that, for example, a list of "at least one of A, B, or C" means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" is not exclusive of the option of a group of items preceding "based on." For example, a process described as "based on conditions A and B" can be based on both A and B, or based on just A if A is satisfied. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0182] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program elements in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0183] The description herein is presented to enable a person of ordinary skill in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those of ordinary skill in the art, and the general principles defined herein can be applied to other variations without departing from the scope of the disclosure. Therefore, the disclosure is not to be limited to the examples and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device, comprising: a memory cell, comprising: a first transistor comprising a control gate and an interstitial gate, wherein a first terminal of the first transistor is coupled with a bit line; and a second transistor, wherein a first terminal of the second transistor is coupled with the bit line and a second terminal of the second transistor is coupled with the interstitial gate of the first transistor; and a controller coupled with the memory cell and configured to: apply a first voltage to the control gate of the first transistor using a first word line coupled with the first transistor, wherein the first voltage activates the first transistor to selectively couple the first terminal of the first transistor with a second terminal of the first transistor based at least in part on a charge stored on the interstitial gate; apply a current to the bit line, wherein a second voltage of the bit line is based at least in part on the application of the current to the bit line and the charge stored on the interstitial gate of the first transistor; and apply a third voltage to a gate of the second transistor to couple the bit line with the interstitial gate of the first transistor based at least in part on the application of the first voltage to the control gate of the first transistor and the application of the current to the bit line, wherein the third voltage is applied by a second word line coupled with the second transistor, wherein the second word line is different than the first word line.

2. The memory device of claim 1, wherein the controller is further configured to: stop the application of the current to the bit line prior to applying the third voltage to the gate of the second transistor, wherein the second voltage of the bit line is based at least in part on the stopping of the application of the current.

3. The memory device of claim 1, wherein the controller is further configured to: apply a fourth voltage to the control gate of the first transistor prior to applying the third voltage to the gate of the second transistor, wherein the fourth voltage deactivates the first transistor to isolate the first terminal of the first transistor from the second terminal of the first transistor.

4. The memory device of claim 1, wherein the charge at the interstitial gate of the first transistor is restored based at least in part on activating the second transistor.

5. The memory device of claim 4, wherein the controller is further configured to: apply a fifth voltage to the gate of the second transistor, wherein the fifth voltage deactivates the second transistor to isolate the bit line from the interstitial gate of the first transistor, and wherein the charge at the interstitial gate of the first transistor is restored based at least in part on deactivating the second transistor.

6. The memory device of claim 1, wherein: the first transistor comprises a P-channel metal oxide semiconductor, and the second transistor comprises an N-channel metal oxide semiconductor.

7. The memory device of claim 1, wherein the second terminal of the first transistor is coupled with a ground of the memory device.

8. An apparatus comprising: a memory array comprising: a first word line coupled with a first transistor of a first memory cell and a second transistor of a second memory cell; a second word line coupled with a third transistor of the first memory cell and a fourth transistor of the second memory cell, wherein the second word line is different than the first word line; a first bit line coupled with the first memory cell; and a second bit line coupled with the second memory cell; and a controller coupled with the memory array and configured to: perform an access operation on the first memory cell, wherein performing the access operation comprises activating the first transistor via the first word line; apply a current to the second bit line based at least in part on performing the access operation on the first memory cell, wherein a voltage of the second bit line is based at least in part on the current and a charge stored at an interstitial gate of the second transistor; and activate the third transistor and the fourth transistor via the second word line, wherein activating the fourth transistor recovers the charge stored at the interstitial gate of the second transistor.

9. The apparatus of claim 8, wherein the controller is further configured to: stop applying the current to the second bit line prior to activating the fourth transistor, wherein the voltage of the second bit line is based at least in part on stopping the application of the current.

10. The apparatus of claim 8, wherein the controller is further configured to: activate the second transistor prior to applying the current to the second bit line, wherein the voltage of the second bit line is based at least in part on activating the second transistor prior to applying the current.

11. The apparatus of claim 10, wherein the controller is further configured to: stop applying the current to the second bit line; and deactivate the second transistor after stopping the application of the current to the second bit line, wherein the charge is recovered at the interstitial gate of the second transistor based at least in part on deactivating the second transistor after stopping the application of the current to the second bit line.

12. The apparatus of claim 11, wherein: the second transistor is deactivated prior to activating the fourth transistor, and the charge is recovered at the interstitial gate of the second transistor based at least in part on deactivating the second transistor prior to activating the fourth transistor.

13. The apparatus of claim 8, wherein the controller is further configured to: deactivate the fourth transistor after activating the fourth transistor, wherein the charge is recovered at the interstitial gate of the second transistor based at least in part on deactivating the fourth transistor after activating the fourth transistor.

14. The apparatus of claim 8, wherein to perform the access operation on the first memory cell, the controller is further configured to: apply the current to the first bit line based at least in part on performing the access operation on the first memory cell, wherein a voltage of the first bit line is based at least in part on the current and a charge stored at a gap fill gate of the first transistor; and latch a representation of the voltage of the first bit line at a sense amplifier, wherein the first bit line and the second bit line are coupled with the sense amplifier via respective selection components.

15. The apparatus of claim 8, further comprising: a set of bit lines including the first bit line and the second bit line; and a set of sense amplifiers, wherein each bit line of the set of bit lines is coupled with a sense amplifier of the set of sense amplifiers via a respective switching component, and wherein a total amount of bit lines of the set of bit lines is greater than a total amount of sense amplifiers of the set of sense amplifiers.

16. The apparatus of claim 8, wherein: the first transistor and the second transistor each comprise a p-type transistor, and the third transistor and the fourth transistor each comprise an n-type transistor.

17. A method comprising: applying a first voltage to a control gate of a first transistor of a memory cell using a first word line coupled with the first transistor, wherein the first voltage activates the first transistor to selectively couple a first terminal of the first transistor with a second terminal of the first transistor based at least in part on a charge stored at a gap fill gate of the first transistor, and wherein the first terminal of the first transistor is coupled with a bit line; applying a current to the bit line, wherein a second voltage of the bit line is based at least in part on applying the current to the bit line and the charge stored on the gap fill gate of the first transistor; and applying a third voltage to a gate of a second transistor of the memory cell to couple the bit line with the gap fill gate of the first transistor based at least in part on applying the first voltage to the control gate of the first transistor and applying the current to the bit line, wherein the third voltage is applied by a second word line coupled with the second transistor, wherein the second word line is different than the first word line, and wherein a first terminal of the second transistor is coupled with the bit line and a second terminal of the second transistor is coupled with the gap fill gate of the first transistor.

18. The method of claim 17, further comprising: stopping applying the current to the bit line prior to applying the third voltage to the gate of the second transistor, wherein the second voltage of the bit line is based at least in part on stopping applying the current.

19. The method of claim 17, further comprising: applying a fourth voltage to the control gate of the first transistor prior to applying the third voltage to the gate of the second transistor, wherein the fourth voltage deactivates the first transistor to isolate the first terminal of the first transistor from the second terminal of the first transistor.

20. The method of claim 17, further comprising: restoring the charge at the trap gate of the first transistor based at least in part on activating the second transistor.

21. The method of claim 20, further comprising: applying a fifth voltage to the gate of the second transistor, wherein the fifth voltage deactivates the second transistor to isolate the bit line from the trap gate of the first transistor, and wherein the charge at the trap gate of the first transistor is restored based at least in part on deactivating the second transistor.

22. The method of claim 17, wherein: the first transistor comprises a P-channel metal oxide semiconductor, and the second transistor comprises an N-channel metal oxide semiconductor.

23. The method of claim 17, wherein the second terminal of the first transistor is coupled to a ground of a memory array comprising the memory cell.

24. A method, comprising: performing an access operation on a first memory cell of a memory array, wherein performing the access operation comprises activating a first transistor of the first memory cell via a first word line coupled to the first transistor, wherein the first memory cell is coupled to a first bit line; applying a current to a second bit line coupled to a second memory cell based at least in part on performing the access operation on the first memory cell, wherein a voltage of the second bit line is based at least in part on the current and a charge stored at a trap gate of a second transistor of the second memory cell; activating a third transistor of the first memory cell and a fourth transistor of the second memory cell via a second word line coupled to the third transistor and the fourth transistor, wherein the second word line is different than the first word line; and restoring the charge stored at the trap gate of the second transistor based at least in part on activating the fourth transistor.

25. The method of claim 24, further comprising: stopping applying the current to the second bit line prior to activating the fourth transistor, wherein the voltage of the second bit line is based at least in part on stopping applying the current.

26. The method of claim 24, further comprising: activating the second transistor prior to applying the current to the second bit line, wherein the voltage of the second bit line is based at least in part on activating the second transistor prior to applying the current.

27. The method of claim 26, further comprising: stopping applying the current to the second bit line; and and deactivating the second transistor after ceasing to apply the current to the second bit line, wherein the charge is restored at the interstitial gate of the second transistor based at least in part on deactivating the second transistor after ceasing to apply the current to the second bit line.

28. The method of claim 27, wherein: deactivating the second transistor before activating the fourth transistor, and restoring the charge at the interstitial gate of the second transistor based at least in part on deactivating the second transistor before activating the fourth transistor.

29. The method of claim 24, further comprising: deactivating the fourth transistor after activating the fourth transistor, wherein the charge is restored at the interstitial gate of the second transistor based at least in part on deactivating the fourth transistor after activating the fourth transistor.

30. The method of claim 24, further comprising: applying the current to the first bit line based at least in part on performing the access operation on the first memory cell, wherein a voltage of the first bit line is based at least in part on the current and a charge stored at an interstitial gate of the first transistor; and latching a representation of the voltage of the first bit line at a sense amplifier, wherein the first bit line and the second bit line are coupled with the sense amplifier via respective selection components.

31. The method of claim 24, wherein: the first transistor and the second transistor each comprise a p-type transistor, and the third transistor and the fourth transistor each comprise an n-type transistor.

32. A non-transitory computer-readable medium comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: apply a first voltage to a control gate of a first transistor of a memory cell using a first word line coupled with the first transistor, wherein the first voltage activates the first transistor to selectively couple a first terminal of the first transistor with a second terminal of the first transistor based at least in part on a charge stored at an interstitial gate of the first transistor, and wherein the first terminal of the first transistor is coupled with a bit line; apply a current to the bit line, wherein a second voltage of the bit line is based at least in part on applying the current to the bit line and the charge stored on the interstitial gate of the first transistor; and apply a third voltage to a gate of a second transistor of the memory cell to couple the bit line with the interstitial gate of the first transistor based at least in part on applying the first voltage to the control gate of the first transistor and applying the current to the bit line, wherein the third voltage is applied by a second word line coupled with the second transistor, wherein the second word line is different than the first word line, and wherein a first terminal of the second transistor is coupled with the bit line and a second terminal of the second transistor is coupled with the interstitial gate of the first transistor.

33. The non-transitory computer-readable medium of claim 32, wherein the instructions, which when executed by the processor of the electronic device, further cause the electronic device to stop applying the current to the bit line prior to applying the third voltage to the gate of the second transistor, wherein the second voltage of the bit line is based at least in part on stopping the application of the current.

34. The non-transitory computer-readable medium of claim 32, wherein the instructions, which when executed by the processor of the electronic device, further cause the electronic device to apply a fourth voltage to the control gate of the first transistor prior to applying the third voltage to the gate of the second transistor, wherein the fourth voltage deactivates the first transistor to isolate the first terminal of the first transistor from the second terminal of the first transistor.

35. The non-transitory computer-readable medium of claim 32, wherein the instructions, which when executed by the processor of the electronic device, further cause the electronic device to restore the charge at the gap fill gate of the first transistor based at least in part on activating the second transistor.

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