A data write method for flash memory and related device

Abstract

The application provides a data writing method of a flash memory and a related device, which is applied to a controller, the controller comprises a linked list, and the method comprises the following steps: the controller receives first data and a first address sent by a central processing unit; in the process of storing the first data, the controller can receive multiple second data and multiple second addresses sent by the central processing unit and store the multiple second data and the multiple second addresses to the linked list; the controller can directly load each second data from the linked list, and the central processing unit does not need to wait for each writing operation to be completed before initiating the next writing operation; in the process of storing each second data to a second address of the flash memory, only the controller needs to be processed; before the controller stores all the second data to the flash memory, the central processing unit can not participate in the specific storage process of the second data, so that the time of the writing operation occupying the central processing unit is reduced, the data writing efficiency is improved, and the system efficiency and the system performance are improved.

Description

Technical Field

[0001] This invention relates to the field of data storage, and in particular to a data writing method and related apparatus for a flash memory. Background Technology

[0002] Current controllers integrate embedded flash memory to improve the operating efficiency of systems including the controller. The Central Processing Unit (CPU) can store data in the flash memory through the controller, a process that is a single write operation. However, current flash memory only supports a single write operation for data at the same address. This means that when you want to store data at multiple addresses in the flash memory, you need to perform multiple write operations on these addresses separately. During one write operation, data at other addresses must wait for that write operation to complete before it can be stored sequentially.

[0003] This means that each write operation can only store data at one address in the flash memory, causing the CPU to be in the process of repeatedly performing write operations for a long time. In other words, write operations occupy too much CPU time, which in turn affects system efficiency and reduces system performance. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a data writing method and related apparatus for flash memory, which can reduce the time occupied by the central processing unit during write operations, improve data writing efficiency, and thus improve system efficiency and system performance.

[0005] This application provides a data writing method for a flash memory, applied to a controller, the controller including a linked list, the method comprising:

[0006] The controller receives first data and a first address sent by the central processing unit;

[0007] The controller stores the first data in a first address of the flash memory. The controller receives multiple second data and multiple second addresses sent by the central processing unit and stores the multiple second data and multiple second addresses in the linked list.

[0008] The controller loads each piece of the second data and its corresponding second address from the linked list, and sequentially stores each piece of the second data into the second address of the flash memory, until the controller stores all the second data into the flash memory.

[0009] Optionally, the controller receives multiple second data and multiple second addresses sent by the central processing unit, and stores the multiple second data and multiple second addresses into the linked list, including:

[0010] The controller receives multiple second data and multiple second addresses sent by the central processing unit;

[0011] The controller matches multiple sets of the second data and multiple sets of the second addresses, and stores the second data and the second addresses in the linked list according to the matching relationship between each set of the second data and each set of the second addresses.

[0012] Optionally, the controller receives multiple second data and multiple second addresses sent by the central processing unit, and stores the multiple second data and multiple second addresses into the linked list;

[0013] The controller loads each piece of second data and the corresponding second address from the linked list, including:

[0014] The controller receives multiple second data and multiple second addresses sent by the central processing unit. After storing all the multiple second data and multiple second addresses into the linked list, the controller loads each second data and the corresponding second address from the linked list.

[0015] Optionally, the controller receives multiple second data and multiple second addresses sent by the central processing unit, and stores the multiple second data and multiple second addresses into the linked list;

[0016] The controller loads each piece of second data and the corresponding second address from the linked list, including:

[0017] The controller receives multiple second data and multiple second addresses sent by the central processing unit in chronological order. During the process of storing the multiple second data and multiple second addresses into the linked list in the chronological order, the controller loads each second data and the second address corresponding to the second data from the linked list in the chronological order.

[0018] Optionally, after the controller stores all of the second data in the flash memory, the method further includes:

[0019] The controller sends a data write completion signal to the central processing unit.

[0020] Optionally, before the controller stores the first data to a first address in the flash memory, the method further includes:

[0021] The controller converts the data format of the first data and the data format of the first address into the data format corresponding to the flash memory.

[0022] Optionally, the controller receiving the first data and the first address sent by the central processing unit includes:

[0023] The controller receives the first data and the first address sent by the central processing unit using the Advanced High Performance AHB bus.

[0024] This application provides a data writing system for a flash memory, the system including a controller; the controller includes a bus control unit interface unit, a linked list control unit, and a flash memory interface control unit;

[0025] The bus control unit interface unit is used to receive first data and a first address sent by the central processing unit; the bus control unit interface unit is used to receive multiple second data and multiple second addresses sent by the central processing unit.

[0026] The flash memory interface control unit is used to store the first data to a first address of the flash memory, and the linked list control unit is used to store multiple sets of the second data and multiple sets of the second addresses to the linked list;

[0027] The flash memory interface control unit is used to load each second data and the second address corresponding to the second data from the linked list, and sequentially store each second data to the second address of the flash memory, until the flash memory interface control unit stores all the second data to the flash memory.

[0028] Optionally, the system further includes: a register configuration unit;

[0029] The register configuration unit is used to configure the control logic of the controller and indicate the operating status of the flash memory.

[0030] This application provides a computer-readable storage medium including instructions that, when executed on a computer, cause the computer to perform the method as described in any of the above embodiments.

[0031] This application provides a data writing method for a flash memory, applied to a controller. The controller includes a linked list. The method includes: the controller receiving first data and a first address sent by a central processing unit (CPU), i.e., the CPU triggers the first write operation and sends the first data and the first address of the first write operation to the controller. The controller can store the first data in the flash memory at the first address, i.e., the first address identifies the storage location of the first data in the flash memory. During the process of the controller storing the first data, the controller can also receive multiple second data and multiple second addresses sent by the central processing unit (CPU). This means the CPU can initiate multiple write operations during the first write operation. The multiple second data and addresses included in these write operations can be stored in a linked list within the controller. Subsequently, the controller can directly load each second data and its corresponding second address from the linked list, without the CPU needing to wait for each write operation to complete before initiating the next. By storing the second data and addresses from multiple write operations in a linked list, the controller only needs to handle the actual storage of each second data at its corresponding address in the flash memory. Until the controller has stored all the second data in the flash memory, the CPU does not need to participate in the actual storage process, thus reducing the CPU time spent on write operations, improving data writing efficiency, and ultimately improving system efficiency and performance. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 A data write timing diagram is shown;

[0034] Figure 2 A schematic flowchart of a data writing method for a flash memory provided in an embodiment of this application is shown;

[0035] Figure 3 This illustration shows a data writing timing diagram provided in an embodiment of this application;

[0036] Figure 4 A schematic diagram of the structure of a flash memory data writing system provided in an embodiment of this application is shown. Detailed Implementation

[0037] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0038] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0039] Current controllers integrate embedded flash memory to improve the operating efficiency of systems including the controller. The central processing unit (CPU) can store data in the flash memory through the controller in a single write operation.

[0040] However, current flash memory only supports a single write operation for data at the same address. This means that when you want to store data at multiple addresses in flash memory, you need to perform multiple write operations on these addresses separately. During one write operation, data at other addresses must wait for that write operation to complete before it can be stored sequentially. In other words, if you need to store data at multiple addresses, the CPU needs to initiate multiple write operations. Each write operation must wait for the flash memory to complete storing the data from the previous write operation, and for the controller to send a write completion flag to the CPU before the CPU can initiate the next write operation.

[0041] refer to Figure 1 The diagram shows a data write timing sequence. As can be seen, after the central processing unit sends the first address 800_a822 and the first data 2, the controller begins the first write operation. `flash_sr_bsy` is set to 1, and the controller stores the first data 2 into the flash memory based on the first address 800_a822. During the first write operation, a second write operation to the flash memory cannot be initiated. If a second write operation is initiated during the first write operation, `hready` will be pulled low from a high-order bit to a low-order bit until the first write operation is completed and `flash_sr_bsy` is set to 0, at which point a second write operation can be initiated.

[0042] This means that each write operation can only store data at one address in the flash memory, causing the CPU to be in the process of repeatedly performing write operations for a long time. In other words, write operations occupy too much CPU time, which in turn affects system efficiency and reduces system performance.

[0043] Based on this, this application provides a data writing method for flash memory, applied to a controller. The controller includes a linked list. The method includes: the controller receiving first data and a first address sent by a central processing unit (CPU), i.e., the CPU triggers the first write operation and sends the first data and the first address of the first write operation to the controller. The controller can store the first data in the first address of the flash memory, i.e., the first address identifies the storage location of the first data in the flash memory. During the process of the controller storing the first data, the controller can also receive multiple second data and multiple second addresses sent by the central processing unit (CPU). This means the CPU can initiate multiple write operations during the first write operation. The multiple second data and addresses included in these write operations can be stored in a linked list within the controller. Subsequently, the controller can directly load each second data and its corresponding second address from the linked list, without the CPU needing to wait for each write operation to complete before initiating the next. By storing the second data and addresses from multiple write operations in a linked list, the controller only needs to handle the actual storage of each second data at its corresponding address in the flash memory. Until the controller has stored all the second data in the flash memory, the CPU does not need to participate in the actual storage process, thus reducing the CPU time spent on write operations, improving data writing efficiency, and ultimately improving system efficiency and performance.

[0044] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0045] See Figure 2 The figure is a schematic flowchart of a data writing method for a flash memory provided in an embodiment of this application.

[0046] The flash memory data writing method provided in this embodiment can be applied to a controller, which includes a linked list for data caching. The controller can communicate with a central processing unit (CPU); specifically, the CPU can communicate with the controller using an Advanced High Performance (AHB) bus. The controller can also communicate with the flash memory to store data. The flash memory can be embedded within the controller.

[0047] The data writing method for flash memory provided in this embodiment includes the following steps:

[0048] S101, the controller receives the first data and the first address sent by the central processing unit.

[0049] In embodiments of this application, the controller can receive a first write operation initiated by the central processing unit. The first write operation includes first data and a first address. The first data is data to be stored in the flash memory, and the first address is the address where the first data is to be stored in the flash memory.

[0050] Specifically, the controller can receive the first data and the first address sent by the central processing unit (CPU) via the AHB bus. Due to the communication protocol of the AHB bus, the first data and the first address are sent separately. When the controller and CPU communicate using other bus protocols, the data transmission requirements for the first data and the first address can be adjusted according to that bus protocol.

[0051] S102, the controller stores the first data into the first address of the flash memory, the controller receives multiple second data and multiple second addresses sent by the central processing unit, and stores the multiple second data and multiple second addresses into a linked list.

[0052] In the embodiments of this application, after receiving the first data and the first address, the controller can perform a first write operation to store the first data in the flash memory at the first address, that is, store the first data in the flash memory according to the first address.

[0053] In the embodiments of this application, when the controller performs the first write operation, the central processing unit (CPU) can also initiate multiple write operations. For example, the CPU can initiate a second write operation, which includes a second piece of data and a second address. That is, each write operation includes a second piece of data and a second address. The multiple second pieces of data and multiple second addresses included in the multiple write operations initiated by the CPU can be stored in a linked list. In other words, the controller can cache multiple pieces of data and multiple second addresses in the linked list. This way, the CPU is not limited by the flash memory storing only one address of data at a time. The CPU can repeatedly execute write operations over a long period, reducing the time occupied by write operations on the CPU, improving data writing efficiency, and thus improving system efficiency and performance.

[0054] In other words, after receiving the first data and the first address, the controller can also receive multiple second data and multiple second addresses sent by the central processing unit. While storing the first data in the flash memory according to the first address, the received second data and second addresses can be stored in the linked list, thereby freeing up the central processing unit, which can temporarily process other operations.

[0055] As one possible implementation, after the controller receives multiple second data and multiple second addresses sent by the central processing unit, it matches the multiple second data and multiple second addresses to obtain the matching relationship between each second data and each second address. The second data and second address are stored in a linked list according to the matching relationship between each second data and each second address. This makes it convenient to use the one-to-one corresponding second address to store the second data later, avoids the second data being stored in the wrong second address, and improves the accuracy of data writing.

[0056] It should be noted that before the controller stores the first data to the first address of the flash memory, the data format can be converted first to the data format of the first data and the data format of the first address, so as to facilitate the storage of the first data in the data format corresponding to the flash memory.

[0057] Accordingly, before storing multiple second data into the flash memory, the controller also converts the data format of the second data and the data format of the second address into the data format corresponding to the flash memory, so as to facilitate storing the second data in the data format corresponding to the flash memory.

[0058] S103, the controller loads each second data and the second address corresponding to the second data from the linked list, and stores each second data to the second address of the flash memory in sequence, until the controller stores all the second data to the flash memory.

[0059] In the embodiments of this application, after the controller receives multiple second data and the second address corresponding to the second data, the central processing unit is released. That is, the central processing unit initiates multiple write operations in a short period of time, and the subsequent write operation process does not require the participation of the central processing unit. The controller can directly execute multiple write operations.

[0060] After the controller stores the first data at the first address into the flash memory, the first write operation is complete. The controller then loads each second data item and its corresponding second address from the linked list, storing each second data item sequentially into the second address of the flash memory, until all the second data items are stored in the flash memory. In other words, after storing one piece of second data in the flash memory, the next piece of second data to be stored is loaded from the linked list, until all the second data in the linked list has been loaded, indicating that all the second data in the linked list has been stored in the flash memory. During this process, no central processing unit (CPU) is required, reducing the CPU time occupied by write operations.

[0061] In the embodiments of this application, the controller stores the second data after all the second data has been received, or the controller stores the second data during the process of receiving multiple pieces of second data. The details are as follows:

[0062] In one possible implementation, the controller receives multiple sets of second data and multiple second addresses from the central processing unit (CPU). After storing all the second data and addresses into a linked list, the controller loads each set of second data and its corresponding second address from the linked list and then sequentially stores the second data into flash memory. In other words, the controller performs all write operations only after the CPU has initiated all write operations and sent all the second data and addresses, storing one set of second data into flash memory each time.

[0063] As another possible implementation, the controller receives multiple sets of second data and multiple second addresses sent by the central processing unit (CPU) in chronological order, and stores these sets of data and addresses in a linked list in the same order. During this process, the controller loads each set of second data and its corresponding second address from the linked list in chronological order, and then stores the second data into flash memory sequentially. In other words, during multiple write operations initiated by the CPU—that is, during the process of the CPU sending multiple sets of second data and addresses—the controller can first perform data writing on a portion of the second data already cached in the linked list, specifically loading the corresponding second data according to the chronological order of the second data cached in the linked list.

[0064] In the embodiments of this application, after the controller stores all the second data into the flash memory, the controller can send a data write completion signal to the central processing unit. After receiving the data write completion signal, the central processing unit can end the write operation of multiple second data initiated by the central processing unit, thereby finally completing the write operation of multiple data.

[0065] To implement the data writing method provided in this application embodiment, the controller can be configured in advance, such as unlocking the flash memory and configuring the controller's control logic.

[0066] refer to Figure 3The diagram shown is a timing diagram provided in an embodiment of this application. As can be seen from the diagram, after the central processing unit (CPU) sends the first address 800_a822 and the first data 2, the controller begins the first write operation, storing the first data 2 into the flash memory according to the first address 800_a822. During the first write operation, the CPU can still initiate a second write operation. During the first write operation, when the CPU initiates a second write operation, hready remains a high-order signal. Throughout the multiple write operations initiated by the CPU, hready remains a high-order signal, and flash_sr_bsy remains set to 0.

[0067] Therefore, the flash memory data writing method provided in this application adds a linked list to the controller to cache data. The address and data to be written by the CPU are stored in the linked list, thereby freeing up the CPU. The controller automatically loads data when the linked list is not empty, decodes the loaded data (i.e., performs data format conversion) to obtain the address and data in the corresponding flash memory data format, and automatically writes it into the flash memory. After loading all data in the linked list, the controller generates a data write completion signal, ending all write operations.

[0068] This application provides a data writing method for a flash memory, applied to a controller. The controller includes a linked list. The method includes: the controller receiving first data and a first address sent by a central processing unit (CPU), i.e., the CPU triggers the first write operation and sends the first data and the first address of the first write operation to the controller. The controller can store the first data in the flash memory at the first address, i.e., the first address identifies the storage location of the first data in the flash memory. During the process of the controller storing the first data, the controller can also receive multiple second data and multiple second addresses sent by the central processing unit (CPU). This means the CPU can initiate multiple write operations during the first write operation. The multiple second data and addresses included in these write operations can be stored in a linked list within the controller. Subsequently, the controller can directly load each second data and its corresponding second address from the linked list, without the CPU needing to wait for each write operation to complete before initiating the next. By storing the second data and addresses from multiple write operations in a linked list, the controller only needs to handle the actual storage of each second data at its corresponding address in the flash memory. Until the controller has stored all the second data in the flash memory, the CPU does not need to participate in the actual storage process, thus reducing the CPU time spent on write operations, improving data writing efficiency, and ultimately improving system efficiency and performance.

[0069] Based on the data writing method for a flash memory provided in the above embodiments, this application also provides a data writing system for a flash memory, and its working principle will be described in detail below with reference to the accompanying drawings.

[0070] See Figure 4 The figure is a schematic diagram of the structure of a flash memory data writing system provided in an embodiment of this application.

[0071] The flash memory data writing system 100 provided in this embodiment includes: a controller 110, which includes a bus control unit interface unit 111, a linked list control unit 112, and a flash memory interface control unit 113.

[0072] The bus control unit interface unit 111 is used to receive first data and a first address sent by the central processing unit; the bus control unit interface unit is used to receive multiple second data and multiple second addresses sent by the central processing unit.

[0073] The flash memory interface control unit 113 is used to store the first data to a first address of the flash memory, and the linked list control unit 112 is used to store multiple second data and multiple second addresses to the linked list;

[0074] The flash memory interface control unit 113 is used to load each second data and the second address corresponding to the second data from the linked list, and sequentially store each second data to the second address of the flash memory, until the flash memory interface control unit 113 stores all the second data to the flash memory.

[0075] Optionally, the system 100 further includes: a register configuration unit 114;

[0076] The register configuration unit 114 is used to configure the control logic of the controller 110 and indicate the operating status of the flash memory.

[0077] Optionally, the linked list control unit 112 is used to match multiple second data and multiple second addresses, and store the second data and the second address in the linked list according to the matching relationship between each second data and each second address.

[0078] Optionally, the linked list control unit 112 is used to store all the second data and the second addresses into the linked list, and the flash memory interface control unit 113 is used to load each second data and the second address corresponding to the second data from the linked list.

[0079] Optionally, the linked list control unit 112 is configured to, during the process of storing multiple second data and multiple second addresses into the linked list in the time order, load each second data and the second address corresponding to the second data from the linked list in the time order.

[0080] Optionally, the controller 110 is also configured to send a data write completion signal to the central processing unit.

[0081] Optionally, the bus control unit interface unit 111 converts the data format of the first data and the data format of the first address into the data format corresponding to the flash memory.

[0082] Optionally, the bus control unit interface unit 111 is used for:

[0083] Receive the first data and the first address sent by the central processing unit using the advanced high-performance AHB bus.

[0084] This application also provides a computer-readable storage medium for storing program code that is used to execute any of the methods in the foregoing embodiments.

[0085] In the context of this application, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0086] It should be noted that the computer-readable medium described above in this application can be a computer-readable signal medium, a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0087] When describing elements of various embodiments of this application, the articles “a,” “an,” “this,” and “described” are all intended to indicate that there are one or more elements. The words “comprising,” “including,” and “having” are inclusive and mean that there may be other elements in addition to those listed.

[0088] It should be noted that those skilled in the art will understand that all or part of the processes in the above method embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the above method embodiments. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0089] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof. These programming languages ​​include, but are not limited to, object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0090] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. The system embodiments described above are merely illustrative. The units and modules described as separate components may or may not be physically separate. Furthermore, some or all of the units and modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0091] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A data writing method for a flash memory, characterized in that, Applied to a controller, the controller comprising a linked list, the method includes: The controller receives first data and a first address sent by the central processing unit; During the process of the controller storing the first data to the first address of the flash memory, the controller receives multiple second data and multiple second addresses sent by the central processing unit, and stores the multiple second data and multiple second addresses to the linked list; The controller loads each piece of the second data and its corresponding second address from the linked list, and sequentially stores each piece of the second data into the second address of the flash memory, until the controller stores all the second data into the flash memory.

2. The method according to claim 1, characterized in that, The controller receives multiple second data and multiple second addresses sent by the central processing unit, and stores the multiple second data and multiple second addresses into the linked list, including: The controller receives multiple second data and multiple second addresses sent by the central processing unit; The controller matches multiple sets of the second data and multiple sets of the second addresses, and stores the second data and the second addresses in the linked list according to the matching relationship between each set of the second data and each set of the second addresses.

3. The method according to claim 1, characterized in that, The controller receives multiple second data and multiple second addresses sent by the central processing unit, and stores the multiple second data and multiple second addresses into the linked list; The controller loads each piece of second data and the corresponding second address from the linked list, including: The controller receives multiple second data and multiple second addresses sent by the central processing unit. After storing all the multiple second data and multiple second addresses into the linked list, the controller loads each second data and the corresponding second address from the linked list.

4. The method according to claim 1, characterized in that, The controller receives multiple second data and multiple second addresses sent by the central processing unit, and stores the multiple second data and multiple second addresses into the linked list; The controller loads each piece of second data and the corresponding second address from the linked list, including: The controller receives multiple second data and multiple second addresses sent by the central processing unit in chronological order. During the process of storing the multiple second data and multiple second addresses into the linked list in the chronological order, the controller loads each second data and the second address corresponding to the second data from the linked list in the chronological order.

5. The method according to claim 1, characterized in that, After the controller stores all of the second data into the flash memory, the method further includes: The controller sends a data write completion signal to the central processing unit.

6. The method according to claim 1, characterized in that, Before the controller stores the first data to a first address in the flash memory, the method further includes: The controller converts the data format of the first data and the data format of the first address into the data format corresponding to the flash memory.

7. The method according to any one of claims 1-6, characterized in that, The controller receives the first data and the first address sent by the central processing unit, including: The controller receives the first data and the first address sent by the central processing unit using the Advanced High Performance AHB bus.

8. A data writing system for a flash memory, characterized in that, The system includes a controller; the controller includes a bus control unit interface unit, a linked list control unit, and a flash memory interface control unit; The bus control unit interface unit is used to receive first data and a first address sent by the central processing unit; the bus control unit interface unit is used to receive multiple second data and multiple second addresses sent by the central processing unit. The flash memory interface control unit is used to store the first data to a first address of the flash memory, and the linked list control unit is used to store multiple sets of the second data and multiple sets of the second addresses to the linked list; The flash memory interface control unit is used to load each second data and the second address corresponding to the second data from the linked list, and sequentially store each second data to the second address of the flash memory, until the flash memory interface control unit stores all the second data to the flash memory.

9. The system according to claim 8, characterized in that, The system also includes: a register configuration unit; The register configuration unit is used to configure the control logic of the controller and indicate the operating status of the flash memory.

10. A computer-readable storage medium, characterized in that, Includes instructions that, when executed on a computer, cause the computer to perform the method as described in any one of claims 1-7.

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