A static model of SiC MOSFET device based on physical characteristics

Abstract

The invention discloses a static model of a SiC MOSFET device based on physical characteristics, including the drain current I. d Model, channel voltage drop V ds Model, gate-source effective voltage V gs The model and the model of the inversion layer channel carrier mobility μ. The drain current I d The model is an improvement on the standard long-channel device model, characterized by the representation of physical processes such as channel modulation effect and depletion layer bulk charge effect; the gate-source effective voltage model introduces the gate-source effective voltage V. gs The interface state trap is characterized by an asymptotic function as a function of the external gate-source voltage V. GS The process by which charge carriers gradually fill the space between the MOSFET and the charge carriers. This model is highly versatile and has good characterization effects on different types of SiC MOSFET devices. The model has high accuracy, and the model parameters all have certain physical meanings, which is conducive to further research based on this model. At the same time, the model is compact, the simulation speed is fast, and it is suitable for circuit simulation.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and more specifically to a static model of a silicon carbide (SiC) MOSFET device. Background Technology

[0002] SiC MOSFETs, as a typical representative of third-generation wide-bandgap power semiconductor devices, are widely used in new energy, automotive, and consumer electronics fields due to their advantages such as fast switching speed and low conduction loss, and are showing strong development momentum. To better study the electrical characteristics of SiC MOSFET devices and to better leverage their performance advantages, it is urgent to establish accurate device simulation models. Compared to Si-based MOSFETs, the SiC / SiO2 interface of SiC-based MOSFETs is more complex, possessing numerous interface traps. These traps reduce the electron density and electron mobility in the channel, thus affecting the electrical performance of the device and making the SiC MOSFET device model more complex.

[0003] Based on different modeling methods, existing SiC MOSFET models can be broadly classified into five categories: numerical models, physical models, semi-numerical models, semi-physical models, and behavioral models. Numerical, physical, and semi-numerical models offer high accuracy, but they are complex, their parameters are difficult to obtain, and both model construction and simulation are time-consuming, making them unsuitable for circuit simulation. Semi-physical and behavioral models offer faster simulation speeds and are more suitable for circuit simulation. However, existing semi-physical models have limited representation of the physical processes, resulting in insufficient model accuracy; their output and transfer characteristic curves deviate significantly from actual values. While existing behavioral models perform well in terms of accuracy, and their characteristic curves are closer to actual values, their versatility is low, and their parameters lack physical meaning, making it difficult to conduct in-depth research based on these models. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the existing technology, the purpose of this invention is to provide a static model of SiCMOSFET device based on physical characteristics, so as to solve the problem that the existing simulation model is difficult to balance universality, accuracy, simulation speed and physical characterization.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A static model of a SiC MOSFET device based on physical characteristics is characterized by including a drain current model. This drain current model is an improvement upon the standard long-channel device model, and the drain current I is obtained by characterizing physical processes such as channel modulation effect and depletion layer body charge effect. d Due to the effective gate-source voltage Vgs Channel voltage drop V ds The determining factor for the influence of parameters such as channel carrier mobility μ;

[0007] The drain current model characterizes physical processes such as channel modulation effect and depletion layer bulk charge effect; it is expressed by the following formula:

[0008]

[0009] Among them, I d V is the drain current; GS V is the external gate-source voltage; th The threshold voltage of the device; μ is the channel carrier mobility; W is the channel width; L is the channel length; C OX Gate oxide capacitance; V gs V is the effective gate-source voltage; ds For channel voltage drop; V DS λ is the external drain-source voltage; k is a coefficient characterizing the effect of depletion layer body charge, and its value is usually greater than 1; λ is the channel modulation coefficient.

[0010] Furthermore, it also includes a gate-source effective voltage model, which introduces the gate-source effective voltage V. gs The interface state trap is characterized by an asymptotic function as a function of the external gate-source voltage V. GS The process by which the voltage rises and is gradually completely occupied by charge carriers; the effective gate-source voltage V is obtained using the following formula. gs :

[0011]

[0012] Among them, V gs V is the effective gate-source voltage; GS V is the external gate-source voltage; th ΔV is the device threshold voltage. th,max is the maximum equivalent threshold voltage shift caused when all interface state traps are occupied; f is the interface state trap saturation coefficient, the larger the value, the easier it is for the interface state traps to be occupied.

[0013] Furthermore, it also includes an inversion layer channel voltage drop model, which describes the channel voltage drop V. ds Subject to external drain-source voltage V DS and external gate-source voltage V GS The influence law is analyzed, and a saturation function is used to describe V. ds With external drain-source voltage V DS The changing pattern, namely: at low V DS Time V ds With V DSApproximately linear change, when V DS Increase V ds Gradually approaching saturation; use the following formula for V ds To describe:

[0014]

[0015] Among them, V ds For channel voltage drop; V DS External drain-source voltage; δ low For low V DS The voltage divider coefficient of the channel resistance; V gs V is the effective gate-source voltage; m is the channel voltage drop saturation rate coefficient, the larger the value, the higher the V. ds The faster it saturates.

[0016] Among them, the low V DS The channel resistance voltage divider δ low Express it using the following formula:

[0017]

[0018] Where, δ low For low V DS The voltage divider coefficient of the channel resistance; R ch R is the inversion layer channel resistance; sta The remaining on-resistance excluding the channel resistance; μ is the channel carrier mobility; W is the channel width; L is the channel length; C OX Gate oxide layer capacitance

[0019] Furthermore, it also includes an inversion layer channel carrier mobility model, which describes the variation of carrier mobility μ with gate-source voltage and is determined by the following formula:

[0020]

[0021] Where μ is the channel carrier mobility; μ0 is the channel carrier mobility without the influence of the transverse electric field; and θ and r are the transverse electric field influence coefficients.

[0022] In practical applications, for a specific device, its channel width W, channel length L, and gate oxide capacitance C are... OX Since it is a constant, a parameter α can be defined to simplify the model, and its definition is as follows:

[0023]

[0024] The drain current model of this invention describes the drain current I by characterizing physical processes such as channel modulation effect and depletion layer charge effect. dSubject to channel voltage drop V ds Gate-source effective voltage V gs And the relationship between the carrier mobility μ and the gate-source effective voltage V. gs The model characterizes the effect of trapped charges at the SiC / SiO2 interface on the device and obtains the effective gate-source voltage V. gs With external gate-source voltage V GS The changing pattern; the channel voltage drop model describes the channel voltage drop V. ds Subject to external drain-source voltage V DS and the effective gate-source voltage V gs The variation law of the influence is efficiently and concisely characterized, showing the impact of the variable resistance in the drift region on the device during saturation. The carrier mobility model describes the variation trend of the channel carrier mobility under the influence of the transverse electric field. Combining the above models, the drain current I can be obtained. d Subject to external gate-source voltage V GS and external drain-source voltage V DS The pattern of influence.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] 1. This model is highly versatile and has good characterization effects on different types of SiC MOSFET devices; the model has high accuracy and the model parameters all have certain physical meanings, which is conducive to further research based on this model; at the same time, the model is compact and the simulation speed is fast, making it suitable for circuit simulation.

[0027] 2. This invention introduces the influence of depletion layer body charge and interface state trap charge on SiC MOSFET devices, and improves the model of the influence of lateral electric field on channel carrier mobility, so that the model parameters have physical meaning while the accuracy of the model is greatly improved.

[0028] 3. By introducing a saturation function, the channel voltage drop V is directly regulated. ds The description directly characterizes the effect of the drift region variable resistance on the device under high drain-source voltage, while avoiding complex modeling of the drift region variable resistance, greatly simplifying the model and making it more compact. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the half-cell structure of a planar gate SiC MOSFET device;

[0030] Figure 2 This is a schematic diagram of the overall structure of the present invention;

[0031] Figure 3The output characteristic simulation waveform diagram of Embodiment 1 of the present invention;

[0032] Figure 4 This is a simulation waveform diagram of the transfer characteristics in Embodiment 1 of the present invention;

[0033] Figure 5 The output characteristic simulation waveform diagram of Embodiment 2 of the present invention;

[0034] Figure 6 This is a simulation waveform diagram of the transfer characteristics in Embodiment 2 of the present invention. Detailed Implementation

[0035] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0036] See Figure 1 For the cell structure of SiC MOSFET devices, taking the planar gate structure as an example, it mainly includes N + Substrate, N - The current path in the drift region, JFET region, and P-type body region during forward current flow is shown in the figure. Define the inversion layer channel voltage drop V. ds The voltage drop between the near-drain terminal d and the near-source terminal s in the inversion layer channel; the effective gate-source voltage V is defined. gs To ensure that the gate-source voltage can continue to be used to form the inversion layer channel and excite carriers after reaching the strong inversion state, the external gate-source voltage V is defined. GS The voltage directly applied between the device gate G and source S; the external drain-source voltage V is defined. DS The voltage applied directly between the drain (D) and source (S) of the device; carrier mobility μ specifically refers to the carrier mobility in the conductive channel of the inversion layer. Figure 1 It can be seen that, unlike standard long-channel devices, the external drain-source voltage V of a SiC MOSFET during forward conduction is... DS It is not directly applied to both ends of the inversion layer channel, so it cannot be directly characterized using the standard long channel model.

[0037] like Figure 2 As shown, the present invention provides a static model of SiC MOSFET device based on physical characteristics, including drain current model, inversion layer channel voltage drop model, gate-source effective voltage model, and inversion layer channel carrier mobility model.

[0038] The drain current model is an improvement on the standard long-channel device model. By characterizing physical processes such as channel modulation effect and depletion layer body charge effect, the drain current I is obtained. d Due to the effective gate-source voltage V gs Channel voltage drop V dsThe determining factor for the influence of parameters such as channel carrier mobility μ is as follows:

[0039]

[0040] Among them, I d V is the drain current; GS V is the external gate-source voltage; th The threshold voltage of the device; μ is the channel carrier mobility; W is the channel width; L is the channel length; C OX Gate oxide capacitance; V gs V is the effective gate-source voltage; ds For channel voltage drop; V DS λ is the external drain-source voltage; k is a coefficient characterizing the effect of depletion layer body charge, and its value is usually greater than 1; λ is the channel modulation coefficient.

[0041] Furthermore, the gate-source effective voltage model introduces the gate-source effective voltage V. gs Furthermore, an asymptotic function was used to characterize the process by which the interface state trap charges of a SiC MOSFET are gradually occupied by charge carriers as the external gate-source voltage increases. gs The decision formula is as follows:

[0042]

[0043] Among them, V gs V is the effective gate-source voltage; GS V is the external gate-source voltage; th ΔV is the device threshold voltage. th,max is the maximum equivalent threshold voltage offset caused when all interface state traps are occupied; f is the interface state trap saturation coefficient, the larger the value, the easier it is for the interface state trap to be occupied.

[0044] Furthermore, the inversion layer channel voltage drop model describes the channel voltage drop V using a saturation function. ds With external drain-source voltage V DS The changing pattern, namely: at low V DS Time V ds With V DS Approximately linear change, when V DS Increase V ds Gradually approaching saturation. Inversion layer channel voltage drop V ds The decision formula is as follows:

[0045]

[0046] Among them, V ds For channel voltage drop; V DS External drain-source voltage; δ low For low VDS The voltage divider coefficient of the channel resistance; V gs V is the effective gate-source voltage; m is the channel voltage drop saturation rate coefficient, the larger the value, the higher the V. ds The faster the saturation; R ch R is the inversion layer channel resistance; sta The remaining on-resistance excluding the channel resistance; μ is the channel carrier mobility; W is the channel width; L is the channel length; C OX This refers to the gate oxide layer capacitance.

[0047] Furthermore, the inversion layer channel carrier mobility model describes the variation of carrier mobility with gate-source voltage, and the relationship is shown in the following formula:

[0048]

[0049] Where μ is the channel carrier mobility; μ0 is the channel carrier mobility without the influence of the transverse electric field; and θ and r are the transverse electric field influence coefficients.

[0050] In practical applications, for a specific device, its channel width W, channel length L, and gate oxide capacitance C are... OX Since it is a constant, a parameter α can be defined to simplify the model, and its definition is as follows:

[0051]

[0052] From formulas (1)-(5), the above model can be simplified to:

[0053]

[0054] Among them, I d V is the drain current; GS V is the external gate-source voltage; th The threshold voltage of the device; μ is the channel carrier mobility; W is the channel width; L is the channel length; C OX Gate oxide capacitance; V gs V is the effective gate-source voltage; ds For channel voltage drop; V DS ΔV is the external drain-source voltage; k is a coefficient characterizing the effect of depletion layer body charge; λ is the channel modulation coefficient; f is the interface state trap saturation coefficient; ΔV th,max α is the maximum equivalent threshold voltage offset caused when the interface state trap is fully occupied; α is the model simplification parameter; α0 is the value of α when it is not affected by the transverse electric field; θ and r are the transverse electric field influence coefficients; δ low For low V DS The voltage divider coefficient of the channel resistance; V gs R is the effective gate-source voltage; m is the channel voltage drop saturation rate coefficient;ch R is the inversion layer channel resistance; sta This is the remaining on-resistance excluding the open-channel resistance.

[0055] The unknown parameters in the above model include: V th α0, k, λ, ΔV th,max f, r, θ, m, R sta Among them, V th ΔV can be obtained through experimental measurement or datasheet. th,max It can be obtained experimentally or by fitting output characteristic curves and transfer characteristic curves; R sta The on-resistance can be measured with respect to the gate-source voltage R. ds,on -V GS The curves can be obtained directly by fitting the output characteristic curve and the transfer characteristic curve; α0, r, and θ can be obtained by different gate-source voltages V. GS The slope of the zero point of the output characteristic curve is obtained by inverse calculation or by directly fitting the output characteristic curve and the transfer characteristic curve; k can be taken as an empirical value or directly obtained by fitting the output characteristic curve and the transfer characteristic curve; the remaining f, m and λ are obtained by directly fitting the output characteristic curve and the transfer characteristic curve.

[0056] Taking the IMW120R220M1H SiC MOSFET as Example 1, its parameter values ​​are shown in Table 1. Substituting the parameters from Table 1 into the formula yields the static simulation model of the device. The simulation results are then compared with the datasheet, and the output characteristic curves are shown below. Figure 3 As shown, the transfer characteristic curve is as follows: Figure 4 As shown.

[0057] Table 1

[0058] value 4.5 0.964 1.1 0.0015 2.9995 1.869 2.1487 0.0026 0.7933 0.058

[0059] Taking the SiC MOSFET with model number IMZ120R060M1H as Example 2, its parameter values ​​are extracted as shown in Table 2. Substituting the parameters from Table 2 into the model yields the static simulation model of the device. The simulation then compares the model with the datasheet, and the output characteristic curves are shown below. Figure 5 As shown, the transfer characteristic curve is as follows: Figure 6 As shown.

[0060] Table 2

[0061] value 4.5 3.3428 1.1 0.002 2.9994 1.7264 2.3541 0.0014 0.8006 0.0158

[0062] As can be seen from the results of Examples 1 and 2, the simulation results of the SiCMOSFET device static model based on physical characteristics proposed in this invention are in high agreement with the datasheet. The model is compact and the model parameters have certain physical meanings, which makes up for the current model's difficulty in balancing universality, accuracy, simulation speed and physical characterization.

[0063] In summary, the drain current model described in this invention can be obtained through the effective gate-source voltage V. gs Channel voltage drop V ds The drain current is calculated using parameters such as channel carrier mobility μ; the inversion layer channel voltage drop model completes the calculation of the channel voltage drop V by introducing an asymptotic function. ds With external drain-source voltage V DS and the effective gate-source voltage V gs The variation law is characterized while avoiding the complex modeling of the variable resistance in the drift region; the gate-source effective voltage model is used to describe the gate-source effective voltage V under the influence of interface state trap charge. gs With external gate-source voltage V GS The variation law of the channel carrier mobility μ is described by the channel carrier mobility model, which describes the variation law of the carrier mobility μ under the influence of the transverse electric field. Combining the above models, the drain current I can be obtained. d Subject to external gate-source voltage V GS and external drain-source voltage V DS The laws of control.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit the technical solutions. Those skilled in the art should understand that any modifications or equivalent substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention should be covered within the scope of the claims of the present invention.

Claims

1. A static model of a SiC MOSFET device based on physical characteristics, characterized in that, This includes drain current model, inversion layer channel voltage drop model, and inversion layer channel voltage drop model; The drain current model is an improvement on the standard long-channel device model. By characterizing the channel modulation effect and the depletion layer body charge effect, the drain current I is obtained. d Due to the effective gate-source voltage V gs Channel voltage drop V ds The formula for determining the channel carrier mobility μ; The drain current model is expressed by the following formula: （1）； Among them, I d V is the drain current; GS V is the external gate-source voltage; th The threshold voltage of the device; μ is the channel carrier mobility; W is the channel width; L is the channel length; C OX Gate oxide capacitance; V gs V is the effective gate-source voltage; ds For channel voltage drop; V DS λ is the external drain-source voltage; k is a coefficient characterizing the effect of depletion layer body charge, with a value greater than 1; λ is the channel modulation coefficient. The gate-source effective voltage model introduces the gate-source effective voltage V. gs The interface state trap is characterized by an asymptotic function as a function of the external gate-source voltage V. GS The process by which the voltage rises and is gradually completely occupied by charge carriers; the effective gate-source voltage V is obtained using the following formula. gs : （2）； Among them, V gs V is the effective gate-source voltage; GS V is the external gate-source voltage; th ΔV is the device threshold voltage. th,max is the maximum equivalent threshold voltage shift caused when all interface state traps are occupied; f is the interface state trap saturation coefficient, the larger the value, the easier it is for the interface state trap to be occupied; The inversion layer channel voltage drop model describes the channel voltage drop V. ds Subject to external drain-source voltage V DS and external gate-source voltage V GS The influence law is analyzed, and a saturation function is used to describe V. ds With external drain-source voltage V DS The changing pattern, namely: at low V DS Time V ds With V DS Approximately linear change, when V DS Increase V ds Gradually approaching saturation; use the following formula for V ds To describe: （3）； Among them, V ds For channel voltage drop; V DS External drain-source voltage; δ low For low V DS The voltage divider coefficient of the channel resistance; V gs V is the effective gate-source voltage; m is the channel voltage drop saturation rate coefficient, the larger the value, the higher the V. ds The faster it saturates.

2. The static model of SiC MOSFET device based on physical characteristics according to claim 1, characterized in that, It also includes an inversion layer channel carrier mobility model, which describes the variation of carrier mobility μ with gate-source voltage and is determined by the following formula: （4）； Where μ is the channel carrier mobility; μ0 is the channel carrier mobility without the influence of the transverse electric field; and θ and r are the transverse electric field influence coefficients.

3. The static model of SiC MOSFET device based on physical characteristics according to claim 1, characterized in that, The low V DS The channel resistance voltage divider coefficient δ low Express it using the following formula: ； Where, δ low For low V DS The voltage divider coefficient of the channel resistance; R ch R is the inversion layer channel resistance; sta The remaining on-resistance excluding the channel resistance; μ is the channel carrier mobility; W is the channel width; L is the channel length; C OX This refers to the gate oxide layer capacitance.

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