An on-chip high-precision clock reference source circuit

Abstract

This invention relates to microcontroller clocks, specifically to an on-chip high-precision clock reference source circuit, including a PTAT generation circuit, a reference voltage generation circuit, and a clock source oscillator. The PTAT generation circuit generates a temperature-varying PTAT current. The reference voltage generation circuit generates a temperature-varying reference voltage based on the PTAT current to compensate for frequency drift caused by temperature changes. The clock source oscillator uses an LC oscillation circuit to generate the required clock frequency. The technical solution provided by this invention can effectively overcome the shortcomings of existing technologies, such as the inability to adequately compensate for frequency drift caused by temperature changes, the inability to accurately control clock accuracy, and high cost.

Description

Technical Field

[0001] This invention relates to microcontroller clocks, specifically to an on-chip high-precision clock reference source circuit. Background Technology

[0002] A microcontroller clock is an electronic component used to provide timing signals to ensure that the various components inside the microcontroller can work together. The main function of a microcontroller clock is to generate stable timing signals to control various operations within the microcontroller. These timing signals ensure that the instructions inside the microcontroller are executed in a set order and at the set time, thereby achieving efficient and stable operation of the microcontroller.

[0003] Clock signals are typically generated by an oscillator and then processed through frequency dividers, multipliers, and other circuits to meet the operational requirements of different modules within the microcontroller. With continuous technological advancements, the demand for low-cost, high-performance designs is increasing. However, most microcontroller clocks are powered by external crystals, but adding an external crystal increases costs. Furthermore, existing microcontroller clock sources cannot adequately compensate for frequency drift caused by temperature variations and cannot precisely control clock accuracy. Summary of the Invention

[0004] (a) Technical problems to be solved

[0005] In view of the above-mentioned shortcomings of the prior art, the present invention provides an on-chip high-precision clock reference source circuit, which can effectively overcome the defects of the prior art, such as the inability to compensate for frequency drift caused by temperature changes, the inability to accurately control clock accuracy, and the high cost.

[0006] (II) Technical Solution

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] An on-chip high-precision clock reference source circuit includes a PTAT generation circuit, a reference voltage generation circuit, and a clock source oscillator;

[0009] The PTAT generation circuit is used to generate a PTAT current that varies with temperature.

[0010] The reference voltage generation circuit generates a temperature-varying reference voltage based on the PTAT current to compensate for frequency drift caused by temperature changes.

[0011] A clock source oscillator uses an LC oscillator circuit to generate the required clock frequency.

[0012] Preferably, the PTAT generation circuit includes NMOS transistors NM0 and NM1, PMOS transistors PM0, PM1, PM3, and PM4, and resistors R6 and R7.

[0013] The gate of the NMOS transistor NM0 is connected to the drain of the NMOS transistor NM0, the gate of the NMOS transistor NM1, and the clock source oscillator. The source of the NMOS transistor NM0 is connected to the source of the NMOS transistor NM1 through resistor R6. The source of the NMOS transistor NM0 is connected to the reference voltage generation circuit and the clock source oscillator. The drain of the NMOS transistor NM0 is connected to the drain of the PMOS transistor PM3.

[0014] The gate of PMOS transistor PM3 is connected to the gate of PMOS transistor PM4 and the reference voltage generation circuit, and the source of PMOS transistor PM3 is connected to the drain of PMOS transistor PM0.

[0015] The gate of PMOS transistor PM0 is connected to the gate of PMOS transistor PM1 and the reference voltage generation circuit, and the source of PMOS transistor PM0 is connected to the source of PMOS transistor PM1, the reference voltage generation circuit and the clock source oscillator.

[0016] The drain of the NMOS transistor NM1 is connected to the drain of the PMOS transistor PM4 through resistor R7, and the drain of the NMOS transistor NM1 is connected to the gate of the PMOS transistor PM4.

[0017] The drain of PMOS transistor PM4 is connected to the gate of PMOS transistor PM1, and the source of PMOS transistor PM4 is connected to the drain of PMOS transistor PM1.

[0018] Preferably, the number of NMOS transistors NM1 is n times the number of NMOS transistors NM0, and the branch current of NMOS transistor NM1 is n times the branch current of NMOS transistor NM0.

[0019] Preferably, the PTAT current generated by the PTAT generating circuit Calculate using the following formula:

[0020]

[0021] in, For fixed parameter values, , The mobility of the NMOS transistor. For CMOS fabrication process oxide layer thickness, These are all design parameters for MOSFETs.

[0022] Preferably, the reference voltage generation circuit includes PMOS transistors PM2 and PM5, and a programmable resistor R5;

[0023] The gate of PMOS transistor PM2 is connected to the gates of PMOS transistors PM0 and PM1, the drain of PMOS transistor PM5, and the clock source oscillator. The source of PMOS transistor PM2 is connected to the sources of PMOS transistors PM0 and PM1 and the clock source oscillator. The drain of PMOS transistor PM2 is connected to the source of PMOS transistor PM5.

[0024] The gate of PMOS transistor PM5 is connected to the gates of PMOS transistors PM3 and PM4, and the drain of PMOS transistor PM5 is connected to the source of NMOS transistor NM0, resistor R6 and clock source oscillator through programmable resistor R5.

[0025] Preferably, the reference voltage generated by the reference voltage generation circuit is... Calculate using the following formula:

[0026] .

[0027] Preferably, the clock source oscillator includes DC blocking resistors R1, R2, R3, and R4, oscillator gain transistors PM6, PM7, NM2, and NM3, and a DC blocking capacitor C. p0 C p1 C n0 C n1 Oscillator frequency programming capacitors C0, C1, ..., C n , oscillator inductance L, and variable capacitor C;

[0028] DC blocking resistors R1, R2, R3, and R4 are used to provide DC operating points for oscillator gain transistors PM6, PM7, NM2, and NM3, and to isolate the noise from PMOS transistors PM0, PM1, PM3, and PM4, ensuring that the oscillator operates in the optimal range.

[0029] The oscillator gain transistors PM6, PM7, NM2, and NM3 need to operate in their optimal range to provide higher gain and lower noise.

[0030] DC blocking capacitor C p0 C p1 C n0 C n1 This isolates the DC outputs of the clock source oscillator (Voutn and Voutp) from the DC outputs of the oscillator gain transistors (PM6, PM7, NM2, and NM3), reducing the impact of the DC outputs of the oscillator gain transistors on Voutn and Voutp and ensuring that the oscillator output DC is within a relatively good range.

[0031] Oscillator frequency programming capacitors C0, C1, ..., C n By programming and optimizing the frequency, the oscillator can reach the target frequency.

[0032] The variable capacitor C varies with the reference voltage. Fine-tuning to change the oscillator frequency, i.e. Then, a reference voltage that varies with temperature is used. Compensation for frequency shifts in LC resonance due to temperature changes.

[0033] Preferably, the gate of the oscillator gain transistor PM6 is connected to one end of the DC blocking resistor R1 and the DC blocking capacitor C. p0 At one end, the source of the oscillator gain transistor PM6 is connected to the source of PMOS transistors PM0, PM1, and PM2, and the drain of the oscillator gain transistor PM6 is connected to the drain of the oscillator gain transistor NM2.

[0034] The gate of the oscillator gain transistor NM2 is connected to one end of the DC blocking resistor R3 and the DC blocking capacitor C. n0 At one end, the source of the oscillator gain transistor NM2 is connected to the source of the NMOS transistor NM0 and resistor R6;

[0035] The gate of the oscillator gain transistor PM7 is connected to one end of the DC blocking resistor R2 and the DC blocking capacitor C. p1 At one end, the source of the oscillator gain transistor PM7 is connected to the source of the oscillator gain transistor PM6, and the drain of the oscillator gain transistor PM7 is connected to the drain of the oscillator gain transistor NM3.

[0036] The gate of the oscillator gain transistor NM3 is connected to one end of the DC blocking resistor R4 and the DC blocking capacitor C. n1 At one end, the source of the oscillator gain transistor NM3 is connected to the source of the oscillator gain transistor NM2;

[0037] The other ends of the DC blocking resistors R1 and R2 are connected to the gate of the PMOS transistor PM2, and the other ends of the DC blocking resistors R3 and R4 are connected to the gate of the NMOS transistor NM0. The DC blocking capacitor C... p0 The other end is connected to a DC blocking capacitor C n0 At the other end, the DC blocking capacitor C p1 The other end is connected to a DC blocking capacitor C n1 At the other end, the C p0 The other end is connected to the DC blocking capacitor C p1 The other end is connected in parallel with oscillator frequency programming capacitors C0, C1, ..., C n A variable capacitor C and an oscillator inductor L are connected, wherein the variable capacitor C is connected to the drain of the PMOS transistor PM5.

[0038] Preferably, the oscillator frequency Calculate using the following formula:

[0039]

[0040] according to Rewrite the above formula as:

[0041] .

[0042] (III) Beneficial Effects

[0043] Compared with the prior art, the on-chip high-precision clock reference source circuit provided by the present invention has the following beneficial effects:

[0044] 1) Traditional reference clocks are made of quartz and cannot be integrated into CMOS processes. However, this application can integrate the clock reference source into the CMOS process without the need to package external components, resulting in a simpler application solution and lower costs.

[0045] 2) The temperature characteristics of CMOS process devices can be used to effectively compensate for frequency drift caused by temperature changes. The programmable resistor R5 in the reference voltage generation circuit can change the slope of the compensation temperature, which is beneficial to production consistency.

[0046] 3) The clock accuracy can be precisely controlled by using a high-precision oscillator frequency programming capacitor, and the clock accuracy can be accurately guaranteed by only calibrating once in production. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0048] Figure 1 This is the circuit diagram of the present invention. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0050] An on-chip high-precision clock reference source circuit, such as Figure 1 As shown, it includes a PTAT generation circuit, a reference voltage generation circuit, and a clock source oscillator;

[0051] The PTAT generation circuit is used to generate a PTAT current that varies with temperature.

[0052] The reference voltage generation circuit generates a temperature-varying reference voltage based on the PTAT current to compensate for frequency drift caused by temperature changes.

[0053] A clock source oscillator uses an LC oscillator circuit to generate the required clock frequency.

[0054] The PTAT generation circuit includes NMOS transistors NM0 and NM1, PMOS transistors PM0, PM1, PM3, and PM4, and resistors R6 and R7.

[0055] The gate of NMOS transistor NM0 is connected to the drain of NMOS transistor NM0, the gate of NMOS transistor NM1, and the clock source oscillator. The source of NMOS transistor NM0 is connected to the source of NMOS transistor NM1 through resistor R6. The source of NMOS transistor NM0 is connected to the reference voltage generation circuit and the clock source oscillator. The drain of NMOS transistor NM0 is connected to the drain of PMOS transistor PM3.

[0056] The gate of PMOS transistor PM3 is connected to the gate of PMOS transistor PM4 and the reference voltage generation circuit, and the source of PMOS transistor PM3 is connected to the drain of PMOS transistor PM0.

[0057] The gate of PMOS transistor PM0 is connected to the gate of PMOS transistor PM1 and the reference voltage generation circuit, and the source of PMOS transistor PM0 is connected to the source of PMOS transistor PM1, the reference voltage generation circuit and the clock source oscillator.

[0058] The drain of NMOS transistor NM1 is connected to the drain of PMOS transistor PM4 through resistor R7, and the drain of NMOS transistor NM1 is connected to the gate of PMOS transistor PM4.

[0059] The drain of PMOS transistor PM4 is connected to the gate of PMOS transistor PM1, and the source of PMOS transistor PM4 is connected to the drain of PMOS transistor PM1.

[0060] Specifically, the number of NMOS transistors NM1 is n times the number of NMOS transistors NM0, and the current in the branch containing NMOS transistor NM1 is n times the current in the branch containing NMOS transistor NM0.

[0061] Specifically, the PTAT current generated by the PTAT generation circuit Calculate using the following formula:

[0062]

[0063] in, For fixed parameter values, , The mobility of the NMOS transistor. For CMOS fabrication process oxide layer thickness, These are all design parameters for MOSFETs, with R6 and n optimized and adjusted according to the magnitude of the PTAT current.

[0064] The reference voltage generation circuit includes PMOS transistors PM2 and PM5, and a programmable resistor R5 (which can change the slope of the compensation temperature, which is beneficial for production consistency).

[0065] The gate of PMOS transistor PM2 is connected to the gates of PMOS transistors PM0 and PM1, the drain of PMOS transistor PM5, and the clock source oscillator. The source of PMOS transistor PM2 is connected to the sources of PMOS transistors PM0 and PM1 and the clock source oscillator. The drain of PMOS transistor PM2 is connected to the source of PMOS transistor PM5.

[0066] The gate of PMOS transistor PM5 is connected to the gates of PMOS transistors PM3 and PM4. The drain of PMOS transistor PM5 is connected to the source of NMOS transistor NM0, resistor R6 and clock source oscillator through programmable resistor R5.

[0067] Specifically, the reference voltage generated by the reference voltage generation circuit Calculate using the following formula:

[0068] .

[0069] The clock source oscillator includes DC blocking resistors R1, R2, R3, and R4, oscillator gain transistors PM6, PM7, NM2, and NM3, and DC blocking capacitor C. p0 C p1 C n0 C n1 Oscillator frequency programming capacitors C0, C1, ..., C n , oscillator inductance L, and variable capacitor C;

[0070] DC blocking resistors R1, R2, R3, and R4 are used to provide DC operating points for oscillator gain transistors PM6, PM7, NM2, and NM3, and to isolate the noise from PMOS transistors PM0, PM1, PM3, and PM4, ensuring that the oscillator operates in the optimal range.

[0071] The oscillator gain transistors PM6, PM7, NM2, and NM3 need to operate within their optimal range to provide higher gain and lower noise. oscillator gain g m It needs to be large enough to ensure that the oscillator can start oscillating stably every time;

[0072] DC blocking capacitor C p0 C p1 C n0 C n1 This isolates the DC outputs of the clock source oscillator (Voutn and Voutp) from the DC outputs of the oscillator gain transistors (PM6, PM7, NM2, and NM3), reducing the impact of the DC outputs of the oscillator gain transistors on Voutn and Voutp and ensuring that the oscillator output DC is within a relatively good range.

[0073] Oscillator frequency programming capacitors C0, C1, ..., C n The frequency is optimized and changed through programming (using thermometer code or binary code programming, etc.) so that the oscillator reaches the target frequency;

[0074] The variable capacitor C varies with the reference voltage. Fine-tuning to change the oscillator frequency, i.e. Then, a reference voltage that varies with temperature is used. Compensation for the frequency shift of LC resonance due to temperature changes (one negative shift and one positive shift).

[0075] The gate of the oscillator gain transistor PM6 is connected to one end of the DC blocking resistor R1 and the DC blocking capacitor C. p0 At one end, the source of oscillator gain transistor PM6 is connected to the source of PMOS transistors PM0, PM1, and PM2, and the drain of oscillator gain transistor PM6 is connected to the drain of oscillator gain transistor NM2.

[0076] The gate of the oscillator gain transistor NM2 is connected to one end of the DC blocking resistor R3 and the DC blocking capacitor C. n0 At one end, the source of the oscillator gain transistor NM2 is connected to the source of the NMOS transistor NM0 and resistor R6;

[0077] The gate of the oscillator gain transistor PM7 is connected to one end of the DC blocking resistor R2 and the DC blocking capacitor C. p1 At one end, the source of oscillator gain transistor PM7 is connected to the source of oscillator gain transistor PM6, and the drain of oscillator gain transistor PM7 is connected to the drain of oscillator gain transistor NM3.

[0078] The gate of the oscillator gain transistor NM3 is connected to one end of the DC blocking resistor R4 and the DC blocking capacitor C. n1 At one end, the source of oscillator gain transistor NM3 is connected to the source of oscillator gain transistor NM2;

[0079] The other ends of DC blocking resistors R1 and R2 are connected to the gate of PMOS transistor PM2, and the other ends of DC blocking resistors R3 and R4 are connected to the gate of NMOS transistor NM0. DC blocking capacitor C... p0 The other end is connected to a DC blocking capacitor C n0 At the other end, the DC blocking capacitor Cp1 The other end is connected to a DC blocking capacitor C n1 On the other end, C p0 The other end is connected to the DC blocking capacitor C p1 The other end is connected in parallel with oscillator frequency programming capacitors C0, C1, ..., C n A variable capacitor C and an oscillator inductor L are connected, with the variable capacitor C connected to the drain of the PMOS transistor PM5.

[0080] In the technical solution of this application, the oscillator frequency... Calculate using the following formula:

[0081]

[0082] according to Rewrite the above formula as:

[0083] .

[0084] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An on-chip high-precision clock reference source circuit, characterized in that: Includes a PTAT generation circuit, a reference voltage generation circuit, and a clock source oscillator; The PTAT generation circuit is used to generate a PTAT current that varies with temperature. The reference voltage generation circuit generates a temperature-varying reference voltage based on the PTAT current to compensate for frequency drift caused by temperature changes. A clock source oscillator uses an LC oscillator circuit to generate the required clock frequency. The PTAT generation circuit includes NMOS transistors NM0 and NM1, PMOS transistors PM0, PM1, PM3, and PM4, and resistors R6 and R7. The gate of the NMOS transistor NM0 is connected to the drain of the NMOS transistor NM0, the gate of the NMOS transistor NM1, and the clock source oscillator. The source of the NMOS transistor NM0 is connected to the source of the NMOS transistor NM1 through resistor R6. The source of the NMOS transistor NM0 is connected to the reference voltage generation circuit and the clock source oscillator. The drain of the NMOS transistor NM0 is connected to the drain of the PMOS transistor PM3. The gate of PMOS transistor PM3 is connected to the gate of PMOS transistor PM4 and the reference voltage generation circuit, and the source of PMOS transistor PM3 is connected to the drain of PMOS transistor PM0. The gate of PMOS transistor PM0 is connected to the gate of PMOS transistor PM1 and the reference voltage generation circuit, and the source of PMOS transistor PM0 is connected to the source of PMOS transistor PM1, the reference voltage generation circuit and the clock source oscillator. The drain of the NMOS transistor NM1 is connected to the drain of the PMOS transistor PM4 through resistor R7, and the drain of the NMOS transistor NM1 is connected to the gate of the PMOS transistor PM4. The drain of PMOS transistor PM4 is connected to the gate of PMOS transistor PM1, and the source of PMOS transistor PM4 is connected to the drain of PMOS transistor PM1. The reference voltage generation circuit includes PMOS transistors PM2 and PM5, and a programmable resistor R5; The gate of PMOS transistor PM2 is connected to the gates of PMOS transistors PM0 and PM1, the drain of PMOS transistor PM5, and the clock source oscillator. The source of PMOS transistor PM2 is connected to the sources of PMOS transistors PM0 and PM1 and the clock source oscillator. The drain of PMOS transistor PM2 is connected to the source of PMOS transistor PM5. The gate of PMOS transistor PM5 is connected to the gates of PMOS transistors PM3 and PM4, and the drain of PMOS transistor PM5 is connected to the source of NMOS transistor NM0, resistor R6 and clock source oscillator through programmable resistor R5. The clock source oscillator includes DC blocking resistors R1, R2, R3, and R4, oscillator gain transistors PM6, PM7, NM2, and NM3, and a DC blocking capacitor C. p0 C p1 C n0 C n1 Oscillator frequency programming capacitors C0, C1, ..., C n , oscillator inductance L, and variable capacitor C; DC blocking resistors R1, R2, R3, and R4 are used to provide DC operating points for oscillator gain transistors PM6, PM7, NM2, and NM3, and to isolate the noise from PMOS transistors PM0, PM1, PM3, and PM4, ensuring that the oscillator operates in the optimal range. The oscillator gain transistors PM6, PM7, NM2, and NM3 need to operate in their optimal range to provide higher gain and lower noise. DC blocking capacitor C p0 C p1 C n0 C n1 This isolates the DC outputs of the clock source oscillator (Voutn and Voutp) from the DC outputs of the oscillator gain transistors (PM6, PM7, NM2, and NM3), reducing the impact of the DC outputs of the oscillator gain transistors on Voutn and Voutp and ensuring that the oscillator output DC is within a relatively good range. Oscillator frequency programming capacitors C0, C1, ..., C n By programming and optimizing the frequency, the oscillator can reach the target frequency. The variable capacitor C varies with the reference voltage. Fine-tuning to change the oscillator frequency, i.e. Then, a reference voltage that varies with temperature is used. Compensation for frequency shifts in LC resonance due to temperature changes.

2. The on-chip high-precision clock reference source circuit according to claim 1, characterized in that: The number of NMOS transistors NM1 is n times the number of NMOS transistors NM0, and the current in the branch containing NMOS transistors NM1 is n times the current in the branch containing NMOS transistors NM0.

3. The on-chip high-precision clock reference source circuit according to claim 2, characterized in that: The PTAT current generated by the PTAT generating circuit Calculate using the following formula: in, For fixed parameter values, , The mobility of the NMOS transistor. For CMOS fabrication process oxide layer thickness, These are all design parameters for MOSFETs.

4. The on-chip high-precision clock reference source circuit according to claim 1, characterized in that: The reference voltage generated by the reference voltage generation circuit Calculate using the following formula: 。 5. The on-chip high-precision clock reference source circuit according to claim 1, characterized in that: The gate of the oscillator gain transistor PM6 is connected to one end of the DC blocking resistor R1 and the DC blocking capacitor C. p0 At one end, the source of the oscillator gain transistor PM6 is connected to the source of PMOS transistors PM0, PM1, and PM2, and the drain of the oscillator gain transistor PM6 is connected to the drain of the oscillator gain transistor NM2. The gate of the oscillator gain transistor NM2 is connected to one end of the DC blocking resistor R3 and the DC blocking capacitor C. n0 At one end, the source of the oscillator gain transistor NM2 is connected to the source of the NMOS transistor NM0 and resistor R6; The gate of the oscillator gain transistor PM7 is connected to one end of the DC blocking resistor R2 and the DC blocking capacitor C. p1 At one end, the source of the oscillator gain transistor PM7 is connected to the source of the oscillator gain transistor PM6, and the drain of the oscillator gain transistor PM7 is connected to the drain of the oscillator gain transistor NM3. The gate of the oscillator gain transistor NM3 is connected to one end of the DC blocking resistor R4 and the DC blocking capacitor C. n1 At one end, the source of the oscillator gain transistor NM3 is connected to the source of the oscillator gain transistor NM2; The other ends of the DC blocking resistors R1 and R2 are connected to the gate of the PMOS transistor PM2, and the other ends of the DC blocking resistors R3 and R4 are connected to the gate of the NMOS transistor NM0. The DC blocking capacitor C... p0 The other end is connected to a DC blocking capacitor C n0 At the other end, the DC blocking capacitor C p1 The other end is connected to a DC blocking capacitor C n1 At the other end, the C p0 The other end is connected to the DC blocking capacitor C p1 The other end is connected in parallel with oscillator frequency programming capacitors C0, C1, ..., C n A variable capacitor C and an oscillator inductor L are connected, wherein the variable capacitor C is connected to the drain of the PMOS transistor PM5.

6. The on-chip high-precision clock reference source circuit according to claim 5, characterized in that: The oscillator frequency Calculate using the following formula: ； according to Rewrite the above formula as: 。

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