Goa circuit and display panel

Abstract

The application provides a GOA circuit and a display panel, and relates to the technical field of display. The GOA circuit comprises a plurality of GOA units connected in cascade. In each GOA unit, a pull-up control module is connected with a signal output end G(N-3) of a (N-3)th GOA unit, a constant-voltage high-potential signal end and a first node respectively, a pull-up module is connected with a clock signal line, the first node and a second node respectively, a capacitor module is connected with the first node and the second node respectively, a pull-down maintenance module is connected with the constant-voltage high-potential signal end, the first node, the second node, a third node and a fourth node respectively, the third node is connected with a gate-off signal end, the fourth node is connected with a constant-voltage negative-potential signal end, a pull-down module is connected with a signal output end G(N+4) of a (N+4)th GOA unit, the first node and the third node respectively, a GOA drive-off module is connected with the gate-off signal end, the second node and the fourth node respectively. The application can keep normal signal level transmission during a display period and reduce the charge leakage of the GOA circuit during a touch period.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a GOA circuit and a display panel. BACKGROUND

[0002] With the rapid development of display technology, touch display panels have been widely accepted and used by people, such as smart phones, tablet computers and the like all use touch display panels (Touch Panel Technology), and the touch display panel is a combination of a touch panel and a liquid crystal panel, so that the liquid crystal panel has the functions of display and sensing touch input. According to the different positions of the touch sensor (Touch sensor), the touch display panel can be divided into Out cell (touch sensor is externally hung on the display panel), On cell (touch sensor is arranged on the display panel) and In cell (touch sensor is integrated in the display panel) and the like technical architecture.

[0003] Among them, the driving architecture of the In cell type touch display panel adopts a gate driving circuit (Gate On Array, GOA) to provide the required gate driving signal of the panel, so that the touch display panel can work normally. However, the In cell type touch display panel needs to have a signal pause function, that is, the stage transmission of the GOA circuit needs to be paused during the touch period, so how to maintain the charge of the GOA circuit not to leak during the touch period is the key problem. SUMMARY

[0004] The present application provides a GOA circuit and a display panel, which can maintain normal signal stage transmission during display period and reduce charge leakage of GOA circuit during touch period.

[0005] In a first aspect, the present application provides a GOA circuit, which comprises a plurality of GOA units connected in cascade, each of the GOA units comprising a pull-up control module, a pull-up module, a capacitor module, a pull-down maintenance module, a pull-down module and a GOA driving off module;

[0006] The pull-up control module is respectively connected with a signal output end G(N-3) of the (N-3)th GOA unit, a constant voltage high potential signal end and a first node, and N is a natural number;

[0007] The pull-up module is respectively connected with a clock signal line, the first node and a second node;

[0008] The capacitor module is respectively connected with the first node and the second node;

[0009] The pull-down maintaining module is connected with the constant-voltage high potential signal end, the first node, the second node, a third node and a fourth node respectively, wherein the third node is connected with a gate-off signal end, and the fourth node is connected with a constant-voltage negative potential signal end.

[0010] The pull-down module is connected with a signal output end G(N+4) of the (N+4)th GOA unit, the first node and the third node respectively.

[0011] The GOA driving-off module is connected with the gate-off signal end, the second node and the fourth node respectively.

[0012] The gate-off signal end is used for providing a low potential signal during a display period and is used for providing a high potential signal during a touch period, the pull-down maintaining module maintains the pull-down maintaining function when the gate-off signal end provides the low potential signal, and the pull-down maintaining module is disabled when the gate-off signal end provides the high potential signal.

[0013] In a possible implementation manner of the application, the pull-up control module comprises an eleventh thin film transistor, a first end of the eleventh thin film transistor is connected with the signal output end G(N-3) of the (N-3)th GOA unit, a second end of the eleventh thin film transistor is connected with the constant-voltage high potential signal end, and a third end of the eleventh thin film transistor is connected with the first node.

[0014] In a possible implementation manner of the application, the pull-up module comprises a twenty-first thin film transistor, a first end of the twenty-first thin film transistor is connected with the first node, a second end of the twenty-first thin film transistor is connected with the clock signal line, and a third end of the twenty-first thin film transistor is connected with the second node.

[0015] In a possible implementation manner of the application, the pull-down module comprises a forty-first thin film transistor, a first end of the forty-first thin film transistor is connected with the signal output end G(N+4) of the (N+4)th GOA unit, a second end of the forty-first thin film transistor is connected with the first node, and a third end of the forty-first thin film transistor is connected with the third node.

[0016] In a possible implementation manner of the application, the pull-down maintaining module comprises a fifty-first thin film transistor, a fifty-second thin film transistor, a fifty-third thin film transistor, a fifty-fourth thin film transistor, a fifty-fifth thin film transistor, a fifty-sixth thin film transistor and a forty-second thin film transistor.

[0017] The first end and the second end of the fifty-first thin film transistor are both connected with the constant-voltage high potential signal end, and the second end of the fifty-first thin film transistor is connected with a fifth node.

[0018] a first terminal of the fifty-second thin film transistor is connected to the first node, a second terminal of the fifty-second thin film transistor is connected to the fifth node, and a third terminal of the fifty-second thin film transistor is connected to the fourth node;

[0019] a first terminal of the fifty-third thin film transistor is connected to the fifth node, a second terminal of the fifty-third thin film transistor is connected to the constant-voltage high-potential signal terminal, and a third terminal of the fifty-third thin film transistor is connected to a sixth node;

[0020] a first terminal of the fifty-fourth thin film transistor is connected to the first node, a second terminal of the fifty-fourth thin film transistor is connected to the sixth node, and a third terminal of the fifty-fourth thin film transistor is connected to the fourth node;

[0021] a first terminal of the fifty-fifth thin film transistor is connected to the third node, a second terminal of the fifty-fifth thin film transistor is connected to the fifth node, and a third terminal of the fifty-fifth thin film transistor is connected to the fourth node;

[0022] a first terminal of the fifty-sixth thin film transistor is connected to the third node, a second terminal of the fifty-sixth thin film transistor is connected to the sixth node, and a third terminal of the fifty-sixth thin film transistor is connected to the fourth node;

[0023] a first terminal of the forty-second thin film transistor is connected to the sixth node, a second terminal of the forty-second thin film transistor is connected to the first node, and a third terminal of the forty-second thin film transistor is connected to the third node.

[0024] In a possible implementation manner of the application, the pull-down maintaining module further includes a thirty-second thin film transistor, a first terminal of the thirty-second thin film transistor is connected to the sixth node, a second terminal of the thirty-second thin film transistor is connected to the second node, and a third terminal of the thirty-second thin film transistor is connected to the fourth node.

[0025] In a possible implementation manner of the application, the GOA driving-off module includes a driving-off thin film transistor, a first terminal of the driving-off thin film transistor is connected to the gate-off signal terminal, a second terminal of the driving-off thin film transistor is connected to the second node, and a third terminal of the driving-off thin film transistor is connected to the fourth node.

[0026] In a possible implementation manner of the application, the GOA circuit further includes a first reset thin film transistor, a first terminal of the first reset thin film transistor is connected to a reset signal terminal, a second terminal of the first reset thin film transistor is connected to the first node, and a third terminal of the first reset thin film transistor is connected to the fourth node.

[0027] In a possible implementation of the present application, the GOA circuit further comprises a second reset thin film transistor, a first end of the second reset thin film transistor is connected to a reset signal end, a second end of the second reset thin film transistor is connected to the second node, and a third end of the second reset thin film transistor is connected to the fourth node.

[0028] In a second aspect, the present application provides a display panel, comprising a plurality of rows of sub-pixels and the GOA circuit as described in the first aspect, the GOA circuit being electrically connected to the plurality of rows of sub-pixels and used for driving the plurality of rows of sub-pixels to emit light.

[0029] The GOA circuit of the present application provides a low-level signal through the gate-off signal end in a display period to make the pull-down maintenance module maintain the pull-down function, uses a periodic clock signal and an output signal of a previous stage to control the pull-up control module to charge the capacitor of the first node, uses the periodic clock signal and the voltage of the first node to control the opening or closing of the pull-up module, and synchronously makes the output signal end G(N) of the GOA a high level according to the periodic clock signal becoming a high potential, thereby effectively opening the corresponding Pixel TFT. The pull-down maintenance module makes the output signal end G(N) of the GOA maintain a low level to make the corresponding Pixel TFT effectively closed; in a touch period, a high potential signal is provided through the gate-off signal end to make the pull-down maintenance module invalid, and the GOA driving-off module is opened at the same time, the invalidation of the pull-down maintenance module makes the leakage of the first node suppressed, and the output signal end G(N) of the Nth-stage GOA unit is pulled down to a low level provided by the constant-voltage negative potential signal end through the GOA driving-off module, thereby keeping the output signal of the output signal end G(N) of the Nth-stage GOA unit continuously inputting a low voltage to the Pixel TFT in the touch period. Therefore, the GOA circuit of the present application can keep normal signal level transmission in the display period and can reduce the charge leakage of the GOA circuit in the touch period. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0031] Figure 1 is a structural schematic diagram of a display panel circuit in the prior art of the present application;

[0032] Figure 2 is a structural schematic diagram of a GOA circuit provided in an embodiment of the present application;

[0033] Figure 3 is a timing diagram of a GOA circuit provided in an embodiment of the present application;

[0034] Figure 4 is a structural diagram of an embodiment of a GOA circuit provided in an embodiment of the present application;

[0035] Figure 5 is a structural diagram of an embodiment of a GOA circuit provided in an embodiment of the present application;

[0036] Figure 6 is a timing diagram of a GOA circuit provided in an embodiment of the present application;

[0037] Figure 7 is a timing diagram of a GOA circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, any other embodiments obtained by a person skilled in the art without creative work fall within the protection scope of the present application.

[0039] In the description of the present application, it should be understood that the terms "first", "second" are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0040] In the present application, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation described as "exemplary" in the present application is not necessarily to be construed as preferred or advantageous over other implementations. The following description is presented to enable any person skilled in the art to make and use the application. In the following description, for purposes of explanation, specific details are set forth. It is apparent to those skilled in the art that the present application can be practiced without using these specific details. In other instances, well-known structures and processes are not described in detail in order to avoid obscuring the description of the present application. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features presented herein.

[0041] Figure 1As shown in the schematic diagram of the display panel circuit in the prior art, the display panel circuit includes an array substrate row driving (Gate Driver On Array, GOA) circuit, a source driving chip (Source IC), and a pixel corresponding thin film transistor (Pixel TFT) corresponding to each pixel (Pixel). The GOA circuit includes a plurality of cascaded GOA units (G1, G2, G3…Gn1, and Gn). Each GOA unit is used to drive a row of Pixel TFTs. The Source IC includes a plurality of source units (S1, S2, S3…Sn 1, and Sn). Each source unit is used to provide power supply for a column of Pixel TFTs.

[0042] With the rapid development of display technology, touch display panels have been widely accepted and used by people, such as smart phones, tablet computers, etc. all use touch display panels (Touch Panel Technology). The touch display panel integrates the touch panel and the liquid crystal panel into one, so that the liquid crystal panel has the functions of display and sensing touch input. According to the different positions of the touch sensor (Touch sensor), the touch display panel can be divided into Out cell (touch sensor is externally hung on the display panel), On cell (touch sensor is arranged on the display panel) and In cell (touch sensor is integrated in the display panel) and other technical architectures.

[0043] Among them, the In cell type touch display panel needs to have a signal pause function, that is, during the display process, when the GOA circuit is normally working, the output end of all GOA units in the GOA circuit needs to be closed during the touch period, the gate scanning driving signal output is stopped to perform touch scanning, and after the touch scanning is completed, the GOA circuit is restored to normal during the display period, and the gate scanning driving signal output is continued.

[0044] In the conventional GOA circuit as shown in Figure 2 , there is a long touch period between two display periods. Since the control node (Q point) needs to be kept at a high level after the touch period, the GOA circuit stage is pulled up again to display again, as shown in the circuit timing of the GOA circuit in Figure 3 , the Q point is easy to leak when kept at a high level during the touch period.

[0045] To solve the above problems, the embodiments of the present application provide a GOA circuit and a display panel, which are described in detail below.

[0046] As shown in Figure 4As shown, it is a structural schematic diagram of an embodiment of the GOA circuit in the application, the GOA circuit includes a plurality of GOA units cascaded, each GOA unit includes a pull-up control module 10, a pull-up module 20, a capacitor module 30, a pull-down maintenance module 40, a pull-down module 60 and a GOA drive-off module 50;

[0047] If the Nth GOA unit is the GOA unit after the first three GOA units, the pull-up control module 10 is connected with the signal output end G(N-3) of the (N-3)th GOA unit, the constant-voltage high potential signal end VGH and the first node Q(N) respectively, and N is a natural number;

[0048] The pull-up module 20 is connected with the clock signal line CK, the first node Q(N) and the second node X(N) respectively;

[0049] The capacitor module 30 is connected with the first node Q(N) and the second node X(N) respectively, in the embodiment, the capacitor module 30 includes a capacitor Cbt, two ends of the capacitor Cbt are connected with the first node Q(N) and the second node X(N) respectively;

[0050] The pull-down maintenance module 40 is connected with the constant-voltage high potential signal end VGH, the first node Q(N), the second node X(N), the third node Y(N) and the fourth node M(N) respectively, wherein the third node Y(N) is connected with the gate-off signal end AGO, and the fourth node M(N) is connected with the constant-voltage negative potential signal end VSS;

[0051] The pull-down module 60 is connected with the signal output end G(N+4) of the (N+4)th GOA unit, the first node Q(N) and the third node Y(N) respectively;

[0052] The GOA drive-off module 50 is connected with the gate-off signal end AGO, the second node X(N) and the fourth node M(N) respectively;

[0053] Wherein, the gate-off signal end AGO is used to provide a low-level signal in a display period, and is used to provide a high-level signal in a touch period, when the gate-off signal end AGO provides a low-level signal, the pull-down maintenance module 40 keeps the pull-down maintenance function, and when the gate-off signal end AGO provides a high-level signal, the pull-down maintenance module 40 is disabled.

[0054] In the embodiment, in the display period, the gate-off signal end AGO provides a low-level signal, at this time, the pull-down maintenance module 40 keeps the pull-down maintenance function, the pull-up control module 10 is controlled to be turned on or turned off by the output signal of the signal output end G(N-3) of the (N-3)th GOA unit, the capacitor module 30 at the first node Q(N) is charged by the constant-voltage high potential signal end VGH signal, and the pull-up module 20 is driven to be turned on.

[0055] In the case that the pull-up module 20 is opened, if the clock signal output by the Nth stage clock signal line CK changes from low level to high level, the output signal of the output signal terminal G(N) of the Nth stage GOA unit also synchronously changes to high level and is input to the panel display area, driving the corresponding pixel TFT to open, so that the pixel fills the correct source voltage.

[0056] After the Pixel TFT in the panel display area receives the source voltage, if the clock signal output by the Nth stage clock signal line CK changes from high level to low level, the output signal terminal G(N) of the Nth stage GOA unit also synchronously changes to low level, so that the Pixel TFT can be effectively closed and the related source voltage can be effectively locked. Therefore, at this time, the first node Q(N) needs to continue to maintain high level, so that the pull-up module 20 can effectively pull down the output signal of the output signal terminal G(N) of the Nth stage GOA unit.

[0057] After the Nth stage GOA unit works, in order to maintain the output signal terminal G(N) of the Nth stage GOA unit to continuously input low voltage to the Pixel TFT, the low voltage of the output signal terminal G(N) of the Nth stage GOA unit is maintained by the pull-down maintenance module 40 in the present application.

[0058] When entering the touch period, the touch sensor of the display panel is started, at this time, the gate-off signal terminal AGO provides a high level signal, the pull-down maintenance module 40 is disabled, and since the gate-off signal terminal AGO provides a high level signal to provide a high level signal for the devices in the pull-down maintenance module 40, in this state, the leakage of the first node Q(N) is inhibited, thereby reducing the leakage of the first node Q(N) in the touch period;

[0059] At the same time, the GOA drive-off module 50 is opened, the output signal terminal G(N) of the Nth stage GOA unit is pulled down to the low level provided by the constant voltage negative potential signal terminal VSS through the GOA drive-off module 50, so that the output signal of the output signal terminal G(N) of the Nth stage GOA unit continuously inputs low voltage to the Pixel TFT.

[0060] That is, in the display period, the GOA circuit of the present application provides a low level signal to the gate-off signal terminal AGO to make the pull-down maintaining module 40 maintain the pull-down function, uses the periodic clock signal and the output signal of the previous stage to control the pull-up control module 10 to charge the capacitor Cbt of the first node Q(N), uses the periodic clock signal and the voltage of the first node Q(N) to control the opening or closing of the pull-up module 20, and synchronously makes the output signal terminal G(N) of the Nth GOA unit high when the periodic clock signal becomes high, thereby effectively opening the corresponding Pixel TFT. The pull-down maintaining module 40 makes the output signal terminal G(N) of the Nth GOA unit maintain low to make the corresponding Pixel TFT effectively closed; in the touch period, a high level signal is provided to the gate-off signal terminal AGO to make the pull-down maintaining module 40 invalid, and at the same time, the GOA drive-off module 50 is opened. The invalidation of the pull-down maintaining module 40 makes the leakage of the first node Q(N) suppressed, and the GOA drive-off module 50 pulls the output signal terminal G(N) of the Nth GOA unit low to the low level provided by the constant voltage negative potential signal terminal VSS, thereby keeping the output signal of the output signal terminal G(N) of the Nth GOA unit continuously inputting low voltage to the Pixel TFT in the touch period. Therefore, the GOA circuit of the present application can keep normal signal level transmission in the display period, and can reduce the charge leakage of the GOA circuit in the touch period.

[0061] In some embodiments of the present application, as shown in Figure 5 The pull-up control module 10 includes an eleventh thin film transistor T11, the first end of the eleventh thin film transistor T11 is connected to the signal output terminal G(N-3) of the (N-3)th GOA unit, the second end of the eleventh thin film transistor T11 is connected to the constant voltage high potential signal terminal VGH, and the third end of the eleventh thin film transistor T11 is connected to the first node Q(N).

[0062] Specifically, the gate of the eleventh thin film transistor T11 is connected to the signal output terminal G(N-3) of the (N-3)th GOA unit, and the source and drain of the eleventh thin film transistor T11 are respectively connected to the constant voltage high potential signal terminal VGH and the first node Q(N).

[0063] In the present embodiment, the pull-up module 20 includes a twenty-first thin film transistor T21, the first end of the twenty-first thin film transistor T21 is connected to the first node Q(N), the second end of the twenty-first thin film transistor T21 is connected to the clock signal line CK, and the second end of the twenty-first thin film transistor T21 is connected to the second node X(N).

[0064] Specifically, the gate of the twenty-first thin film transistor T21 is connected to the first node Q(N), and the source and the drain of the twenty-first thin film transistor T21 are connected to the clock signal line CK and the second node X(N) respectively.

[0065] In the embodiment, the eleventh thin film transistor T11 and the twenty-first thin film transistor T21 are both thin film transistors (TFT).

[0066] When the signal output end G(N-3) of the (N-3)th GOA unit changes from low level to high level, the eleventh thin film transistor T11 is turned on, and the first node Q(N) is charged through the capacitor Cbt, until the voltage at the first node Q(N) meets the opening condition of the twenty-first thin film transistor T21, the twenty-first thin film transistor T21 is turned on, at this time, the output signal end G(N) of the Nth GOA unit outputs low voltage according to the low level input of the Nth clock signal line CK.

[0067] When the clock signal provided by the Nth clock signal line CK changes from low level to high level, the capacitor Cbt stops charging, at this time, the output signal end G(N) of the Nth GOA unit outputs high level from low level according to the high level input of the Nth clock signal line CK, so as to effectively open the corresponding Pixel TFT.

[0068] When the clock signal provided by the mth clock signal line Ckm changes from high level to low level, since the first node Q(N) still maintains high level, the output signal end G(N) of the Nth GOA unit outputs low level from high level according to the low level input of the Nth clock signal line CK, and at this time, the Gout maintains low level due to the action of the pull-down maintaining module 40, so as to effectively close the corresponding Pixel TFT.

[0069] In some embodiments of the present application, the pull-down module 60 comprises a forty-first thin film transistor T41, the first end of the forty-first thin film transistor T41 is connected to the signal output end G(N+4) of the (N+4)th GOA unit, the second end of the forty-first thin film transistor T41 is connected to the first node Q(N), and the third end of the forty-first thin film transistor T41 is connected to the third node Y(N).

[0070] Specifically, the gate of the forty-first thin film transistor T41 is connected to the signal output end G(N+4) of the (N+4)th GOA unit, and the source and the drain of the forty-first thin film transistor T41 are connected to the first node Q(N) and the third node Y(N) respectively. In the embodiment, the forty-first thin film transistor T41 is a thin film transistor TFT.

[0071] In the display period, the gate-off signal terminal AGO provides a low level signal, when the Nth GOA unit works completely and the signal output terminal G(N+4) of the (N+4)th GOA unit cascaded with the Nth GOA unit outputs a high level, the forty-first thin film transistor T41 is turned on, at this time, the potential of the first node Q(N) is pulled down to the low potential provided by the gate-off signal terminal AGO.

[0072] In some embodiments of the present application, the pull-down maintaining module 40 includes a fifty-first thin film transistor T51, a fifty-second thin film transistor T52, a fifty-third thin film transistor T53, a fifty-fourth thin film transistor T54, a fifty-fifth thin film transistor T55, a fifty-sixth thin film transistor T56 and a forty-second thin film transistor T42.

[0073] The first end and the second end of the fifty-first thin film transistor T51 are both connected to the constant-voltage high potential signal terminal VGH, and the second end of the fifty-first thin film transistor T51 is connected to the fifth node J(N).

[0074] The first end of the fifty-second thin film transistor T52 is connected to the first node Q(N), the second end of the fifty-second thin film transistor T52 is connected to the fifth node J(N), and the third end of the fifty-second thin film transistor T52 is connected to the fourth node M(N).

[0075] The first end of the fifty-third thin film transistor T53 is connected to the fifth node J(N), the second end of the fifty-third thin film transistor T53 is connected to the constant-voltage high potential signal terminal VGH, and the third end of the fifty-third thin film transistor T53 is connected to the sixth node K(N).

[0076] The first end of the fifty-fourth thin film transistor T54 is connected to the first node Q(N), the second end of the fifty-fourth thin film transistor T54 is connected to the sixth node K(N), and the third end of the fifty-fourth thin film transistor T54 is connected to the fourth node M(N).

[0077] The first end of the fifty-fifth thin film transistor T55 is connected to the third node Y(N), the second end of the fifty-fifth thin film transistor T55 is connected to the fifth node J(N), and the third end of the fifty-fifth thin film transistor T55 is connected to the fourth node M(N).

[0078] The first end of the fifty-sixth thin film transistor T56 is connected to the third node Y(N), the second end of the fifty-sixth thin film transistor T56 is connected to the sixth node K(N), and the third end of the fifty-sixth thin film transistor T56 is connected to the fourth node M(N).

[0079] A first terminal of the forty-second thin film transistor T42 is connected to the sixth node K(N), a second terminal of the forty-second thin film transistor T42 is connected to the first node Q(N), and a third terminal of the forty-second thin film transistor T42 is connected to the third node Y(N).

[0080] Specifically, the gate and the source of the fifty-first thin film transistor T51 and the source of the fifty-third thin film transistor T53 are connected to the constant-voltage high-potential signal terminal VGH, the drain of the fifty-first thin film transistor T51, the gate of the fifty-third thin film transistor T53, the source of the fifty-second thin film transistor T52, and the source of the fifty-fifth thin film transistor T55 are commonly connected to form the fifth node J(N), the drain of the fifty-third thin film transistor T53, the source of the fifty-fourth thin film transistor T54, the source of the fifty-sixth thin film transistor T56, and the gate of the forty-second thin film transistor T42 are commonly connected to form the sixth node K(N), the gate of the fifty-second thin film transistor T52 and the gate of the fifty-fourth thin film transistor T54 are both connected to the first node Q(N), the gate of the fifty-fifth thin film transistor T55 and the drain of the forty-second thin film transistor T42 are both connected to the third node Y(N), and the drain of the fifty-second thin film transistor T52, the drain of the fifty-fourth thin film transistor T54, the drain of the fifty-fifth thin film transistor T55, the drain of the fifty-sixth thin film transistor T56, and the drain of the fifty-fifth thin film transistor T55 are commonly connected to the fourth node M(N), and the source of the forty-second thin film transistor T42 is connected to the first node Q(N).

[0081] In this embodiment, the pull-down maintaining module 40 further includes a thirty-second thin film transistor T32, a first terminal of the thirty-second thin film transistor T32 is connected to the sixth node K(N), a second terminal of the thirty-second thin film transistor T32 is connected to the second node X(N), and a third terminal of the thirty-second thin film transistor T32 is connected to the fourth node M(N).

[0082] Specifically, the gate of the thirty-second thin film transistor T32 is connected to the sixth node K(N), and the source and the drain of the thirty-second thin film transistor T32 are connected to the second node X(N) and the fourth node M(N), respectively.

[0083] In this embodiment, the fifty-first thin film transistor T51, the fifty-second thin film transistor T52, the fifty-third thin film transistor T53, the fifty-fourth thin film transistor T54, the fifty-fifth thin film transistor T55, the fifty-sixth thin film transistor T56, the forty-second thin film transistor T42, and the thirty-second thin film transistor T32 are all thin film transistors TFT.

[0084] In the embodiment, the fifty-first thin film transistor T51, the fifty-second thin film transistor T52, the fifty-third thin film transistor T53, the fifty-fourth thin film transistor T54, the fifty-fifth thin film transistor T55 and the fifty-sixth thin film transistor T56 together constitute an inverter in the GOA unit.

[0085] After the Nth-stage GOA unit is operated, the output signal terminal G(N) of the Nth-stage GOA unit needs to continuously output a low level to the Pixel TFT. Therefore, during the display period, the pull-down maintaining module 40 needs to continuously maintain the output signal terminal G(N) at a low level.

[0086] Specifically, during the display period and when the clock signal provided by the Nth-stage clock signal line CK is in the process of low level-high level-low level, the constant-voltage high potential signal terminal VGH provides a high level to turn on the fifty-first thin film transistor T51, and the high level at the first node Q(N) turns on the fifty-second thin film transistor T52 and the fifty-fourth thin film transistor T54. At this time, the sixth node K(N) is pulled down to the low level provided by the constant-voltage negative potential signal terminal VSS, and because the gate-off signal terminal AGO provides a low level signal, at this time, the fifty-fifth thin film transistor T55, the fifty-sixth thin film transistor T56 and the forty-second thin film transistor T42 are all turned off, so that the first node Q(N) maintains a high level.

[0087] When the Nth-stage GOA unit is operated and the signal output terminal G(N+4) of the (N+4)th-stage GOA unit cascaded with the Nth-stage GOA unit outputs a high level, the forty-first thin film transistor T41 in the pull-down module 60 is turned on, at this time, the potential of the first node Q(N) is pulled down to the low level provided by the gate-off signal terminal AGO, and finally the output of the output signal terminal G(N) of the Nth-stage GOA unit is maintained at a low level.

[0088] During the touch period, the gate-off signal terminal AGO provides a high level signal, at this time, the fifty-fifth thin film transistor T55 and the fifty-sixth thin film transistor T56 are turned on, at this time, the fifth node J(N) and the sixth node K(N) are both pulled down to the low level provided by the constant-voltage negative potential signal terminal VSS, so that the inverter composed of the fifty-first thin film transistor T51, the fifty-second thin film transistor T52, the fifty-third thin film transistor T53, the fifty-fourth thin film transistor T54, the fifty-fifth thin film transistor T55 and the fifty-sixth thin film transistor T56 is disabled, and the forty-second thin film transistor T42 is turned off. At the same time, because the drain of the forty-first thin film transistor T41 and the drain of the forty-second thin film transistor T42 are both connected to the gate-off signal terminal AGO to provide a high level signal, that is, the drain of the forty-first thin film transistor T41 and the drain of the forty-second thin film transistor T42 are both high level, so that the leakage of the first node Q(N) can be inhibited.

[0089] The application further stabilizes the sixth node K(N) to be pulled down to a low level in the display stage by adding a fifty-sixth thin film transistor T56 in the inverter, so that the forty-second thin film transistor T42 is closed more tightly.

[0090] After the touch period, the gate-off signal end AGO is switched to a low-level signal, at this time, the GOA unit with the first node Q(N) being a high potential continues to be level-shifted, and the normal GOA circuit driving is restored.

[0091] In some embodiments of the application, the GOA driving-off module 50 comprises a driving-off thin film transistor Tago, a first end of the driving-off thin film transistor Tago being connected to the gate-off signal end AGO, a second end of the driving-off thin film transistor Tago being connected to the second node X(N), and a third end of the driving-off thin film transistor Tago being connected to the fourth node M(N).

[0092] Specifically, a gate of the driving-off thin film transistor Tago is connected to the gate-off signal end AGO, a source and a drain of the driving-off thin film transistor Tago are connected to the second node X(N) and the fourth node M(N) respectively. In this embodiment, the driving-off thin film transistor Tago is a thin film transistor TFT.

[0093] In the display period, the gate-off signal end AGO provides a low level, and the driving-off thin film transistor Tago is closed, and in the touch period, the gate-off signal end AGO provides a high level, and the driving-off thin film transistor Tago is opened, at this time, the output signal end G(N) of the Nth GOA unit is pulled down to a low level provided by the constant-voltage negative potential signal end VSS, which is equivalent to locking all the output signal ends G(N) of the GOA units at a low level in the touch period.

[0094] In summary, the application is equivalent to proposing an inverter structure, in which the AGO signal input from the gate-off signal end AGO is input to the Vin of the inverter structure, so that the AGO signal is combined with the Q point signal of the first node Q(N) in the same inverter, and by using the special timing setting of the AGO signal, specifically, in the normal period, the gate-off signal end AGO is a low level, the fifty-fifth thin film transistor T55 is closed, the inverter is consistent with the principle of the normal inverter, and the normal pull-down maintaining function is realized; in the touch period, the gate-off signal end AGO is a high level, the fifty-fifth thin film transistor T55 is opened, the inverter function is closed, and the leakage of the first node Q(N) is effectively reduced.

[0095] In some embodiments of this application, the GOA circuit further includes a first reset thin-film transistor TrQ, the first terminal of which is connected to the reset signal terminal Reset, the second terminal of which is connected to the first node Q(N), and the third terminal of which is connected to the fourth node M(N).

[0096] Specifically, the gate of the first reset thin-film transistor TrQ is connected to the reset signal terminal Reset, and the source and drain of the first reset thin-film transistor TrQ are connected to the first node Q(N) and the fourth node M(N), respectively. In this embodiment, the first reset thin-film transistor TrQ is a thin-film transistor (TFT).

[0097] After any frame of the image is displayed, a reset signal is provided through the Reset signal terminal to turn on the first reset thin-film transistor TrQ, so as to pull the potential of the first node Q(N) down to the low potential provided by the constant voltage negative potential signal terminal VSS, thereby realizing the reset of the first node Q(N) of the Nth level GOA unit.

[0098] In some embodiments of this application, the GOA circuit further includes a second reset thin-film transistor TrG, the first terminal of which is connected to the reset signal terminal Reset, the second terminal of which is connected to the second node X(N), and the third terminal of which is connected to the fourth node M(N).

[0099] Specifically, the gate of the second reset thin-film transistor TrG is connected to the reset signal terminal Reset, and the source and drain of the second reset thin-film transistor TrG are connected to the second node X(N) and the fourth node M(N), respectively. In this embodiment, the second reset thin-film transistor TrG is a thin-film transistor (TFT).

[0100] After any frame of the image is displayed, a reset signal is provided through the Reset signal terminal to turn on the second reset thin-film transistor TrG, so as to pull down the output potential of the output signal terminal G(N) of the GOA unit to the low potential provided by the constant voltage negative potential signal terminal VSS, thereby resetting the output signal terminal G(N) of the Nth stage GOA unit.

[0101] The timing of the GOA circuit in this application adopts Figure 6 The time-division multiplexing timing shown divides a frame into multiple display and touch periods, effectively enhancing the touch sensitivity of the display panel. Furthermore, the GOA circuit in this application uses a Touch and Display Driver Integration (TDDI) for driving.

[0102] Combination Figure 6 andFigure 7 The working principle of the present application is described.

[0103] (1) In the display period (non-touch period):

[0104] The gate-off signal terminal AGO provides a low-level signal to drive the thin-film transistor Tago, the fifty-fifth thin-film transistor T55 and the fifty-sixth thin-film transistor T56 to be closed, so that the pull-down maintenance module 40 maintains the pull-down maintenance function;

[0105] When the signal output terminal G(N-3) of the (N-3)th GOA unit changes from low level to high level, the eleventh thin-film transistor T11 is turned on, the first node Q(N) is charged through the capacitor Cbt, and when the voltage at the first node Q(N) meets the opening condition of the twenty-first thin-film transistor T21, the twenty-first thin-film transistor T21 is turned on. At this time, the output signal terminal G(N) of the Nth GOA unit outputs a low voltage according to the low level input by the Nth clock signal line CK;

[0106] When the clock signal provided by the Nth clock signal line CK changes from low level to high level, the capacitor Cbt stops charging. At this time, the output signal terminal G(N) of the Nth GOA unit outputs from low level to high level according to the high level input by the Nth clock signal line CK, so as to effectively open the corresponding Pixel TFT;

[0107] When the clock signal provided by the mth clock signal line Ck changes from high level to low level, since the first node Q(N) still maintains high level, the output signal terminal G(N) of the Nth GOA unit outputs from high level to low level according to the low level input by the Nth clock signal line CK;

[0108] At the same time in the pull-down maintenance module 40, the constant-voltage high-potential signal terminal VGH provides high level to make the fifty-first thin-film transistor T51 open, and the high level at the first node Q(N) makes the fifty-second thin-film transistor T52 and the fifty-fourth thin-film transistor T54 open. At this time, the sixth node K(N) is pulled down to the low potential provided by the constant-voltage negative potential signal terminal VSS, so that the forty-second thin-film transistor T42 is closed, the first node Q(N) maintains high level, and the output signal terminal G(N) of the Nth GOA unit maintains output low level, so as to effectively close the corresponding Pixel TFT.

[0109] (2) In the touch period:

[0110] The touch sensor of the display panel is turned on, the gate off signal end AGO provides a high level signal, the driving off thin film transistor Tago, the fifty-fifth thin film transistor T55 and the fifty-sixth thin film transistor T56 are all turned on, at this time, the fifth node J(N), the sixth node K(N) and all the output signal ends G(N) in the pull-down maintaining module 40 are all pulled down to the low potential provided by the constant voltage negative potential signal end VSS, the forty-second thin film transistor T42 is turned off, and the pull-down maintaining module 40 and all the output signal ends G(N) are all disabled;

[0111] Since the drain of the forty-first thin film transistor T41 and the drain of the forty-second thin film transistor T42 are both connected to the gate off signal end AGO to provide a high level signal, that is, the drain of the forty-first thin film transistor T41 and the drain of the forty-second thin film transistor T42 are both high level, so that the leakage of the first node Q(N) can be inhibited;

[0112] As shown in FIG. 6, during the touch period, all the GOA signals follow the COM modulation, and the same coupling effect as the in-plane is maintained, which effectively reduces the capacitive coupling effect (Touch Loading) with the in-plane line during the touch period. Figure 7

[0113] After the touch period ends, the gate off signal end AGO is switched to a low level signal, at this time, the GOA unit with the first node Q(N) being high potential continues to perform level transmission, and the normal GOA circuit driving is restored.

[0114] The application also provides a display panel, which comprises a plurality of rows of sub-pixels and the GOA circuit in any one of the embodiments of the application; the GOA circuit is electrically connected to the plurality of rows of sub-pixels and is used for driving the plurality of rows of sub-pixels to emit light. The display panel can be a passive light-emitting display panel, such as a liquid crystal display panel, or an active light-emitting display panel, such as an organic light-emitting diode display panel, a mini light-emitting diode display panel, and a micro light-emitting diode display panel.

[0115] The GOA circuit and the display panel provided by the embodiments of the application are described in detail above, and the principles and implementation manners of the application are described by applying specific examples in this paper; the above description of the embodiments is only used to help understand the method of the application and the core idea thereof; meanwhile, for those skilled in the art, according to the idea of the application, the specific implementation manners and application ranges will all be changed, and the above description should not be understood as limiting the application.​

Claims

1. A GOA circuit, characterized in that, The GOA circuit includes multiple cascaded GOA units, each of which includes a pull-up control module, a pull-up module, a capacitor module, a pull-down sustaining module, a pull-down module, and a GOA drive shutdown module. The pull-up control module is connected to the signal output terminal G(N-3) of the (N-3)th level GOA unit, the constant voltage high potential signal terminal and the first node, respectively, where N is a natural number; The pull-up module is connected to the clock signal line, the first node, and the second node, respectively. The capacitor module is connected to the first node and the second node respectively; The pull-down sustaining module is connected to the constant voltage high potential signal terminal, the first node, the second node, the third node and the fourth node respectively, wherein the third node is connected to the gate turn-off signal terminal and the fourth node is connected to the constant voltage negative potential signal terminal; The pull-down module is connected to the signal output terminal G(N+4) of the (N+4)th level GOA unit, the first node, and the third node, respectively. The GOA drive shutdown module is connected to the gate shutdown signal terminal, the second node, and the fourth node, respectively. The gate-off signal terminal is used to provide a low-potential signal during the display period and a high-potential signal during the touch period. When the gate-off signal terminal provides a low-potential signal, the pull-down sustaining module maintains its pull-down sustaining function. When the gate-off signal terminal provides a high-potential signal, the pull-down sustaining module fails. The pull-down sustaining module includes a 51st thin-film transistor, a 52nd thin-film transistor, a 53rd thin-film transistor, a 54th thin-film transistor, a 55th thin-film transistor, a 56th thin-film transistor, and a 42nd thin-film transistor. The first and second terminals of the fifty-first thin-film transistor are both connected to the constant voltage high-potential signal terminal, and the second terminal of the fifty-first thin-film transistor is connected to the fifth node; The first terminal of the fifty-second thin-film transistor is connected to the first node, the second terminal of the fifty-second thin-film transistor is connected to the fifth node, and the third terminal of the fifty-second thin-film transistor is connected to the fourth node. The first terminal of the fifty-third thin-film transistor is connected to the fifth node, the second terminal of the fifty-third thin-film transistor is connected to the constant voltage high potential signal terminal, and the third terminal of the fifty-third thin-film transistor is connected to the sixth node. The first terminal of the fifty-fourth thin-film transistor is connected to the first node, the second terminal of the fifty-fourth thin-film transistor is connected to the sixth node, and the third terminal of the fifty-fourth thin-film transistor is connected to the fourth node. The first terminal of the fifty-fifth thin-film transistor is connected to the third node, the second terminal of the fifty-fifth thin-film transistor is connected to the fifth node, and the third terminal of the fifty-fifth thin-film transistor is connected to the fourth node. The first terminal of the fifty-sixth thin-film transistor is connected to the third node, the second terminal of the fifty-sixth thin-film transistor is connected to the sixth node, and the third terminal of the fifty-sixth thin-film transistor is connected to the fourth node. The first terminal of the forty-second thin-film transistor is connected to the sixth node, the second terminal of the forty-second thin-film transistor is connected to the first node, and the third terminal of the forty-second thin-film transistor is connected to the third node.

2. The GOA circuit as described in claim 1, characterized in that, The pull-up control module includes an eleventh thin-film transistor. The first terminal of the eleventh thin-film transistor is connected to the signal output terminal G(N-3) of the (N-3)th level GOA unit. The second terminal of the eleventh thin-film transistor is connected to the constant voltage high potential signal terminal. The third terminal of the eleventh thin-film transistor is connected to the first node.

3. The GOA circuit as described in claim 2, characterized in that, The pull-up module includes a 21st thin-film transistor, the first end of which is connected to the first node, the second end of which is connected to the clock signal line, and the third end of which is connected to the second node.

4. The GOA circuit as described in claim 3, characterized in that, The pull-down module includes a forty-first thin-film transistor. The first end of the forty-first thin-film transistor is connected to the signal output terminal G(N+4) of the (N+4)th level GOA unit. The second end of the forty-first thin-film transistor is connected to the first node. The third end of the forty-first thin-film transistor is connected to the third node.

5. The GOA circuit as described in claim 4, characterized in that, The pull-down sustaining module also includes a 32nd thin-film transistor, the first end of which is connected to the 6th node, the second end of which is connected to the 2nd node, and the third end of which is connected to the 4th node.

6. The GOA circuit as described in claim 5, characterized in that, The GOA drive shutdown module includes a drive shutdown thin-film transistor, the first end of which is connected to the gate shutdown signal terminal, the second end of which is connected to the second node, and the third end of which is connected to the fourth node.

7. The GOA circuit as described in any one of claims 1 to 6, characterized in that, The GOA circuit further includes a first reset thin-film transistor, the first end of which is connected to a reset signal terminal, the second end of which is connected to the first node, and the third end of which is connected to the fourth node.

8. The GOA circuit as described in any one of claims 1 to 6, characterized in that, The GOA circuit further includes a second reset thin-film transistor, the first end of which is connected to a reset signal terminal, the second end of which is connected to the second node, and the third end of which is connected to the fourth node.

9. A display panel, characterized in that, The display panel includes multiple rows of sub-pixels and a GOA circuit as described in any one of claims 1 to 8, wherein the GOA circuit is electrically connected to the multiple rows of sub-pixels and is used to drive the multiple rows of sub-pixels to emit light.

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