Gate drive circuit and display device
By introducing a combination of pull-up module, isolation module, pull-down sustaining module and inverting module into the gate drive circuit, the instability of transistors caused by the first node potential change in narrow bezel display devices is solved, and the stability and accuracy of signal output are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGZHOU CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
- Filing Date
- 2023-09-11
- Publication Date
- 2026-06-05
Smart Images
Figure CN117456942B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of display technology, and more specifically to a gate driving circuit and a display device. Background Technology
[0002] Existing gate drive circuits such as Figure 1 As shown, in the gate drive circuit, transistor T21 is turned on or off according to the potential of the first node N1. Therefore, when the potential of the first node N1 fluctuates due to clock signal fluctuations and parasitic capacitance coupling between the gate and source of transistor T21, it affects the operating state of transistor T21 and the output performance of the gate drive circuit. Especially in narrow-bezel display devices, the gate drive circuit uses a single inverter to pull down and maintain the potential of the first node N1, causing the pull-down effect of the pull-down module to decrease after prolonged use. If this is compounded by the fluctuations in the potential of the first node N1 caused by coupling, it can lead to errors in the output signal of the gate drive circuit, causing the gate drive circuit to fail. Summary of the Invention
[0003] This invention provides a gate driving circuit and a display device, which can improve the problem of gate driving circuit failure.
[0004] This invention provides a gate driving circuit, including a pull-up module, an isolation module, a pull-down sustaining module, and an inverting module. The pull-up module is electrically connected to a first node and is configured to connect a clock signal line to the signal output terminal of the gate driving circuit, or disconnect the clock signal line from the signal output terminal, depending on the potential of the first node. The isolation module is electrically connected to the first node and a second node and is configured to block the coupling effect of potential changes in the first node on the potential of the second node. The pull-down sustaining module is electrically connected to the first node and a first power supply terminal. The inverting module is electrically connected to the second node and is configured to control the pull-down sustaining module to connect the first power supply terminal to the first node, or disconnect the electrical connection between the first power supply terminal and the first node, depending on the potential of the second node.
[0005] Embodiments of the present invention provide a display device including any of the above-described gate driving circuits.
[0006] This invention provides a gate driving circuit and a display device, including a pull-up module, an isolation module, a pull-down sustaining module, and an inverting module. By setting up the isolation module, the coupling effect of potential changes in the first node on the potential of the second node is blocked. This prevents the potential changes in the first node from propagating to the second node when fluctuations in the clock signal transmitted through the clock signal line cause fluctuations in the potential of the first node, thus stabilizing the potential of the second node. This allows the inverting module to control the pull-down sustaining module to maintain its effect on the first node based on the potential of the second node. This improves the problem of the pull-down sustaining module's pull-down effect on the first node decreasing after prolonged use, and the first node's potential fluctuating due to coupling with clock signal changes, leading to erroneous output signals from the gate driving circuit and ultimately, gate driving circuit failure. Attached Figure Description
[0007] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0008] Figure 1 This is a schematic diagram of the gate drive circuit in the prior art;
[0009] Figure 2 This is a schematic block diagram of the first structure of the gate driving circuit provided in the embodiment of the present invention;
[0010] Figure 3 This is a schematic diagram of the first type of gate driving circuit provided in the embodiments of the present invention;
[0011] Figure 4 This is a second circuit diagram of the gate driving circuit provided in an embodiment of the present invention;
[0012] Figure 5 This is a schematic block diagram of a second structure of the gate driving circuit provided in the embodiments of this application;
[0013] Figure 6 This is a schematic block diagram of the third structure of the gate driving circuit provided in the embodiments of this application;
[0014] Figure 7 This is a schematic diagram of a third type of gate driving circuit provided in an embodiment of the present invention;
[0015] Figure 8 This is a timing diagram of the gate drive circuit application provided in the embodiments of the present invention;
[0016] Figure 9 This is a schematic diagram of the structure of the display device provided in an embodiment of the present invention;
[0017] Figure 10 This is a schematic diagram of the first type of cascaded multi-stage gate drive circuit provided in an embodiment of the present invention;
[0018] Figure 11 This is a schematic diagram of a second type of cascaded multi-stage gate drive circuit provided in an embodiment of the present invention;
[0019] Figure 12 This is the first timing diagram for the application of the multi-stage gate drive circuit provided in the embodiments of the present invention;
[0020] Figure 13 This is a second timing diagram for the application of the multi-stage gate drive circuit provided in the embodiments of the present invention. Detailed Implementation
[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention. In the present invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.
[0022] Specifically, Figure 2 This is a schematic block diagram of the first structure of the gate driving circuit provided in the embodiments of this application; the embodiments of the present invention provide a gate driving circuit, including a pull-up module 100, an isolation module 200, a pull-down sustaining module 300, and an inverting module 400.
[0023] The pull-up module 100 is electrically connected to the first node N1. The pull-up module 100 is configured to connect the clock signal line CKL to the signal output terminal G(N) of the gate drive circuit according to the potential of the first node N1, or disconnect the electrical connection between the clock signal line CKL and the signal output terminal G(N) of the gate drive circuit.
[0024] Optionally, the clock signal line CKL transmits the clock signal CK.
[0025] Figure 3This is a schematic diagram of a first type of gate drive circuit provided in an embodiment of the present invention; the pull-up module 100 includes a pull-up transistor To and a bootstrap capacitor Cb. The control terminal of the pull-up transistor To is electrically connected to the first node N1, the input terminal of the pull-up transistor To is electrically connected to the clock signal line CKL, and the output terminal of the pull-up transistor To is electrically connected to the signal output terminal G(N); the bootstrap capacitor Cb is connected in series between the first node N1 and the signal output terminal G(N).
[0026] Wherein, the pull-up transistor To is configured to be turned on or off according to the potential of the first node N1, so as to transmit the clock signal CK to the signal output terminal G(N) when the pull-up transistor To is turned on; the bootstrap capacitor Cb is configured to bootstrap the potential of the first node N1 according to the clock signal CK when the pull-up transistor To is turned on.
[0027] Please continue reading. Figure 2 The isolation module 200 is electrically connected to the first node N1 and the second node N2. The isolation module 200 is configured to block the coupling effect of the potential change of the first node N1 on the potential of the second node N2.
[0028] In one specific embodiment, such as Figure 3 As shown, the isolation module 200 includes an isolation transistor Ts, the input terminal of which is electrically connected to the second node N2, and the output terminal of which is electrically connected to the first node N1.
[0029] Optionally, the control terminal of the isolation transistor Ts can be electrically connected to the second power supply terminal V2 so that the isolation transistor Ts is always in the on state.
[0030] Optionally, the isolation transistor Ts is an N-type transistor, and the voltage supplied by the second power supply terminal V2 is greater than the voltage supplied by the first power supply terminal VSS. Optionally, the third power supply terminal VGH can be reused as the second power supply terminal V2.
[0031] Optionally, the isolation transistor Ts is a P-type transistor, and the first power supply terminal VSS can be reused as the second power supply terminal V2.
[0032] Optionally, the control terminal of the isolation transistor Ts can be electrically connected to the isolation control signal SeC, so that the isolation transistor Ts is turned on or off according to the isolation control signal SeC, thereby improving the effect of blocking the influence of the first node N1 potential on the second node N2 potential while reducing the power consumption of the gate drive circuit.
[0033] Please continue reading. Figure 2The inverting module 400 is electrically connected to the second node N2. The inverting module 400 is configured to control the pull-down sustaining module 300 to connect the first power supply terminal VSS to the first node N1, or disconnect the electrical connection between the first power supply terminal VSS and the first node N1, according to the potential of the second node N2.
[0034] In one specific embodiment, such as Figure 3 As shown, the inverter module 400 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. The control terminal of the first transistor T1 is electrically connected to the third power supply terminal VGH, and the input terminal of the first transistor T1 is also electrically connected to the third power supply terminal VGH. The control terminal of the second transistor T2 is electrically connected to the second node N2, the output terminal of the second transistor T2 is electrically connected to the output terminal of the first transistor T1, and the input terminal of the second transistor T2 is electrically connected to the first power supply terminal VSS. The control terminal of the third transistor T3 is electrically connected to the output terminal of the first transistor T1, the input terminal of the third transistor T3 is electrically connected to the third power supply terminal VGH, and the output terminal of the third transistor T3 is electrically connected to the pull-down sustaining module 300 through the third node N3. The control terminal of the fourth transistor T4 is electrically connected to the second node N2, the input terminal of the fourth transistor T4 is electrically connected to the first power supply terminal VSS, and the output terminal of the fourth transistor T4 is electrically connected to the third node N3.
[0035] By electrically connecting the control terminals of the second transistor T2 and the fourth transistor T4 to the second node N2, not only can the isolation module 200 block the influence of the potential changes of the first node N1 on the potential of the second node N2, but the second transistor T2 and the fourth transistor T4 can also maintain the electrical connection between the first power supply terminal VSS and the first node N1 according to the potential of the second node N2. This allows the second transistor T2 and the fourth transistor T4 to maintain their effect on the first node N1, reducing the probability of the gate control signal Scan(N) output by the gate drive circuit having a valid pulse error and improving the output stability of the gate drive circuit.
[0036] Furthermore, the control terminals of the second transistor T2 and the fourth transistor T4 are electrically connected to the second node N2, which reduces the load corresponding to the first node N1. Therefore, the factors that interfere with the potential of the first node N1 are reduced, which helps to improve the potential stability of the first node N1 and makes the potential change waveform of the first node N1 tend to the design expectation.
[0037] Please continue reading. Figure 2 The pull-down sustaining module 300 is electrically connected to the first node N1 and the first power supply terminal VSS. The pull-down sustaining module 300 is configured to connect the first power supply terminal VSS to the first node N1, or disconnect the electrical connection between the first power supply terminal VSS and the first node N1.
[0038] In one specific embodiment, such as Figure 3 As shown, the pull-down sustaining module 300 includes a first pull-down sustaining transistor Th1. The control terminal of the first pull-down sustaining transistor Th1 is electrically connected to the third node N3, the input terminal of the first pull-down sustaining transistor Th1 is electrically connected to the first power supply terminal VSS, and the output terminal of the first pull-down sustaining transistor Th1 is electrically connected to the first node N1. The first pull-down sustaining transistor Th1 is configured to connect the first power supply terminal VSS and the first node N1 according to the potential of the third node N3, or to disconnect the electrical connection between the first power supply terminal VSS and the first node N1.
[0039] Optionally, the first pull-down holding transistor Th1 is an N-type transistor, and the voltage supplied by the second power supply terminal V2 is greater than the voltage supplied by the first power supply terminal VSS.
[0040] Optionally, such as Figure 3 As shown, the pull-down sustaining module 300 further includes a second pull-down sustaining transistor Th2. The control terminal of the second pull-down sustaining transistor Th2 is electrically connected to the third node N3, the input terminal of the second pull-down sustaining transistor Th2 is electrically connected to the first power supply terminal VSS, and the output terminal of the second pull-down sustaining transistor Th2 is electrically connected to the signal output terminal G(N). The second pull-down sustaining transistor Th2 is configured to connect the first power supply terminal VSS and the signal output terminal G(N) according to the potential of the third node N3, or to disconnect the electrical connection between the first power supply terminal VSS and the signal output terminal G(N).
[0041] The gate drive circuit provided in this application embodiment reduces the impact of potential fluctuations of the first node N1 on the potential of the second node N2 by setting an isolation module 200. Consequently, the inverting module 400, which is electrically connected to the second node N2, can control the pull-down sustaining module 300 to maintain the electrical connection between the first power supply terminal VSS and the first node N1 according to the potential stability of the second node N2. This allows the first node N1 to remain stable under the first voltage supplied by the first power supply terminal VSS, reducing the risk of gate drive circuit failure.
[0042] In practical applications, the pull-up transistor To is generally the largest transistor in the gate drive circuit, and therefore the parasitic capacitance corresponding to the pull-up transistor To is also large. The isolation module 200, as verified by the inventors in actual products, can reduce the impact of the potential fluctuation of the second node N2 and the pull-down sustaining module 300 on the potential fluctuation of the first node N1.
[0043] Figure 4 This is a second circuit diagram of the gate drive circuit provided in an embodiment of the present invention. Optionally, in some embodiments of the present invention, the isolation module 200 further includes a first capacitor C1, which is connected in series between the signal output terminal G(N) and the second node N2, so as to further stabilize the potential of the second node N2 through the first capacitor C1, so that when the gate control signal Scan(N) output by the signal output terminal G(N) has a transition from a low level state to a high level state, the potential of the second node N2 is coupled through the first capacitor C1, so that the inverting module 400 can further stably control the pull-down sustaining module 300 to disconnect the electrical connection between the first power supply terminal VSS and the first node N1, maintain the stability of the potential of the first node N1, and reduce the probability of the potential of the first node N1 being abnormally pulled down. When the gate control signal Scan(N) output from the signal output terminal G(N) transitions from a high level to a low level, the potential of the second node N2 is coupled through the first capacitor C1, so that the inverting module 400 can further stably control the pull-down sustaining module 300 to maintain the electrical connection between the first power supply terminal VSS and the first node N1, so that the first node N1 can be kept stable by the first voltage supplied by the first power supply terminal VSS.
[0044] Alternatively, please continue reading Figure 2 The gate drive circuit further includes a pull-up control module 500, which is configured to raise the potential of the first node N1 and the second node N2 according to the pull-up control signal Scan(NX).
[0045] In some specific embodiments, please refer to the following: Figure 3 and Figure 4 The pull-up control module 500 includes a pull-up control transistor Tu. The control terminal and input terminal of the pull-up control transistor Tu are configured to receive a pull-up control signal Scan(NX). The output terminal of the pull-up control transistor Tu is electrically connected to the second node N2.
[0046] Alternatively, please continue reading Figure 2The gate drive circuit further includes a pull-down module 600, which is configured to electrically connect the first power supply terminal VSS and the second node N2 according to the pull-down control signal Scan(N+Y).
[0047] In some specific embodiments, please refer to the following: Figure 3 and Figure 4 The pull-down module 600 includes a first pull-down transistor Td1. The control terminal of the first pull-down transistor Td1 is configured to receive a pull-down control signal Scan(N+Y). The input terminal of the first pull-down transistor Td1 is electrically connected to a first power supply terminal VSS, and the output terminal of the first pull-down transistor Td1 is electrically connected to a second node N2. The first pull-down transistor Td1 is configured to disconnect the electrical connection between the second node N2 and the first power supply terminal VSS according to the pull-down control signal Scan(N+Y); or to connect the second node N2 and the first power supply terminal VSS, such that the inverting module 400 controls the pull-down maintenance module 300 to achieve an electrical connection between the first power supply terminal VSS and the first node N1.
[0048] In some specific embodiments, please refer to the following: Figure 3 and Figure 4 The pull-down module 600 is further configured to electrically connect the first power supply terminal VSS and the signal output terminal G(N) according to the pull-down control signal Scan(N+Y). Optionally, the pull-down module 600 includes a second pull-down transistor Td2, the control terminal of which is configured to receive the pull-down control signal Scan(N+Y), the input terminal of which is electrically connected to the first power supply terminal VSS, and the output terminal of which is electrically connected to the signal output terminal G(N). The second pull-down transistor Td2 is configured to connect the signal output terminal G(N) to the first power supply terminal VSS or disconnect the electrical connection between the signal output terminal G(N) and the first power supply terminal VSS according to the pull-down control signal Scan(N+Y).
[0049] Figure 5 This is a schematic block diagram of a second structure of the gate driving circuit provided in the embodiments of this application. The gate driving circuit further includes a reset module 700, which is configured to initialize the potential of the second node N2 according to the reset control signal Reset.
[0050] In some specific embodiments, please refer to the following: Figure 3 and Figure 4The reset module 700 includes a first reset transistor Ti1. The control terminal of the first reset transistor Ti1 is configured to receive a reset control signal Reset. The input terminal of the first reset transistor Ti1 is electrically connected to a first power supply terminal VSS, and the output terminal of the first reset transistor Ti1 is electrically connected to a second node N2. The first reset transistor Ti1 is configured to connect the first power supply terminal VSS and the second node N2, or disconnect the electrical connection between the first power supply terminal VSS and the second node N2, according to the reset control signal Reset.
[0051] Optionally, the reset module 700 is configured to initialize the potential of the signal output terminal G(N) according to the reset control signal Reset.
[0052] Optionally, such as Figures 3-4 As shown, the reset module 700 further includes a second reset transistor Ti2. The control terminal of the second reset transistor Ti2 is configured to receive the reset control signal Reset. The input terminal of the second reset transistor Ti2 is electrically connected to the first power supply terminal VSS, and the output terminal of the second reset transistor Ti2 is electrically connected to the signal output terminal G(N). The second reset transistor Ti2 is configured to connect the first power supply terminal VSS and the signal output terminal G(N) or disconnect the electrical connection between the first power supply terminal VSS and the signal output terminal G(N) according to the reset control signal Reset.
[0053] Furthermore, since the first reset transistor Ti1 and the second reset transistor Ti2 can be turned on simultaneously according to the reset control signal Reset, the potential across the first capacitor C1 can be initialized using the first reset transistor Ti1, the second reset transistor Ti2, and the first power supply terminal VSS.
[0054] Optionally, when the gate driving circuit is applied to the display panel, the reset control signal Reset can have an effective pulse during the end time of displaying a frame on the display panel (including after the last row of sub-pixels is driven, and the vertical blanking interval) to eliminate the residual charge of the second node N2 and the signal output terminal G(N) to improve display quality.
[0055] Optionally, when the gate driving circuit is applied to the display panel, the reset control signal Reset can have a valid pulse when the display panel is powered on, so as to initialize the potential of the second node N2 and the signal output terminal G(N) before the display panel displays the screen.
[0056] Figure 6This is a schematic block diagram of a third structure of the gate driving circuit provided in this application embodiment. The gate driving circuit may further include a stage transmission module 800. The stage transmission module 800 is electrically connected to the first node N1 and the clock signal line CKL. The stage transmission module 800 is configured to connect the clock signal line CKL to the stage transmission output terminal ST(N) of the gate driving circuit according to the potential output of the first node N1, or to disconnect the electrical connection between the clock signal line CKL and the stage transmission output terminal ST(N) of the gate driving circuit, so that in the device using the gate driving circuit, multiple gate driving circuits can be set up in a stage transmission manner by means of the stage transmission module 800.
[0057] Figure 7 This is a schematic diagram of the third type of gate driving circuit provided in the embodiment of the present invention. The stage transmission module 800 includes a stage transmission transistor Tst. The control terminal of the stage transmission transistor Tst is electrically connected to the first node N1. The input terminal of the stage transmission transistor Tst is electrically connected to the clock signal line CKL. The output terminal of the stage transmission transistor Tst is electrically connected to the stage transmission output terminal ST(N).
[0058] Optionally, such as Figure 7 As shown, the pull-down sustaining module 300 further includes a third pull-down sustaining transistor Th3. The control terminal of the third pull-down sustaining transistor Th3 is electrically connected to the third node N3, the input terminal of the third pull-down sustaining transistor Th3 is electrically connected to the first power supply terminal VSS, and the output terminal of the third pull-down sustaining transistor Th3 is electrically connected to the stage transmission output terminal ST(N).
[0059] Optionally, the gate drive circuit may further include two sets of the inverting modules 400 and two sets of the pull-down sustaining modules 300, wherein the topology of each set of the inverting modules 400 can be referred to Figure 3 The inverting module 400 is shown in the diagram. The control terminal, input terminal, and input terminal of the first transistor T1 included in the two sets of inverting modules 400 receive the inverted control signal. The control terminals of the second transistor T2 and the fourth transistor T4 included in the two sets of inverting modules 400 are still electrically connected to the second node N2.
[0060] like Figure 8 This is a timing diagram of the gate drive circuit provided in an embodiment of the present invention. Taking an example where all transistors in the gate drive circuit are N-type transistors, the working principle of the gate drive circuit is explained as follows:
[0061] Initial stage t10: The clock signal CK transmitted by the clock signal line CKL is at a high level, and the pull-up control signal Scan(NX), the reset control signal Reset, and the pull-down control signal Scan(N+Y) are at a low level.
[0062] The pull-up control transistor Tu is turned off according to the pull-up control signal Scan(NX), the first transistor T1 is turned on according to the third voltage supplied by the third power supply terminal VGH, causing the third transistor T3 to be turned on, the first pull-down sustaining transistor Th1 and the second pull-down sustaining transistor Th2 are turned on, the first power supply terminal VSS is electrically connected to the first node N1 and the signal output terminal G(N), the potential of the first node N1 is kept at a low level, and the gate control signal Scan(N) output by the signal output terminal G(N) is at a low level.
[0063] If the control terminal of the isolation transistor Ts is electrically connected to the second power supply terminal V2, the isolation transistor Ts remains on during the initial stage t10. If the control terminal of the isolation transistor Ts receives the isolation control signal SeC, the isolation transistor Ts may remain on or off during the initial stage t10.
[0064] Optionally, to avoid the second node N2's voltage affecting the first node N1's voltage during the initial stage t10, the first reset transistor Ti1 may be turned on before the initial stage t10 according to the valid pulse of the reset control signal Reset, so that the second node N2's voltage is in a low-level state before the initial stage t10.
[0065] Precharge phase t11: The pull-up control signal Scan(NX) is high, and the clock signal CK, the reset control signal Reset, and the pull-down control signal Scan(N+Y) are low.
[0066] If the control terminal of the isolation transistor Ts is electrically connected to the second power supply terminal V2, the isolation transistor Ts remains on during the pre-charge phase t11. If the control terminal of the isolation transistor Ts receives the isolation control signal SeC, the isolation transistor Ts can remain on during the pre-charge phase t11 according to the valid pulse of the isolation control signal SeC.
[0067] When the pull-up control transistor Tu is turned on, the potential of the first node N1 and the second node N2 is raised, which turns on the pull-up transistor To, the second transistor T2 and the fourth transistor T4, keeping the gate control signal Scan(N) at a low level, and turning off the first pull-down sustaining transistor Th1 and the second pull-down sustaining transistor Th2.
[0068] Output stage t12: The clock signal CK is high, and the pull-up control signal Scan(NX), the reset control signal Reset, and the pull-down control signal Scan(N+Y) are low.
[0069] If the control terminal of the isolation transistor Ts is electrically connected to the second power supply terminal V2, the isolation transistor Ts remains on during the output phase t12. If the control terminal of the isolation transistor Ts receives the isolation control signal SeC, the isolation transistor Ts may remain on during the output phase t12 according to the effective pulse of the isolation control signal SeC.
[0070] When the pull-up control transistor Tu is turned off, the potential of the first node N1 is further raised, and the pull-up transistor To, the second transistor T2 and the fourth transistor T4 remain on, so that the gate control signal Scan(N) has a high level state, and the first pull-down sustaining transistor Th1 and the second pull-down sustaining transistor Th2 remain off.
[0071] Pull-down phase t13: The pull-down control signal Scan(N+Y) is high, while the pull-up control signal Scan(NX), the reset control signal Reset, and the clock signal CK are low.
[0072] If the control terminal of the isolation transistor Ts is electrically connected to the second power supply terminal V2, the isolation transistor Ts remains on during the pull-down phase t13. If the control terminal of the isolation transistor Ts receives the isolation control signal SeC, the isolation transistor Ts can be turned on or off during the pull-down phase t13.
[0073] The first pull-down transistor Td1 and the second pull-down transistor Td2 are turned on according to the pull-down control signal Scan(N+Y). The first power supply terminal VSS, the second node N2, and the signal output terminal G(N) are electrically connected. The gate control signal Scan(N) is in a low-level state. The potential of the second node N2 is pulled down. The second transistor T2 and the fourth transistor T4 are turned off. The first transistor T1, the third transistor T3, the first pull-down sustaining transistor Th1, and the second pull-down sustaining transistor Th2 are turned on. The potential of the first node N1 is pulled down. The pull-up transistor To is turned off.
[0074] Then, the reset control signal Reset can be given a valid pulse to turn on the first reset transistor Ti1 and the second reset transistor Ti2, so as to initialize the potential of the second node N2, the potential of the signal output terminal G(N), and the potentials across the first capacitor C1.
[0075] like Figure 9 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. The embodiment of the present invention provides a display device including any of the above-described gate driving circuits.
[0076] Optionally, the display device includes a display panel and a gate driving unit, the display panel being electrically connected to the gate driving unit, and the gate driving unit including a plurality of gate driving circuits (such as...). Figure 9 As shown in Figure 10, multiple gate drive circuits 10 are cascaded together.
[0077] Optionally, the display panel includes passive light-emitting display panels (such as liquid crystal display panels, reflective display panels, etc.) and self-emissive display panels (such as display panels that include light-emitting devices such as organic light-emitting diodes, sub-millimeter light-emitting diodes, and micro light-emitting diodes as sub-pixels, etc.).
[0078] Optionally, the display panel includes a plurality of sub-pixels Pi, each sub-pixel Pi including a pixel driving circuit, and at least one transistor in the pixel driving circuit is electrically connected to the corresponding gate driving circuit 10.
[0079] Optionally, the pixel driving circuit can be designed in the form of 2T1C (2 transistors and 1 capacitor), 5T2C, 7T1C, 7T2C, 8T2C, etc.
[0080] Optionally, if the pixel driving circuit adopts the form of 7T1C, the gate driving unit can be electrically connected to the reset transistor that realizes the voltage reset of the driving transistor control terminal, the compensation transistor that compensates the threshold voltage of the driving transistor, or the data transistor that controls the writing of data signals to the control terminal of the driving transistor.
[0081] Optionally, the gate driving unit may be electrically connected to multiple clock signal lines so that multiple gate driving circuits 10 generate effective pulses of the gate control signal Scan(N) according to the clock signal CK transmitted by the multiple clock signal lines.
[0082] Optionally, multiple gate drive circuits 10 are electrically connected to m clock signal lines. Where m ≥ 2, and m can be determined according to different design requirements. Optionally, m is equal to 2, 6, 8, or 12, etc.
[0083] Figure 10 This is a schematic diagram of a first cascaded multi-stage gate driving circuit provided in an embodiment of the present invention. Multiple gate driving circuits 10 are electrically connected to two clock signal lines (i.e., a first clock signal line and a second clock signal line). The first clock signal CK1 transmitted by the first clock signal line and the second clock signal CK2 transmitted by the second clock signal line are inverted. Optionally, odd-numbered gate driving circuits are electrically connected to the first clock signal line, and even-numbered gate driving circuits are electrically connected to the second clock signal line.
[0084] Optionally, when multiple gate drive circuits 10 are cascaded, the pull-up control signal received by the first-stage gate drive circuit can be the start signal STV. Multiple gate drive circuits cascaded after the first-stage gate drive circuit can use the cascade transmission signal output from the stage transmission output terminal of the preceding gate drive circuit or the gate control signal output from the signal output terminal of the preceding gate drive circuit as the pull-up control signal.
[0085] For example, the Nth-stage gate drive circuit located after the first-stage gate drive circuit can use the stage transmission signal or gate control signal Scan(NX) output by the NXth-stage gate drive circuit as the pull-up control signal. Wherein, N>1, X≥1, and NX≥1.
[0086] Optionally, when multiple gate drive circuits are cascaded, the cascade signal or gate control signal output by the subsequent gate drive circuit can be used as the pull-down control signal of the preceding gate drive circuit.
[0087] For example, the M-th stage gate drive circuit can use the stage transmission signal or gate control signal Scan(N+Y) output by the M+Y-th stage gate drive circuit as the pull-down control signal. Where M≥1, Y≥1.
[0088] Alternatively, please continue reading Figure 10The control terminals of the isolation transistors Ts in the multiple gate drive circuits can all be electrically connected to the second power supply terminal, so that the isolation transistors Ts in the multiple gate drive circuits are always turned on, reducing the control complexity of the display device. Specifically, when the isolation transistor Ts is an N-type transistor, the third power supply terminal VGH can be reused as the second power supply terminal; when the isolation transistor Ts is a P-type transistor, the first power supply terminal VSS can be reused as the second power supply terminal.
[0089] Figure 11 This is a second cascaded schematic diagram of a multi-stage gate drive circuit provided in an embodiment of the present invention. Multiple isolation control signals SeC can be set for multiple gate drive circuits so that the isolation transistor Ts of each gate drive circuit is turned off after the output gate control signal outputs a valid pulse, thereby reducing the power consumption of each gate drive circuit and better blocking the influence of the potential change of the first node N1 on the potential of the second node N2.
[0090] Optionally, since each gate drive circuit corresponds to an isolation control signal SeC, the layout space occupied by the gate drive unit will increase. Therefore, in order to balance power consumption, control difficulty, layout space, and the blocking effect between the potential of the first node N1 and the potential of the second node N2, multiple gate drive circuits can share multiple isolation control signals SeC.
[0091] Optionally, multiple gate driving circuits may share Z isolation control signals SeC, so that the multiple gate driving circuits can sequentially output gate control signals Scan(N). Where Z ≥ 1. It is understood that the number of isolation control signals SeC shared by the multiple gate driving circuits can be set according to actual needs.
[0092] Optionally, in multiple gate drive circuits, two gate drive circuits separated by p stages share the isolation control signal SeC. Where p ≥ 1. In a specific embodiment, as... Figure 11 As shown, p=2, and the first-stage gate drive circuit and the fourth-stage gate drive circuit are separated by two gate drive circuits (i.e., the second-stage gate drive circuit and the third-stage drive circuit). The first-stage gate drive circuit and the fourth-stage gate drive circuit share the first isolation control signal SeC1. Similarly, the first-stage gate drive circuit, the fourth-stage gate drive circuit, and the seventh-stage gate drive circuit share the first isolation control signal SeC. Likewise, the second-stage gate drive circuit, the fifth-stage gate drive circuit, and the eighth-stage gate drive circuit share the second isolation control signal SeC2; and the third-stage gate drive circuit, the sixth-stage gate drive circuit, and the ninth-stage gate drive circuit share the third isolation control signal SeC3.
[0093] Figure 12 This is the first timing diagram for the application of a multi-stage gate driving circuit provided in this embodiment of the invention. Odd-numbered gate driving circuits are electrically connected to the first clock signal line, and even-numbered gate driving circuits are electrically connected to the second clock signal line. Multiple gate driving circuits share three isolation control signals SeC (i.e., the first-stage gate driving circuit, the fourth-stage gate driving circuit, the seventh-stage gate driving circuit, etc., share the first isolation control signal SeC1; the second-stage gate driving circuit, the fifth-stage gate driving circuit, the eighth-stage gate driving circuit, etc., share the second isolation control signal SeC2; the third-stage gate driving circuit, the sixth-stage gate driving circuit, the ninth-stage gate driving circuit, etc., share the third isolation control signal SeC3). Taking the example of each gate driving circuit after the first-stage gate driving circuit using the gate control signal output from the previous stage as the pull-up control signal and the gate control signal output from the next stage as the pull-down control signal (i.e., X = Y = 1), the working principle of the gate driving unit is explained.
[0094] In the first stage t21: the start signal STV and the first isolation control signal SeC1 are at high level, while the first clock signal CK1 transmitted by the first clock signal line, the second clock signal CK2 transmitted by the second clock signal line, the second isolation control signal SeC2, the third isolation control signal SeC3, and the reset control signal Reset are at low level.
[0095] In the first-stage gate drive circuit, the pull-up control transistor Tu is turned on according to the start signal STV, and the isolation transistor Ts is turned on according to the first isolation control signal SeC1, so that the potential of the first node (i.e. N11 in 12) and the potential of the second node N2 are raised, so that the pull-up transistor To, the second transistor T2 and the fourth transistor T4 are turned on, and the first-stage gate control signal Scan(1) output by the first-stage gate drive circuit has a low level state, and the first pull-down sustaining transistor Th1 and the second pull-down sustaining transistor Th2 are turned off.
[0096] The gate control signals Scan(2) to Scan(n) output by the multiple gate drive circuits cascaded after the first-stage gate drive circuit are in a low-level state because the gate control signal output by the previous-stage gate drive circuit is used as the pull-up control signal.
[0097] In the second stage t22: the first isolation control signal SeC1, the second isolation control signal SeC2 and the first clock signal CK1 are at high level, while the start signal STV, the second clock signal CK2, the third isolation control signal SeC3 and the reset control signal Reset are at low level.
[0098] In the first-stage gate drive circuit, the pull-up control transistor Tu is turned off, the potential of the first node N1 is further raised, the pull-up transistor To, the second transistor T2 and the fourth transistor T4 remain on, so that the first-stage gate control signal Scan(1) output by the first-stage gate drive circuit has a high level state, and the first pull-down sustaining transistor Th1 and the second pull-down sustaining transistor Th2 remain off.
[0099] The second-stage gate drive circuit uses the first-stage gate control signal Scan(1) output by the first-stage gate drive circuit as a pull-up control signal and performs the same operation as the first-stage gate drive circuit in the first stage t21. Meanwhile, the gate control signals Scan(3) to Scan(n) output by the multiple gate drive circuits cascaded after the second-stage gate drive circuit remain in a low-level output state.
[0100] In the third stage t23: the second isolation control signal SeC2, the third isolation control signal SeC3 and the second clock signal CK2 are at high level, while the start signal STV, the first clock signal CK1, the first isolation control signal SeC1 and the reset control signal Reset are at low level.
[0101] The second-stage gate drive circuit performs the same operation as the first-stage gate drive circuit in the second stage t22, such that the second-stage gate control signal Scan(2) output by the second-stage gate drive circuit has a high-level state.
[0102] Since the first-stage gate drive circuit uses the second-stage gate control signal Scan(2) output by the second-stage gate drive circuit as the pull-down control signal, in the first-stage gate drive circuit, the first pull-down transistor Td1 and the second pull-down transistor Td2 are turned on according to the second-stage gate control signal Scan(2), so that the first-stage gate control signal Scan(1) has a low level state, the potential of the second node N2 is pulled down, the second transistor T2 and the fourth transistor T4 are turned off, the first transistor T1, the third transistor T3, the first pull-down sustaining transistor Th1 and the second pull-down sustaining transistor Th2 are turned on, the potential of the first node N1 is pulled down, and the pull-up transistor To is turned off.
[0103] The third-stage gate drive circuit uses the second-stage gate control signal Scan(2) output by the second-stage gate drive circuit as a pull-up control signal and performs the same operation as the second-stage gate drive circuit in the second stage t22. The gate control signals Scan(4) to Scan(n) output by the multiple gate drive circuits cascaded after the third-stage gate drive circuit remain in a low-level output state.
[0104] In the fourth stage t24: the first isolation control signal SeC1, the third isolation control signal SeC3, and the first clock signal CK1 are at high level, while the start signal STV, the second clock signal CK2, the second isolation control signal SeC2, and the reset control signal Reset are at low level.
[0105] The first-stage gate control signal Scan(1) output by the first-stage gate drive circuit remains at a low level; the second-stage gate drive circuit performs the same operation as the first-stage gate drive circuit in the third stage t23, so that the second-stage gate control signal Scan(2) output by the second-stage gate drive circuit is at a low level; the third-stage gate drive circuit performs the same operation as the second-stage gate drive circuit in the third stage t23, so that the third-stage gate control signal Scan(3) output by the third-stage gate drive circuit is at a high level.
[0106] Since the fourth-stage gate drive circuit uses the third-stage gate control signal Scan(3) output by the third-stage gate drive circuit as the pull-up control signal, and the isolation transistor Ts in the fourth-stage gate drive circuit is turned on according to the first isolation control signal SeC1, the fourth-stage gate drive circuit performs the same operation as the first-stage gate drive circuit in the first stage t21, so that the fourth-stage gate control signal Scan(4) output by the fourth-stage gate drive circuit has a low level state.
[0107] Meanwhile, the gate control signals Scan(5) to Scan(n) output by the multiple gate drive circuits cascaded after the fourth-stage gate drive circuit remain at a low level.
[0108] By analogy, we can understand the working principle that the gate control signals Scan(5) to Scan(n) output by the fourth-stage gate drive circuit and the multiple gate drive circuits cascaded after the fourth-stage gate drive circuit are sequentially in a high-level state.
[0109] Optionally, after multiple gate drive circuits sequentially output multiple gate control signals Scan with valid pulses, the reset control signal Reset has valid pulses to turn on the first reset transistor Ti1 and the second reset transistor Ti2 included in the multiple gate drive circuits, so as to initialize the potential of the second node N2, the potential of the signal output terminal G(N), and the potential across the first capacitor C1 of the multiple gate drive circuits.
[0110] Optionally, the reset control signal Reset may have a valid pulse after the last stage gate drive circuit outputs a valid pulse, or it may have a valid pulse within the vertical blanking interval tb, in order to avoid the valid pulse of the reset control signal Reset being located in the frame corresponding to the display panel when it is displayed, which would cause display abnormalities.
[0111] It is understandable that the working principle of the gate drive unit when multiple gate drive circuits are cascaded and the control terminal of the isolation transistor Ts included in the multiple gate drive circuits is electrically connected to the second power supply terminal V2 can be obtained by referring to the working principle of multiple gate drive circuits sharing multiple isolation control signals SeC, which will not be elaborated here.
[0112] Optionally, Figure 13 This is a second timing diagram for the application of the multi-level gate driving circuit provided in the embodiments of the present invention. When multiple gate driving circuits are cascaded and multiple gate driving circuits share multiple isolation control signals SeC, the display panel can also be divided into zones and frequency controls by controlling the isolation control signals SeC.
[0113] Optionally, by controlling whether the isolation control signal SeC has a valid pulse, the isolation transistor Ts in the corresponding gate drive circuit can be kept off, so that the pull-up transistor To in the corresponding gate drive circuit cannot be turned on, thereby preventing the corresponding clock signal CK from being output to the signal output terminal G(N), and thus controlling the gate control signal Scan(N) output by the corresponding gate drive circuit to have no valid pulse.
[0114] In one specific embodiment, please continue to refer to Figure 13 Taking the example of the first-stage gate drive circuit, the fourth-stage gate drive circuit, and the seventh-stage gate drive circuit sharing the first isolation control signal SeC1; the second-stage gate drive circuit, the fifth-stage gate drive circuit, and the eighth-stage gate drive circuit sharing the second isolation control signal SeC2; and the third-stage gate drive circuit, the sixth-stage gate drive circuit, and the ninth-stage gate drive circuit sharing the third isolation control signal SeC3, the working principle of controlling the isolation control signal SeC to achieve segmented frequency control of the display panel is explained. To achieve segmented frequency control, the display panel's display cycle may include a write frame (WF) and a hold frame (HF). Corresponding to the write frame (WF), the control terminal of the driving transistor in the pixel drive circuit of the sub-pixel has a data signal writing action; corresponding to the hold frame (HF), the control terminal of the driving transistor in the sub-pixel does not have a data signal writing action.
[0115] During the write frame WF, multiple gate control signals Scan(N) output by multiple gate drive circuits have valid pulses in sequence, so that the pixel drive circuit of the corresponding sub-pixel can control the data signal to be normally written to the gate of the drive transistor according to the corresponding gate control signals Scan(1) to Scan(n).
[0116] If the display panel divides the row of the sub-pixel connected to the fourth-level gate driving circuit in the HF frame, then the first isolation control signal SeC1 can be controlled to not have an invalid pulse to an effective pulse transition at the first frequency division time Tf1. This is so that when the fourth-level gate driving circuit receives the third-level gate control signal Scan(3) output by the third-level gate circuit, the isolation transistor Ts in the fourth-level gate driving circuit remains in the off state, and the pull-up transistor To remains in the off state. This prevents the fourth-level gate control signal Scan(4) output by the fourth-level gate driving circuit from having a high level state when the first clock signal CK1 is high. As a result, the sub-pixel electrically connected to the fourth-level gate driving circuit cannot have its data signal rewritten to the control terminal of the driving transistor, so that the row of the sub-pixel electrically connected to the fourth-level gate driving circuit displays the same image as the written frame WF.
[0117] The first-level gate control signal Scan(1) to the third-level gate control signal Scan(3) output by the first-level gate drive circuit to the third-level gate drive circuit still have a high level state in sequence. Therefore, the row of sub-pixels that are electrically connected to the first-level gate drive circuit to the third-level gate drive circuit can control the data signal to be rewritten to the control terminal of the drive transistor, thereby making the row of sub-pixels that are electrically connected to the first-level gate drive circuit to the third-level gate drive circuit display a different picture from the written frame WF.
[0118] The multiple gate drive circuits cascaded after the fourth-stage gate drive circuit have no effective pulse output from the pull-up control signals Scan(4) to Scan(n-1), resulting in no output of the gate control signals Scan(5) to Scan(n) from the multiple gate drive circuits cascaded after the fourth-stage gate drive circuit.
[0119] The third-stage gate drive circuit uses the fourth-stage gate control signal Scan(4) output by the fourth-stage gate drive circuit as the pull-down control signal. Therefore, in order to avoid the first node N1 potential and the second node N2 potential of the third gate drive circuit being unable to be further pulled down when the fourth-stage gate control signal Scan(4) output by the fourth-stage gate drive circuit has no effective pulse, the first reset transistor Ti1 and the second reset transistor Ti2 of the third-stage gate drive circuit can be turned on separately by the reset control signal Reset to further pull down the first node N1 potential and the second node N2 potential.
[0120] Furthermore, since the fourth-stage gate drive circuit and the circuit cascaded to the fourth-stage gate drive circuit do not output effective pulses due to the isolation control signal SeC, the reset control signal Reset can also be controlled to have effective pulses at the first frequency division time Tf1. This allows the first reset transistor Ti1 and the second reset transistor Ti2 of all gate drive circuits to be turned on simultaneously through the reset control signal Reset, thereby further pulling down the potential of the first node N1 and the second node N2 of the third-stage gate drive circuit.
[0121] For cases where the display panel uses frequency division at a fixed position, a frequency-dividing pull-down transistor can be used in the corresponding gate drive circuit. The input terminal of the frequency-dividing pull-down transistor is electrically connected to the first power supply terminal VSS, and the output terminal is electrically connected to the corresponding first node N1 and second node N2. The control terminal of the frequency-dividing pull-down transistor receives a frequency-dividing pull-down control signal to control the frequency-dividing pull-down transistor to conduct at the corresponding frequency division time, pulling down the potential of the first node N1 and the second node N2 of the corresponding gate drive circuit. Alternatively, the frequency-dividing pull-down transistor can be set in the third-stage gate drive circuit. The input terminal of the frequency-dividing pull-down transistor is electrically connected to the first power supply terminal VSS, and the output terminal is electrically connected to the first node N1 and the second node N2 in the third-stage gate drive circuit. The control terminal of the frequency-dividing pull-down transistor receives a frequency-dividing pull-down control signal, which has a valid pulse starting at the first frequency division time Tf1.
[0122] It is understood that this application only uses the example of controlling the output of the fourth-stage gate drive circuit by controlling the effective pulse of the first isolation control signal SeC1 to control the display panel's segmentation and frequency control. Similarly, the display panel's segmentation and frequency control can also be achieved by controlling at least one of the second isolation control signal SeC2 and the third isolation control signal SeC3.
[0123] Optionally, when the display panel is controlled by frequency division in at least one of the multiple isolation control signals SeC, the remaining isolation control signals SeC can be controlled to go low after the corresponding effective pulse output at the frequency division time, in order to reduce power consumption. For example... Figure 13 During stage ta, the second isolation control signal SeC2 and the third isolation control signal SeC3 can be kept at a low level.
[0124] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.
Claims
1. A gate driving circuit, characterized in that, include: The pull-up module is electrically connected to the first node and is configured to connect the clock signal line to the signal output terminal of the gate drive circuit according to the potential of the first node, or disconnect the electrical connection between the clock signal line and the signal output terminal. An isolation module, electrically connected to the first node and the second node, is configured to block the coupling effect of the potential change of the first node on the potential of the second node. The pull-down sustaining module is electrically connected to the first node and the first power supply terminal; as well as An inverting module, electrically connected to the second node and the pull-down sustaining module, is configured to control the pull-down sustaining module to connect the first power supply terminal to the first node or disconnect the electrical connection between the first power supply terminal and the first node based on the potential of the second node. The isolation module includes an isolation transistor and a first capacitor. The control terminal of the isolation transistor is electrically connected to a second power supply terminal, the input terminal of the isolation transistor is electrically connected to a second node, and the output terminal of the isolation transistor is electrically connected to the first node. The first capacitor is connected in series between the signal output terminal and the second node.
2. The gate driving circuit according to claim 1, characterized in that, The pull-up module includes: A pull-up transistor, wherein the control terminal of the pull-up transistor is electrically connected to the first node, the input terminal of the pull-up transistor is electrically connected to the clock signal line, and the output terminal of the pull-up transistor is electrically connected to the signal output terminal; and A bootstrap capacitor is connected in series between the first node and the signal output terminal.
3. The gate driving circuit according to claim 1, characterized in that, The inverting module includes: A first transistor, wherein the control terminal of the first transistor is electrically connected to a third power supply terminal, and the input terminal of the first transistor is electrically connected to the third power supply terminal; The second transistor has its control terminal electrically connected to the second node, its output terminal electrically connected to the output terminal of the first transistor, and its input terminal electrically connected to the first power supply terminal. A third transistor, wherein the control terminal of the third transistor is electrically connected to the output terminal of the first transistor, the input terminal of the third transistor is electrically connected to the third power supply terminal, and the output terminal of the third transistor is electrically connected to the pull-down sustaining module through a third node; and The fourth transistor has its control terminal electrically connected to the second node, its input terminal electrically connected to the first power supply terminal, and its output terminal electrically connected to the third node.
4. The gate driving circuit according to claim 3, characterized in that, The pull-down sustaining module includes: A first pull-down sustaining transistor, the control terminal of which is electrically connected to the third node, the input terminal of which is electrically connected to the first power supply terminal, and the output terminal of which is electrically connected to the first node; and The second pull-down sustaining transistor has its control terminal electrically connected to the third node, its input terminal electrically connected to the first power supply terminal, and its output terminal electrically connected to the signal output terminal.
5. The gate driving circuit according to claim 1, characterized in that, It also includes a dropdown module, which includes: A first pull-down transistor, wherein the control terminal of the first pull-down transistor is configured to receive a pull-down control signal, the input terminal of the first pull-down transistor is electrically connected to the first power supply terminal, and the output terminal of the first pull-down transistor is electrically connected to the second node; and The second pull-down transistor has a control terminal configured to receive the pull-down control signal, an input terminal electrically connected to the first power supply terminal, and an output terminal electrically connected to the signal output terminal.
6. The gate driving circuit according to claim 1, characterized in that, It also includes a reset module, which comprises: A first reset transistor, wherein the control terminal of the first reset transistor is configured to receive a reset control signal, the input terminal of the first reset transistor is electrically connected to the first power supply terminal, and the output terminal of the first reset transistor is electrically connected to the second node; and A second reset transistor, wherein the control terminal of the second reset transistor is configured to receive the reset control signal, the input terminal of the second reset transistor is electrically connected to the first power supply terminal, and the output terminal of the second reset transistor is electrically connected to the signal output terminal.
7. The gate driving circuit according to claim 1, characterized in that, It also includes a pull-up control module, which includes: A pull-up control transistor, wherein the control terminal and input terminal of the pull-up control transistor are configured to receive a pull-up control signal, and the output terminal of the pull-up control transistor is electrically connected to the second node.
8. A display device, characterized in that, Includes the gate drive circuit as described in any one of claims 1 to 7.