A method for manufacturing a solar cell, a solar cell and a battery string

Abstract

The present invention discloses a method for manufacturing a solar cell, a solar cell and a cell string, and relates to the technical field of solar cells, in order to solve the problem that the main grid contacts with the silicon substrate, destroys the passivation layer, causes the open circuit voltage to decrease, and affects the photoelectric conversion efficiency. The method for manufacturing the solar cell comprises: forming an emitter layer on one side of a semiconductor substrate, the semiconductor substrate and the emitter layer have opposite conductivity types, and the emitter layer and the semiconductor substrate together form a PN junction. A passivation layer is formed on the emitter layer, and an insulating layer is formed on the passivation layer. A main grid extending in a first direction and distributed at intervals in a second direction is formed on the insulating layer, and the first direction is different from the second direction. A fine grid extending in the second direction and distributed at intervals in the first direction is formed on the insulating layer. The main grid extends in the direction of the emitter layer, and the depth of the main grid extension does not exceed 90% of the thickness of the passivation layer and exceeds 20% of the thickness of the insulating layer.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a method for manufacturing a solar cell, a solar cell and a cell string. Background Art

[0002] A solar cell is a semiconductor device that can convert light energy into electrical energy. Specifically, when a solar cell is exposed to light, the semiconductor substrate included in the solar cell absorbs photons and generates electron-hole pairs. The electron-hole pairs are separated under the action of the built-in electric field of the PN junction, and are respectively led out through the emitter and back field of the solar cell, and finally collected by the electrode structure arranged on the semiconductor substrate.

[0003] The electrode structure mentioned above generally includes a main grid and a fine grid formed by integrated printing. During the sintering process, as the corrosion proceeds simultaneously, both the main grid and the fine grid are in contact with the silicon substrate.

[0004] However, when the main gate contacts the silicon substrate, the passivation layer will be seriously damaged, which will cause the open circuit voltage (Uoc) to decrease, thus affecting the photoelectric conversion efficiency. Summary of the invention

[0005] The object of the present invention is to provide a method for manufacturing a solar cell, a solar cell and a cell string, which are used to reduce or eliminate damage to a passivation layer, increase the open circuit voltage, and reduce the impact on the photoelectric conversion efficiency.

[0006] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a method for manufacturing a solar cell. The method for manufacturing a solar cell comprises:

[0007] First, a semiconductor substrate is provided. Next, an emitter layer is formed on one side of the semiconductor substrate. The semiconductor substrate and the emitter layer have opposite conductivity types, and the emitter layer and the semiconductor substrate together form a PN junction. Next, a passivation layer is formed on the emitter layer. Next, an insulating layer is formed on the passivation layer. Next, a main gate is formed on the insulating layer. The main gate extends along a first direction and is spaced apart along a second direction, and the first direction is different from the second direction. Next, a fine gate is formed on the insulating layer. The fine gate extends along the second direction and is spaced apart along the first direction. Each main gate intersects with a plurality of fine gates, and the fine gates pass through the passivation layer and the insulating layer and are connected to the emitter layer. The main gate extends toward the emitter layer, and the depth of the main gate extension does not exceed 90% of the thickness of the passivation layer and exceeds 20% of the thickness of the insulating layer, and the depth direction, the thickness direction of the passivation layer, and the thickness direction of the insulating layer are all consistent with the direction toward the semiconductor substrate.

[0008] In the manufacturing method of the solar cell provided by the present invention, since the main grid is formed on the insulating layer and extends toward the emitter layer, the depth of the main grid extension does not exceed 90% of the thickness of the passivation layer and exceeds 20% of the thickness of the insulating layer. At this time, the extended part of the main grid (i.e., part of the main grid area) may be located only in the insulating layer; or it may be located in both the insulating layer and the passivation layer, but not exceeding 90% of the thickness of the passivation layer.

[0009] When the extended portion of the main grid is only located in the insulating layer, the main grid does not damage the passivation layer, thereby ensuring the passivation effect of the passivation layer. Based on this, the open circuit voltage can be increased to reduce or avoid the impact on the photoelectric conversion efficiency.

[0010] When the extended part of the main grid is located in both the insulating layer and the passivation layer, but does not exceed 90% of the thickness of the passivation layer, compared with the prior art where the main grid passes through the passivation layer and is connected to the silicon substrate, the degree of damage to the passivation layer by the main grid is reduced, thereby ensuring the passivation effect of the passivation layer. Based on this, the open circuit voltage can be increased, thereby reducing the impact on the photoelectric conversion efficiency. Furthermore, the above-mentioned main grid is connected to the insulating layer and the passivation layer at the same time, at which time the mechanical properties of the main grid can be guaranteed and the tensile properties of the main grid can be improved. Based on this, the probability of the main grid detaching from the solar cell can be reduced or eliminated to ensure the quality and performance of the solar cell.

[0011] In one implementation, the ratio of the depth of the main gate extending into the passivation layer to the thickness of the passivation layer is greater than or equal to 20%.

[0012] When the above technical solution is adopted, the main grid is connected to the insulating layer and the passivation layer at the same time. At this time, the mechanical properties of the main grid can be guaranteed and the tensile properties of the main grid can be improved to reduce or eliminate the probability of the main grid detaching from the solar cell, thereby ensuring the quality and performance of the solar cell.

[0013] In one implementation, the main gate extends into the passivation layer to a depth of zero.

[0014] When the above technical solution is adopted, the main grid can be prevented from damaging the passivation layer, so as to ensure the passivation effect of the passivation layer. Based on this, the open circuit voltage can be increased and the influence on the photoelectric conversion efficiency can be avoided.

[0015] In one implementation, when the thickness of the passivation layer is greater than or equal to 5 nm and less than or equal to 20 nm, the main gate extends into the passivation layer to a depth greater than or equal to 1 nm and less than or equal to 18 nm.

[0016] In the case of adopting the above technical solution, since the depth is greater than or equal to 1nm, it can be ensured that the main grid is connected to the insulating layer and the passivation layer at the same time. Based on this, the mechanical properties of the main grid can be guaranteed, and the tensile properties of the main grid can be improved to reduce or eliminate the probability of the main grid detaching from the solar cell, thereby ensuring the quality and performance of the solar cell. Furthermore, since the depth is less than or equal to 18nm, the degree of damage to the passivation layer by the main grid can be reduced, ensuring the passivation effect of the passivation layer, thereby increasing the open circuit voltage and reducing the impact on the photoelectric conversion efficiency.

[0017] In one implementation, the thickness of the insulating layer is greater than or equal to 40 nanometers and less than or equal to 100 nanometers.

[0018] In one implementation, each busbar includes a busbar connection line and a pad. A plurality of pads are spaced from the busbar connection line along a first direction, the pads are wider than the busbar connection line, and the widths of the pads and the busbar connection line are consistent with the second direction.

[0019] In the case of adopting the above technical solution, when the number of main grid connection lines is the same, compared with the case where the width of the main grid connection line is equal to the width of the pad, it is possible to reduce the amount of raw materials used to make the main grid connection line while ensuring that the current collection capacity of the main grid connection line meets actual needs, thereby saving raw material costs. At the same time, it is also possible to reduce the shielding of the semiconductor substrate by the main grid connection line, increase the light receiving area of ​​the semiconductor substrate, and improve the photoelectric conversion efficiency of the solar cell. Furthermore, when the battery string is manufactured at a later stage, the welding strip needs to be connected to the pad. At this time, compared with the case where the width of the main grid connection line is equal to the width of the pad, the welding strip is easier to connect to the pad, which reduces the difficulty of manufacturing and improves the manufacturing efficiency.

[0020] In one implementation, the number of the main grids is greater than or equal to 8 and less than or equal to 25. And / or the width of the main grid connection line is greater than or equal to 35 micrometers and less than or equal to 60 micrometers. The width of the pad is greater than or equal to 0.6 millimeters and less than or equal to 1.3 millimeters.

[0021] When the above technical solution is adopted, the shielding area of ​​the main grid to the semiconductor substrate can be controlled by controlling the number of main grids, the width of the main grid connection line and the width of the pad. At this time, the amount of light injected into the semiconductor substrate can be increased, and the light receiving area of ​​the semiconductor substrate can be increased to improve the cell efficiency of the solar cell.

[0022] In one implementation, the number of the fine gates is greater than or equal to 100 and less than or equal to 200. The width of the fine gate is greater than or equal to 20 micrometers and less than or equal to 45 micrometers, and the width direction of the fine gate is consistent with the first direction.

[0023] When the above technical solution is adopted, the current collection capability of the fine grid can be improved, so as to improve the cell efficiency of the solar cell.

[0024] In one implementation, forming a busbar on the insulating layer includes: first, printing a busbar material on the insulating layer to form an initial busbar. Next, processing the initial busbar to form a busbar. The ratio of the width of the busbar to the width of the initial busbar is greater than 1 and less than or equal to 1.1, and the width direction of the busbar and the width direction of the initial busbar are both consistent with the second direction.

[0025] When the above technical solution is adopted, by controlling the size of the main grid that is finally formed and extends in the second direction, not only can the adverse effects on the insulating layer and / or the passivation layer be reduced, but also the adverse effects on the anti-reflection effect and / or the passivation effect of the solar cell can be reduced. At the same time, the main grid can also reduce the shielding of the semiconductor substrate, increase the light receiving area of ​​the semiconductor substrate, and improve the photoelectric conversion efficiency of the solar cell.

[0026] In one implementation, forming the fine gate on the insulating layer includes: first, printing a fine gate material on the insulating layer to form an initial fine gate. Next, processing the initial fine gate to form the fine gate. The ratio of the width of the fine gate to the width of the initial fine gate is greater than 1 and less than or equal to 1.2, and the width direction of the fine gate and the width direction of the initial fine gate are both consistent with the first direction.

[0027] When the above technical solution is adopted, by controlling the size of the fine grid finally formed extending in the second direction, not only the adverse effect on the insulating layer and / or the passivation layer can be reduced, but also the adverse effect on the anti-reflection effect and / or the passivation effect of the solar cell can be reduced. At the same time, the shielding of the semiconductor substrate by the fine grid can be reduced, the light receiving area of ​​the semiconductor substrate can be increased, and the photoelectric conversion efficiency of the solar cell can be improved.

[0028] In one implementation, the metal solid content in the main grid material is less than the metal solid content in the fine grid material.

[0029] When the above technical solution is adopted, the depth of the main gate extending toward the emitter layer is less than the depth of the fine gate extending toward the emitter layer. At this time, the degree of damage of the main gate to the passivation layer can be reduced to ensure the passivation effect of the passivation layer. Furthermore, when the metal solid content in the fine gate raw material remains unchanged, compared with the case where the metal solid content in the main gate raw material and the fine gate raw material is the same in the prior art, not only can the cost of the main gate raw material be reduced, so as to reduce the manufacturing cost of solar cells. At the same time, it can also ensure that the depth of the fine gate extending toward the emitter layer in the present invention is basically the same or consistent with the depth of the fine gate extending toward the emitter layer in the prior art, so as to ensure that the performance of the fine gate remains unchanged.

[0030] In a second aspect, the present invention also provides a solar cell. The solar cell comprises: a semiconductor substrate, an emitter layer, a passivation layer, an insulating layer, a main grid and a fine grid. The emitter layer is located on one side of the semiconductor substrate, the semiconductor substrate and the emitter layer have opposite conductivity types, and the emitter layer and the semiconductor substrate form a PN junction together. The passivation layer is located on the emitter layer, and the insulating layer is located on the passivation layer. The main grid is located on the insulating layer, the main grid extends along a first direction, and is spaced apart along a second direction, and the first direction is different from the second direction. The fine grid is located on the insulating layer, the fine grid extends along the second direction, and is spaced apart along the first direction, and each main grid intersects with a plurality of fine grids. The fine grid passes through the passivation layer and the insulating layer, and is connected to the emitter layer. The main grid extends in the direction of the emitter layer, the depth of the main grid extension does not exceed 90% of the thickness of the passivation layer, and exceeds 20% of the thickness of the insulating layer, and the depth direction, the thickness direction of the passivation layer, and the thickness direction of the insulating layer are all consistent with the direction toward the semiconductor substrate.

[0031] In the solar cell provided by the present invention, since the main grid is formed on the insulating layer and extends toward the emitter layer, the depth of the main grid extension does not exceed 90% of the thickness of the passivation layer and exceeds 20% of the thickness of the insulating layer. At this time, the extended part of the main grid (i.e., part of the main grid area) may be located only in the insulating layer; or it may be located in both the insulating layer and the passivation layer, but not exceeding 90% of the thickness of the passivation layer.

[0032] When the extended portion of the main grid is only located in the insulating layer, the main grid does not damage the passivation layer, thereby ensuring the passivation effect of the passivation layer. Based on this, the open circuit voltage can be increased to reduce or avoid the impact on the photoelectric conversion efficiency.

[0033] When the extended part of the main grid is located in both the insulating layer and the passivation layer, but does not exceed 90% of the thickness of the passivation layer, compared with the prior art where the main grid passes through the passivation layer and is connected to the silicon substrate, the degree of damage to the passivation layer by the main grid is reduced, thereby ensuring the passivation effect of the passivation layer. Based on this, the open circuit voltage can be increased, thereby reducing the impact on the photoelectric conversion efficiency. Furthermore, the above-mentioned main grid is connected to the insulating layer and the passivation layer at the same time, at which time the mechanical properties of the main grid can be guaranteed and the tensile properties of the main grid can be improved. Based on this, the probability of the main grid detaching from the solar cell can be reduced or eliminated to ensure the quality and performance of the solar cell.

[0034] In one implementation, the ratio of the depth of the main gate extending into the passivation layer to the thickness of the passivation layer is greater than or equal to 20%.

[0035] When the above technical solution is adopted, the main grid is connected to the insulating layer and the passivation layer at the same time. At this time, the mechanical properties of the main grid can be guaranteed and the tensile properties of the main grid can be improved to reduce or eliminate the probability of the main grid detaching from the solar cell, thereby ensuring the quality and performance of the solar cell.

[0036] In one implementation, the main gate extends into the passivation layer to a depth of zero.

[0037] When the above technical solution is adopted, the main grid can be prevented from damaging the passivation layer, so as to ensure the passivation effect of the passivation layer. Based on this, the open circuit voltage can be increased and the influence on the photoelectric conversion efficiency can be avoided.

[0038] In one implementation, when the thickness of the passivation layer is greater than or equal to 5 nm and less than or equal to 20 nm, the main gate extends into the passivation layer to a depth greater than or equal to 1 nm and less than or equal to 18 nm.

[0039] In the case of adopting the above technical solution, since the depth is greater than or equal to 1nm, it can be ensured that the main grid is connected to the insulating layer and the passivation layer at the same time. Based on this, the mechanical properties of the main grid can be guaranteed, and the tensile properties of the main grid can be improved to reduce or eliminate the probability of the main grid detaching from the solar cell, thereby ensuring the quality and performance of the solar cell. Furthermore, since the depth is less than or equal to 18nm, the degree of damage to the passivation layer by the main grid can be reduced, ensuring the passivation effect of the passivation layer, thereby increasing the open circuit voltage and reducing the impact on the photoelectric conversion efficiency.

[0040] In one implementation, the thickness of the insulating layer is greater than or equal to 40 nanometers and less than or equal to 100 nanometers.

[0041] In one implementation, each busbar includes a busbar connection line and a pad. A plurality of pads are spaced from the busbar connection line along a first direction, the pads are wider than the busbar connection line, and the widths of the pads and the busbar connection line are consistent with the second direction.

[0042] In the case of adopting the above technical solution, when the number of main grid connection lines is the same, compared with the case where the width of the main grid connection line is equal to the width of the pad, it is possible to reduce the amount of raw materials used to make the main grid connection line while ensuring that the current collection capacity of the main grid connection line meets actual needs, thereby saving raw material costs. At the same time, it is also possible to reduce the shielding of the semiconductor substrate by the main grid connection line, increase the light receiving area of ​​the semiconductor substrate, and improve the photoelectric conversion efficiency of the solar cell. Furthermore, when the battery string is manufactured at a later stage, the welding strip needs to be connected to the pad. At this time, compared with the case where the width of the main grid connection line is equal to the width of the pad, the welding strip is easier to connect to the pad, which reduces the difficulty of manufacturing and improves the manufacturing efficiency.

[0043] In one implementation, the number of the busbars is greater than or equal to 8 and less than or equal to 25; and / or the width of the busbar connection line is greater than or equal to 35 micrometers and less than or equal to 60 micrometers. The width of the pad is greater than or equal to 0.6 millimeters and less than or equal to 1.3 millimeters.

[0044] When the above technical solution is adopted, the shielding area of ​​the main grid to the semiconductor substrate can be controlled by controlling the number of main grids, the width of the main grid connection line and the width of the pad. At this time, the amount of light injected into the semiconductor substrate can be increased, and the light receiving area of ​​the semiconductor substrate can be increased to improve the cell efficiency of the solar cell.

[0045] In one implementation, the number of the fine gates is greater than or equal to 100 and less than or equal to 200. The width of the fine gate is greater than or equal to 20 micrometers and less than or equal to 45 micrometers, and the width direction of the fine gate is consistent with the first direction.

[0046] When the above technical solution is adopted, the current collection capability of the fine grid can be improved, so as to improve the cell efficiency of the solar cell.

[0047] In a third aspect, the present invention further provides a battery string, which comprises a plurality of welding strips and a plurality of solar cells arranged at intervals as described in the above technical solution, wherein the welding strips are correspondingly connected to the main grid.

[0048] Compared with the prior art, the beneficial effects of the battery string provided by the present invention are the same as the beneficial effects of the solar cell described in the above technical solution, which will not be described in detail here.

[0049] In one implementation, when the busbar includes a busbar connection line and a pad, the soldering strip is disposed on the pad along the first direction and covers the busbar connection line. The maximum width of the soldering strip is less than or equal to the width of the pad, and the width direction of the soldering strip and the width direction of the pad are both consistent with the second direction.

[0050] When the above technical solution is adopted, the shielding of the semiconductor substrate by the welding strip can be reduced, the light receiving area of ​​the semiconductor substrate can be increased, and the photoelectric conversion efficiency of the solar cell can be improved.

[0051] In one implementation, the width of the welding strip is less than or equal to the width of the main grid connection line, and the width direction of the welding strip and the width direction of the main grid connection line are both consistent with the second direction.

[0052] When the above technical solution is adopted, the shielding of the semiconductor substrate by the welding strip can be reduced, the light receiving area of ​​the semiconductor substrate can be increased, and the photoelectric conversion efficiency of the solar cell can be improved.

[0053] In one implementation, the ratio of the width of the welding strip to the width of the main grid connection line is greater than or equal to 50% and less than or equal to 90%.

[0054] When the above technical solution is adopted, since the welding strip includes a core layer of metal material and a solder layer located on the outer surface of the core layer. In the actual process of welding the welding strip and the pad, the solder layer melts under heat and has a certain fluidity. Since the above ratio is greater than or equal to 50% and less than or equal to 90%, the flowing solder can be distributed at the interface between the welding strip and the main grid connection line, giving it sufficient flow space. At this time, the solder can be prevented from flowing onto the semiconductor substrate to avoid solder contamination and shielding of the semiconductor substrate, thereby ensuring the quality and performance of the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0056] Figure 1 It is a schematic diagram of the structure of a solar cell in the prior art;

[0057] Figure 2 The structure of the solar cell in the embodiment of the present invention is shown in FIG. Figure 1 ;

[0058] Figure 3 The structure of the solar cell in the embodiment of the present invention is shown in FIG. Figure 2 .

[0059] Reference numerals:

[0060] 1- semiconductor substrate, 2- emitter layer, 3- passivation layer,

[0061] 4-insulation layer, 5-main grid, 50-main grid connection line,

[0062] 51- pad, 6- fine grid. DETAILED DESCRIPTION

[0063] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0064] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0065] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0066] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by the terms "up", "down", "front", "back", "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0067] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0068] Screen printing is the core of process management in the manufacturing process of solar cells. Screen printing is mainly used for electrode formation of solar cells. Specifically, printing is performed based on the basic principle that the mesh holes of the graphic part of the screen are permeable to the slurry, while the mesh holes of the non-graphic part are not permeable to the slurry. When printing, pour the slurry at one end of the screen, and use a scraper to apply a certain pressure to the slurry part of the screen while moving toward the other end of the screen. During the movement, the slurry is squeezed from the mesh holes of the graphic part to the substrate by the scraper to form the required pattern. Conventional solar cell screen printing adopts the mainstream SP (Single Print) mode, that is, the main and fine grid integrated printing mode. The main grid and fine grid are taken into consideration at the same time in the screen design, and the main and fine grid lines are overlapped after a single printing of the slurry. After printing, the slurry contacts the insulating layer (such as SiNx). The phosphate glass component contained in the slurry is corrosive to a certain extent, and will corrode the SiNx and the underlying passivation layer (such as AlOx) on the contact surface, causing the Ag and Si in the slurry to form a silver-silicon alloy, thereby forming a better ohmic contact.

[0069] Specifically, in the existing screen printing electrode manufacturing process, the battery that has completed a single integrated slurry printing enters the sintering furnace. The first stage of sintering is carried out in the temperature range of 200℃ to 400℃. At this stage, organic binders such as ethyl cellulose and polyvinyl alcohol will be burned. The second stage is carried out at 600℃ to 900℃. This stage is an important step in forming the electrode. At this stage, the phosphate glass material changes from a solid state to a molten state at high temperature, which can corrode the polysilicon layer (such as the emitter layer), play a role in widening the window, and carry the metal conductive phase silver particles forward, melt and corrode the lower dielectric film (such as the emitter layer). The silver particles are melted or reacted by calcination, and further contact is formed with the lower film layer. In this process, the main grid formed by SP integrated printing also corrodes the lower layer, penetrates the insulating layer and the passivation layer (the thickness of the passivation layer is generally greater than or equal to 5nm and less than or equal to 20nm), and the final stay depth is consistent with the fine grid. That is, during the sintering process, as the corrosion proceeds simultaneously, the main gate and the fine gate are in contact with the silicon substrate. However, the main gate will seriously damage the passivation layer during the contact with the silicon substrate. At this time, the open circuit voltage (Uoc) will be reduced, which will affect the photoelectric conversion efficiency. Figure 1 , the main gate 5 contacts the emitter layer 2 on the silicon substrate (i.e., the semiconductor substrate 1), which will also cause the open circuit voltage (Uoc) to decrease, thereby affecting the photoelectric conversion efficiency. It should be noted that the emitter layer 2 can be formed by doping in the original structure of the single crystal silicon semiconductor substrate, such as by diffusion or ion implantation, or it can be an additional layer formed on the surface of the original single crystal silicon semiconductor substrate by deposition or other processes.

[0070] In order to solve the above technical problems, in a first aspect, an embodiment of the present invention provides a method for manufacturing a solar cell. The method for manufacturing a solar cell comprises the following steps:

[0071] See also Figure 2 and Figure 3 First, a semiconductor substrate 1 is provided.

[0072] In the actual application process, the specific structure of the above-mentioned semiconductor substrate can be determined according to the actual application scenario, and no specific limitation is made here. For example: the above-mentioned semiconductor substrate can be only a semiconductor substrate. Exemplarily, the above-mentioned semiconductor substrate can be a substrate of semiconductor materials such as a single crystal silicon substrate, a polycrystalline silicon substrate or an amorphous silicon substrate. In terms of conductivity type, the semiconductor substrate can be an N-type conductive substrate or a P-type conductive substrate. In terms of structure, the first surface of the semiconductor substrate can be a velvet surface to improve the light trapping effect of the solar cell to the light surface, thereby improving the utilization rate of light by the solar cell. Of course, the first surface of the semiconductor substrate can also be a plane. As for the second surface of the semiconductor substrate, it can be a polished surface or a velvet surface, which is not specifically limited here. Further, the size of the above-mentioned semiconductor substrate can be 182, 210 or other semiconductor substrates such as a rectangular shape. The thickness of the semiconductor substrate is generally greater than or equal to 100 microns and less than or equal to 180 microns.

[0073] Next, an emitter layer 2 is formed on one side of the semiconductor substrate 1. The semiconductor substrate 1 and the emitter layer 2 have opposite conductivity types, and the emitter layer 2 and the semiconductor substrate 1 together form a PN junction.

[0074] Exemplarily, the emitter layer is a region doped with impurities of a second conductivity type (e.g., N type) opposite to the first conductivity type (e.g., P type) of the semiconductor substrate. Furthermore, the emitter layer may be formed by doping in the original structure of the single crystal silicon semiconductor substrate, for example, by industry-wide means such as diffusion or ion implantation, or may be an additional layer formed on the surface of the original single crystal silicon semiconductor substrate by deposition or other processes. Further, the emitter layer is located on the light-receiving surface of the semiconductor substrate. In addition, other descriptions of the emitter layer may refer to the prior art and are not specifically limited here.

[0075] Next, the passivation layer 3 is formed on the emitter layer 2 .

[0076] Exemplarily, the material of the passivation layer 3 may include one or more of aluminum oxide, zinc oxide, and silicon nitride.

[0077] Next, the insulating layer 4 is formed on the passivation layer 3 .

[0078] Exemplarily, the material of the insulating layer 4 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0079] Next, a main gate 5 is formed on the insulating layer 4. The main gate 5 extends along a first direction and is spaced apart along a second direction, and the first direction is different from the second direction.

[0080] Exemplarily, the first direction and the second direction may be any two directions parallel to the surface of the semiconductor substrate and different from each other. Figure 3 , the first direction A and the second direction B are orthogonal.

[0081] Next, fine gates 6 are formed on the insulating layer 4. The fine gates 6 extend along the second direction and are spaced apart along the first direction. Each main gate 5 intersects with a plurality of fine gates 6. The fine gates 6 pass through the passivation layer 3 and the insulating layer 4 and are connected to the emitter layer 2.

[0082] For example, in the direction of the semiconductor substrate 1, the fine gate can be connected to the emitter layer through openings on the passivation layer and the insulating layer, or through through holes on the passivation layer and the insulating layer, or by other means. It should be understood that as long as the fine gate can be connected to the emitter layer, the connection method is not limited to the above description.

[0083] The main gate 5 extends in the direction C of the emitter layer 2, the depth D1 of the main gate 5 does not exceed 90% of the thickness D2 of the passivation layer 3, and exceeds 20% of the thickness D3 of the insulating layer 4, and the depth direction, the thickness direction of the passivation layer 3, and the thickness direction of the insulating layer 4 are all consistent with the direction toward the semiconductor substrate 1. Exemplarily, the depth of the main gate 5 extension can be 0%, 10%, 15%, 30%, 50%, 80% or 90% of the thickness of the passivation layer 3, etc.

[0084] In the method for manufacturing a solar cell provided by an embodiment of the present invention, since the main grid 5 is formed on the insulating layer 4 and the main grid 5 extends toward the emitter layer 2, the depth of the extension of the main grid 5 does not exceed 90% of the thickness of the passivation layer 3 and exceeds 20% of the thickness of the insulating layer. At this time, the extended portion of the main grid 5 (i.e., a portion of the main grid) may be located only in the insulating layer 4; or it may be located in both the insulating layer 4 and the passivation layer 3, but not exceeding 90% of the thickness of the passivation layer 3.

[0085] When the extended portion of the main gate 5 is only located in the insulating layer 4, the main gate 5 does not damage the passivation layer 3, thereby ensuring the passivation effect of the passivation layer 3. Based on this, the open circuit voltage can be increased to reduce or avoid the impact on the photoelectric conversion efficiency.

[0086] When the extended portion of the main grid 5 is located in both the insulating layer 4 and the passivation layer 3, but does not exceed 90% of the thickness of the passivation layer 3, compared with the prior art where the main grid 5 passes through the passivation layer 3 and is connected to the silicon substrate, the degree of damage to the passivation layer 3 by the main grid 5 is reduced, and the passivation effect of the passivation layer 3 is ensured. Based on this, the open circuit voltage can be increased, thereby reducing the impact on the photoelectric conversion efficiency. Further, when the battery string is made to establish an electrical connection in the later stage, the welding strip will cover the main grid 5. Due to the mechanical effects brought by the welding strip (including but not limited to stress, expansion coefficient mismatch, etc.), the main grid 5 will be unfavorable (for example, the main grid 5 may be peeled off from the solar cell). When the extended portion of the main grid 5 is located in both the insulating layer 4 and the passivation layer 3, but does not exceed 90% of the thickness of the passivation layer 3, the above-mentioned main grid 5 is connected to the insulating layer 4 and the passivation layer 3 at the same time, and the mechanical properties of the main grid 5 can be guaranteed at this time, and the tensile properties of the main grid 5 can be improved. Based on this, the probability of the main grid 5 detaching from the solar cell can be reduced or eliminated to ensure the quality and performance of the solar cell.

[0087] In an optional manner, the solar cell mentioned above may be a back contact cell.

[0088] As a possible implementation, see Figure 2 , the ratio of the depth of the main grid 5 extending into the passivation layer 3 to the thickness of the passivation layer 3 is greater than or equal to 20%. Exemplarily, the ratio may be 20%, 30%, 35%, 46%, 50%, etc. At this time, the main grid 5 is connected to the insulating layer 4 and the passivation layer 3 at the same time. Based on this, the mechanical properties of the main grid 5 can be guaranteed, and the tensile properties of the main grid 5 can be improved to reduce or eliminate the probability of the main grid 5 detaching from the solar cell, thereby ensuring the quality and performance of the solar cell.

[0089] In combination with the above description, after the main gate 5 extends into the passivation layer 3 , the ratio of the depth of the main gate 5 extending into the passivation layer 3 to the thickness of the passivation layer 3 is greater than or equal to 20% and less than or equal to 90%.

[0090] As a possible implementation, the main gate 5 extends into the passivation layer 3 to a depth of 0. That is, the main gate 5 is only located in the insulating layer 4, specifically, the main gate 5 is only located inside the insulating layer 4, or the main gate 5 is located at the junction of the insulating layer 4 and the passivation layer 3, or the main gate 5 is only located on the surface of the insulating layer 4. At this time, the main gate 5 can be prevented from damaging the passivation layer 3 to ensure the passivation effect of the passivation layer 3. Based on this, the open circuit voltage can be increased to avoid affecting the photoelectric conversion efficiency.

[0091] As a possible implementation, when the thickness of the passivation layer is greater than or equal to 5 nm and less than or equal to 20 nm, the main gate extends into the passivation layer to a depth greater than or equal to 1 nm and less than or equal to 18 nm. For example, the main gate extends into the passivation layer to a depth of 1 nm, 5 nm, 9 nm, 13 nm, 15 nm, or 18 nm.

[0092] Since the depth is greater than or equal to 1nm, it can be ensured that the main grid is connected to the insulating layer and the passivation layer at the same time. Based on this, the mechanical properties of the main grid can be guaranteed, and the tensile properties of the main grid can be improved to reduce or eliminate the probability of the main grid detaching from the solar cell, thereby ensuring the quality and performance of the solar cell. Furthermore, since the depth is less than or equal to 18nm, the degree of damage to the passivation layer by the main grid can be reduced at this time, ensuring the passivation effect of the passivation layer, so as to increase the open circuit voltage and reduce the impact on the photoelectric conversion efficiency. In addition, it can be ensured that the thickness of the passivation layer above 2nm is not damaged.

[0093] As a possible implementation, the emitter layer includes a heavily doped region and a lightly doped region. The fine gate is connected to the heavily doped region to form an alloy region. The depth of the alloy region extending into the emitter layer is less than the junction depth of the emitter of the emitter layer, and the depth direction and the junction depth direction of the emitter are consistent with the direction toward the semiconductor substrate.

[0094] In an optional manner, when the junction depth of the emitter is greater than or equal to 300 nanometers and less than or equal to 1200 nanometers, the depth of the alloy region extending into the emitter is greater than or equal to 50 nanometers and less than or equal to 1000 nanometers. For example, the depth of the alloy region extending into the emitter can be 50 nanometers, 80 nanometers, 100 nanometers, 260 nanometers, 390 nanometers, 550 nanometers or 1000 nanometers. Since the depth is greater than or equal to 50 nanometers, the fine gate can be alloyed with the semiconductor substrate to form a better ohmic contact.

[0095] Preferably, when the junction depth of the emitter is greater than or equal to 300 nanometers and less than or equal to 1200 nanometers, the depth of the alloy region extending into the emitter is greater than or equal to 50 nanometers and less than or equal to 100 nanometers.

[0096] As a possible implementation, the thickness of the insulating layer is greater than or equal to 40 nanometers and less than or equal to 100 nanometers. For example, the thickness of the insulating layer can be 40 nanometers, 50 nanometers, 60 nanometers, 70 nanometers, 80 nanometers, 90 nanometers or 100 nanometers.

[0097] As a possible implementation, see Figure 3Each busbar 5 includes: a busbar connection line 50 and a pad 51. A plurality of pads 51 are arranged at intervals on the busbar connection line 50 along the first direction, the width of the pad 51 is greater than the width of the busbar connection line 50, and the width direction of the pad 51 and the width direction of the busbar connection line 50 are consistent with the second direction.

[0098] See also Figure 2 and Figure 3 , when the number of main grid connection lines 50 is the same, compared with the case where the width of the main grid connection line 50 is equal to the width of the pad 51, it is possible to reduce the amount of raw materials used to make the main grid connection line 50 while ensuring that the current collection capacity of the main grid connection line 50 meets the actual needs, thereby saving the cost of raw materials. At the same time, it is also possible to reduce the shielding of the semiconductor substrate 1 by the main grid connection line 50, increase the light receiving area of ​​the semiconductor substrate 1, and improve the photoelectric conversion efficiency of the solar cell. Furthermore, when the battery string is manufactured later, the welding strip needs to be connected to the pad 51. At this time, compared with the case where the width of the main grid connection line 50 is equal to the width of the pad 51, the welding strip is easier to connect to the pad 51, which reduces the difficulty of manufacturing and improves the manufacturing efficiency. It should be understood that the specific structure, manufacturing material, etc. of the above-mentioned main grid connection line 50 and the pad 51 can refer to the prior art and are not specifically limited here.

[0099] In an alternative approach, see Figure 3 , the number of the above-mentioned main grids 5 is greater than or equal to 8 and less than or equal to 25. For example, the number of the main grids 5 can be 8, 10, 12, 15, 18, 20, 22 or 25, etc. And / or, the width of the main grid connection line 50 is greater than or equal to 35 microns and less than or equal to 60 microns. For example, the width of the main grid connection line 50 can be 35 microns, 40 microns, 45 microns, 52 microns, 55 microns or 60 microns, etc. The width of the pad 51 is greater than or equal to 0.6 mm and less than or equal to 1.3 mm. For example, the width of the pad 51 can be 0.6 mm, 0.8 mm, 1.0 mm, 1.16 mm, 1.23 mm or 1.3 mm, etc.

[0100] By controlling the number of main grids 5, the width of the main grid connection line and the width of the pad, the shielding area of ​​the main grid 5 on the semiconductor substrate 1 can be controlled. At this time, the amount of light injected into the semiconductor substrate 1 can be increased, and the light receiving area of ​​the semiconductor substrate 1 can be increased to improve the cell efficiency of the solar cell.

[0101] As a possible implementation, see Figure 3, the number of the fine grids 6 is greater than or equal to 100 and less than or equal to 200. For example, the number of the fine grids 6 can be 100, 120, 150, 180, 195 or 200. The width of the fine grid 6 is greater than or equal to 20 microns and less than or equal to 45 microns, and the width direction of the fine grid 6 is consistent with the first direction. For example, the width of the fine grid 6 can be 20 microns, 26 microns, 30 microns, 36 microns, 40 microns or 45 microns. At this time, the current collection capability of the fine grid 6 can be improved to improve the cell efficiency of the solar cell.

[0102] As a possible implementation manner, forming a main gate on the insulating layer includes:

[0103] First, a main grid material is printed on the insulating layer to form an initial main grid.

[0104] Exemplarily, the main grid raw material contains glass material and metal. For example, the glass material includes one or more of PbO, B2O3, Na2O, Li2O, Bi2O3, WO3, TeO2, Te / W, and the specific proportion can refer to the prior art, which is not specifically limited here. The metal includes but is not limited to silver. Furthermore, the main grid raw material can be printed by screen printing, and the specific printing process can refer to the prior art, which is not specifically limited here.

[0105] Next, the initial busbar is processed to form a busbar.

[0106] The ratio of the width of the main grid to the width of the initial main grid is greater than 1 and less than or equal to 1.1, and the width direction of the main grid and the width direction of the initial main grid are consistent with the second direction. For example, the ratio can be 1.01, 1.02, 1.04, 1.05, 1.08, 1.09 or 1.1.

[0107] In the actual process of manufacturing the main grid, the main grid will not only extend in the direction of the emitter layer, but also extend in the second direction. Therefore, by controlling the size of the main grid finally formed extending in the second direction, not only the adverse effects on the insulating layer and / or the passivation layer can be reduced, but also the adverse effects on the anti-reflection effect and / or the passivation effect of the solar cell can be reduced. At the same time, the main grid can also reduce the shielding of the semiconductor substrate, increase the light receiving area of ​​the semiconductor substrate, and improve the photoelectric conversion efficiency of the solar cell.

[0108] In addition, the main gate does not extend into the semiconductor substrate. It should be noted that the term "not extending into the semiconductor substrate" means that the metal component (e.g., silver) in the main gate material will not enter the interface of the semiconductor substrate, or the metal component (e.g., silver) in the main gate material will not form an alloy (e.g., silver-silicon alloy) with the semiconductor material in the semiconductor substrate.

[0109] Preferably, the ratio of the width of the main grid to the width of the initial main grid is greater than 1 and less than or equal to 1.05. For example, the ratio may be 1.01, 1.02, 1.03, 1.04 or 1.05.

[0110] As a possible implementation manner, forming a fine gate on the insulating layer includes:

[0111] First, a fine grid material is printed on the insulating layer to form an initial fine grid.

[0112] Exemplarily, the fine grid raw material contains glass material and metal. For example, the glass material includes one or more of PbO, B2O3, Na2O, Li2O, Bi2O3, WO3, TeO2, Te / W, and the specific proportion can refer to the prior art, which is not specifically limited here. The metal includes but is not limited to silver. Furthermore, the method of printing the fine grid raw material can be screen printing, and the specific printing process can refer to the prior art, which is not specifically limited here.

[0113] Next, the initial fine gate is processed to form a fine gate.

[0114] The ratio of the width of the fine gate to the width of the initial fine gate is greater than 1 and less than or equal to 1.2, and the width direction of the fine gate and the width direction of the initial fine gate are both consistent with the first direction. For example, the ratio can be 1.01, 1.02, 1.04, 1.05, 1.08, 1.09, 1.1 or 1.2.

[0115] In the actual process of making the fine grid, the fine grid will extend in the second direction, and the corrosiveness of the fine grid material is greater than that of the main grid material. Therefore, by controlling the size of the fine grid finally formed extending in the second direction, not only can the adverse effect on the insulating layer and / or the passivation layer be reduced, but also the adverse effect on the anti-reflection effect and / or passivation effect of the solar cell can be reduced. At the same time, the shielding of the semiconductor substrate by the fine grid can be reduced, the light receiving area of ​​the semiconductor substrate can be increased, and the photoelectric conversion efficiency of the solar cell can be improved.

[0116] Furthermore, the fine gate will extend to the emitter layer. Under the windowing effect of the phosphate glass, the metal component in the fine gate raw material enters the emitter layer and forms an alloy (such as a silver-silicon alloy) with the semiconductor component. The silver-silicon alloy formation area greatly improves the contact performance, and the silver-silicon alloy distribution area is located within the area covered by the fine gate. The silver-silicon alloy distribution area can be continuous, but due to the migration of silver particles, the distribution of the silver-silicon alloy can be discrete and discontinuous, or both. The depth of the silver-silicon alloy distribution area can be adjusted according to the process and the composition of the fine gate raw material. Generally speaking, the higher the glass content, the stronger the extension performance of the fine gate.

[0117] Furthermore, the above-mentioned heavily doped region is generally located below the fine gate, but the heavily doped region can also be located below the main gate. In an embodiment of the present invention, it is preferred that the heavily doped region is located below the fine gate, and no heavily doped region is provided below the main gate. The silver-silicon alloy is distributed in the heavily doped region, but sometimes the silver-silicon alloy will also migrate laterally beyond the heavily doped region and enter the adjacent lightly doped region, but the content of the exceeding part is less and is generally discrete. The total amount of silver-silicon alloy entering the adjacent lightly doped region does not exceed 10% of the total silver-silicon alloy, or even less than 5% or 2%. The transitional entry of the silver-silicon alloy into the adjacent lightly doped region will bring about adverse effects.

[0118] Preferably, the ratio of the width of the fine gate to the width of the initial fine gate is greater than 1 and less than or equal to 1.08. For example, the ratio may be 1.01, 1.02, 1.03, 1.04, 1.05, 1.06, 1.07 or 1.08.

[0119] In an optional manner, the metal solid content in the main grid material is less than the metal solid content in the fine grid material. Exemplarily, the silver solid content in the main grid material is less than the silver solid content in the fine grid material.

[0120] At this time, the depth of the main gate extending toward the emitter layer is less than the depth of the fine gate extending toward the emitter layer. Based on this, the degree of damage to the passivation layer by the main gate can be reduced to ensure the passivation effect of the passivation layer. Furthermore, when the metal solid content in the fine gate raw material remains unchanged, compared with the case where the metal solid content in the main gate raw material and the fine gate raw material is the same in the prior art, not only can the cost of the main gate raw material be reduced, so as to reduce the production cost of solar cells. At the same time, it can also ensure that the depth of the fine gate extending toward the emitter layer in the embodiment of the present invention is basically the same or consistent with the depth of the fine gate extending toward the emitter layer in the prior art, so as to ensure that the performance of the fine gate remains unchanged.

[0121] In addition, the extension depth of the main grid and the fine grid can be adjusted by controlling the specific composition of the main grid material and the fine grid material, for example, by increasing the glass content or metal content in the main grid material and the fine grid material.

[0122] In a second aspect, an embodiment of the present invention further provides a solar cell. Figure 2 and Figure 3The solar cell comprises: a semiconductor substrate 1, an emitter layer 2, a passivation layer 3, an insulating layer 4, a main grid 5 and a fine grid 6. The emitter layer 2 is located on one side of the semiconductor substrate 1, the semiconductor substrate 1 and the emitter layer 2 have opposite conductivity types, and the emitter layer 2 and the semiconductor substrate 1 together form a PN junction. The passivation layer 3 is located on the emitter layer 2, and the insulating layer 4 is located on the passivation layer 3. The main grid 5 is located on the insulating layer 4, the main grid 5 extends along a first direction, and is distributed at intervals along a second direction, and the first direction is different from the second direction. The fine grid 6 is located on the insulating layer 4, the fine grid 6 extends along the second direction, and is distributed at intervals along the first direction, and each main grid 5 intersects with multiple fine grids 6. The fine grid 6 passes through the passivation layer 3 and the insulating layer 4, and is connected to the emitter layer 2. The main gate 5 extends toward the emitter layer 2, the depth D1 of the main gate 5 does not exceed 90% of the thickness D2 of the passivation layer 3, and exceeds 20% of the thickness D3 of the insulating layer 4, and the depth direction, the thickness direction of the passivation layer 3, and the thickness direction of the insulating layer 4 are all consistent with the direction toward the semiconductor substrate 1. Exemplarily, the depth of the main gate 5 extension can be 0%, 10%, 15%, 30%, 50%, 80% or 90% of the thickness of the passivation layer 3, etc.

[0123] The relevant information of the semiconductor substrate 1, emitter layer 2, passivation layer 3 and insulating layer 4 can refer to the description of the first aspect, and will not be repeated here. Furthermore, the first direction and the second direction can be any two directions parallel to the surface of the semiconductor substrate 1 and different from each other. Preferably, see Figure 3 , the first direction A and the second direction B are orthogonal.

[0124] In the solar cell provided by the embodiment of the present invention, since the main grid 5 is formed on the insulating layer 4 and the main grid 5 extends toward the emitter layer 2, the depth of the extension of the main grid 5 does not exceed 90% of the thickness of the passivation layer 3 and exceeds 20% of the thickness of the insulating layer. At this time, the extended part of the main grid 5 (i.e., part of the main grid area) may be located only in the insulating layer 4; or it may be located in both the insulating layer 4 and the passivation layer 3, but not more than 90% of the thickness of the passivation layer 3.

[0125] When the extended portion of the main gate 5 is only located in the insulating layer 4, the main gate 5 does not damage the passivation layer 3, thereby ensuring the passivation effect of the passivation layer 3. Based on this, the open circuit voltage can be increased to reduce or avoid the impact on the photoelectric conversion efficiency.

[0126] When the extended portion of the main grid 5 is located in both the insulating layer 4 and the passivation layer 3, but does not exceed 90% of the thickness of the passivation layer 3, compared with the prior art where the main grid 5 passes through the passivation layer 3 and is connected to the silicon substrate, the degree of damage to the passivation layer 3 by the main grid 5 is reduced, thereby ensuring the passivation effect of the passivation layer 3. Based on this, the open circuit voltage can be increased, thereby reducing the impact on the photoelectric conversion efficiency. Furthermore, the above-mentioned main grid 5 is connected to the insulating layer 4 and the passivation layer 3 at the same time, at which time the mechanical properties of the main grid 5 can be guaranteed and the tensile properties of the main grid 5 can be improved. Based on this, the probability of the main grid 5 detaching from the solar cell can be reduced or eliminated to ensure the quality and performance of the solar cell.

[0127] As a possible implementation, see Figure 2 , the ratio of the depth of the main grid 5 extending into the passivation layer 3 to the thickness of the passivation layer 3 is greater than or equal to 20%. Exemplarily, the ratio may be 20%, 30%, 35%, 46%, 50%, etc. At this time, the main grid 5 is connected to the insulating layer 4 and the passivation layer 3 at the same time, and the mechanical properties of the main grid 5 can be guaranteed, and the tensile properties of the main grid 5 can be improved to reduce or eliminate the probability of the main grid 5 detaching from the solar cell, thereby ensuring the quality and performance of the solar cell.

[0128] In combination with the above description, after the main gate 5 extends into the passivation layer 3 , the ratio of the depth of the main gate 5 extending into the passivation layer 3 to the thickness of the passivation layer 3 is greater than or equal to 20% and less than or equal to 90%.

[0129] As a possible implementation, the main gate extends into the passivation layer to a depth of 0. That is, the main gate is only located in the insulating layer, specifically, the main gate is only located inside the insulating layer, or the main gate is located at the junction of the insulating layer and the passivation layer, or the main gate is only located on the surface of the insulating layer. In this case, the main gate can be prevented from damaging the passivation layer to ensure the passivation effect of the passivation layer. Based on this, the open circuit voltage can be increased to avoid affecting the photoelectric conversion efficiency.

[0130] As a possible implementation, when the thickness of the passivation layer is greater than or equal to 5 nm and less than or equal to 20 nm, the main gate extends into the passivation layer to a depth greater than or equal to 1 nm and less than or equal to 18 nm. For example, the main gate extends into the passivation layer to a depth of 1 nm, 5 nm, 9 nm, 13 nm, 15 nm or 18 nm.

[0131] Since the depth is greater than or equal to 1nm, it can be ensured that the main grid is connected to the insulating layer and the passivation layer at the same time. Based on this, the mechanical properties of the main grid can be guaranteed, and the tensile properties of the main grid can be improved to reduce or eliminate the probability of the main grid detaching from the solar cell, thereby ensuring the quality and performance of the solar cell. Furthermore, since the depth is less than or equal to 18nm, the degree of damage to the passivation layer by the main grid can be reduced, ensuring the passivation effect of the passivation layer, thereby increasing the open circuit voltage and reducing the impact on the photoelectric conversion efficiency.

[0132] As a possible implementation, the emitter layer includes a heavily doped region and a lightly doped region. The fine gate is connected to the heavily doped region to form an alloy region. The depth of the alloy region extending into the emitter layer is less than the junction depth of the emitter of the emitter layer, and the depth direction and the junction depth direction of the emitter are consistent with the direction toward the semiconductor substrate.

[0133] In an optional manner, when the junction depth of the emitter is greater than or equal to 300 nanometers and less than or equal to 1200 nanometers, the depth of the alloy region extending into the emitter is greater than or equal to 50 nanometers and less than or equal to 1000 nanometers. For example, the depth of the alloy region extending into the emitter can be 50 nanometers, 80 nanometers, 100 nanometers, 260 nanometers, 390 nanometers, 550 nanometers or 1000 nanometers. Since the depth is greater than or equal to 50 nanometers, the fine gate can be alloyed with the semiconductor substrate to form a better ohmic contact.

[0134] Preferably, when the junction depth of the emitter is greater than or equal to 300 nanometers and less than or equal to 1200 nanometers, the depth of the alloy region extending into the emitter is greater than or equal to 50 nanometers and less than or equal to 100 nanometers.

[0135] As a possible implementation, the thickness of the insulating layer is greater than or equal to 40 nanometers and less than or equal to 100 nanometers. For example, the thickness of the insulating layer can be 40 nanometers, 50 nanometers, 60 nanometers, 70 nanometers, 80 nanometers, 90 nanometers or 100 nanometers.

[0136] As a possible implementation, see Figure 3 Each busbar 5 includes: a busbar connection line 50 and a pad 51. A plurality of pads 51 are arranged at intervals on the busbar connection line 50 along the first direction, the width of the pad 51 is greater than the width of the busbar connection line 50, and the width direction of the pad 51 and the width direction of the busbar connection line 50 are consistent with the second direction.

[0137] When the number of main grid connection lines 50 is the same, compared with the case where the width of the main grid connection line 50 is equal to the width of the pad 51, the amount of raw materials used to make the main grid connection line 50 can be reduced while ensuring that the current collection capacity of the main grid connection line 50 meets the actual needs, saving raw material costs. At the same time, it is also possible to reduce the shielding of the semiconductor substrate 1 by the main grid connection line 50, increase the light receiving area of ​​the semiconductor substrate 1, and improve the photoelectric conversion efficiency of the solar cell. Furthermore, when the battery string is manufactured later, the welding strip needs to be connected to the pad 51. At this time, compared with the case where the width of the main grid connection line 50 is equal to the width of the pad 51, the welding strip is easier to connect to the pad 51, reducing the difficulty of manufacturing and improving the manufacturing efficiency. It should be understood that the specific structure, manufacturing material, etc. of the above-mentioned main grid connection line 50 and the pad 51 can refer to the prior art and are not specifically limited here.

[0138] In an alternative approach, see Figure 3 , the number of the main grids 5 is greater than or equal to 8 and less than or equal to 25. For example, the number of the main grids 5 may be 8, 10, 12, 15, 18, 20, 22 or 25, etc.

[0139] And / or, the width of the main grid connection line 50 is greater than or equal to 35 microns and less than or equal to 60 microns. For example, the width of the main grid connection line 50 can be 35 microns, 40 microns, 45 microns, 52 microns, 55 microns or 60 microns. The width of the pad 51 is greater than or equal to 0.6 mm and less than or equal to 1.3 mm. For example, the width of the pad 51 can be 0.6 mm, 0.8 mm, 1.0 mm, 1.16 mm, 1.23 mm or 1.3 mm.

[0140] By controlling the number of main grids 5, the width of the main grid connection line and the width of the pad, the shielding area of ​​the main grid 5 on the semiconductor substrate 1 can be controlled. At this time, the amount of light injected into the semiconductor substrate 1 can be increased, and the light receiving area of ​​the semiconductor substrate 1 can be increased to improve the cell efficiency of the solar cell.

[0141] As a possible implementation, see Figure 3 , the number of the fine grids 6 is greater than or equal to 100 and less than or equal to 200. For example, the number of the fine grids 6 can be 100, 120, 150, 180, 195 or 200. The width of the fine grid 6 is greater than or equal to 20 microns and less than or equal to 45 microns, and the width direction of the fine grid 6 is consistent with the first direction. For example, the width of the fine grid 6 can be 20 microns, 26 microns, 30 microns, 36 microns, 40 microns or 45 microns. At this time, the current collection capability of the fine grid 6 can be improved to improve the cell efficiency of the solar cell.

[0142] In a third aspect, an embodiment of the present invention further provides a battery string, which includes a plurality of welding strips and a plurality of solar cells arranged at intervals as described in the above technical solution, wherein the welding strips are connected to the main grids accordingly.

[0143] The beneficial effects of the battery string provided by the embodiment of the present invention are the same as the beneficial effects of the solar cell described in the above technical solution, and will not be described in detail here.

[0144] As a possible implementation, when the main grid includes a main grid connection line and a pad, the welding strip is arranged on the pad along the first direction and covers the main grid connection line. The maximum width of the welding strip is less than or equal to the width of the pad, and the width direction of the welding strip and the width direction of the pad are consistent with the second direction. In this case, the shielding of the semiconductor substrate by the welding strip can be reduced, the light receiving area of ​​the semiconductor substrate can be increased, and the photoelectric conversion efficiency of the solar cell can be improved.

[0145] In an optional manner, the width of the above-mentioned welding strip is less than or equal to the width of the main grid connection line, and the width direction of the welding strip and the width direction of the main grid connection line are both consistent with the second direction. In this case, the shielding of the semiconductor substrate by the welding strip can be reduced, the light receiving area of ​​the semiconductor substrate can be increased, and the photoelectric conversion efficiency of the solar cell can be improved.

[0146] In an optional manner, the ratio of the width of the solder strip to the width of the main grid connection line is greater than or equal to 50% and less than or equal to 90%. For example, the ratio may be 50%, 60%, 65%, 70%, 80% or 90%.

[0147] Since the soldering ribbon includes a core layer of metal material and a solder layer located on the outer surface of the core layer. In the actual process of soldering the soldering ribbon and the soldering pad, the solder layer melts under heat and has a certain fluidity. Since the above ratio is greater than or equal to 50% and less than or equal to 90%, the flowing solder can be distributed at the interface between the soldering ribbon and the main grid connection line, giving it sufficient flow space. At this time, the solder can be prevented from flowing onto the semiconductor substrate to avoid solder contamination and shielding the semiconductor substrate, thereby ensuring the quality and performance of the solar cell.

[0148] In the embodiment of the present invention, the number of welding strips is consistent with the number of main grid connection lines.

[0149] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0150] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for manufacturing a solar cell, characterized in that: include: Providing a semiconductor substrate; forming an emitter layer on one side of the semiconductor substrate; The semiconductor substrate and the emitter layer have opposite conductivity types, and the emitter layer and the semiconductor substrate together form a PN junction; forming a passivation layer on the emitter layer; forming an insulating layer on the passivation layer; forming a main grid on the insulating layer; The main grids extend along a first direction and are spaced apart along a second direction; the first direction is different from the second direction; forming a fine gate on the insulating layer; the fine gate extends along the second direction and is spaced apart along the first direction; each of the main gates intersects with a plurality of the fine gates; the fine gate passes through the passivation layer and the insulating layer and is connected to the emitter layer; The main gate extends toward the emitter layer, the main gate extends into the insulating layer to a depth exceeding 20% ​​of the thickness of the insulating layer, and the main gate extends into the passivation layer to a depth not exceeding 90% of the thickness of the passivation layer; the depth direction, the thickness direction of the passivation layer, and the thickness direction of the insulating layer are all consistent with the direction toward the semiconductor substrate; The thickness of the insulating layer is greater than or equal to 40 nanometers and less than or equal to 100 nanometers.

2. The method for manufacturing a solar cell according to claim 1, characterized in that: The ratio of the depth of the main gate extending into the passivation layer to the thickness of the passivation layer is greater than or equal to 20%; or, The main gate extends into the passivation layer to a depth of 0.

3. The method for manufacturing a solar cell according to claim 1, characterized in that: When the thickness of the passivation layer is greater than or equal to 5 nm and less than or equal to 20 nm, the main gate extends into the passivation layer to a depth greater than or equal to 1 nm and less than or equal to 18 nm.

4. The method for manufacturing a solar cell according to claim 1, characterized in that: Each of the main grids comprises: a main grid connection line and a welding pad; A plurality of the pads are arranged at intervals on the main grid connection line along the first direction; The width of the pad is greater than the width of the main grid connection line, and the width direction of the pad and the width direction of the main grid connection line are both consistent with the second direction.

5. The method for manufacturing a solar cell according to claim 4, characterized in that: The number of the main grids is greater than or equal to 8 and less than or equal to 25; and / or, The width of the main grid connection line is greater than or equal to 35 micrometers and less than or equal to 60 micrometers; the width of the pad is greater than or equal to 0.6 millimeters and less than or equal to 1.3 millimeters.

6. The method for manufacturing a solar cell according to claim 1, 4 or 5, characterized in that: The number of the fine grids is greater than or equal to 100 and less than or equal to 200; The width of the fine grid is greater than or equal to 20 micrometers and less than or equal to 45 micrometers; the width direction of the fine grid is consistent with the first direction.

7. The method for manufacturing a solar cell according to claim 1, characterized in that: Forming a main gate on the insulating layer comprises: Printing a main grid material on the insulating layer to form an initial main grid; Processing the initial busbar to form the busbar; The ratio of the width of the main grid to the width of the initial main grid is greater than 1 and less than or equal to 1.1; the width direction of the main grid and the width direction of the initial main grid are both consistent with the second direction.

8. The method for manufacturing a solar cell according to claim 7, characterized in that: Forming a fine gate on the insulating layer includes: Printing a fine grid material on the insulating layer to form an initial fine grid; processing the initial fine grid to form the fine grid; The ratio of the width of the fine gate to the width of the initial fine gate is greater than 1 and less than or equal to 1.2; the width direction of the fine gate and the width direction of the initial fine gate are both consistent with the first direction.

9. The method for manufacturing a solar cell according to claim 8, characterized in that: The metal solid content in the main grid material is less than the metal solid content in the fine grid material.

10. A solar cell, characterized in that: include: Semiconductor substrate; An emitter layer, located on one side of the semiconductor substrate; The semiconductor substrate and the emitter layer have opposite conductivity types, and the emitter layer and the semiconductor substrate together form a PN junction; A passivation layer, located on the emitter layer; an insulating layer, located on the passivation layer; A main grid, located on the insulating layer; The main grids extend along a first direction and are spaced apart along a second direction; the first direction is different from the second direction; A fine gate is located on the insulating layer; the fine gate extends along the second direction and is spaced apart along the first direction; each of the main gates intersects with a plurality of the fine gates; the fine gate passes through the passivation layer and the insulating layer and is connected to the emitter layer; The main gate extends toward the emitter layer, the main gate extends into the insulating layer to a depth exceeding 20% ​​of the thickness of the insulating layer, and the main gate extends into the passivation layer to a depth not exceeding 90% of the thickness of the passivation layer; the depth direction, the thickness direction of the passivation layer, and the thickness direction of the insulating layer are all consistent with the direction toward the semiconductor substrate; The thickness of the insulating layer is greater than or equal to 40 nanometers and less than or equal to 100 nanometers.

11. The solar cell according to claim 10, characterized in that The ratio of the depth of the main gate extending into the passivation layer to the thickness of the passivation layer is greater than or equal to 20%; or, The main gate extends into the passivation layer to a depth of 0.

12. The solar cell according to claim 10, characterized in that: When the thickness of the passivation layer is greater than or equal to 5 nm and less than or equal to 20 nm, the main gate extends into the passivation layer to a depth greater than or equal to 1 nm and less than or equal to 18 nm.

13. The solar cell according to claim 10, characterized in that: Each of the main grids comprises: a main grid connection line and a welding pad; A plurality of the pads are arranged at intervals on the main grid connection line along the first direction; The width of the pad is greater than the width of the main grid connection line, and the width direction of the pad and the width direction of the main grid connection line are both consistent with the second direction.

14. The solar cell according to claim 13, characterized in that: The number of the main grids is greater than or equal to 8 and less than or equal to 25; and / or, The width of the main grid connection line is greater than or equal to 35 micrometers and less than or equal to 60 micrometers; the width of the pad is greater than or equal to 0.6 millimeters and less than or equal to 1.3 millimeters.

15. The solar cell according to claim 10, 13 or 14, characterized in that: The number of the fine grids is greater than or equal to 100 and less than or equal to 200; The width of the fine grid is greater than or equal to 20 micrometers and less than or equal to 45 micrometers; the width direction of the fine grid is consistent with the first direction.

16. A battery string, characterized in that: A solar cell according to any one of claims 10 to 15 comprising a plurality of solder strips and a plurality of spaced-apart arrangements; The welding strips are correspondingly connected to the main grids.

17. The battery string according to claim 16, characterized in that: When the main grid includes a main grid connection line and a welding pad, the welding strip is arranged on the welding pad along the first direction and covers the main grid connection line; the maximum width of the welding strip is less than or equal to the width of the welding pad; the width direction of the welding strip and the width direction of the welding pad are both consistent with the second direction.

18. The battery string according to claim 17, characterized in that: The width of the welding strip is less than or equal to the width of the main grid connection line; the width direction of the welding strip and the width direction of the main grid connection line are both consistent with the second direction.

19. The battery string according to claim 17 or 18, characterized in that: The ratio of the width of the welding strip to the width of the main grid connection line is greater than or equal to 50% and less than or equal to 90%.

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