Voltage tracking circuit and electronic circuit

Abstract

A voltage tracking circuit is used to track one of a first voltage on a first voltage terminal and a second voltage on a second voltage terminal to generate an output voltage. The voltage tracking circuit includes a first and a second P-type transistor and a control circuit. A drain of the first P-type transistor is coupled to the first voltage terminal. A gate of the second P-type transistor is coupled to the first voltage terminal and a drain of the second P-type transistor is coupled to the second voltage terminal. The control circuit is coupled to the first and the second voltage terminals and generates a control voltage according to the first and the second voltages. A source of the first P-type transistor and a source of the second P-type transistor are coupled to an output terminal of the voltage tracking circuit and the output voltage is generated at the output terminal. When the second voltage is greater than the first voltage, the control circuit generates the control voltage to turn off the first P-type transistor.

Description

Technical Field

[0001] This invention relates to a voltage tracking circuit, and more particularly to a voltage tracking circuit with low power consumption. Background Technology

[0002] Generally, when an N-type metal oxide semiconductor (NMOS) is used on the high-voltage side of an electronic circuit, overvoltage may occur at its source / base, causing the parasitic bipolar diode of the NMOS transistor to conduct, resulting in leakage current. Leakage current can lead to overheating and damage to the electronic circuit. Therefore, reducing leakage current caused by overvoltage is an important issue. Summary of the Invention

[0003] In view of this, the present invention proposes a voltage tracking circuit. This voltage tracking circuit is used to track one of a first voltage at a first voltage terminal and a second voltage at a second voltage terminal to generate an output voltage. The voltage tracking circuit includes a first P-type transistor, a second P-type transistor, and a control circuit. The first P-type transistor has a gate, a drain, and a source. The drain of the first P-type transistor is coupled to the first voltage terminal. The second P-type transistor has a gate, a drain, and a source. The gate of the second P-type transistor is coupled to the first voltage terminal, and the drain of the second P-type transistor is coupled to the second voltage terminal. The control circuit is coupled to the first voltage terminal and the second voltage terminal, and generates a control voltage based on the first voltage and the second voltage. The sources of the first P-type transistor and the second P-type transistor are coupled to an output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal. When the second voltage is greater than the first voltage, the control circuit generates a control voltage to turn off the first P-type transistor.

[0004] The present invention also proposes an electronic circuit. This electronic circuit includes a high-voltage side element and a voltage tracking circuit. The high-voltage side element has a first terminal and a second terminal, and is surrounded by an isolation well region. The voltage tracking circuit is coupled to the first terminal and the second terminal to track one of a first voltage on the first terminal and a second voltage on the second terminal to generate an output voltage at an output terminal, and applies the output voltage to the isolation well region surrounding the high-voltage side element. The voltage tracking circuit includes a first P-type transistor, a second P-type transistor, and a control circuit. The first P-type transistor has a gate, a drain, and a source. The drain of the first P-type transistor is coupled to the first voltage terminal. The second P-type transistor has a gate, a drain, and a source. The gate of the second P-type transistor is coupled to the first voltage terminal, and the drain of the second P-type transistor is coupled to the second voltage terminal. The control circuit is coupled to the first voltage terminal and the second voltage terminal, and generates a control voltage based on the first voltage and the second voltage. The source of the first P-type transistor and the source of the second P-type transistor are coupled to the output of the voltage tracking circuit, and the output voltage is generated at the output terminal. When the second voltage is greater than the first voltage, the control circuit generates a control voltage to turn off the first P-type transistor. Attached Figure Description

[0005] Figure 1 This describes an electronic circuit according to an embodiment of the present invention.

[0006] Figure 2 This indicates that according to an embodiment of the present invention, Figure 1 A schematic diagram of the operation of the voltage tracking circuit under the first voltage condition.

[0007] Figure 3 This indicates that according to an embodiment of the present invention, Figure 1 A schematic diagram of the operation of the voltage tracking circuit under the second voltage condition.

[0008] Figure 4 This indicates that according to an embodiment of the present invention, Figure 1 A schematic diagram of the operation of the voltage tracking circuit under the third voltage condition.

[0009] Figure 5 This indicates that according to an embodiment of the present invention, Figures 2 to 4 The driving circuit of the voltage tracking circuit has a first architecture.

[0010] Figure 6 According to another embodiment of the present invention, Figures 2 to 4 The voltage tracking circuit's drive circuit has a second architecture.

[0011] Figure 7 According to another embodiment of the present invention, Figures 2 to 4 The voltage tracking circuit's drive circuit has a third architecture.

[0012] Figure 8 This represents another embodiment of the present invention. Figure 1 Voltage tracking circuit of electronic circuit.

[0013] Figure 9 This indicates that according to an embodiment of the present invention, Figure 8 The driving circuit of the voltage tracking circuit has a first architecture.

[0014] Figure 10 According to another embodiment of the present invention, Figure 8 The voltage tracking circuit's drive circuit has a second architecture.

[0015] Figure 11 According to another embodiment of the present invention, Figure 8 The voltage tracking circuit's drive circuit has a third architecture.

[0016] Figure 12 express Figure 1 A cross-sectional view of the NMOS transistor on the medium-to-high voltage side.

[0017] Explanation of reference numerals in the attached figures:

[0018] 1: Electronic circuits

[0019] 10: Voltage Tracking Circuit

[0020] 11, 12: NMOS transistors

[0021] 13: Input / output pads

[0022] 14: Inductor

[0023] 20: Control Circuit

[0024] 21: Drive Circuit

[0025] 22-24: PMOS transistors

[0026] 51~53, 61~63: PMOS transistors

[0027] 71-73: Diodes

[0028] 80: PMOS transistor

[0029] 125: P-type well area

[0030] 126: N-type well area

[0031] 127: N-type doped region

[0032] 128: P-type doped region

[0033] 129: P-type well area

[0034] DW10, DW11: Type N isolation deep well zone

[0035] GND: Ground terminal

[0036] N10: Node

[0037] N20A, N20B, N21A: Input nodes

[0038] N20C, N21B: Output nodes

[0039] N50, N51, N60, N61, N70, N71: Nodes

[0040] NBL: N-type embedded layer

[0041] P22, P23: Current path

[0042] SUB: P-type substrate

[0043] T10A, T10B: Voltage terminals

[0044] T10C: Output terminal

[0045] T11A, T12A, T22A, T23A, T24A, T51A, T52A, T53A, T61A, T62A, T63A, T80A: Gate

[0046] T11B, T12B, T22B, T23B, T24B, T51B, T52B, T53B, T61B, T62B, T63B, T80B: Drain electrode

[0047] T11C, T12C, T22C, T23C, T24C, T51C, T52C, T53C, T61C, T62C, T63C, T80C: Source Electrode

[0048] T11D, T12D, T22D, T23D, T24D, T51D, T52D, T53D, T61D, T62D, T63D, T80D: Base

[0049] V20: Control voltage

[0050] V21: Drive voltage

[0051] VD: Voltage

[0052] VTH: Output voltage

[0053] VS / B: Voltage Detailed Implementation

[0054] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, a preferred embodiment is described below in detail with reference to the accompanying drawings.

[0055] Figure 1 This illustrates an electronic circuit according to an embodiment of the present invention. (See also...) Figure 1 The electronic circuit 1 includes a voltage tracking circuit 10, an N-type metal oxide semiconductor (NMOS) transistor 11 located on the high-voltage side (i.e., as a high-voltage side element), an NMOS transistor 12 located on the low-voltage side (i.e., as a low-voltage side element), an input / output pad (PAD) 13, and an inductor 14. In this embodiment, NMOS transistors 11 and 12 are N-type laterally diffused metal oxide semiconductor (LDMOS) transistors, and each is surrounded by an N-type isolation deep well region. For example, see [reference needed]. Figure 1 The symbol “DW10” represents the N-type isolation deep well region surrounding LDNMOS transistor 11, while the symbol “DW11” represents the N-type isolation deep well region surrounding LDNMOS transistor 12.

[0056] like Figure 1 As shown, LDNMOS transistor 11 includes four terminals T11A to T11D, namely gate T11A, drain T11B, source T11C, and base (bulk) T11D. Gate T11A receives signals generated from other components in electronic circuit 1. Drain T11B is coupled to the voltage terminal T10A of voltage tracking circuit 10. Source T11C and base T11D are coupled to each other at node N10. Voltage terminal T10B of voltage tracking circuit 10 is coupled to node N10, that is, coupled to source T11C and base T11D (source / base T111C / T112D). LDNMOS transistor 12 includes four terminals T12A to T12D, namely gate T12A, drain T12B, source T12C, and base T12D. Gate T12A receives signals generated from other components in electronic circuit 1. The drain T12B is coupled to node N10. The source T12C and base T12D are both coupled to ground GND. Inductor 14 is coupled between node N10 and output input pad 13.

[0057] See Figure 1The voltage tracking circuit 10 has its voltage terminal T10A coupled to the drain T11B of the LDNMOS transistor 11, and its voltage terminal T10B coupled to the source T11C and base T11D of the LDNMOS transistor 11. When the electronic circuit 1 operates, the voltage tracking circuit 10 generates an output voltage VTH at its output terminal T10C based on the higher of the voltages VD at the drain T11B and VS / B at the source T11C and base T11D. In other words, the voltage tracking circuit 10 tracks the higher of voltages VD and VS / B and makes the output voltage VTH equal to the tracked higher voltage. Therefore, it can be seen that the voltage tracking circuit 10 can change the output voltage VTH according to voltages VD and VS / B.

[0058] The output voltage VTH is supplied from the voltage tracking circuit 10 to the N-type isolated deep well region DW10 surrounding the LDNMOS transistor 11. In some cases, when an overvoltage event occurs at the input / output pad 13, the voltage VS / B increases above the voltage VD through conduction via the inductor 14. According to an embodiment of the invention, the output voltage VTH increases with the voltage VS / B through the operation of the voltage tracking circuit 10. The increase in the output voltage VTH can turn off the parasitic bipolar transistor associated with the N-type isolated deep well region DW10, or can reduce the conduction efficiency of the parasitic bipolar transistor associated with the N-type isolated deep well region DW10, thereby avoiding or reducing leakage current. According to the above, by controlling the output voltage VTH applied to the N-type isolated deep well region DW10 through the voltage tracking circuit 10, the situation where high temperatures caused by leakage current damage the electronic components in the electronic circuit 1 can be avoided.

[0059] The following will describe various embodiments and operations of the voltage tracking circuit 10.

[0060] See Figures 2 to 4 This is a schematic diagram illustrating the operation of a voltage tracking circuit under different voltage conditions according to an embodiment of the present invention. The following will explain... Figure 2 This will illustrate the circuit architecture of the voltage tracking circuit 10. See [reference needed]. Figure 2The voltage tracking circuit 10 includes a control circuit 20, a drive circuit 21, and P-type metal-oxide-semiconductor (N-type metal oxide-semiconductor) transistors 22 and 23. PMOS transistor 22 has four terminals T22A to T22D, namely the gate T22A, drain T22B, source T22C, and base T22D. The drain T22B is coupled to the voltage terminal T10A, and its source T22C and base T22D are coupled to the output terminal T10C. The drive circuit 21 has an input node N21A and an output node N21B. The input node N21A is coupled to the voltage terminal T10A, and the output node N21B is coupled to the gate T22A of PMOS transistor 22. PMOS transistor 23 includes four terminals T23A to T23D, namely the gate T23A, drain T23B, source T23C, and base T23D. The gate T23A is coupled to the voltage terminal T10A, its drain T23B is coupled to the voltage terminal T10B, and its source T23C and base T23D are coupled to the output terminal T10C.

[0061] The control circuit 20 has input nodes N20A and N20B and an output node N20C. Input node N20A is coupled to voltage terminal T20A, input node N20B is coupled to voltage terminal T10B, and output node N20C is coupled to the gate T22A of PMOS transistor 22. In this embodiment, the control circuit 20 includes a PMOS transistor 24. The PMOS transistor 24 includes four terminals T24A to T24D, which are the gate T24A, drain T24B, source T24C, and base T24D, respectively. The gate T24A is coupled to input node N20A, its drain T24B is coupled to input node N20B, and its source T24C and base T24D are coupled to output node N20C.

[0062] See Figure 2 When electronic circuit 1 operates, voltage tracking circuit 10 receives voltage VD through power supply terminal T10A and voltage VS / B through power supply terminal T10B. Figure 2In an embodiment, the voltage VS / B is equal to the voltage VD (VS / B = VD). For example, both the voltage VD and the voltage VS / B are 44V. At this time, the PMOS transistor 23 is turned off. The driving circuit 21 provides an adjustment voltage. When the driving circuit 21 receives the voltage VD through the input node N21A, it performs a buck operation to reduce the voltage VD through this adjustment voltage to generate the driving voltage V21 at the output node N21B. In other words, the driving circuit 21 generates the driving voltage V21 according to the voltage VD, and the driving voltage V21 is less than the voltage VD (V21 < VD). For example, the adjustment voltage is 2.1V, and the driving voltage V21 is 41.9V. At this time, the voltage of the gate T22A of the PMOS transistor 22 is equal to the driving voltage V21. Since the driving voltage V21 is less than the voltage VD, the PMOS transistor 22 is turned on to provide a current path P22 between the voltage terminal T10A and the output terminal T10C. Through the current path P22 of the PMOS transistor 22, the output voltage VTH on the output terminal T10C follows the voltage VD and increases, and finally equals the voltage VD (VTH = VD = 44V).

[0063] In addition, when the voltage VS / B is equal to the voltage VD (VS / B = VD), the control circuit 20 blocks the current path between the input node N20B and the output node N20C according to the voltage VD. Specifically, the PMOS transistor 24 is turned off according to the voltage VD, so that there is no current path between the drain T24B and the source T24C. In this way, the driving voltage V21 can be stably maintained at a level of, for example, 41.9V, so that the on-state of the PMOS transistor 22 is not affected by the voltage VS / B.

[0064] Refer to Figure 3 , in some cases, the voltage VS / B is less than the voltage VD (VS / B < VD). For example, the voltage VD is 44V, and the voltage VS / B is 0V. At this time, the PMOS transistor 23 is turned off. The driving circuit 21 performs a buck operation to reduce the voltage VD through the adjustment voltage (for example, 2.1V) to generate the driving voltage V21 at the output node N21B. The driving voltage V21 is less than the voltage VD (V21 < VD). For example, the driving voltage V21 is 41.9V. At this time, the voltage of the gate T22A of the PMOS transistor 22 is equal to the driving voltage V21. Since the driving voltage V21 is less than the voltage VD, the PMOS transistor 22 is turned on to provide the current path P22. Through the current path P22, the output voltage VTH on the output terminal T10C follows the voltage VD and increases, and finally equals the voltage VD (VTH = VD = 44V).

[0065] In addition, when the voltage VS / B is less than the voltage VD (VS / B < VD), the control circuit 20 blocks the current path between the input node N20B and the output node N20C according to the voltage VD. Specifically, the PMOS transistor 24 is turned off according to the voltage VD, so that there is no current path between the drain T24B and the source T24C. In this way, the driving voltage V21 can be stably maintained at a level of, for example, 41.9V, so that the on-state of the PMOS transistor 22 is not affected by the voltage VS / B.

[0066] Refer to Figure 4 , in some cases, the voltage VS / B is greater than the voltage VD (VS / B > VD). For example, the voltage VD is 44V, and the voltage VS / B is 46.5V. At this time, the PMOS transistor 23 is turned on to provide a current path P23 between the voltage terminal T10B and the output terminal T10C. Through the current path P23, the output voltage VTH on the output terminal T10C follows the voltage VS / B and increases, and finally equals the voltage VS / B (VTH = VS / B = 46.5).

[0067] In addition, when the voltage VS / B is greater than the voltage VD (VS / B > VD), the control circuit 20 provides a current path between the input node N20B and the output node N20C according to the voltage VD. The control circuit 20 thus provides a control voltage V20, and the control voltage V20 is equal to the voltage VS / B (46.5V). Specifically, the PMOS transistor 24 is turned on according to the voltage VD, and there is a current path between the drain T24B and the source T24C, so that the control voltage V20 is equal to the voltage VS / B (V = VS / B > VD). At this time, although the driving circuit 21 also performs the above-mentioned step-down operation, since the control circuit 20 provides a larger control voltage V20 of 46.5V, the PMOS transistor 22 is in the off state in this case. In other words, the control circuit 20 turns off the PMOS transistor 22. Based on the off state of the PMOS transistor 22, even if the output voltage VTH (46.5V) is greater than the voltage VD (44V), no leakage current from the output terminal T10C to the voltage terminal T10A will occur. Through the off operation of the PMOS transistor by the control circuit 20, the output voltage VTH can finally be stably maintained equal to the voltage VS / B, that is, stably maintained at 46.5V.

[0068] As described above, the voltage tracking circuit 10 generates an output voltage VTH at the output terminal T10C based on the higher of voltages VD and VS / B. In this way, the output voltage VTH follows the higher of VD and VS / B. Through the operation of the control circuit 20, the output voltage VTH can be stably maintained at the higher of VD and VS / B. Furthermore, when VS / B is greater than VD (VS / B>VD), the control circuit 20 blocks the leakage current path from the output terminal T10C to the voltage terminal T10A, which reduces the power consumption of the electronic circuit 1.

[0069] The driving circuit 21 in this invention includes multiple step-down components connected in series between the input node N21A and the output node N21B, thereby achieving step-down operation. There are various implementations of the step-down components. The following will explain... Figures 5 to 7 This will illustrate the detailed architecture of the drive circuit 21.

[0070] Figure 5 This illustrates a voltage tracking circuit 10 according to an embodiment of the present invention, wherein the driving circuit 21 has a first architecture. (See also...) Figure 5 The driving circuit 21 includes PMOS transistors (step-down devices) 51-53 connected in series between the input node N21A and the output node N21B. The actual number can be adjusted according to the actual needs of voltage regulation, and the present invention is not limited thereto. PMOS transistor 51 has four terminals T51A-T51D, namely gate T51A, drain T51B, source T51C, and base T51D. Drain T51B is coupled to input node N21A. Source T51C and base T51D are coupled to node N50. PMOS transistor 52 has four terminals T52A-T52D, namely gate T52A, drain T52B, source T52C, and base T52D. Drain T52B is coupled to node N50. Source T52C and base T52D are coupled to node N51. PMOS transistor 43 has four terminals T53A to T53D, namely gate T53A, drain T53B, source T53C, and base T53D. Drain T53B is coupled to node N51. Source T53C and base T53D are coupled to output node N21B. The gates T51A, T52A, and T53A of PMOS transistors 51 to 53 are all coupled to output terminal T10C.

[0071] For example, when electronic circuit 1 operates, voltage tracking circuit 10 receives voltage VD through power supply terminal T10A, for example, 44V, but this invention is not limited thereto. At this time, PMOS transistors 51-53 are in the off state. Since parasitic diodes exist in PMOS transistors 51-53, each of PMOS transistors 51-53 has a voltage difference of 0.7V between its drain and source. Therefore, the voltage difference between input node N21A and output node N21B of drive circuit 21 is 2.1V (0.7V x 3 = 2.1V). The voltage difference (2.1V) between input node N21A and output node N21B serves as the adjustment voltage provided by drive circuit 21. At this time, the drive voltage V21 on output node N21B is 41.9V (44V - 2.1V = 41.9V), thereby realizing a step-down operation, that is, reducing voltage VD by adjusting the voltage to generate drive voltage V21 at output node N21B. In this embodiment, the output voltage VTH at the output terminal T10C follows the higher of the voltage VD and the voltage VS / B. Therefore, the gates T51A, T52A, and T53A of PMOS transistors 51-53 have higher voltages, which enables PMOS transistors 51-53 to stably maintain the off state.

[0072] Figure 6 This illustrates a voltage tracking circuit 10 according to another embodiment of the present invention, wherein the second architecture of the drive circuit 21 is shown. See also... Figure 6 The driving circuit 21 includes PMOS transistors (step-down devices) 61-63 connected in series between the input node N21A and the output node N21B. The actual number can be adjusted according to the actual needs of voltage regulation, and the present invention is not limited thereto. PMOS transistor 61 has four terminals T61A-T61B, namely gate T61A, drain T61B, source T61C, and base T61D. Drain T61B is coupled to input node N21A. Gate T61A, source T61C, and base T61D are coupled to node N60. PMOS transistor 62 has four terminals T62A-T62B, namely gate T62A, drain T62B, source T62C, and base T62D. Drain T62B is coupled to node N60. Gate T62A, source T62C, and base T62D are coupled to node N61. PMOS transistor 63 has four terminals T63A to T63D, namely gate T63A, drain T63B, source T63C, and base T63D. Drain T63B is coupled to node N61. Gate T63A, source T63C, and base T63D are coupled to output node N21B.

[0073] For example, when electronic circuit 1 operates, voltage tracking circuit 10 receives voltage VD through power supply terminal T10A, for example, 44V, but this invention is not limited thereto. At this time, PMOS transistors 61-63 are in the off state. Due to the presence of parasitic diodes in PMOS transistors 61-63, each of PMOS transistors 61-63 has a voltage difference of 0.7V between its drain and source. Therefore, the voltage difference between input node N21A and output node N21B of drive circuit 21 is 2.1V (0.7V x 3 = 2.1V). The voltage difference (2.1V) between input node N21A and output node N21B serves as the adjustment voltage provided by drive circuit 21. At this time, the drive voltage V21 at output node N21B is 41.9V (44V - 2.1V = 41.9V), thereby achieving a step-down operation, that is, reducing voltage VD by adjusting the voltage to generate drive voltage V21 at output node N21B.

[0074] Figure 7 This illustrates a voltage tracking circuit 10 according to another embodiment of the present invention, wherein the driving circuit 21 has a third architecture. (See also...) Figure 7 The driving circuit 21 includes diodes (step-down elements) 71 to 73 connected in series between the input node N21A and the output node N21B. The actual number can be adjusted according to the actual needs for voltage regulation, and the present invention is not limited thereto. The anode of diode 71 is coupled to the input node N21A, and its cathode is coupled to node N70. The anode of diode 72 is coupled to node N70, and its cathode is coupled to node N71. The anode of diode 73 is coupled to node N71, and its cathode is coupled to the output node N21B.

[0075] For example, when electronic circuit 1 operates, voltage tracking circuit 10 receives voltage VD through power supply terminal T10A, for example, 44V, though this invention is not limited thereto. At this time, each of diodes 71-73 provides a 0.7V voltage across its anode and cathode. Therefore, the voltage difference between input node N21A and output node N21B of drive circuit 21 is 2.1V (0.7V x 3 = 2.1V). This voltage difference (2.1V) between input node N21A and output node N21B serves as the regulating voltage provided by drive circuit 21. At this time, the drive voltage V21 at output node N21B is 41.9V (44V - 2.1V = 41.9V), thereby achieving a step-down operation, i.e., reducing voltage VD by regulating the voltage to generate drive voltage V21 at output node N21.

[0076] Figures 5 to 7 The operation of the voltage tracking circuit shown is as described above; please refer to [link / reference]. Figures 2 to 4 The relevant explanation is omitted here.

[0077] In some embodiments, in the voltage tracking circuit 10, in addition to the PMOS transistor 23 being coupled between the voltage terminal T10B and the output terminal T10C, there is another PMOS transistor connected in series with the PMOS transistor 23 between the voltage terminal T10B and the output terminal T10C.

[0078] Refer to Figure 8 , the PMOS transistor 80 is connected in series with the PMOS transistor 23 between the voltage terminal T10B and the output terminal T10C. The PMOS transistor 80 has four electrode terminals T80A to T80D, namely the gate T80A, the drain T80B, the source T80C, and the base T80D. The gate T80A is coupled to the voltage terminal T10A. The drain T80B is coupled to the voltage terminal T10B. The source T80C and the base T80D are coupled to the output terminal T10C. In Figure 8 's embodiments, since the two PMOS transistors 80 and 23 are connected in series between the voltage terminal T10B and the output terminal T10C, only when both the PMOS transistors 80 and 23 are in the on state, a current path between the voltage terminal T10B and the output terminal T10C will be provided, such as Figure 4 the current path P23 shown. In this way, when the voltage VS / B is less than the voltage VD (VS / B < VD) or equal to the voltage VD (VS / B = VD), the current path between the voltage terminal T10B and the output terminal T10C can be effectively blocked, so that the output voltage VTH on the output terminal T10C can accurately follow the voltage VD and is not affected by the voltage VS / B.

[0079] Therefore, in Figures 3 to 5 each example of the driving circuit 21 shown, the PMOS transistors 80 and 23 are connected in series between the voltage terminal T10B and the output terminal T10C, respectively as shown in Figures 9 to 11 . Figures 9 to 11 The operation of the voltage tracking circuit shown is as described above. Please refer to Figures 2 to 4 for the description.

[0080] Figure 12 Represents Figure 1 the structural cross-sectional view of the NMOS transistor 11 on the high-voltage side in. Refer to Figure 12An NMOS transistor 11 is formed on a P-type substrate SUB. An N-type buried layer NBL and a P-type well region 129 are formed within the P-type substrate SUB. An N-type isolation deep well region DW10 is formed on the N-type buried layer NBL and within the P-type well region 129. A P-type well region 125 is formed within the N-type isolation deep well region DW10. An N-type well region 126 is formed within the P-type well region 125 to serve as the drain region of the NMOS transistor 11. A contact electrode electrically connected to the N-type well region 126 serves as the drain T11B. An N-type doped region 127 is formed within the P-type well region 125 to serve as the source region of the NMOS transistor 11. A P-type doped region 128 is formed within the P-type well region 125 to serve as the base region of the NMOS transistor 11. Contact electrodes electrically connected to the N-type doped region 107 and the P-type doped region 108 serve as the source T11C and the base T11D, respectively. Since the source T11C and the base T11D are connected to each other... Figure 12 Only a single contact electrode is shown. A gate dielectric layer and a gate layer are formed on the P-type well region 125, and the contact electrode electrically connected to the gate layer serves as the gate T11A.

[0081] according to Figure 12 The architecture contains several parasitic bipolar transistors, including a parasitic NPN bipolar transistor LNPN formed between the N-type isolation deep well region DW10, the P-type well region 125, and the N-type well region 126; a parasitic PNP bipolar transistor LPNP formed between the P-type well region 125, the N-type isolation deep well region DW10, and the P-type well region 129; a parasitic NPN bipolar transistor VNPN formed between the N-type well region 126, the P-type well region 125, and the N-type buried layer NBL; and a parasitic PNP bipolar transistor VPNP formed between the P-type well region 125, the N-type buried layer NBL, and the P-type substrate SUB.

[0082] like Figure 12As shown, the N-type isolated deep well region DW10 is not connected to the drain T11B. The voltage of the N-type isolated deep well region DW10 is independent of the voltage of the drain T11B. According to the operation of the voltage tracking circuit 10, the output voltage VTH generated by it is the higher of the voltage VD and the voltage VS / B. By applying the output voltage VTH to the N-type isolated deep well region DW10, parasitic bipolar transistors are prevented from turning on. For example, parasitic bipolar transistors include NPN bipolar transistors LNPN, parasitic PNP bipolar transistors LPNP, parasitic NPN bipolar transistors VNPN, or parasitic PNP bipolar transistors VPNP, but the present invention is not limited thereto. In one embodiment, none of the above parasitic bipolar transistors are turned on. For example, when the voltage VS / B is greater than the voltage VD, since the voltage tracking circuit 10 generates an output voltage VTH equal to the voltage VS / B, the voltage of the N-type isolated deep well region DW10 is close to or equal to the voltage of the N-type buried layer NBL. Therefore, the parasitic NPN bipolar transistor VNPN and the parasitic PNP bipolar transistor VPNP are not turned on, reducing the leakage current through the substrate.

[0083] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A voltage tracking circuit, characterized in that, The voltage tracking circuit, used to track one of a first voltage at a first voltage terminal and a second voltage at a second voltage terminal to generate an output voltage, includes: A first P-type transistor has a gate, a drain, and a source; wherein the drain of the first P-type transistor is coupled to the first voltage terminal; A second P-type transistor has a gate, a drain, and a source; wherein the gate of the second P-type transistor is coupled to the first voltage terminal, and the drain of the second P-type transistor is coupled to the second voltage terminal; and A control circuit is coupled to the first voltage terminal and the second voltage terminal, and generates a control voltage based on the first voltage and the second voltage. Wherein, the source of the first P-type transistor and the source of the second P-type transistor are coupled to an output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal; and When the second voltage is greater than the first voltage, the control circuit generates the control voltage to turn off the first P-type transistor.

2. The voltage tracking circuit as described in claim 1, characterized in that, When the second voltage is greater than the first voltage, the second P-type transistor is turned on, and the output voltage is equal to the second voltage.

3. The voltage tracking circuit as described in claim 1, characterized in that, The control circuit includes: A third P-type transistor has a gate, a drain, and a source, wherein the gate of the third P-type transistor is coupled to a first voltage terminal, the drain of the third P-type transistor is coupled to a second voltage terminal, and the source of the third P-type transistor is coupled to the gate of the first P-type transistor.

4. The voltage tracking circuit as described in claim 1, characterized in that, Also includes: A driving circuit is coupled between the first voltage terminal and the gate of the first P-type transistor, and generates a driving voltage according to the first voltage; wherein the driving circuit provides the driving voltage to the gate of the first P-type transistor.

5. The voltage tracking circuit as described in claim 4, characterized in that, When the first voltage is greater than or equal to the second voltage, the driving circuit turns on the first P-type transistor through the driving voltage, and the output voltage is equal to the first voltage.

6. The voltage tracking circuit as described in claim 4, characterized in that, The driving circuit provides an adjustable voltage and uses the adjustable voltage to reduce the first voltage to generate the driving voltage.

7. The voltage tracking circuit as described in claim 4, characterized in that, The driving circuit includes: An input node is coupled to the first voltage terminal to receive the first voltage; An output node, coupled to the gate of the first P-type transistor; and Multiple step-down components are connected in series between the input node and the output node.

8. The voltage tracking circuit as described in claim 7, characterized in that, The plurality of step-down components include: A third P-type transistor has a drain coupled to the input node, a source coupled to a first node, and a gate; A fourth P-type transistor has a drain coupled to the first node, a source coupled to a second node, and a gate; and A fifth P-type transistor has a drain coupled to the second node, a source coupled to the output node, and a gate; The gates of the third P-type transistor, the fourth P-type transistor, and the fifth P-type transistor are all coupled to the output terminal of the voltage tracking circuit.

9. The voltage tracking circuit as described in claim 8, characterized in that, The control circuit includes: A sixth P-type transistor has a gate, a drain, and a source; wherein the gate of the sixth P-type transistor is coupled to a first voltage terminal, the drain of the sixth P-type transistor is coupled to a second voltage terminal, and the source of the sixth P-type transistor is coupled to the gate of the first P-type transistor.

10. The voltage tracking circuit as described in claim 7, characterized in that, The plurality of step-down components include: A third P-type transistor has a drain coupled to the input node and a gate and a source coupled to a first node; A fourth P-type transistor has a drain coupled to the first node, and a gate and a source coupled to a second node; and A fifth P-type transistor has a drain coupled to the second node and a gate and a source coupled to the output node.

11. The voltage tracking circuit as described in claim 10, characterized in that, The control circuit includes: A sixth P-type transistor has a gate, a drain, and a source; wherein the gate of the sixth P-type transistor is coupled to a first voltage terminal, the drain of the sixth P-type transistor is coupled to a second voltage terminal, and the source of the sixth P-type transistor is coupled to the gate of the first P-type transistor.

12. The voltage tracking circuit as described in claim 7, characterized in that, The plurality of step-down components include: A first diode has an anode coupled to the input node and a cathode coupled to a first node; A second diode having an anode coupled to the first node and a cathode coupled to a second node; and A third diode has an anode coupled to the second node and a cathode coupled to the output node.

13. The voltage tracking circuit as described in claim 12, characterized in that, The control circuit includes: A third P-type transistor has a gate, a drain, and a source; wherein the gate of the third P-type transistor is coupled to a first voltage terminal, the drain of the third P-type transistor is coupled to a second voltage terminal, and the source of the third P-type transistor is coupled to the gate of the first P-type transistor.

14. The voltage tracking circuit as described in claim 1, characterized in that, Also includes: A third P-type transistor has a gate, a drain, and a source; wherein the gate of the third P-type transistor is coupled to a first voltage terminal, the drain of the third P-type transistor is coupled to a second voltage terminal of the voltage tracking circuit, and the source of the third P-type transistor is coupled to the drain of a second P-type transistor.

15. The voltage tracking circuit as described in claim 1, characterized in that, When the voltage tracking circuit is in operation, the first voltage is maintained at a fixed value, while the second voltage is a variable voltage.

16. The voltage tracking circuit as described in claim 1, characterized in that, The output voltage is applied to an isolated deep well area surrounding a high-voltage side element.

17. An electronic circuit, characterized in that, include: A high-voltage side element has a first electrode and a second electrode, and is surrounded by an isolated deep well zone; as well as A voltage tracking circuit, coupled to the first terminal and the second terminal, is used to track one of a first voltage on the first terminal and a second voltage on the second terminal to generate an output voltage at an output terminal and to apply the output voltage to the isolation deep well region surrounding the high-voltage side element. The voltage tracking circuit includes: A first P-type transistor has a gate, a drain, and a source; wherein the drain of the first P-type transistor is coupled to the first terminal. A second P-type transistor has a gate, a drain, and a source; wherein the gate of the second P-type transistor is coupled to the first terminal, and the drain of the second P-type transistor is coupled to the second terminal; and A control circuit, coupled to the first terminal and the second terminal, generates a control voltage based on the first voltage and the second voltage; and Wherein, the source of the first P-type transistor and the source of the second P-type transistor are coupled to the output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal; and When the second voltage is greater than the first voltage, the control circuit generates the control voltage to turn off the first P-type transistor.

18. The electronic circuit as described in claim 17, characterized in that, When the second voltage is greater than the first voltage, the second P-type transistor is turned on, and the output voltage is equal to the second voltage.

19. The electronic circuit as described in claim 17, characterized in that, The control circuit includes: A third P-type transistor has a gate, a drain, and a source; The gate of the third P-type transistor is coupled to the first terminal, the drain of the third P-type transistor is coupled to the second terminal, and the source of the third P-type transistor is coupled to the gate of the first P-type transistor.

20. The electronic circuit as described in claim 17, characterized in that, Also includes: A driving circuit is coupled between the first electrode and the gate of the first P-type transistor, and provides a regulating voltage; A driving voltage is generated based on the first voltage; The driving circuit uses the adjusted voltage to reduce the first voltage to generate the driving voltage, and provides the driving voltage to the gate of the first P-type transistor.

21. The electronic circuit as described in claim 20, characterized in that, The driving circuit includes: An input node is coupled to the first electrode to receive the first voltage; An output node, coupled to the gate of the first P-type transistor; and Multiple step-down components are connected in series between the input node and the output node, and provide the regulated voltage.

22. The electronic circuit as described in claim 20, characterized in that, When the first voltage is greater than or equal to the second voltage, the driving circuit conducts a current path of the first P-type transistor through the driving voltage, and the output voltage is equal to the first voltage.

23. The electronic circuit as described in claim 17, characterized in that, Also includes: A third P-type transistor has a gate, a drain, and a source; wherein the gate of the third P-type transistor is coupled to the first terminal, the drain of the third P-type transistor is coupled to the second terminal, and the source of the third P-type transistor is coupled to the drain of the second P-type transistor.

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