Display panel

Abstract

The present application provides a display panel, comprising: a reset signal line; a clock signal line; a plurality of scan signal lines; and a plurality of cascaded gate driving units, including a first type of gate driving unit. The first type of gate driving unit includes: a redundant input unit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal and the second input terminal of the redundant input unit are in a floating state; a first type of output unit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the first type of output unit is connected to the output terminal of the redundant input unit and the reset signal line, the second input terminal of the first type of output unit is connected to the reset signal line and is disconnected from the clock signal line, and the output terminal of the first type of output unit is connected to one of the scan signal lines.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display panel. Background Art

[0002] For a display panel with a gate driving circuit disposed on an array substrate, when a large-sized display panel needs to be re-cut to prepare a small-sized display panel, there may be a problem that the small-sized display panel after cutting cannot display.

[0003] Therefore, a technical solution is needed to solve the problem that the small-sized display panel after cutting cannot display. Summary of the Invention

[0004] The purpose of this application is to provide a display panel to ensure that the display panel can display normally.

[0005] In a first aspect, this application provides a display panel, including:

[0006] A reset signal line;

[0007] A clock signal line;

[0008] Multiple scan signal lines; and

[0009] Multiple cascaded gate driving units, including a first type of gate driving unit, and the first type of gate driving unit includes:

[0010] A redundant input unit, having a first input terminal, a second input terminal, and an output terminal, and the first input terminal and the second input terminal of the redundant input unit are in a floating state;

[0011] A first type of output unit, having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the first type of output unit is connected to the output terminal of the redundant input unit and the reset signal line, the second input terminal of the first type of output unit is connected to the reset signal line and is disconnected from the clock signal line, and the output terminal of the first type of output unit is connected to one of the scan signal lines.

[0012] In some embodiments, the multiple cascaded gate driving units further include a second type of gate driving unit, and the second type of gate driving unit includes:

[0013] An input unit for outputting a driving signal;

[0014] The second type of output unit has a first input end, a second input end and an output end, the first input end of the second type of output unit is connected to the output end of the input unit, the second input end of the second type of output unit is connected to the clock signal line, and the output end of the second type of output unit is connected to one of the scanning signal lines.

[0015] In some embodiments, the display panel further includes a constant voltage signal line;

[0016] The first type of gate driving unit further includes: a redundant reset unit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the redundant reset unit is connected to the reset signal line, the output terminal of the redundant reset unit is connected to the output terminal of the redundant input unit and the first input terminal of the first type of output unit, and the second input terminal of the redundant reset unit is disconnected from the constant voltage signal line;

[0017] The second type of gate driving unit also includes: a reset unit having a first input terminal, a second input terminal and an output terminal, the first input terminal of the reset unit is connected to the reset signal line, the second input terminal of the reset unit is connected to the constant voltage signal line, and the output terminal of the reset unit is connected to the first input terminal of the second type of output unit and the output terminal of the input unit.

[0018] In some embodiments, the display panel further includes: a first connecting line connected between the constant voltage signal line and the redundant reset unit, and including a first break.

[0019] In some embodiments, the display panel further includes: a second connecting line connected between the clock signal line and the first type output unit, and including a second break.

[0020] In some embodiments, the second connection line is connected to the reset signal line through a first via hole, and the second connection line connects the first type output unit and the reset signal line, and the first via hole and the second break are spaced apart.

[0021] In some embodiments, the display panel further comprises:

[0022] substrate;

[0023] A first conductive layer, disposed on the substrate and including the reset signal line;

[0024] a second conductive layer, disposed on a side of the first conductive layer away from the substrate, and comprising the second connecting line, wherein the second fracture is staggered with a conductive portion of the first conductive layer;

[0025] An insulating layer is disposed between the first conductive layer and the second conductive layer, and includes the first via hole. A positive projection of the first via hole on the substrate overlaps with a positive projection of the reset signal line on the substrate.

[0026] In some embodiments, the second conductive layer further includes:

[0027] A third connection line connects the first input end of the first type of output unit to the reset signal line and is connected to the reset signal line through a second via hole on the insulating layer. The second via hole is spaced apart from the first via hole.

[0028] In some embodiments, the display panel further includes:

[0029] Multiple data lines;

[0030] A source driver circuit is connected to the multiple data lines and is disposed on one side of the display panel;

[0031] Wherein, the first type of gate driver unit is located on a side of the second type of gate driver unit away from the source driver circuit.

[0032] In some embodiments, the display panel further includes:

[0033] A start signal line is disconnected from the first type of gate driver unit.

[0034] Beneficial effects of some embodiments of the present application include: The present application provides a display panel. For the first type of gate driver unit, when the first input end and the second input end of the redundant input unit are in a floating state, the first input end of the first type of output unit, the output end of the redundant input unit, and the reset signal line are connected. Furthermore, the potential of the first input end of the first type of output unit is pulled up by the reset signal transmitted through the reset signal line. Moreover, the second input end of the first type of output unit is connected to the reset signal line and is disconnected from the clock signal line, and the output end of the first type of output unit is connected to a scan signal line. In this way, under the control of the reset signal at the first input end, the reset signal input at the second input end is output as a scan signal to the scan signal line, ensuring that the first type of gate driver unit normally outputs a scan signal, and further ensuring that the display panel can be normally displayed. Description of the Drawings

[0035] Figure 1 It is a schematic structural diagram of an initial display panel in some related technologies;

[0036] Figure 2 It is a schematic plan view of the display panel according to some embodiments of the present application;

[0037] Figure 3Schematic diagram of the first type of gate driving unit according to some embodiments of the present application;

[0038] Figure 4 Schematic diagram of the second type of gate driving unit according to some embodiments of the present application;

[0039] Figure 5 Partial enlarged schematic diagram of the non-display area according to some embodiments of the present application;

[0040] Figure 6 is along Figure 5 Schematic cross-sectional structure taken along the tangent line A-A' in Detailed implementation manners

[0041] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0042] Please refer to Figure 1 as shown, which is a schematic diagram of the structure of an initial display panel in some related technologies. The initial display panel 100 is a large-size display panel. For example, the resolution of the initial display panel is 1920×1080, but it is not limited thereto. The initial display panel 100 includes, but is not limited to, any one of a liquid crystal display panel, an organic light-emitting diode display panel, and a quantum dot display panel.

[0043] The initial display panel 100 includes an initial display area 100a and an initial non-display area 100b, and the initial non-display area 100b is disposed around the initial display area 100a. The initial display panel 100 further includes a source driving circuit 11, a gate driving circuit 12, a plurality of data lines 13, and a plurality of scanning signal lines 14. The plurality of data lines 13 intersect with the plurality of scanning signal lines 14. The plurality of data lines 13 are connected to the source driving circuit 11. The plurality of scanning signal lines 14 are connected to the gate driving circuit 12.

[0044] The gate driving circuit 12 is located on at least one side of the initial display area 100a. For example, the gate driving circuit 12 is located on one side of the initial display area 100a, but it is not limited thereto. It can be understood that the gate driving circuit 12 can also be located on opposite sides of the initial display area 100a.

[0045] The gate driving circuit 12 includes a plurality of cascaded gate driving units 121. For example, the plurality of cascaded gate driving units 121 include a first-stage gate driving unit GOA(1) to an nth-stage gate driving unit GOA(n), where n is 1080, but not limited thereto. The first-stage gate driving unit GOA(1) to the nth-stage gate driving unit GOA(n) are arranged in sequence along the extending direction of the data line 13. The first-stage gate driving unit GOA(1) is disposed away from the source driving circuit 11, and the nth-stage gate driving unit GOA(n) is disposed close to the source driving circuit 11.

[0046] The plurality of cascaded gate driving units 121 are all connected to the reset signal line 15. The first-stage gate driving unit GOA(1) to the mth-stage gate driving unit GOA(m) (not shown) in the plurality of cascaded gate driving units 121 are all connected to the start signal line 16, where m is an integer greater than or equal to 1 and less than n. The (m + 1)th-stage gate driving unit GOA(m + 1) to the nth-stage gate driving unit GOA(n) in the plurality of cascaded gate driving units 121 are respectively connected to a plurality of clock signal lines 17. For example, m is equal to 4, but not limited thereto.

[0047] When the initial display panel 100 needs to be cut into smaller-sized display panels, it can be cut along Figure 1 the cutting line A - A' as shown. After cutting off the panel portion including the first-stage gate driving unit GOA(1), the cut display panel is obtained. For example, the resolution of the cut display panel is 1920×540 or 1920×810.

[0048] For the cut display panel, the cut gate driving circuit 12 includes an ith-stage gate driving unit GOA(i) to an nth-stage gate driving unit GOA(n), where i is an integer greater than m and less than n. After cutting, since the ith-stage gate driving unit GOA(i) is not connected to the start signal line 16, the ith-stage gate driving unit GOA(i) cannot output a scan signal and the corresponding stage transmission signal. Therefore, the gate driving circuit 12 of the cut display panel cannot normally output a scan signal, resulting in the cut display panel being unable to display normally.

[0049] In view of the problems in the related art, the inventive concept of the present application includes that the reset signal transmitted by the reset signal line and the start signal transmitted by the start signal line have the same frequency and the same potential characteristics, and the reset signal line is connected to each stage of the gate driving unit of the gate driving circuit. Therefore, the reset signal transmitted by the reset signal line can be used to replace the start signal. Moreover, the high-level signal of the reset signal can also be used as the driving signal of the pull-up node.

[0050] The specific solution of this application includes that for the first type of gate driving units of the display panel after cutting and processing, that is, the first few gate driving units of the gate driving circuit in the scanning direction, when the first input terminal and the second input terminal of the redundant input unit are in a floating state, the first input terminal of the first type of output unit is connected to the output terminal of the redundant input unit and the reset signal line. In this way, the potential of the first input terminal of the first type of output unit can be pulled up by the reset signal transmitted through the reset signal line, and the conduction and shutdown of the first type of output unit can be controlled. Moreover, the second input terminal of the first type of output unit is connected to the reset signal line and disconnected from the clock signal line, that is, the reset signal transmitted through the reset signal line is used to replace the start signal. In this way, under the control of the reset signal at the first input terminal, the reset signal input at the second input terminal is output as a scanning signal to the scanning signal line, ensuring that the first type of gate driving unit normally outputs a scanning signal, and further ensuring that the display panel can be normally displayed.

[0051] The display panel of some embodiments of this application will be described in detail below in conjunction with specific embodiments.

[0052] Refer to Figure 2 As shown, it is a schematic plan view of the display panel of some embodiments of this application. The display panel 200 is obtained through cutting and subsequent processing. The display panel 200 includes a display area 200a and a non-display area 200b disposed around the display area 200a. The display panel 200 includes a source driving circuit 21, a gate driving circuit 22, a plurality of data lines 23, and a plurality of scanning signal lines 24.

[0053] At least a part of each of the plurality of data lines 23 is disposed in the display area 200a. The plurality of data lines 23 extend along the second direction y1 and are arranged at intervals along the first direction x. The plurality of data lines 23 are connected to the source driving circuit 21. The source driving circuit 21 may be located on the first side of the display area 200a in the second direction y1. The first direction x intersects the second direction y1. Specifically, the first direction x is perpendicular to the second direction y1, but is not limited thereto.

[0054] At least a part of each of the plurality of scanning signal lines 24 is disposed in the display area 200a. The plurality of scanning signal lines 24 extend along the first direction x and are arranged at intervals along the second direction y1. The plurality of scanning signal lines 24 are all connected to the gate driving circuit 22. The gate driving circuit 22 may be located on the second side of the display area 200a in the first direction x, and the second side is adjacent to the first side, but is not limited thereto. It can be understood that the gate driving circuit 22 may also be located on the second side and the third side of the display area 200a in the first direction x, and both the second side and the third side are adjacent to the first side.

[0055] As Figure 2As shown, the gate driving circuit 22 includes a plurality of gate driving units 221. The plurality of gate driving units 221 includes a first-stage gate driving unit GOA(1) to a j-stage gate driving unit GOA(j), where j is an integer greater than 1. The first-stage gate driving unit GOA(1) to the j-stage gate driving unit GOA(j) are arranged in sequence along the second direction y1. The first-stage gate driving unit GOA(1) is disposed away from the source driving circuit 21, and the j-stage gate driving unit GOA(j) is disposed close to the source driving circuit 21.

[0056] When the display panel 200 is displaying, the first-stage gate driving unit GOA(1) to the j-stage gate driving unit GOA(j) output scan signals in sequence, that is, when the display panel 200 is displaying, it scans along the second direction y1, which is a reverse scan. In this way, when the plurality of data lines 23 transmit data signals to the proximal end of the data line closer to the source driving circuit 21 and the distal end of the data line farther from the source driving circuit 21 respectively, the loads tend to be uniform, which is beneficial to improving the display effect of the display panel 200.

[0057] Please continue to refer to Figure 2 As shown, the plurality of gate driving units 221 includes a first type of gate driving unit 222 and a second type of gate driving unit 223. The first type of gate driving unit 222 is located on the side of the second type of gate driving unit 223 away from the source driving circuit 21. In this way, the distance between the first type of gate driving unit 222 and the source driving circuit 21 is relatively far. The first type of gate driving unit 222 is a gate driving unit that has been processed after cutting, and the second type of gate driving unit 223 is a gate driving unit that has not been processed after cutting.

[0058] Among them, the plurality of first type of gate driving units 222 may include one or more adjacent gate driving units 221 disposed away from the source driving circuit 21. All the gate driving units 221 of the plurality of gate driving units 221 except the plurality of first type of gate driving units 222 are the second type of gate driving units 223. For example, the first type of gate driving unit 222 includes the first-stage gate driving unit GOA(1), and the second type of gate driving unit 223 includes the j-stage gate driving unit GOA(j), but it is not limited thereto.

[0059] In the present application, the display panel 200 further includes a start signal line 25, a constant voltage signal line 28, a reset signal line 26, and a plurality of clock signal lines 27. One start signal line 25, one reset signal line 26, a plurality of clock signal lines 27, and the constant voltage signal line 28 are located on a side of the gate driving circuit 22 away from the display area 200a. The start signal line 25 is used to transmit a start signal. The reset signal line 26 is used to transmit a reset signal Reset. The plurality of clock signal lines 27 are used to transmit a clock signal CK. The constant voltage signal line 28 is used to transmit a constant voltage signal VSS.

[0060] The display panel 200 is obtained through cutting and subsequent processing. Before cutting, the first several levels of gate driving units in the scanning direction are all connected to the start signal line 25. After cutting, the first several levels of gate driving units connected to the start signal line 25 are all cut off, and neither the first type of gate driving units 222 nor the second type of gate driving units 223 of the gate driving circuit 22 on the display panel 200 are connected to the start signal line 25.

[0061] Refer to Figure 3 As shown, it is a circuit schematic diagram of the first type of gate driving unit in some embodiments of the present application. Hereinafter, the first-level gate driving unit GOA(1) in the first type of gate driving units 222 will be described. The other levels in the first type of gate driving units 222 can be analogized in this way and will not be elaborated here. The first type of gate driving units 222 includes a redundant input unit 2221, a first type of output unit 2222, a redundant reset unit 2223, a first type of pull-down maintenance unit 2224, a first type of pull-down unit 2225, a first type of stage transmission unit 2226, and a first type of bootstrap capacitor 2227.

[0062] The redundant input unit 2221 has a first input terminal, a second input terminal, and an output terminal. Before cutting, the first input terminal and the second input terminal of the redundant input unit 2221 can be connected to the previous-stage gate driving unit to respectively receive the previous-stage stage transmission signal and the previous-stage scanning signal. After cutting, the previous-stage gate driving units connected to the first input terminal and the second input terminal of the redundant input unit 2221 are cut off.

[0063] Therefore, both the first input terminal and the second input terminal of the redundant input unit 2221 are in a floating state, that is, no signal is connected to the first input terminal and the second input terminal of the redundant input unit 2221.

[0064] Specifically, the redundant input unit 2221 includes a first transistor T11, and the gate of the first transistor T11 is in a floating state. One of the source and the drain of the first transistor T11 is also in a floating state, and the other of the source and the drain of the first transistor T11 is connected to the first input terminal of the first type of output unit 2222.

[0065] The first type of output unit 2222 has a first input terminal, a second input terminal, and an output terminal. The output terminal of the first type of output unit 2222 is connected to a scan signal line 24.

[0066] The first input terminal of the first type of output unit 2222 is connected to the output terminal of the redundant input unit 2221 and a reset signal line 26. The first pull-up node Q1 (such as the first pull-up node Q(1)) of the first type of output unit 2222 is located on the connection line between the first input terminal of the first type of output unit 2222 and the output terminal of the redundant input unit 2221. The first pull-up node Q1 is connected to the reset signal line 26, and the reset signal Reset transmitted by the reset signal line 26 can be directly output to the first pull-up node Q1.

[0067] When the two input terminals of the redundant input unit 2221 are in a floating state and cannot output a pull-up control signal to the first pull-up node Q1, the reset signal Reset transmitted by the reset signal line 26 can control the potential of the first input terminal of the first type of output unit 2222 and the first pull-up node Q, and further control the conduction and cut-off of the first type of output unit 2222.

[0068] The second input terminal of the first type of output unit 2222 is connected to the reset signal line 26 and is disconnected from the clock signal line 27. In this application, based on the characteristics that the reset signal Reset transmitted by the reset signal line 26 and the start signal transmitted by the start signal line are of the same frequency and the same potential, when the second input terminal of the first type of output unit 2222 is disconnected from the clock signal line 27, the reset signal Reset transmitted by the reset signal line 26 is used to replace the start signal as the input signal of the first type of output unit 2222 to ensure the output of the first type of output unit 2222.

[0069] It should be noted that before cutting, the second input terminal of the first type of output unit 2222 is connected to the clock signal line 27. After cutting and subsequent processing, the second input terminal of the first type of output unit 2222 of the display panel 200 is connected to the reset signal line 26 while the clock signal line 27 is disconnected.

[0070] It can be seen that for the first type of output unit 2222 of the first type of gate driving unit 222, under the control of the reset signal Reset at the first input terminal, the reset signal Reset input at the second input terminal is output as a scan signal to the scan signal line 24, ensuring that the first type of gate driving unit 222 normally outputs a scan signal, and further ensuring that the display panel 200 can be normally displayed.

[0071] Specifically, the first type of output unit 2222 includes a second transistor T21. The gate of the second transistor T21 is connected to the other of the source and drain of the first transistor T11 and the reset signal line 26. One of the source and drain of the second transistor T21 is connected to the reset signal line 26 and is set to be disconnected from the clock signal line 27. The other of the source and drain of the second transistor T21 is connected to a scan signal line 24.

[0072] The first type of stage transfer unit 2226 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first type of stage transfer unit 2226 is connected to the output terminal of the redundant input unit 2221 and the reset signal line 26. The second input terminal of the first type of stage transfer unit 2226 is connected to the reset signal line 26 and is set to be disconnected from the clock signal line 27. Therefore, for the first type of stage transfer unit 2226 of the first type of gate driving unit 222, under the control of the reset signal Reset at the first input terminal, the reset signal Reset input at the second input terminal is output as the stage transfer signal of this stage (e.g., ST(1)) through the output terminal of the first type of stage transfer unit 2226 to control the output of other stage gate driving units 221.

[0073] Specifically, the first type of stage transfer unit 2226 includes a third transistor T22. The gate of the third transistor T22 is connected to the other of the source and drain of the first transistor T11 and the reset signal line 26. One of the source and drain of the third transistor T22 is connected to the reset signal line 26 and is set to be disconnected from the clock signal line 27. The other of the source and drain of the third transistor T22 outputs the stage transfer signal of this stage.

[0074] The two plates of the first type of bootstrap capacitor C are respectively connected to the first type of pull-up node Q1 and the output terminal of the first type of output unit 2222.

[0075] The redundant reset unit 2223 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the redundant reset unit 2223 is connected to the reset signal line 26. The output terminal of the redundant reset unit 2223 is connected to the output terminal of the redundant input unit 2221 and the first input terminal of the first type of output unit 2222. The second input terminal of the redundant reset unit 2223 is disconnected from the constant voltage signal line 28. In this way, when the reset signal line 26 outputs the reset signal Reset to the first type of pull-up node Q1, the redundant reset unit 2223 is disconnected from the constant voltage signal line 28, preventing the redundant reset unit 2223 from conducting and outputting the constant voltage signal VSS transmitted by the constant voltage signal line 28 to the first type of pull-up node Q1 and affecting the potential of the first type of pull-up node Q1. Moreover, the redundant reset unit 2223 being disconnected from the constant voltage signal line 28 can also improve the problem of leakage current through the redundant reset unit 2223 when the reset signal line 26 outputs the reset signal Reset to the first type of pull-up node Q1.

[0076] Specifically, the redundant reset unit 2223 includes a fourth transistor T71. The gate of the fourth transistor T71 is connected to the reset signal line 26. One of the source and drain of the fourth transistor T71 is disconnected from the constant voltage signal line 28. The other of the source and drain of the fourth transistor T71 is connected to the output terminal of the redundant input unit 2221 and the first input terminal of the first type of output unit 2222. At this time, the other of the source and drain of the fourth transistor T71 is connected to the first type of pull-up node Q1. The constant voltage signal VSS can be a low-level signal, but is not limited thereto.

[0077] The first type of pull-down unit 2225 is used to pull down the potential of the first type of pull-up node Q1. The first type of pull-down unit 2225 is also used to pull down the potential of the scan signal (such as G(1)) output by the first type of output unit 2222 to the constant voltage signal VSS. The first type of pull-down unit 2225 has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal of the first type of pull-down unit 2225 is connected to the constant voltage signal line 28 to receive the constant voltage signal VSS. The second input terminal of the first type of pull-down unit 2225 receives the next-level scan signal (such as G(1+X)), where X is an integer greater than or equal to 1. The first output terminal of the first type of pull-down unit 2225 is connected to the first type of pull-up node Q1. The second output terminal of the first type of pull-down unit 2225 is connected to the output terminal of the first type of output unit 2222, that is, the second output terminal of the first type of pull-down unit 2225 is connected to a scan signal line 24.

[0078] The first type of pull-down unit 2225 includes a fifth transistor T31 and a sixth transistor T41. The gates of the fifth transistor T31 and the sixth transistor T41 both receive the lower-level scan signal G(1 + X). One of the source and drain of the fifth transistor T31 and one of the source and drain of the sixth transistor T41 both receive the constant voltage signal VSS transmitted by the constant voltage signal line 28. The other of the source and drain of the fifth transistor T31 is connected to the output terminal of the first type of output unit 2222. The other of the source and drain of the sixth transistor T41 is connected to the first type of pull-up node Q1.

[0079] The first type of pull-down maintenance unit 2224 includes a first pull-down maintenance unit and a second pull-down maintenance unit. During the display process of the display panel 200, the first pull-down maintenance unit and the second pull-down maintenance unit work alternately to extend the service life of the gate driving circuit 22, and thus extend the service life of the display panel 200.

[0080] The first pull-down maintenance unit includes a first inverter 224 and a first pull-down voltage stabilizing unit 225. The first inverter 224 includes a seventh transistor T51, an eighth transistor T52, a ninth transistor T53, and a tenth transistor T54. The first pull-down voltage stabilizing unit 225 includes an eleventh transistor T32 and a twelfth transistor T42.

[0081] The gate of the seventh transistor T51 and one of the source and drain of the seventh transistor T51 receive the first control signal LC1.

[0082] The gate of the eighth transistor T52 is connected to the first type of pull-up node Q1. One of the source and drain of the eighth transistor T52 receives the constant voltage signal VSS. The other of the source and drain of the eighth transistor T52 is connected to the other of the source and drain of the seventh transistor T51.

[0083] The gate of the ninth transistor T53 is connected to the other of the source and drain of the eighth transistor T52 and the other of the source and drain of the seventh transistor T51. One of the source and drain of the ninth transistor T53 receives the first control signal LC1. The other of the source and drain of the ninth transistor T53 is connected to the gates of the eleventh transistor T32 and the twelfth transistor T42.

[0084] The gate of the tenth transistor T54 is connected to the first type of pull-up node Q1. One of the source and drain of the tenth transistor T54 receives the constant voltage signal VSS. The other of the source and drain of the tenth transistor T54 is connected to the gates of the eleventh transistor T32 and the twelfth transistor T42.

[0085] One of the source and drain of the eleventh transistor T32 receives a constant voltage signal VSS. The other of the source and drain of the eleventh transistor T32 is connected to the output terminal of the first type of output unit 2222. The pull-down maintenance unit including the eleventh transistor T32 is used to pull down the potential of the scan signal to the constant voltage signal VSS during the pull-down maintenance phase.

[0086] One of the source and drain of the twelfth transistor T42 receives a constant voltage signal VSS. The other of the source and drain of the twelfth transistor T42 is connected to the first type of pull-up node Q1. The pull-down maintenance unit including the twelfth transistor T42 is used to pull down the potential of the first type of pull-up node Q1 to the constant voltage signal VSS during the pull-down maintenance phase.

[0087] The second pull-down maintenance unit includes a second inverter 227 and a second pull-down voltage stabilizing unit 226. The second inverter 227 includes a thirteenth transistor T61, a fourteenth transistor T62, a fifteenth transistor T63, and a sixteenth transistor T64. The second pull-down voltage stabilizing unit 226 includes a seventeenth transistor T33 and an eighteenth transistor T43.

[0088] The gate of the thirteenth transistor T61 and one of the source and drain of the thirteenth transistor T61 receive a second control signal LC2.

[0089] Wherein, the phase of the second control signal LC2 is opposite to the phase of the first control signal LC1, and the phase of the second control signal LC2 and the phase of the first control signal LC1 change periodically and alternately. For example, in frames 1 to 100, one of the second control signal LC2 and the first control signal LC1 is a high-level signal, and the other of the second control signal LC2 and the first control signal LC1 is a low-level signal; in frames 101 to 200, one of the second control signal LC2 and the first control signal LC1 is a low-level signal, and the other of the second control signal LC2 and the first control signal LC1 is a high-level signal.

[0090] The gate of the fourteenth transistor T62 is connected to the first type of pull-up node Q1. One of the source and drain of the fourteenth transistor T62 receives a constant voltage signal VSS. The other of the source and drain of the fourteenth transistor T62 is connected to the other of the source and drain of the thirteenth transistor T61.

[0091] The gate of the fifteenth transistor T63 is connected to the other one of the source and drain of the fourteenth transistor T62 and the other one of the source and drain of the thirteenth transistor T61. One of the source and drain of the fifteenth transistor T63 receives the second control signal LC2. The other one of the source and drain of the fifteenth transistor T63 is connected to the gates of the seventeenth transistor T33 and the eighteenth transistor T43.

[0092] The gate of the sixteenth transistor T64 is connected to the first type of pull-up node Q1. One of the source and drain of the sixteenth transistor T64 receives the constant voltage signal VSS. The other one of the source and drain of the sixteenth transistor T64 is connected to the gates of the seventeenth transistor T33 and the eighteenth transistor T43.

[0093] One of the source and drain of the seventeenth transistor T33 receives the constant voltage signal VSS. The other one of the source and drain of the seventeenth transistor T33 is connected to the output terminal of the first type of output unit 2222. Therefore, the pull-down maintenance unit including the seventeenth transistor T33 is used to pull down the potential of the scan signal to the constant voltage signal VSS during the pull-down maintenance phase.

[0094] One of the source and drain of the eighteenth transistor T43 receives the constant voltage signal VSS. The other one of the source and drain of the eighteenth transistor T43 is connected to the first type of pull-up node Q1. Therefore, the pull-down maintenance unit including the eighteenth transistor T43 is used to pull down the potential of the first type of pull-up node Q1 to the constant voltage signal VSS during the pull-down maintenance phase.

[0095] In some embodiments, the first transistor T11 to the eighteenth transistor T43 may all be N-type transistors, but are not limited thereto. The first transistor T11 to the eighteenth transistor T43 may also all be P-type transistors.

[0096] As Figure 4 shown, it is a circuit schematic diagram of the second type of gate driving unit according to some embodiments of the present application. Taking the Nth-stage gate driving unit in the second type of gate driving unit 223 as an example for illustration, the circuits of other stages in the second type of gate driving unit 223 can be analogized accordingly, which will not be elaborated here. N is an integer greater than 1 and less than or equal to j. The design of the second type of gate driving unit 223 is basically similar to the design of the first type of gate driving unit 222. The same parts will not be elaborated. The differences include that the second type of gate driving unit 223 further includes an input unit 2231, a second type of output unit 2232, a reset unit 2233, and a second type of stage transmission unit 2234.

[0097] The input unit 2231 is configured to output a driving signal to the second type of pull-up node Q2 (such as Q(N)). The second type of pull-up node Q2 is located on the connection line between the input unit 2231 and the second type of output unit 2232. The input unit 2231 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the input unit 2231 receives the upper-level transfer signal ST(N-X). The second input terminal of the input unit 2231 receives the upper-level scan signal G(N-X). The output terminal of the input unit 2231 is connected to the second type of pull-up node Q2.

[0098] Specifically, the input unit 2231 includes a transistor T11’. The gate of the transistor T11’ receives the upper-level transfer signal ST(N-X). One of the source and the drain of the transistor T11’ receives the upper-level scan signal G(N-X). The other of the source and the drain of the transistor T11’ is connected to the second type of pull-up node Q2.

[0099] The second type of output unit 2232 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second type of output unit 2232 is connected to the output terminal of the input unit 2231. The second input terminal 2232 of the second type of output unit 2232 is connected to the clock signal line 27 to receive the clock signal CK transmitted by the clock signal line 27. The output terminal of the second type of output unit 2232 is connected to a scan signal line 24.

[0100] Specifically, the second type of output unit 2232 includes a transistor T21’. The gate of the transistor T21’ is connected to the second type of pull-up node Q2. One of the source and the drain of the transistor T21’ is connected to the clock signal line 27 to receive the clock signal CK. The other of the source and the drain of the transistor T21’ is connected to a scan signal line 24.

[0101] The reset unit 2233 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the reset unit 2233 is connected to the reset signal line 26. The second input terminal of the reset unit 2233 is connected to the constant voltage signal line 28 to receive the constant voltage signal VSS. The output terminal of the reset unit 2233 is connected to the second type of pull-up node Q2. With such an arrangement, the reset unit 2233 can reset the potential of the second type of pull-up node Q2 to the constant voltage signal VSS during the reset period.

[0102] Specifically, the reset unit 2233 includes a transistor T71’. The gate of the transistor T71’ is connected to the reset signal line 26 to receive the reset signal Reset. One of the source and the drain of the transistor T71’ receives the constant voltage signal VSS. The other of the source and the drain of the transistor T71’ is connected to the second type of pull-up node Q2.

[0103] The first input terminal of the second - type stage transmission unit 2234 is connected to the second - type pull - up node Q2. The second input terminal of the second - type stage transmission unit 2234 is connected to the clock signal line 27 to receive the clock signal CK. The output terminal of the second - type stage transmission unit 2234 outputs the stage transmission signal of this stage (such as ST(N)).

[0104] Specifically, the second - type stage transmission unit 2234 includes a transistor T22'. The gate of the transistor T22' is connected to the second - type pull - up node Q2. One of the source and drain of the transistor T22' is connected to the clock signal line 27 to receive the clock signal CK. The other of the source and drain of the transistor T22' outputs the stage transmission signal of this stage.

[0105] In addition, for Figure 4 the connection relationships of the transistors T51', T52', T53', T54', T61', T62', T63', T64', T31', T32', T33', T41', T42', T43' and the second - type bootstrap capacitor C' in

[0106] Refer to Figure 5 , which is a partial enlarged schematic diagram of the non - display area in some embodiments of the present application.

[0107] The display panel 200 further includes a first connection line 31 and a constant - voltage signal line 28 located in the non - display area 200b. The first connection line 31 is connected between the constant - voltage signal line 28 and the redundant reset unit 2223, and includes a first break 311. The first connection line 31 is disconnected at the position where the first break 311 is located. In this way, the constant - voltage signal line 28 and the redundant reset unit 2223 are disconnected.

[0108] In some embodiments, the first break 311 can be obtained by processing the first connection line 31 through a laser ablation process.

[0109] The display panel 200 further includes a second connection line 32 located in the non - display area 200b. The second connection line 32 is connected between the clock signal line 27 and the first - type output unit 2222, and includes a second break 321. The second connection line 32 is disconnected at the position where the second break 321 is located. In this way, the clock signal line 27 and the second input terminal of the first - type output unit 2222 are disconnected.

[0110] In some embodiments, the second connection line 32 is also connected to the first type of stage transmission unit 2226, and the second break 321 is provided to disconnect the first type of stage transmission unit 2226 from the clock signal line 27. Therefore, through the design of the second break 321, the connections between the first type of output unit 2222 and the first type of stage transmission unit 2226 and the clock signal line 27 can be disconnected simultaneously.

[0111] In some embodiments, the second break 321 is obtained by processing the second connection line 32 through laser ablation. The second break 321 is spaced apart from the first break 311.

[0112] In some embodiments, the second connection line 32 is connected to the reset signal line 26 through the first via V1, and the second connection line 32 connects the first type of output unit 2222 and the reset signal line 26. The first via V1 is spaced apart from the second break 321. With such a setting, the second connection line 32 connects the second input terminal of the first type of output unit 2222 and the reset signal line 26, and also connects the second input terminal of the first type of stage transmission unit 2226 and the reset signal line 26.

[0113] In some embodiments, the display panel 200 further includes a third connection line 33. The third connection line 33 connects the first input terminal of the first type of output unit 2222 and the reset signal line 26.

[0114] In some embodiments, the second connection line 32, the first connection line 31, and the third connection line 33 are located in the same conductive layer and are spaced apart from each other.

[0115] In some embodiments, as Figure 6 shown, the display panel 200 includes a substrate 41, an insulating layer 42, a first conductive layer 43, and a second conductive layer 44. The insulating layer 42, the first conductive layer 43, and the second conductive layer 44 are all disposed on the substrate 41. The first conductive layer 43 is disposed on the substrate 41. The insulating layer 42 is located on the side of the first conductive layer 43 away from the substrate 41. The second conductive layer 44 is located on the side of the insulating layer 42 away from the first conductive layer 43.

[0116] Specifically, the first conductive layer 43 is disposed on the substrate 41. The first conductive layer 43 is a gate metal layer, that is, the first conductive layer 43 includes a gate. The first conductive layer 43 further includes a reset signal line 26. The second conductive layer 44 is disposed on a side of the first conductive layer 43 away from the substrate 41. The second conductive layer 44 is a source-drain metal layer, and the second conductive layer 44 includes source-drain electrodes, a first connection line 31, a second connection line 32, and a third connection line 33. The insulating layer 42 is disposed between the first conductive layer 43 and the second conductive layer 44. The insulating layer 42 may include an interlayer insulating layer. The insulating layer 42 includes a first via V1 and a second via V2 that are spaced apart. The orthographic projections of the first via V1 and the second via V2 on the substrate 41 overlap with the orthographic projection of the reset signal line 26 on the substrate 41. With such a setting, the second connection line 32 is connected to the reset signal line 26 through the first via V1, and further the reset signal line 26 is connected to the first input end of the first type of output unit 2222. At the same time, the third connection line 33 is connected to the reset signal line 26 through the second via V2 on the insulating layer 42, and further the third connection line 33 connects the first input end of the first type of output unit 2222 and the reset signal line 26.

[0117] In some embodiments, when the second conductive layer 44 includes the first connection line 31 and the second connection line 32, the first break 311 and the second break 321 are staggered from the conductive portion of the first conductive layer 43. In this way, when the first connection line 31 and the second connection line 32 are laser ablated to form the first break 311 and the second break 321 respectively, the problem of short circuit between the second connection line 32 and the conductive layer below the second break 321 and the problem of short circuit between the first connection line 31 and the conductive layer below the first break 311 are improved.

[0118] The descriptions of the above embodiments are only used to help understand the technical solutions and their core ideas of the present application; those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that, include: Reset signal line; Clock signal line; Multiple scanning signal lines; as well as A plurality of cascaded gate driving units include a first type of gate driving unit, wherein the first type of gate driving unit includes: A redundant input unit, comprising a first input terminal, a second input terminal and an output terminal, wherein the first input terminal and the second input terminal of the redundant input unit are in a floating state; The first type of output unit has a first input end, a second input end and an output end, the first input end of the first type of output unit is connected to the output end of the redundant input unit and the reset signal line, the second input end of the first type of output unit is connected to the reset signal line and disconnected from the clock signal line, and the output end of the first type of output unit is connected to one of the scan signal lines.

2. The display panel according to claim 1, wherein The plurality of cascaded gate driving units further include a second type of gate driving unit, and the second type of gate driving unit includes: An input unit, used for outputting a driving signal; The second type of output unit has a first input end, a second input end and an output end, the first input end of the second type of output unit is connected to the output end of the input unit, the second input end of the second type of output unit is connected to the clock signal line, and the output end of the second type of output unit is connected to one of the scanning signal lines.

3. The display panel according to claim 2, wherein The display panel also includes a constant voltage signal line; The first type of gate driving unit further includes: a redundant reset unit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the redundant reset unit is connected to the reset signal line, the output terminal of the redundant reset unit is connected to the output terminal of the redundant input unit and the first input terminal of the first type of output unit, and the second input terminal of the redundant reset unit is disconnected from the constant voltage signal line; The second type of gate driving unit also includes: a reset unit having a first input terminal, a second input terminal and an output terminal, the first input terminal of the reset unit is connected to the reset signal line, the second input terminal of the reset unit is connected to the constant voltage signal line, and the output terminal of the reset unit is connected to the first input terminal of the second type of output unit and the output terminal of the input unit.

4. The display panel according to claim 3, wherein, The display panel further includes: The first connecting line is connected between the constant voltage signal line and the redundant reset unit and includes a first break.

5. The display panel according to claim 1, wherein The display panel further includes: The second connecting line is connected between the clock signal line and the first type output unit and includes a second break.

6. The display panel according to claim 5, characterized in that, The second connection line is connected to the reset signal line through a first via hole, and the second connection line connects the first type output unit and the reset signal line, and the first via hole and the second break are spaced apart.

7. The display panel according to claim 6, wherein The display panel further includes: substrate; A first conductive layer, disposed on the substrate and including the reset signal line; a second conductive layer, disposed on a side of the first conductive layer away from the substrate, and comprising the second connecting line, wherein the second break is staggered with a conductive portion of the first conductive layer; An insulating layer is disposed between the first conductive layer and the second conductive layer, and includes the first via hole, and a positive projection of the first via hole on the substrate overlaps with a positive projection of the reset signal line on the substrate.

8. The display panel according to claim 7, wherein The second conductive layer further includes: A third connection line connecting the first input end of the first type of output unit to the reset signal line and connected to the reset signal line through a second via hole in the insulating layer, and the second via hole is spaced apart from the first via hole.

9. The display panel according to claim 2, wherein, The display panel further includes: A plurality of data lines; A source driver circuit connected to the plurality of data lines and disposed on one side of the display panel; Wherein, the first type of gate driving unit is located on a side of the second type of gate driving unit away from the source driver circuit.

10. The display panel according to claim 1, characterized in that, The display panel further includes: A start signal line, which is disconnected from the first type of gate driving unit.

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