Pixel compensation circuit and driving method thereof, display panel

Abstract

The application discloses a pixel compensation circuit, a driving method thereof and a display panel. The pixel compensation circuit comprises a driving transistor, a data writing module, a first initialization module, a second initialization module, a storage capacitor and a light emitting device. The driving timing of the pixel compensation circuit comprises a threshold voltage compensation stage. In the threshold voltage compensation stage, the detection threshold voltage of the driving transistor is less than the actual threshold voltage of the driving transistor. The application can greatly improve the threshold voltage compensation range of the driving transistor and improve the display uniformity of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a pixel compensation circuit and its driving method, and a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) displays are gradually becoming the high-end displays that replace LCDs due to their advantages such as ultra-high contrast, wide color gamut, fast response, and active emission. In existing pixel driving circuits, current-driven methods are commonly used to drive the light-emitting devices. However, current-driven methods are quite sensitive to electrical variations in the driving transistors; shifts in the threshold voltage of the driving transistors can affect the brightness uniformity of the displayed image.

[0003] Currently, pixel compensation circuits have been developed in the industry to detect and compensate for the threshold voltage of the driving transistor, ensuring display uniformity. However, when evaluating and simulating the pixel compensation circuit for large-size OLED displays, the threshold voltage compensation range of the driving transistor was found to be only ±0.3V. This clearly demonstrates insufficient compensation capability when the threshold voltage drift of the driving transistor is large. Summary of the Invention

[0004] This application provides a pixel compensation circuit and its driving method, as well as a display panel, to solve the technical problem of insufficient threshold voltage compensation range in the prior art.

[0005] In a first aspect, this application provides a pixel compensation circuit, comprising:

[0006] A driving transistor, wherein the gate of the driving transistor is connected to a first node, the drain of the driving transistor is connected to a first power supply terminal, and the source of the driving transistor is connected to a second node.

[0007] A data writing module is connected to a first control signal line, a data line, and a first node, and transmits the data signal transmitted by the data line to the first node in response to a first control signal transmitted by the first control signal line.

[0008] A first initialization module is connected to a second control signal line, a first trace, and a second node, and in response to a second control signal transmitted by the second control signal line, transmits a first initialization signal transmitted by the first trace to the second node;

[0009] The second initialization module is connected to the third control signal line, the second trace, and the first node, and in response to the third control signal transmitted by the third control signal line, transmits the second initialization signal transmitted by the second trace to the first node;

[0010] Storage capacitor, wherein the two plates of the storage capacitor are respectively connected to the first node and the second node; and

[0011] A light-emitting device, one end of which is connected to the first power supply terminal and the other end of which is connected to the second power supply terminal;

[0012] The driving timing of the pixel compensation circuit includes a threshold voltage compensation stage, in which the detection threshold voltage of the driving transistor is less than the actual threshold voltage of the driving transistor.

[0013] Optionally, in some embodiments of this application, during the threshold voltage detection stage, the detection threshold voltage of the driving transistor is determined by the pulse width of the third control signal.

[0014] Optionally, in some embodiments of this application, the threshold voltage compensation range of the pixel compensation circuit is different when the pulse width of the third control signal is different.

[0015] Optionally, in some embodiments of this application, the threshold voltage compensation range of the pixel compensation circuit is -0.85V to 1.45V.

[0016] Optionally, in some embodiments of this application, the threshold voltage compensation stage includes a first compensation stage and a second compensation stage, wherein the third control signal in the first compensation stage and the third control signal in the second compensation stage are out of phase.

[0017] Secondly, this application provides a method for driving a pixel compensation circuit, used to drive the pixel compensation circuit as described in any of the above claims, the method for driving the pixel compensation circuit includes:

[0018] Initialize the potentials of the second node and the first node;

[0019] The pulse width of the third control signal is determined such that, during the threshold voltage compensation phase, the detection threshold voltage of the driving transistor is less than the actual threshold voltage of the driving transistor.

[0020] Driven by the corresponding data signal, the light-emitting device is driven to emit light.

[0021] Optionally, in some embodiments of this application, the step of determining the pulse width of the third control signal includes:

[0022] Multiple third control signals are set, and the pulse widths of the multiple third control signals are different;

[0023] Driven by the same data signal, the rate of change of current flowing through the light-emitting device is measured respectively, and the pulse width of the third control signal is determined based on the rate of change of current.

[0024] Optionally, in some embodiments of this application, the formula for calculating the rate of change of current is: Δ=(I i -I0) / I0;

[0025] Wherein, I0 is the reference current flowing through the light-emitting device when the detection threshold voltage is zero, I i The current flowing through the light-emitting device when the detection threshold voltage is non-zero.

[0026] Optionally, in some embodiments of this application, the compensation range of the threshold voltage of the driving transistor includes a threshold voltage offset that satisfies the current change rate within ±5%.

[0027] Thirdly, this application also provides a display panel, the display panel including a plurality of pixel units arranged in an array, each pixel unit including a pixel compensation circuit as described in any of the above claims; or each pixel unit employs a driving method for the pixel compensation circuit as described in any of the above claims.

[0028] This application discloses a pixel compensation circuit and its driving method, as well as a display panel. The pixel compensation circuit includes a driving transistor, a data writing module, a first initialization module, a second initialization module, a storage capacitor, and a light-emitting device. The driving timing of the pixel compensation circuit includes a threshold voltage compensation stage, in which the detected threshold voltage of the driving transistor is less than the actual threshold voltage of the driving transistor. The pixel compensation circuit provided by this application can detect and compensate for the threshold voltage of the driving transistor, offsetting the influence of the threshold voltage offset of the driving transistor on the current flowing through the light-emitting device. In addition, by setting the detected threshold voltage of the threshold voltage compensation stage to be less than the actual threshold voltage, this application ensures that the Vgs (gate-source voltage of the driving transistor) detected in the threshold voltage compensation stage is greater than the actual threshold voltage, achieving over-detection. This can significantly improve the threshold voltage compensation range of the driving transistor and improve the display uniformity of the display panel. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the pixel compensation circuit provided in this application;

[0031] Figure 2 yes Figure 1 The first signal timing diagram of the pixel compensation circuit shown is shown.

[0032] Figure 3 yes Figure 1 The second signal timing diagram of the pixel compensation circuit is shown below;

[0033] Figure 4 This is a simulation diagram of the working timing of the pixel compensation circuit provided in this application;

[0034] Figure 5 This is a schematic diagram showing the relationship between the rate of change of current and the threshold voltage offset of the driving transistor under different third control signals provided in this application.

[0035] Figure 6 This is a schematic diagram of a display panel provided in this application. Detailed Implementation

[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0037] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" and "second," etc., may explicitly or implicitly include one or more of the stated features, and thus should not be construed as limiting this application. Furthermore, it should be noted that unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly, for example, they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0038] This application provides a pixel compensation circuit and its driving method, as well as a display panel, which will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments of this application.

[0039] Please see Figure 1 , Figure 1 This is a schematic diagram of the pixel compensation circuit provided in this application. In the embodiments of this application, the pixel compensation circuit 100 includes a driving transistor T1, a data writing module 101, a first initialization module 102, a second initialization module 103, a storage capacitor C, and a light-emitting device D.

[0040] The gate of driving transistor T1 is connected to the first node P. The drain of driving transistor T1 is connected to the first power supply terminal, and the source of driving transistor T1 is connected to the second node Q.

[0041] The data writing module 101 is connected to the first control signal line 11, the data line 12, and the first node P. In response to the first control signal Gn transmitted via the first control signal line 11, the data writing module 101 transmits the data signal Vdata transmitted via the data line 12 to the first node P.

[0042] The first initialization module 102 is connected to the second control signal line 13, the first trace 14, and the second node Q. In response to the second control signal INI transmitted on the second control signal line 13, the first initialization module 102 transmits the first initialization signal Vini transmitted on the first trace 14 to the second node Q.

[0043] The second initialization module 103 is connected to the third control signal line 15, the second trace 16, and the first node P. In response to the third control signal REF transmitted through the third control signal line 15, the second initialization module 103 transmits the second initialization signal Vref transmitted through the second trace 16 to the first node P.

[0044] The two plates of the storage capacitor C are connected to the first node P and the second node Q, respectively.

[0045] One end of the light-emitting device D is connected to the first power supply terminal VDD. The other end of the light-emitting device is connected to the second power supply terminal VSS.

[0046] The driving timing of the pixel compensation circuit 100 includes a threshold voltage compensation stage. In the threshold voltage compensation stage, the detection threshold voltage of the driving transistor T1 is less than the actual threshold voltage of the driving transistor T1.

[0047] It is understood that in the pixel compensation circuit 100, during the threshold voltage compensation stage, the detection threshold voltage of the driving transistor T1 needs to be determined by detecting the gate-source voltage Vgs of the driving transistor T1 (equivalent to detecting the voltage difference between the first node P and the second node Q). Therefore, in this embodiment, the detection threshold voltage detected during the threshold voltage compensation stage is also the gate-source voltage Vgs of the driving transistor T1.

[0048] The pixel compensation circuit 100 provided in this application embodiment can detect and compensate for the threshold voltage of the driving transistor T1, thus offsetting the influence of the threshold voltage offset of the driving transistor T1 on the current flowing through the light-emitting device D. Furthermore, this application embodiment sets the detected threshold voltage during the threshold voltage compensation stage to be lower than the actual threshold voltage. That is, the gate-source voltage Vgs of the driving transistor T1 detected during the threshold voltage compensation stage is greater than the actual threshold voltage, achieving over-detection. Therefore, the threshold voltage compensation range of the driving transistor T1 can be significantly improved, enhancing display uniformity.

[0049] Please continue reading. Figure 1 In some embodiments of this application, the data writing module 101 includes a first transistor T2. The gate of the first transistor T2 is connected to the first control signal line 11. The drain of the first transistor T2 is connected to the data line 12. The source of the first transistor T2 is connected to the first node P. Of course, the structure of the data writing module 101 in the embodiments of this application is not limited to this.

[0050] In some embodiments of this application, the first initialization module 102 includes a second transistor T3. The gate of the second transistor T3 is connected to the second control signal line 13. The drain of the second transistor T3 is connected to the first trace 14. The source of the second transistor T3 is connected to the second node Q. Of course, the structure of the first initialization module 102 in the embodiments of this application is not limited to this.

[0051] In some embodiments of this application, the second initialization module 103 includes a third transistor T4. The gate of the third transistor T4 is connected to the third control signal line 15. The drain of the third transistor T4 is connected to the second trace 16. The source of the third transistor T4 is connected to the first node P. Of course, the structure of the first initialization module 102 in the embodiments of this application is not limited to this.

[0052] In some embodiments of this application, the anode of the light-emitting device D is connected to the second node Q. The cathode of the light-emitting device D is connected to the second power supply terminal VSS. The voltage of the power signal output from the first power supply terminal VDD is greater than the voltage of the power signal output from the second power supply terminal VSS.

[0053] The light-emitting device D can be a mini light-emitting diode, a micro light-emitting diode, or an organic light-emitting diode; this application does not specifically limit this.

[0054] It should be noted that the transistors used in all embodiments of this application can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of this application, to distinguish the two terminals of the transistor other than the gate, one terminal is called the source and the other terminal is called the drain. According to the configuration in the accompanying drawings, the middle terminal of the switching transistor is the gate, the signal input terminal is the drain, and the output terminal is the source. In addition, the transistors used in the embodiments of this application can include both P-type transistors and / or N-type transistors. The P-type transistor is turned on when the gate is low and turned off when the gate is high, while the N-type transistor is turned on when the gate is high and turned off when the gate is low.

[0055] Furthermore, the following embodiments of this application are all described using N-type transistors in the pixel compensation circuit 100 as an example, but they should not be construed as limiting this application.

[0056] For details, please refer to Figure 1 and Figure 2 , Figure 2 yes Figure 1 The diagram shows the timing sequence of the first signal in the pixel compensation circuit. (Combined with...) Figure 1 and Figure 2 The first control signal G1, the second control signal INI, and the third control signal REF are combined sequentially to correspond to the reset phase, the threshold voltage compensation phase, the data writing phase, and the light emission phase t6. That is, within one frame, the driving timing of the pixel compensation circuit 100 provided in this application embodiment includes the reset phase, the threshold voltage compensation phase, the data writing phase, and the light emission phase t6.

[0057] The reset phase includes a first reset phase t0 and a second reset phase t1.

[0058] During the first reset phase t0, both the first control signal Gn and the third control signal REF are low, and both the first transistor T2 and the third transistor T4 are turned off. The second control signal INI is high, and the second transistor T3 is turned on. The first initialization signal Vint is transmitted to the second node Q, i.e., the source of the driving transistor T1, via the second transistor T3 to initialize the potential of the source of the driving transistor T1.

[0059] During the second reset phase t1, the first control signal Gn and the second control signal INI are low, and both the first transistor T2 and the second transistor T3 are turned off. The third control signal REF is high, and the third transistor T4 is turned on. The second initialization signal Vref is transmitted to the first node P, i.e., the gate of the driving transistor T1, via the third transistor T4 to initialize the potential of the gate of the driving transistor T1.

[0060] The threshold voltage compensation stage includes a first compensation stage t2 and a second compensation stage t3.

[0061] During the first compensation phase t2, the first control signal Gn and the second control signal INI remain low, while the third control signal REF remains high. The driving transistor T1 is turned on, and the power signal output from the first power supply terminal VDD charges the second node Q (the source s of the driving transistor T1) until the potential of the second node Q gradually changes from the potential of the first initialization signal Vint to the difference between the potential of the second initialization signal Vref and the threshold voltage of the driving transistor T1. At this point, the driving transistor T1 is turned off. Thus, the actual threshold voltage of the driving transistor T1 is detected. That is, in this embodiment, the detected threshold voltage of the driving transistor T1 is equal to the actual threshold voltage of the driving transistor T1.

[0062] During the second compensation phase t3, the first control signal Gn, the second control signal INI, and the third control signal REF are all at low levels. The purpose of setting the second compensation phase t3 is to allow the detection time of the threshold voltage of the driving transistor T1 to be adjusted. That is, the detection time of the threshold voltage of the driving transistor T1 can be adjusted from the duration of the first compensation phase t2 to the sum of the durations of the first compensation phase t2 and the second compensation phase t3. It is understood that different threshold voltages result in different detection durations, and the embodiments of this application can be applied to driving transistors T1 with different threshold voltages.

[0063] The data writing phase includes a first writing phase t4 and a second writing phase t5.

[0064] During the first write phase t4, both the second control signal INI and the third control signal REF are low, and both the second transistor T3 and the third transistor T4 are off. The first control signal Gn is high, and the first transistor T2 is on. The data signal Vdata is transmitted to the gate of the driving transistor T1 via the first transistor T2.

[0065] It should be noted that the setting of t5 in the second write stage is to ensure that the data signal Vdata can be completely written.

[0066] During the light-emitting stage t6, the first control signal Gn, the second control signal INI, and the third control signal REF are all at low levels. The driving transistor T1 is turned on, and the current flowing through the light-emitting device D is independent of the threshold voltage of the driving transistor T1, thus ensuring that the current flowing through the light-emitting device D remains constant. Even if the threshold voltage of the driving transistor T1 drifts, it will not affect the normal light emission of the light-emitting device D, thereby improving the uniformity of light emission of the display panel.

[0067] However, when the pixel compensation circuit 100 adopts such Figure 2 When the first signal timing is shown, the threshold voltage compensation range of the pixel compensation circuit 100 for the driving transistor T1 is only ±0.3V.

[0068] The reason is that, theoretically, the formula for the driving transistor current of the pixel compensation circuit 100 is:

[0069]

[0070] In reality, there is a DTE (Data Transfer Efficiency, referring to the voltage efficiency lost from writing the data signal Vdata to the light emission stage) loss during the light emission stage. For ease of understanding, let's define the slope k:

[0071]

[0072] Where Vg1 and Vg2 refer to the gate potentials of the driving transistor T1 before and after the threshold voltage shift, Vs1 and Vs2 refer to the source potentials of the driving transistor T1 before and after the threshold voltage shift, ΔVgs_sense refers to the actual detected change in the gate-source voltage Vgs of the driving transistor T1, and ΔVgs_shift refers to the actual change in the threshold voltage shift of the driving transistor T1.

[0073] The DTE loss can be calculated by recording the written data signal Vdata and the second initialization signal Vref using the timing of the light emission stage, while simultaneously measuring the gate voltage Vg and source voltage Vs of the driving transistor T1 during stable light emission. The specific calculation formula is: DTE = (Vg - Vs) / (Vdata - Vref), based on... and In fact, the current of the driving transistor T1 in the pixel compensation circuit 100 is:

[0074]

[0075] When the emission stage K = 1, i.e. ΔVgs_sense = ΔVgs_shift, the rate of change of current can be reduced, thus mitigating the impact of current changes caused by threshold voltage drift. This improves the threshold voltage compensation effect, resulting in the over-detection current reaching the theoretical current value.

[0076]

[0077] In response, this application provides a second driving timing for the pixel compensation circuit 100. Please refer to [link / reference]. Figure 1 and Figure 3 , Figure 3 yes Figure 1 The second signal timing diagram of the pixel compensation circuit is shown. Figure 2 The difference in the first driving timing shown is that, in this embodiment, during the threshold voltage compensation stage, the detection threshold voltage of the driving transistor T1 is less than the actual threshold voltage of the driving transistor T1.

[0078] Specifically, such as Figure 1 and Figure 3 As shown, in the first compensation stage t2, the pulse width of the third control signal REF is controlled so that the third transistor T4 is turned off before the source voltage Vs of the driving transistor T1 rises to Vgs = Vth during the compensation stage, resulting in insufficient detection of Vgs, so that the gate voltage Vg and the source voltage Vs are in a floating state, and the detected Vgs > Vth.

[0079] In this process, the third control signal REF in the first compensation stage t2 and the third control signal REF in the second compensation stage t3 are out of phase. Similarly, the setting of the second compensation stage t3 allows the detection time of the threshold voltage of the driving transistor T1 to be adjusted, thus making it suitable for driving transistors T1 with different threshold voltages.

[0080] That is, in the embodiments of this application, during the detection phase, the detection threshold voltage of the driving transistor T1 is determined by the pulse width of the third control signal REF.

[0081] However, the power signal output from the first power supply terminal VDD continues to charge the source of the driving transistor T1, causing the source voltage Vs to rise continuously. Due to the coupling effect of the storage capacitor Cst, the gate voltage Vg is also coupled up, and the rise rate of the source voltage Vs is faster than that of the gate voltage Vg. Furthermore, the more negatively biased the threshold voltage, the faster the rise rate of the source voltage Vs. The gate-source voltage Vgs will gradually decrease until Vgs = Vth, at which point the driving transistor T1 will turn off.

[0082] Furthermore, since K has been defined in the above embodiments, it represents the ratio of the detected threshold voltage to the actual threshold voltage. At different stages of the pixel compensation circuit 100's operation, K = 1 indicates that the simulated detected threshold voltage (i.e., the detected Vgs) is the same as the actual threshold voltage of the driving transistor T1. However, this is not possible in reality because of capacitive coupling losses; the value of K tends to decrease over time. This often leads to DTE losses during the light-emitting stage, meaning that the gate-source voltage Vgs at the actual light-emitting stage t6 is less than the gate-source voltage Vgs when the data signal data is written.

[0083] To reduce the DTE loss during the light emission stage t6, the detection threshold voltage can be made greater than the actual threshold voltage before the writing stage, i.e., during the compensation stage in the pixel compensation circuit 100's operating timing. This achieves an over-detection compensation effect. Even if K > 1 before the light emission stage, it's possible that even if K decreases, the K value during the writing and light emission stages t6 will equal 1, thereby reducing the current change rate caused by threshold voltage drift.

[0084] In some embodiments of this application, when the pulse width of the third control signal REF is different, the detection threshold voltage detected in the threshold voltage detection stage is different, and the threshold voltage compensation range of the pixel compensation circuit 100 is also different.

[0085] In some embodiments of this application, the duration of the reset phase is 2 hours. The duration of the first compensation phase t2 (i.e., the pulse width of the third control signal REF) is 12 hours. The duration of the second compensation phase t3 is 43 hours, and the durations of the first write phase t4 and the second write phase t5 are both 0.5 hours. Therefore, the threshold voltage compensation range of the pixel compensation circuit 100 can reach -0.85V to 1.45V.

[0086] Where 1H = 1 / (screen refresh rate * number of rows on the display). For example, for a display panel with a refresh rate of 120Hz and a resolution of 2160*1800, 1H is equal to 1 / (120 * 2160) = 3.85us, where the unit is time: seconds.

[0087] This application also provides a driving method for a pixel compensation circuit, used to drive the pixel compensation circuit 100 as described in any of the above embodiments. The driving method for the pixel compensation circuit 100 includes:

[0088] S1. Initialize the potentials of the second node Q and the first node P.

[0089] For details on how to initialize the potentials of the second node Q and the first node P, please refer to the above embodiments, which will not be repeated here.

[0090] S2. Determine the pulse width of the third control signal REF such that during the threshold voltage compensation stage t, the detection threshold voltage of the driving transistor T1 is less than the actual threshold voltage of the driving transistor T1.

[0091] Specifically, in some embodiments of this application, step S2 may include the following steps: setting multiple third control signals REF, each with a different pulse width; under the drive of the same data signal Vdata, testing the corresponding rate of change of current flowing through the light-emitting device, and determining the pulse width of the third control signal REF based on the rate of change of current.

[0092] In some embodiments of this application, the formula for calculating the rate of change of current can be: Δ=(Ii-I0) / I0.

[0093] Where I0 is the reference current flowing through the light-emitting device D when the detection threshold voltage is zero, and Ii is the current flowing through the light-emitting device D when the detection threshold voltage is non-zero.

[0094] In some embodiments of this application, the compensation range for the threshold voltage of the driving transistor T1 includes a threshold voltage offset that satisfies a current change rate within ±5%.

[0095] For details, please refer to Figure 4 and Figure 5 , Figure 4 This is a simulation diagram of the working timing of the pixel compensation circuit provided in this application. Figure 5 This is a schematic diagram showing the relationship between the rate of change of current and the threshold voltage offset of the driving transistor under different third control signals, as provided in this application.

[0096] exist Figure 4 In the process, the gate voltage Vg and source voltage Vs change differently depending on the pulse width of the third control signal REF.

[0097] according to Figure 4 The simulation results yielded a schematic diagram showing the relationship between the rate of change of current and the threshold voltage offset of the driving transistor under different third control signals. (See diagram for example.) Figure 5 As shown, curve A represents the relationship between the current change rate Δ and the threshold voltage offset of the driving transistor when the pulse width of the third control signal REF is 11H. It can be seen that the threshold voltage compensation range of the driving transistor T1 is -1.4V to 0.75V.

[0098] Curve B represents the relationship between the rate of change of current Δ and the threshold voltage offset of the driving transistor when the pulse width of the third control signal REF is 12H. It can be seen that the threshold voltage compensation range of the driving transistor T1 is -0.85V to 1.45V.

[0099] Curve C represents the relationship between the rate of change of current Δ and the threshold voltage offset of the driving transistor when the pulse width of the third control signal REF is 13H. It can be seen that the threshold voltage compensation range of the driving transistor T1 is -0.55V to 0.85V.

[0100] Therefore, when the pulse width of the third control signal REF is 12H, the threshold voltage compensation range of the driving transistor T1 is at its maximum. This verifies that the compensation capability of the pixel compensation circuit 100 can be controlled by adjusting the detection time of the compensation stage.

[0101] S3. Driven by the corresponding data signal Vdata, the light-emitting device is driven to emit light.

[0102] After determining the pulse width of the third control signal REF, the pixel compensation circuit 100 is driven normally, and the corresponding data signal Vdata is written, which drives the light-emitting device D to emit light.

[0103] Please see Figure 6 , Figure 6 This is a schematic diagram of a display panel provided in an embodiment of this application. This application also provides a display panel 1000, including a plurality of pixel units 110 arranged in an array. Each pixel unit 110 includes the pixel compensation circuit 100 described in any of the above embodiments or employs the driving method of the pixel compensation circuit described in any of the above embodiments. For details, please refer to the above description; further elaboration is not provided here.

[0104] In this embodiment, the display panel 1000 may be an OLED (Organic Light-Emitting Diode) display panel, a Mini LED (Mini Light-Emitting Diode) display panel, a Micro LED (Micro Light-Emitting Diode) display panel, etc.

[0105] In the display panel 1000 provided in this application embodiment, the pixel compensation circuit 100 includes a driving transistor, a data writing module, a first initialization module, a second initialization module, a storage capacitor, and a light-emitting device. The driving timing of the pixel compensation circuit 100 includes a threshold voltage compensation stage, in which the detected threshold voltage of the driving transistor is less than the actual threshold voltage of the driving transistor. The pixel compensation circuit 100 provided in this application embodiment can detect and compensate for the threshold voltage of the driving transistor, offsetting the influence of the threshold voltage offset of the driving transistor on the current flowing through the light-emitting device. In addition, by setting the detected threshold voltage of the threshold voltage compensation stage to be less than the actual threshold voltage, this application embodiment ensures that the gate-source voltage Vgs detected in the threshold voltage compensation stage is greater than the actual threshold voltage, achieving over-detection. This can significantly improve the threshold voltage compensation range of the driving transistor and improve the display uniformity of the display panel 1000.

[0106] The pixel compensation circuit and its driving method, as well as the display panel, provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A pixel compensation circuit, characterized in that, include: A driving transistor, wherein the gate of the driving transistor is connected to a first node, the drain of the driving transistor is connected to a first power supply terminal, and the source of the driving transistor is connected to a second node. A data writing module is connected to a first control signal line, a data line, and a first node, and transmits the data signal transmitted by the data line to the first node in response to a first control signal transmitted by the first control signal line. A first initialization module is connected to a second control signal line, a first trace, and a second node, and in response to a second control signal transmitted by the second control signal line, transmits a first initialization signal transmitted by the first trace to the second node; The second initialization module is connected to the third control signal line, the second trace, and the first node, and in response to the third control signal transmitted by the third control signal line, transmits the second initialization signal transmitted by the second trace to the first node; A storage capacitor, wherein the two plates of the storage capacitor are respectively connected to the first node and the second node; as well as A light-emitting device, one end of which is connected to the first power supply terminal and the other end of which is connected to the second power supply terminal; The driving timing of the pixel compensation circuit includes a threshold voltage compensation stage, which includes a first compensation stage and a second compensation stage. In the first compensation stage, by controlling the pulse width of the third control signal, the second initialization module is turned off before the source voltage of the driving transistor rises to the point where the gate-source voltage of the driving transistor is equal to the actual threshold voltage of the driving transistor. In the threshold voltage compensation stage, the detection threshold voltage of the driving transistor is less than the actual threshold voltage of the driving transistor.

2. The pixel compensation circuit according to claim 1, characterized in that, During the threshold voltage compensation phase, the detection threshold voltage of the driving transistor is determined by the pulse width of the third control signal.

3. The pixel compensation circuit according to claim 1, characterized in that, When the pulse width of the third control signal is different, the threshold voltage compensation range of the pixel compensation circuit is different.

4. The pixel compensation circuit according to claim 3, characterized in that, The threshold voltage compensation range of the pixel compensation circuit is -0.85V to 1.45V.

5. The pixel compensation circuit according to claim 3, characterized in that, The threshold voltage compensation stage includes a first compensation stage and a second compensation stage, wherein the third control signal in the first compensation stage and the third control signal in the second compensation stage are out of phase.

6. A driving method for a pixel compensation circuit, characterized in that, The method for driving the pixel compensation circuit as described in any one of claims 1-5 includes: Initialize the potentials of the second node and the first node; The pulse width of the third control signal is determined such that, during the threshold voltage compensation phase, the detection threshold voltage of the driving transistor is less than the actual threshold voltage of the driving transistor. Driven by the corresponding data signal, the light-emitting device is driven to emit light.

7. The driving method for the pixel compensation circuit according to claim 6, characterized in that, The step of determining the pulse width of the third control signal includes: Multiple third control signals are set, and the pulse widths of the multiple third control signals are different; Driven by the same data signal, the corresponding rate of change of current flowing through the light-emitting device is tested and obtained respectively, and the pulse width of the third control signal is determined based on the rate of change of current.

8. The driving method for the pixel compensation circuit according to claim 7, characterized in that, The formula for calculating the rate of change of current is: Δ = (I i -I0) / I0; Wherein, I0 is the reference current flowing through the light-emitting device when the detection threshold voltage is zero, I i The current flowing through the light-emitting device when the detection threshold voltage is non-zero.

9. The driving method for the pixel compensation circuit according to claim 7, characterized in that, The compensation range for the threshold voltage of the driving transistor includes a threshold voltage offset that satisfies the current change rate within ±5%.

10. A display panel, characterized in that, The display panel includes a plurality of pixel units arranged in an array, each pixel unit including a pixel compensation circuit as described in any one of claims 1-5; or each pixel unit employs a driving method for the pixel compensation circuit as described in any one of claims 6-9.

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