Array substrate, preparation method thereof and display panel

Abstract

The invention relates to an array substrate and a preparation method thereof, and a display panel. The array substrate comprises a substrate; the spacing layer is located on one side of the substrate, the spacing layer comprises a first surface deviating from the substrate, at least one groove sunken towards the substrate is formed in the first surface, and the groove has a first orthographic projection on the substrate; the first metal layer is located on the first surface and comprises a first grid electrode of a first transistor; the active layer is insulated from the first metal layer and located on the side, away from the substrate, of the first metal layer, the active layer comprises an active structure, the active structure comprises a channel region, at least part of the channel region and at least part of the first grid electrode are oppositely arranged, and the active structure comprises a first part and a second part; the orthographic projection of the first part on the substrate at least partially covers the first orthographic projection; the second metal layer is located on the side, away from the substrate, of the active layer, the second metal layer comprises a first electrode of the first transistor, the first electrode of the first transistor comprises a second surface facing the substrate, and the second surface makes contact with the second part.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to array substrates and their fabrication methods, and display panels. Background Technology

[0002] With the rapid iteration of near-eye display technologies such as Virtual Reality (VR) and Augmented Reality (AR), users have placed higher demands on the pixel density (Pixels Per Inch, PPI) of display panels in order to achieve immersive, grain-free displays.

[0003] Organic light-emitting diode (OLED) display panels are considered the mainstream technology for high PPI displays due to their advantages such as self-illumination, high contrast, and wide viewing angle. However, OLED pixel circuits require multiple thin-film transistors (TFTs) (such as switching TFTs, driving TFTs, and compensation TFTs) to achieve pixel charging, discharging, and brightness control. The area ratio of the TFTs directly affects the space utilization of the pixel circuit. For example, the larger the TFT area, the lower the pixel aperture ratio, and the more difficult it is to meet the high PPI requirements for small-sized devices.

[0004] In related technologies, oxide semiconductor TFTs are widely used in the driving circuits of OLED display panels due to their excellent properties such as high carrier mobility and low off-state current. However, when the channel length is reduced to the submicron level to shrink the device area, a problem of negative threshold voltage dispersion occurs, meaning that the voltage values ​​of different devices differ significantly, leading to uneven pixel brightness and mura phenomena in the display image. To ensure voltage consistency, related technologies have to increase the channel length, which directly results in an increase in the horizontal projected area of ​​the TFT, making it impossible to meet the high PPI requirements of small-sized TFTs. Summary of the Invention

[0005] Based on this, an array substrate and its fabrication method, as well as a display panel, are provided, which can increase the channel path length and improve overall performance.

[0006] An array substrate includes a first transistor, the array substrate comprising:

[0007] Substrate;

[0008] A spacer layer, located on one side of the substrate, the spacer layer includes a first surface facing away from the substrate, the first surface having at least one trench recessed toward the substrate, the trench having a first orthographic projection on the substrate, and the first surface located outside the trench having a second orthographic projection on the substrate;

[0009] A first metal layer, located on the first surface, includes a first gate of the first transistor, wherein the orthogonal projection of the first gate onto the substrate at least partially covers the first orthogonal projection.

[0010] An active layer, insulated from the first metal layer, is located on the side of the first metal layer away from the substrate. The active layer includes an active structure, which includes a channel region. At least a portion of the channel region and at least a portion of the first gate are disposed opposite each other. The active structure includes a first portion and a second portion. The orthographic projection of the first portion on the substrate at least partially covers the first orthographic projection, and the orthographic projection of the second portion on the substrate at least partially covers the second orthographic projection.

[0011] A second metal layer is located on the side of the active layer away from the substrate. The second metal layer includes a first electrode of the first transistor, and the first electrode of the first transistor includes a second surface facing the substrate. The second surface is in contact with the second portion.

[0012] In one embodiment, the first electrode of the first transistor includes a third surface remote from the substrate, the orthographic projection of the third surface onto the substrate being within the orthographic projection of the second surface onto the substrate;

[0013] Preferably, the edge of the channel region in the orthographic projection of the substrate coincides with the edge of the first electrode of the first transistor in the orthographic projection of the substrate;

[0014] Preferably, the trench includes a bottom wall opposite to the substrate, and the orthographic projection of the trench region onto the bottom wall at least partially overlaps with the orthographic projection of the first gate onto the bottom wall;

[0015] Preferably, the trench includes a sidewall surrounding the bottom wall, and the orthographic projection of the trench region onto the sidewall at least partially overlaps with the orthographic projection of the first gate onto the sidewall.

[0016] Preferably, the material of the spacer layer includes an organic insulating material;

[0017] Preferably, the array substrate further includes a first insulating layer located between the first metal layer and the active layer, wherein the first insulating layer at least covers the first gate.

[0018] Preferably, the material of the first insulating layer includes inorganic materials;

[0019] Preferably, the second metal layer further includes a second electrode of the first transistor, the second electrode of the first transistor including a fourth surface facing the substrate, the fourth surface being in contact with the second portion;

[0020] Preferably, the second electrode of the first transistor includes a fifth surface remote from the substrate, the orthographic projection of the fifth surface onto the substrate being within the orthographic projection of the fourth surface onto the substrate.

[0021] In one embodiment, it further includes:

[0022] The second insulating layer is located on the side of the second metal layer and the active layer away from the substrate, and the orthographic projection of the second insulating layer on the substrate covers the orthographic projection of the second metal layer on the substrate and the orthographic projection of the active layer on the substrate.

[0023] A third metal layer, located on the side of the second insulating layer away from the substrate, includes the second gate of the first transistor, the orthogonal projection of the second gate onto the substrate covering the orthogonal projection of the channel region onto the substrate;

[0024] Preferably, the material of the second insulating layer includes inorganic materials.

[0025] In one embodiment, it further includes:

[0026] A third insulating layer is located on the side of the third metal layer away from the substrate, and the thickness of the third insulating layer is greater than the thickness of the first insulating layer, and / or the thickness of the third insulating layer is greater than the thickness of the second insulating layer;

[0027] Preferably, the material of the third insulating layer includes organic materials;

[0028] Preferably, the active layer is made of at least one of oxide semiconductor, monocrystalline silicon, polycrystalline silicon, and amorphous silicon.

[0029] In one embodiment, the orthographic projection of the channel region onto the second metal layer is located between the first electrode and the second electrode;

[0030] Preferably, the orthographic projection of the second surface on the substrate has a first dimension l, the orthographic projection of the fourth surface on the substrate has a second dimension m, the orthographic projection of the first surface on the substrate has a third dimension n, and the orthographic projection of the channel region on the substrate has a dimension p = n - (l + m).

[0031] In one embodiment, the first part includes a first sub-channel area disposed opposite to the bottom wall of the trench and a second sub-channel area disposed opposite to the side wall of the trench, such that the first sub-channel area and the second sub-channel area form a preset angle.

[0032] Preferably, the range of the preset included angle is [90°, 150°].

[0033] In one embodiment, the array substrate includes a pixel driving circuit, the pixel driving circuit including at least one of the first transistors;

[0034] Preferably, the pixel driving circuit includes a driving module and at least one switching module, wherein at least one transistor in the driving module and the at least one switching module is the first transistor.

[0035] In one embodiment, the pixel driving circuit includes a plurality of first transistors, the at least one switching module includes a data writing module, the transistor in the driving module is one of the plurality of first transistors, and the transistor in the data writing module is one of the plurality of first transistors, wherein:

[0036] The area of ​​the channel region of the first transistor in the driving module projected onto the substrate is greater than the area of ​​the channel region of the first transistor in the data writing module projected onto the substrate.

[0037] A display panel comprising an array substrate as described above.

[0038] A method for fabricating an array substrate, comprising:

[0039] Provide substrate;

[0040] A spacer layer is formed on one side of the substrate, the spacer layer including a first surface facing away from the substrate, the spacer layer is patterned to form a trench recessed toward the substrate on the first surface, the trench having a first orthographic projection on the substrate, and the first surface located outside the trench having a second orthographic projection on the substrate.

[0041] A first metal layer is formed on the first surface using physical vapor deposition or atomic layer deposition techniques. The first metal layer is then patterned to form the first gate of the first transistor. The orthogonal projection of the first gate onto the substrate at least partially covers the first orthogonal projection.

[0042] An active layer is formed on the side of the first metal layer away from the substrate, and the active layer is insulated from the first metal layer; wherein, the active layer is formed by physical vapor deposition or atomic layer deposition, and the active layer is patterned to form an active structure, the active structure including a channel region, at least a portion of the channel region and at least a portion of the first gate are disposed opposite to each other, the active structure includes a first part and a second part, the orthographic projection of the first part on the substrate at least partially covers the first orthographic projection, and the orthographic projection of the second part on the substrate at least partially covers the second orthographic projection;

[0043] A second metal layer is formed on the side of the active layer away from the substrate, and the second metal layer is patterned to form a first electrode of the first transistor. The first electrode of the first transistor includes a second surface facing the substrate, and the second surface is in contact with a second portion of the active layer.

[0044] The aforementioned array substrate, its fabrication method, and display panel, by setting trenches recessed towards the substrate in the spacer layer, and the orthogonal projection of the first gate on the substrate covering the first orthogonal projection of the trench, enable the first part of the channel region to extend in a direction perpendicular to the substrate. The path length of the channel region is determined by the depth of the trench. With a very small horizontal projection area, a sufficiently long channel region path length can be obtained by increasing the trench depth. This avoids the short channel effect caused by channel shortening and significantly reduces the area occupied by the thin film transistor on the substrate, thereby improving the pixel aperture ratio and meeting the requirements of high PPI display panels for small-sized devices.

[0045] The first gate is buried in the trench and is positioned opposite to the first part of the active layer located in the trench. The trench allows the first gate to form a surrounding or at least multi-faceted electric field modulation on the channel region from the sidewalls and bottom of the trench, enhancing the gate electric field's control over the channel region, effectively suppressing the drain-induced barrier reduction effect, making the threshold voltage more stable, reducing voltage differences between different devices, thereby avoiding pixel brightness unevenness and spot phenomena, and improving display uniformity.

[0046] The second portion of the active layer is located on the first surface outside the trench, and the first electrode of the second metal layer is in direct contact with this second portion. Since the active layer extends to a flat surface outside the trench, the first electrode can directly contact the active layer without needing a via penetrating the insulating layer, eliminating the complex steps of fabricating interlayer insulating layers and drilling holes in related technologies, thus simplifying the fabrication process. Simultaneously, planar contact has a larger contact area and a more stable interface compared to via contact, effectively reducing contact resistance and improving the transmission efficiency of the drive current and the reliability of the device. Attached Figure Description

[0047] Figure 1 This is a schematic cross-sectional view of an array substrate in an exemplary embodiment.

[0048] Figure 2 This is a schematic flowchart of a method for fabricating an array substrate in an exemplary embodiment.

[0049] Figure 3 This is a schematic cross-sectional view of an array substrate in an exemplary embodiment.

[0050] Figure 4 This is a schematic cross-sectional view of an array substrate in an exemplary embodiment.

[0051] Figure 5 This is a schematic cross-sectional view of an array substrate in an exemplary embodiment.

[0052] Figure 6 This is a schematic cross-sectional view of an array substrate in an exemplary embodiment.

[0053] Figure 7 This is a schematic cross-sectional view of an array substrate in an exemplary embodiment.

[0054] Figure 8 This is a schematic cross-sectional view of an array substrate in an exemplary embodiment.

[0055] Figure 9 This is a schematic cross-sectional view of an array substrate in an exemplary embodiment.

[0056] Figure 10 This is a schematic cross-sectional view of an array substrate in an exemplary embodiment.

[0057] Figure 11 This is a schematic cross-sectional view of an array substrate in an exemplary embodiment.

[0058] Figure label:

[0059] 1. Substrate; 2. Spacer layer; 21. First surface; 22. Trench; 221. Bottom wall; 222. Sidewall; 3. First metal layer; 31. First gate; 4. Active layer; 41. Active structure; 411. First portion; 4111. First sub-channel region; 4112. Second sub-channel region; 412. Second portion; 5. Second metal layer; 51. First electrode; 511. Second surface; 512. Third surface; 52. Second electrode; 521. Fourth surface; 522. Fifth surface; 6. First insulating layer; 7. Second insulating layer; 8. Third metal layer; 81. Second gate; 9. Third insulating layer. Detailed Implementation

[0060] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0061] First Embodiment

[0062] like Figure 1As shown, an array substrate suitable for high-resolution OLED display panels effectively suppresses short-channel effects and improves the performance of pixel driving circuits by introducing a vertical channel structure. The array substrate includes a first transistor T, a substrate 1, a spacer layer 2, a first metal layer 3, an active layer 4, and a second metal layer 5.

[0063] Substrate 1 can be a rigid substrate made of glass, which has good flatness and light transmittance, and is suitable for the substrate requirements of OLED display panels.

[0064] In this embodiment, as Figure 1 As shown, spacer layer 2 is located on one side of substrate 1. Spacer layer 2 is made of organic insulating material. The ease with which organic materials can be formed to a large thickness provides a basis for subsequent deep trench formation. The thickness of spacer layer 2 can be flexibly adjusted according to the target trench length. A thicker spacer layer allows for the etching of deeper trenches, thus forming a longer effective trench length, which is particularly suitable for high PPI pixel driving circuits.

[0065] After the spacer layer 2 is formed, in order to ensure the accuracy of subsequent processes, chemical mechanical polishing (CMP) is used to planarize the surface of the spacer layer 2, reduce the surface roughness, and provide a smooth foundation for subsequent trench etching.

[0066] The planarized spacer layer 2 is patterned to form trenches 22 recessed towards the substrate 1 on the first surface 21 facing away from the substrate 1. For example, photoresist is uniformly coated on the surface of the spacer layer 2, and ultraviolet (or yellow) light exposure is performed using a mask. The pattern on the mask corresponds to the layout of the trenches 22, and is typically designed as a slit structure arranged in strips, grids, or a matrix.

[0067] After treatment with a developing solution, the photoresist in the exposed areas is removed, exposing the areas to be etched. Subsequently, reactive ion etching or inductively coupled plasma etching is used to precisely control the depth and sidewall angle of the trench 22. The cross-sectional shape of the trench 22 can be rectangular, inverted trapezoidal (narrow at the bottom, wide at the opening), or V-shaped. In this embodiment, an inverted trapezoidal cross-section can be selected to facilitate the stepped coverage of the subsequent metal layer and prevent line breaks. After etching, residual photoresist is removed using oxygen plasma ashing or wet stripping solution, ultimately forming a spacer layer 2 with a deep trench structure.

[0068] It should be noted that the number of grooves 22 is not limited to one, such as Figure 10 and Figure 11As shown, one, two, three, or more trenches 22 can be configured according to design requirements. When multiple trenches 22 are configured, the total length of the channel path can be further extended, thereby improving the driving capability of the transistor. The trench 22 has a first orthographic projection on the substrate 1, and the first surface 21 located outside the trench 22 has a second orthographic projection on the substrate 1. The depth direction of the trench 22 is perpendicular to the surface of the substrate 1, making the length of the subsequently formed channel physically equal to the trench depth, thus achieving long-channel characteristics with a very small horizontal projection area.

[0069] In this embodiment, as Figure 1 As shown, a first metal layer 3 is formed on the first surface 21 after the trench 22 is formed. The first metal layer 3 includes a first gate 31 of the first transistor T. The orthogonal projection of the first gate 31 on the substrate 1 at least partially covers the aforementioned first orthogonal projection (i.e., the projection of the trench 22), and the first gate 31 is buried inside the trench 22.

[0070] The first gate 31 can be made of molybdenum (Mo) as the main metal layer, which has low resistivity, high melting point and good etching resistance, making it suitable for subsequent dry etching processes. Of course, one or more of aluminum (Al), copper (Cu), titanium (Ti), tungsten (W) or indium tin oxide (ITO) can also be used in a stacked structure.

[0071] A molybdenum thin film is deposited to the target thickness using magnetron sputtering to ensure complete filling of the trench 22 and provide sufficient conductive cross-sectional area; then photoresist is applied for patterning; finally, dry etching is performed to remove the molybdenum thin film not protected by the photoresist, forming the first gate 31 embedded in the trench 22.

[0072] In this embodiment, as Figure 1 As shown, an active layer 4 is formed on the side of the first metal layer 3 away from the substrate 1, and the active layer 4 is insulated from the first metal layer 3. The active layer 4 includes an active structure 41, which includes a channel region, and at least a portion of the channel region and at least a portion of the first gate 31 are disposed opposite each other.

[0073] The material selection for the active layer 4 is diverse, including at least one of amorphous silicon, polycrystalline silicon, monocrystalline silicon, and oxide semiconductors. In this embodiment, an oxide semiconductor (e.g., IGZO material containing In, Ga, Zn, O, and doped elements) can be selected and deposited using atomic layer deposition (ALD) technology. The ALD process enables the active layer 4 to uniformly cover the surface of the first gate 31, which is beneficial for achieving high carrier mobility, low off-state current, and excellent threshold voltage uniformity.

[0074] The active structure 41 includes a first portion 411 and a second portion 412. The orthographic projection of the first portion 411 onto the substrate 1 at least partially covers the first orthographic projection (the trench 22 projection), forming a vertical conductive channel using the trench 21 of the spacer layer 2. The orthographic projection of the second portion 412 onto the substrate 1 at least partially covers the second orthographic projection (the outer surface of the trench 22). The length of the channel region is determined by both the first portion 411 and the second portion 412, with the length of the first portion 411 determined by the depth of the trench 21, thus achieving a long vertical channel design.

[0075] In this embodiment, as Figure 1 As shown, a second metal layer 5 is formed on the side of the active layer 4 away from the substrate 1. The second metal layer 5 includes a first electrode 51 of the first transistor T, such as a source or drain. The first electrode 51 includes a second surface 511 facing the substrate 1, which is in direct contact with the second portion 412 of the active layer 4.

[0076] The first electrode 51 is formed by magnetron sputtering deposition, photolithography, and dry etching. Since the second portion 412 of the active layer 4 extends directly to the flat surface outside the trench 22, the first electrode 51 can be directly connected to the active layer 4 without the need for additional via processes. This design eliminates the steps of "preparing an insulating layer and drilling" in related technologies, simplifying the process, reducing costs, and ensuring good ohmic contact between the first electrode 51 and the active layer 4.

[0077] This embodiment constructs a thin-film transistor with a vertical channel structure by setting a vertical trench 22 in the spacer layer 2 and utilizing a buried first gate 31 and a cover active layer 4. This structure achieves long channel characteristics in a very small planar area, effectively suppresses short channel effects, and simplifies the source-drain connection process, making it very suitable for high-resolution, high-integration OLED display panels.

[0078] In this embodiment, as Figure 1 As shown, the first electrode 51 of the first transistor T includes a third surface 512 away from the substrate 1, and the orthographic projection of the third surface 512 on the substrate 1 lies within the orthographic projection of the second surface 511 on the substrate 1. The first electrode 51 has a solid frustum or truncated cone structure with a smaller top and larger bottom in the direction perpendicular to the substrate 1, or at least its horizontal cross-sectional dimension at the top is smaller than that at the bottom. The first electrode 51 is a solid metal electrode directly formed on the surface of the active layer 4, avoiding the drilling and filling processes in related technologies. The first electrode 51 forms a direct physical connection with the second part 412 of the active layer 4.

[0079] To optimize transistor performance, the edge of the channel region projected onto the substrate 1 coincides with the edge of the first electrode 51 of the first transistor T projected onto the substrate 1. This ensures a precise match between the lateral dimensions of the channel region and the contact area of ​​the first electrode 51, maximizing carrier injection efficiency and minimizing parasitic capacitance, thereby significantly improving the switching speed and driving capability of the transistor.

[0080] The trench 22 includes a bottom wall 221 opposite to the substrate 1 and sidewalls 222 surrounding the bottom wall 221. Exemplarily, the orthographic projection of the channel region onto the bottom wall 221 at least partially overlaps with the orthographic projection of the first gate 31 onto the bottom wall 221; simultaneously, the orthographic projection of the channel region onto the sidewalls 222 also at least partially overlaps with the orthographic projection of the first gate 31 onto the sidewalls 222. This omnidirectional projection overlap design ensures that the gate electric field can simultaneously perform three-dimensional surround modulation of the channel region from the bottom and sidewalls of the trench 22, greatly enhancing the control capability of the first gate 31 over the channel. Especially when using a deep trench structure, it can effectively suppress short-channel effects and improve the threshold voltage stability and drive current of the transistor.

[0081] In this embodiment, as Figure 1 As shown, the array substrate also includes a first insulating layer 6, located between the first metal layer 3 and the active layer 4, for achieving electrical insulation between the first gate 31 and the active layer 4. The first insulating layer 6 at least covers the first gate 31; that is, the first insulating layer 6 not only covers the flat surface but also fills and covers the first gate 31 within the trench 22.

[0082] The material of the first insulating layer 6 includes inorganic materials. For example, the material of the first insulating layer 6 can be one or more of silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), hafnium oxide (HfO2), and tantalum oxide (Ta2O5). In one possible implementation, the first insulating layer 6 adopts a stacked structure. For example, the lower layer (the layer that directly contacts the first gate 31) is aluminum oxide (Al2O3), and the upper layer is silicon nitride (SiNx). The aluminum oxide layer is deposited using atomic layer deposition (ALD) technology. ALD technology has excellent conformal properties and atomic-level interface control capabilities, which can effectively repair fine defects on the metal surface of the first gate 31 and improve interface quality. The silicon nitride layer, as the main insulating barrier layer, provides high dielectric strength and the ability to block water and oxygen penetration.

[0083] Because trench 22 has a large aspect ratio, physical vapor deposition (PEV) techniques such as magnetron sputtering can easily produce a shadowing effect at the bottom or sidewalls of trench 22, leading to film breakage or uneven thickness. This embodiment uses atomic layer deposition (ALD) to deposit the first insulating layer 6. ALD technology utilizes self-limiting surface chemical reactions to form the film, resulting in excellent step coverage and conformal properties. Regardless of the depth of trench 22, the ALD process ensures that the first insulating layer 6 uniformly covers the sidewalls and bottom of the first gate 31 without breaks or pinholes, thus completely avoiding the risk of short circuits between the gate and the active layer, guaranteeing high device reliability and high yield.

[0084] In this embodiment, as Figure 1 As shown, the second metal layer 5 also includes a second electrode 52 of the first transistor T. The second electrode 52 and the first electrode 51 are respectively disposed on both sides of the trench 22, serving as the source and drain, respectively. The second electrode 52 includes a fourth surface 521 facing the substrate 1. The fourth surface 521 is in direct contact with the second portion 412 of the active layer 4, and is used to introduce or extract charge carriers in the channel region.

[0085] Similarly, to clarify the physical structure of the second electrode 52, the second electrode 52 of the first transistor T includes a fifth surface 522 located away from the substrate 1, the orthographic projection of the fifth surface 522 onto the substrate 1 lying within the orthographic projection of the fourth surface 521 onto the substrate 1. Like the first electrode 51, the second electrode 52 is also a solid electrode without vias.

[0086] The second electrode 52 is formed using standard semiconductor processes such as magnetron sputtering deposition, photolithography, and dry etching. Since the second portion 412 of the active layer 4 extends to the flat surface outside the trench 22 (i.e., the second orthographic projection region), the second electrode 52 can directly contact this portion without requiring additional via processes. This self-aligned planar contact design eliminates the complex steps of "preparing interlayer insulating layers and drilling" in related processes, simplifying the fabrication process, reducing costs, and significantly decreasing the contact resistance between the source / drain electrode and the active layer 4, thereby improving the overall electrical performance of the device.

[0087] This embodiment constructs a thin-film transistor structure with vertical long channel characteristics, high integration, high reliability and excellent process compatibility by precisely defining the electrode projection relationship, designing the three-dimensional overlap of the inner and outer gates and channels of trench 22, and using a high-quality gate insulating layer with ALD process. It is suitable for pixel driving circuits of high-resolution OLED display panels.

[0088] Second Embodiment

[0089] like Figure 9As shown, an array substrate suitable for high-resolution OLED display panels effectively suppresses short-channel effects and improves the performance of pixel driving circuits by introducing a vertical channel structure. The array substrate includes a first transistor T, a substrate 1, a spacer layer 2, a first metal layer 3, an active layer 4, and a second metal layer 5. The second embodiment differs from the first embodiment in that the array substrate further includes a second insulating layer 7 and a third metal layer 8, forming a dual-gate structure to achieve precise control of the transistor threshold voltage and further improve the electrical performance and stability of the device.

[0090] After forming the second metal layer 5 (including the first electrode 51 and the second electrode 52), a second insulating layer 7 is formed on the side of the second metal layer 5 away from the substrate 1. The material of the second insulating layer 7 preferably includes inorganic materials, such as silicon nitride (SiNx), silicon oxide (SiO2), or silicon oxynitride (SiON), which gives it excellent insulation properties and the ability to block water and oxygen.

[0091] In this embodiment, as Figure 9 As shown, the orthographic projection of the second insulating layer 7 onto the substrate 1 not only covers the orthographic projection of the second metal layer 5 onto the substrate 1, but also covers the orthographic projection of the active layer 4 onto the substrate 1. The second insulating layer 7 fills in the source, drain, and active layer structure 41 below, providing a flat base for the upper metal layer.

[0092] The third metal layer 8 is located on the side of the second insulating layer 7 away from the substrate 1. The third metal layer 8 includes the second gate 81 of the first transistor T. The orthogonal projection of the second gate 81 onto the substrate 1 covers the orthogonal projection of the channel region onto the substrate 1. Since the channel region is located in the active layer 4 and is opposite to the first gate 31, the second gate 81 corresponds exactly to the channel region in the vertical direction.

[0093] During the fabrication process, the second insulating layer 7 can be formed using processes such as atomic layer deposition or plasma-enhanced chemical vapor deposition. Since the second insulating layer 7 is deposited over the entire surface, it seamlessly covers the first electrode 51 and the second electrode 52 of the second metal layer 5, as well as the surface of the active layer 4. Subsequently, a metal material (such as molybdenum, aluminum, or copper) is deposited on the second insulating layer 7, and a third metal layer 8 and a second gate electrode 81 are formed through a patterning process.

[0094] The second gate 81 serves as a control gate. By applying a specific bias voltage, the carrier concentration in the channel region of the active layer 4 can be effectively adjusted, thereby precisely controlling the threshold voltage of the transistor. Unlike related technologies that require connecting electrodes of different layers through vias, the second insulating layer 7 in this embodiment is a continuous, full-surface layer, and the second gate 81 is formed directly on it, avoiding the risk of interlayer short circuits caused by via alignment deviations or poor filling.

[0095] The second insulating layer 7 completely covers the underlying metal traces and active layer 4, providing excellent protection and preventing damage to the underlying structure from subsequent processes. Simultaneously, the second gate 81 completely covers the channel region, ensuring the effectiveness and reliability of electric field control and resolving the technical problem in related technologies where complete coverage is impossible due to the presence of vias.

[0096] This embodiment introduces a second gate structure composed of a second insulating layer 7 and a third metal layer 8. While retaining the advantages of the long vertical channel in the first embodiment, it increases the ability to control the threshold voltage, significantly improving the performance and yield of thin-film transistors in high PPI display applications.

[0097] Third Embodiment

[0098] like Figure 1 , Figure 9 As shown, an array substrate suitable for high-resolution OLED display panels effectively suppresses short-channel effects and improves the performance of pixel driving circuits by introducing a vertical channel structure. The array substrate includes a first transistor T, a substrate 1, a spacer layer 2, a first metal layer 3, an active layer 4, and a second metal layer 5. The third embodiment differs from the first embodiment in that the array substrate further includes a third insulating layer 9 to address the surface step problem caused by the underlying vertical structure and to achieve physical and electrical isolation between layers.

[0099] The third insulating layer 9 serves as an interlayer dielectric layer, and its specific location varies depending on the underlying structure.

[0100] In the first embodiment, the third insulating layer 9 covers the second metal layer 5 and the active layer 4. In this case, the third insulating layer 9 not only fills the gap between the second metal layer 5 (the first electrode 51 and the second electrode 52), but also completely covers the exposed surface of the active layer 4, including the first portion 411 corresponding to the vertical channel region within the trench 22 and the second portion 412 located on the flat surface. The third insulating layer 9 physically completely isolates the underlying second metal layer 5 and the active layer 4 from the subsequently fabricated upper structure, preventing short circuits.

[0101] In the second embodiment, the third insulating layer 9 covers the third metal layer 8. At this time, the third insulating layer 9 is located on the side of the third metal layer 8 (second gate 81) away from the substrate 1.

[0102] Due to the presence of the second metal layer 5 and the trench 22, the bottom surface has significant undulations (steps). In order to fabricate subsequent functional layers (such as pixel electrodes) on this uneven surface, the thickness of the third insulating layer 9 is specifically designed in this embodiment.

[0103] The thickness of the third insulating layer 9 is greater than the thickness of the second insulating layer 7 (based on the first embodiment) or greater than the thickness of the first insulating layer 6 (based on the second embodiment). The thicker insulating layer has a stronger step coverage capability.

[0104] The third insulating layer 9 is used to achieve global planarization. After the third insulating layer 9 is deposited, its surface is polished by chemical mechanical polishing (CMP) to eliminate the steps caused by the vertical structure of the underlying layer, and to process the uneven surface of the underlying layer into a smooth plane. After CMP treatment, the surface flatness of the third insulating layer 9 can meet the stringent requirements of subsequent photolithography processes (such as the fabrication of pixel electrodes).

[0105] The material selection for the third insulating layer 9 is diverse and can be flexibly chosen according to specific performance requirements. For example, organic materials can be selected. Organic materials include polyimide (PI), benzocyclobutene (BCB), or acrylic resin. Organic materials have a lower dielectric constant (k value), which can effectively reduce the parasitic capacitance between the source / drain electrodes and the upper metal layer, thereby improving the switching speed and high-frequency characteristics of the device.

[0106] For example, inorganic materials can be selected. Inorganic materials are one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), aluminum oxide (Al2O3), or hafnium oxide (HfO2). Inorganic materials possess high dielectric strength, good moisture barrier properties, and excellent semiconductor process compatibility.

[0107] For example, a multilayer structure can be chosen. The third insulating layer 9 can also be a composite structure of inorganic and organic insulating materials. For example, SiO2 or SiNx can be used at the bottom to provide water and oxygen barrier capabilities for the device due to their density; PI or BCB can be used at the top to achieve good planarization and reduce the k value due to their fluidity.

[0108] The third insulating layer 9 completely encapsulates the complex metal traces and active layer 4 structure below, preventing short-circuit risks with the upper structure and improving device reliability. By optimizing the thickness and combining it with CMP technology, the third insulating layer 9 effectively eliminates surface undulations caused by the underlying vertical channels and metal electrodes, providing a flat substrate for the fabrication of pixel electrodes in high PPI display panels, ensuring the film quality and patterning accuracy of the pixel electrodes.

[0109] This embodiment solves the planarization and interlayer isolation problems in multilayer structures by adding a third insulating layer 9 with specific thickness and material properties, while retaining the advantages of the vertical channel structure, thus providing a process basis for the fabrication of highly integrated, high-resolution OLED display panels.

[0110] Fourth embodiment

[0111] like Figure 1 As shown, an array substrate suitable for high-resolution OLED display panels effectively suppresses short-channel effects and improves the performance of pixel driving circuits by introducing a vertical channel structure. The array substrate includes a first transistor T, a substrate 1, a spacer layer 2, a first metal layer 3, an active layer 4, and a second metal layer 5. Compared with the previous embodiments, this embodiment defines the specific geometric layout of the channel region, the cross-sectional shape of the trench 22, and the dimensional relationship between the channel region and the source / drain electrodes, further optimizing the electrical performance and process yield of the transistor.

[0112] In this embodiment, as Figure 1 As shown, the orthographic projection of the channel region on the second metal layer 5 is located between the first electrode 51 and the second electrode 52. For example, the orthographic projection of the second surface 511 on the substrate 1 has a first dimension l, the orthographic projection of the fourth surface 521 on the substrate 1 has a second dimension m, the orthographic projection of the first surface 21 on the substrate 1 has a third dimension n, and the dimension of the orthographic projection of the channel region on the substrate 1 is p, which satisfies p = n - (l + m).

[0113] The horizontal projection size of the channel region is equal to the total horizontal projection size of the spacer layer 2 minus the width of the source and drain electrodes. This ensures the precise positioning of the channel region in the horizontal direction, avoids the erosion of the channel by the source and drain electrodes, and thus effectively suppresses the short-channel effect.

[0114] In this embodiment, as Figure 1 As shown, the first part 411 of the active layer 4 includes a first sub-channel region 4111 and a second sub-channel region 4112.

[0115] The first sub-channel region 4111 is disposed opposite to the bottom wall 221 of the trench 22 and is located at the bottom of the trench 22. It is relatively less affected by the gate electric field. The second sub-channel region 4112 is disposed opposite to the side wall 222 of the trench 22 and is located on the side wall of the trench 22. It is controlled by the gate electric field and is the main conductive channel.

[0116] The first sub-channel region 4111 and the second sub-channel region 4112 form a preset angle, which ranges from [90°, 150°].

[0117] When the included angle is 90° (i.e., rectangular trench 22), the fabrication difficulty is lowest, and the gate's coverage control over the channel is strongest. When the included angle is 100°, 110°, 120°, 130°, 140°, or 150°, the sidewalls of trench 22 form slopes, creating an inclined path in the channel region. This slope structure not only further increases the effective transport path length of charge carriers (achieving a larger equivalent channel length at the same trench 22 depth), but also makes the active layer 4 more gentle when covering the opening of trench 22, avoiding film breakage caused by excessively steep steps and significantly improving device yield.

[0118] Trench 22 adopts an inverted trapezoidal (wider at the top and narrower at the bottom) cross-section. During the etching of spacer layer 2, the slope is formed on the sidewalls by adjusting the proportion of etching gas and utilizing the polymer deposition effect. The inverted trapezoidal structure makes the electric field lines distributed more smoothly on the sloping sidewalls, avoiding electric field concentration at the corners of the rectangular trench, significantly reducing the standard deviation of the threshold voltage, and improving the uniformity of the panel display. By setting the extension direction of the channel region to be perpendicular to the substrate 1 and located within the trench 22, the decoupling of "small horizontal area" and "long channel length" is successfully achieved. The channel length is no longer limited by the minimum feature size in the horizontal space, but by the film thickness in the vertical direction, which is easy to control and has high precision, thus solving the area technology problem of pixel driving circuits in high PPI OLED panels.

[0119] The second part 412 is located on both sides of the trench 22, serving as a bridge connecting the vertical channel and the planar electrode. The actual path length of the channel region (i.e., the total distance of carrier transport) is equal to the sum of the first part 411 (vertical path) and the second part 412 (horizontal path), forming a "folded path".

[0120] The second part 412 serves as a contact transition region, acting as a buffer between the second metal layer 5 and the first part 411. The second metal layer 5 forms a large-area planar contact with the active layer 4 through the planar second part 412, effectively reducing contact resistance. The second part 412 provides a wider carrier injection path, ensuring efficient connectivity between the source / drain and the channel region.

[0121] This embodiment achieves long channel characteristics with a very small horizontal projected area by precisely defining the size relationship between the channel region and the electrode, adopting an inverted trapezoidal trench structure with a specific included angle, and optimizing the segmented design of the channel region. At the same time, it improves the electric field distribution and film coverage quality, greatly enhancing the performance uniformity and production yield of thin film transistors. It is particularly suitable for pixel driving circuits of high PPI OLED display panels.

[0122] Fifth embodiment

[0123] like Figure 1 , Figure 9 As shown, an array substrate integrates a pixel driving circuit. The pixel driving circuit is used to drive display units (such as OLED light-emitting devices) for display, and includes at least one first transistor T. The first transistor T adopts the vertical channel structure in the aforementioned embodiments. By setting trenches 22 in the spacer layer 2 and utilizing buried gates and capped active layers, a balance between long channel characteristics and small planar area is achieved, making it particularly suitable for high-resolution (high PPI) display panels.

[0124] In this embodiment, as Figure 1 , Figure 9As shown, the pixel driving circuit includes a driving module and at least one switching module.

[0125] The driving module provides driving current to illuminate the pixel units. In this embodiment, the transistor in the driving module is the first transistor T. Because the driving module needs to carry a large current to ensure display brightness, the driving capability of the transistor is required to be high.

[0126] The switching module is used to control the writing and cutoff of signals. In this embodiment, the switching module includes at least a data writing module, and the transistor in the data writing module is also a first transistor T. The data writing module is mainly responsible for transmitting the data voltage signal to the gate or source of the driving module. Its main requirements are high-speed switching characteristics and low leakage current, and the requirement for driving current is relatively low.

[0127] In this embodiment, the pixel driving circuit includes a plurality of first transistors T. In order to optimize circuit performance within a limited pixel space, this embodiment has differentiated the design of the first transistors T in different functional modules.

[0128] For example, the area of ​​the channel region of the corresponding first transistor T in the driving module projected onto the substrate 1 is greater than the area of ​​the channel region of the corresponding first transistor T in the data writing module projected onto the substrate 1.

[0129] To achieve a larger drive current, the first transistor T in the drive module employs a larger trench 22 size and / or a wider active layer coverage. This results in a larger projected area of ​​its channel region, thereby increasing the channel width, effectively reducing on-resistance, and improving current drive capability.

[0130] The data writing module performs the switching function and does not require a large current. Therefore, its corresponding first transistor T uses a relatively small trench 22 size and active layer coverage, resulting in a small projected area of ​​the channel region. This not only meets the switching speed requirements but also significantly reduces the planar area occupied by the transistor, which is beneficial for achieving a high aperture ratio and high integration density of the pixel.

[0131] In this embodiment, the first transistor T of the vertical channel structure is applied to the pixel driving circuit. By precisely controlling the ratio of the orthogonal projection area of ​​the transistor channel region in the driving module and the data writing module, the defect between driving capability and pixel area in the high-resolution display panel is successfully solved, and the overall performance of the display panel is improved.

[0132] Sixth Embodiment

[0133] A display panel includes an array substrate as described in any of the above embodiments. The display panel provided in this embodiment, by employing an array substrate with a vertical channel structure, achieves long-channel characteristics within a very small horizontal projected area, effectively suppressing short-channel effects. This allows the display panel to maintain good electrical performance and uniformity even at high resolutions.

[0134] By integrating the aforementioned array substrate, this display panel achieves high resolution, high aperture ratio, low power consumption, and high reliability, making it particularly suitable for high-end OLED display products.

[0135] Seventh Embodiment

[0136] A method for fabricating an array substrate, suitable for high-resolution OLED display panels, effectively suppresses short-channel effects and improves the performance of pixel driving circuits by constructing thin-film transistors with vertical channel structures. Figure 2 As shown, the method for fabricating the array substrate includes the following steps:

[0137] S1, Provide a substrate.

[0138] In step S1, as Figure 3 As shown, glass was selected as substrate 1. It underwent pretreatment to remove surface impurities, consisting of ultrasonic cleaning with deionized water, acetone, and ethanol in sequence, followed by drying with high-purity nitrogen and baking in an oven to remove moisture. This pretreatment provides a flat, clean device substrate, ensuring the adhesion of subsequent thin films.

[0139] S2. A spacer layer is formed on one side of the substrate. The spacer layer includes a first surface facing away from the substrate. The spacer layer is patterned to form a trench on the first surface that is recessed toward the substrate.

[0140] In step S2, as Figure 4 As shown, the spacer layer 2 can be made of organic materials. The ease with which organic materials can be formed into larger thicknesses provides a basis for the subsequent formation of deep trenches. The spacer layer 2 has a first surface 21 facing away from the substrate 1.

[0141] Subsequently, the spacer layer 2 is patterned. For example, photoresist is coated on the surface of the spacer layer 2, and ultraviolet or yellow light is applied through a mask. After development, the photoresist in the exposed area is removed to expose the area to be etched. A trench 22 is formed on the first surface 21 facing the substrate 1 using reactive ion etching or inductively coupled plasma etching.

[0142] The trench 22 has a first orthographic projection on the substrate 1, and the first surface 21 located outside the trench 22 has a second orthographic projection on the substrate 1. By controlling the ratio of etching gas, the sidewalls of the trench 22 are sloped using the polymer deposition effect, thereby obtaining an inverted trapezoidal (wider at the top and narrower at the bottom) cross-sectional shape to facilitate the step coverage of subsequent metal layers and prevent line breaks. After etching, residual photoresist is removed using oxygen plasma ashing or wet photoresist stripping solution.

[0143] S3. A first metal layer is formed on the first surface using physical vapor deposition or atomic layer deposition techniques, and the first metal layer is patterned to form the first gate of the first transistor.

[0144] In step S3, as Figure 5 As shown, a first metal layer 3 is formed on the first surface 21 using either physical vapor deposition (PVD) or atomic layer deposition (ALD) techniques. If PVD is used, one or more layers of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), or indium tin oxide (ITO) can be deposited to ensure low resistivity and high etching resistance. If ALD is used, its excellent conformability ensures uniform coverage of the metal layer on the bottom and sidewalls of the deep trench.

[0145] The first metal layer 3 is photolithographically and dry-etched to form the first gate 31 of the first transistor T.

[0146] The orthogonal projection of the first gate 31 on the substrate 1 at least partially covers the first orthogonal projection (i.e., the projection of the trench 22), and the first gate 31 is buried inside the trench 22. Due to the use of PVD or ALD technology, the first gate 31 can completely fill the trench 22 and provide sufficient conductive cross-sectional area.

[0147] S4. An active layer is formed on the side of the first metal layer away from the substrate, and the active layer is insulated from the first metal layer; wherein, physical vapor deposition or atomic layer deposition technology is used to form the active layer film, and the active layer is patterned to form an active structure.

[0148] In step S4, as Figure 6 As shown, an active layer 4 is formed on the side of the first metal layer 3 away from the substrate 1. The active layer 4 is isolated from the first metal layer 3 by an insulating layer. The active layer 4 is formed using physical vapor deposition (PVD) or atomic layer deposition (ALD) techniques.

[0149] When the active layer 4 is made of oxide semiconductor (such as IGZO material containing In, Ga, Zn, and O), the ALD process is used. The ALD process forms a film through a self-limiting surface chemical reaction, which has excellent conformal properties and step coverage. It can ensure that the active layer 4 is uniformly covered on the sidewalls, bottom walls, and flat surface of the spacer layer 2 of the first gate 31, which is beneficial to achieving high carrier mobility, low off-state current, and excellent threshold voltage uniformity.

[0150] When the active layer 4 is made of amorphous silicon or polycrystalline silicon, PVD deposition can be used.

[0151] The active layer 4 is photolithographically and etched to form an active structure 41. The active structure 41 includes a channel region, and at least a portion of the channel region and at least a portion of the first gate 31 are disposed opposite to each other. The active structure 41 includes a first portion 411 and a second portion 412.

[0152] The orthographic projection of the first part 411 on the substrate 1 at least partially covers the first orthographic projection (the trench 22 projection), and the trench 22 of the spacer layer 2 forms a vertical conductive channel, the length of which is determined by the depth of the trench 22.

[0153] The orthographic projection of the second part 412 on the substrate 1 at least partially covers the second orthographic projection (outer surface of trench 22), serving as the region in contact with the source and drain electrodes.

[0154] S5. A second metal layer is formed on the side of the active layer away from the substrate, and the second metal layer is patterned to form the first electrode of the first transistor.

[0155] In step S5, as Figure 7 As shown, a second metal layer 5 is formed on the side of the active layer 4 away from the substrate 1. The second metal layer 5 is formed using magnetron sputtering deposition, photolithography, and dry etching processes.

[0156] The second metal layer 5 includes a first electrode 51 (source or drain) of the first transistor T. The first electrode 51 includes a second surface 511 facing the substrate 1, which is in direct contact with the second portion 412 of the active layer 4.

[0157] Since the second part 412 of the active layer 4 extends to the flat surface outside the trench 22 (i.e., the second orthographic projection area), the first electrode 51 can directly contact this part without the need for vias, thus eliminating the need for the process steps of preparing the insulating layer and drilling, simplifying the process, reducing costs, and ensuring good ohmic contact between the source / drain electrode and the active layer 4.

[0158] It should be noted that between steps S3 and S4 above, such as Figure 1As shown, the process may also include the step of forming a first insulating layer 6. The first insulating layer 6 is deposited using an atomic layer deposition (ALD) process, and the materials include silicon oxide, silicon nitride, aluminum oxide, etc. The excellent conformality of the ALD process ensures that the first insulating layer 6 can uniformly cover the sidewalls and bottom of the first gate 31 without any breaks, effectively preventing short circuits between the first gate 31 and the active layer 4.

[0159] After step S5, as Figure 1 As shown, the process may also include the step of forming a third insulating layer 9. The third insulating layer 9 is deposited on the second metal layer 5 and the active layer 4, and planarized by a chemical mechanical polishing process to eliminate the steps caused by the vertical structure of the underlying layer, providing a flat substrate for the subsequent fabrication of pixel electrodes.

[0160] The fabrication method of this embodiment precisely controls the etching of trench 22, deposits functional layers using PVD or ALD technology, and utilizes the precise alignment of orthographic projection to fabricate thin-film transistors with vertical long-channel characteristics, thus solving the area problem and short-channel effect problem of pixel driving circuits in high-resolution display panels.

[0161] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0162] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An array substrate, characterized in that, The array substrate includes a first transistor and comprises: Substrate; A spacer layer, located on one side of the substrate, the spacer layer includes a first surface facing away from the substrate, the first surface having at least one trench recessed toward the substrate, the trench having a first orthographic projection on the substrate, and the first surface located outside the trench having a second orthographic projection on the substrate; A first metal layer, located on the first surface, includes a first gate of the first transistor, wherein the orthogonal projection of the first gate onto the substrate at least partially covers the first orthogonal projection. An active layer, insulated from the first metal layer, is located on the side of the first metal layer away from the substrate. The active layer includes an active structure, which includes a channel region. At least a portion of the channel region and at least a portion of the first gate are disposed opposite each other. The active structure includes a first portion and a second portion. The orthographic projection of the first portion on the substrate at least partially covers the first orthographic projection, and the orthographic projection of the second portion on the substrate at least partially covers the second orthographic projection. A second metal layer is located on the side of the active layer away from the substrate. The second metal layer includes a first electrode of the first transistor, and the first electrode of the first transistor includes a second surface facing the substrate. The second surface is in contact with the second portion.

2. The array substrate according to claim 1, characterized in that, The first electrode of the first transistor includes a third surface remote from the substrate, and the orthographic projection of the third surface onto the substrate lies within the orthographic projection of the second surface onto the substrate; Preferably, the edge of the channel region in the orthographic projection of the substrate coincides with the edge of the first electrode of the first transistor in the orthographic projection of the substrate; Preferably, the trench includes a bottom wall opposite to the substrate, and the orthographic projection of the trench region onto the bottom wall at least partially overlaps with the orthographic projection of the first gate onto the bottom wall; Preferably, the trench includes a sidewall surrounding the bottom wall, and the orthographic projection of the trench region onto the sidewall at least partially overlaps with the orthographic projection of the first gate onto the sidewall. Preferably, the material of the spacer layer includes an organic insulating material; Preferably, the array substrate further includes a first insulating layer located between the first metal layer and the active layer, wherein the first insulating layer at least covers the first gate. Preferably, the material of the first insulating layer includes inorganic materials; Preferably, the second metal layer further includes a second electrode of the first transistor, the second electrode of the first transistor including a fourth surface facing the substrate, the fourth surface being in contact with the second portion; Preferably, the second electrode of the first transistor includes a fifth surface remote from the substrate, the orthographic projection of the fifth surface onto the substrate being within the orthographic projection of the fourth surface onto the substrate.

3. The array substrate according to claim 1, characterized in that, Also includes: The second insulating layer is located on the side of the second metal layer and the active layer away from the substrate, and the orthographic projection of the second insulating layer on the substrate covers the orthographic projection of the second metal layer on the substrate and the orthographic projection of the active layer on the substrate. A third metal layer, located on the side of the second insulating layer away from the substrate, includes the second gate of the first transistor, the orthogonal projection of the second gate onto the substrate covering the orthogonal projection of the channel region onto the substrate; Preferably, the material of the second insulating layer includes inorganic materials.

4. The array substrate according to claim 3, characterized in that, Also includes: A third insulating layer is located on the side of the third metal layer away from the substrate, and the thickness of the third insulating layer is greater than the thickness of the first insulating layer, and / or the thickness of the third insulating layer is greater than the thickness of the second insulating layer; Preferably, the material of the third insulating layer includes organic materials; Preferably, the active layer is made of at least one of oxide semiconductor, monocrystalline silicon, polycrystalline silicon, and amorphous silicon.

5. The array substrate according to claim 2, characterized in that, The orthogonal projection of the channel region onto the second metal layer is located between the first electrode and the second electrode; Preferably, the orthographic projection of the second surface on the substrate has a first dimension l, the orthographic projection of the fourth surface on the substrate has a second dimension m, the orthographic projection of the first surface on the substrate has a third dimension n, and the orthographic projection of the channel region on the substrate has a dimension p = n - (l + m).

6. The array substrate according to claim 1, characterized in that, The first part includes a first sub-channel area disposed opposite to the bottom wall of the trench and a second sub-channel area disposed opposite to the side wall of the trench, such that the first sub-channel area and the second sub-channel area form a preset angle. Preferably, the range of the preset included angle is [90°, 150°].

7. The array substrate according to claim 1, characterized in that, The array substrate includes a pixel driving circuit, and the pixel driving circuit includes at least one of the first transistors; Preferably, the pixel driving circuit includes a driving module and at least one switching module, wherein at least one transistor in the driving module and the at least one switching module is the first transistor.

8. The array substrate according to claim 7, characterized in that, The pixel driving circuit includes a plurality of first transistors, and the at least one switching module includes a data writing module. The transistor in the driving module is one of the plurality of first transistors, and the transistor in the data writing module is one of the plurality of first transistors, wherein: The area of ​​the channel region of the first transistor in the driving module projected onto the substrate is greater than the area of ​​the channel region of the first transistor in the data writing module projected onto the substrate.

9. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-8.

10. A method for fabricating an array substrate, characterized in that, include: Provide substrate; A spacer layer is formed on one side of the substrate, the spacer layer including a first surface facing away from the substrate, the spacer layer is patterned to form a trench recessed toward the substrate on the first surface, the trench having a first orthographic projection on the substrate, and the first surface located outside the trench having a second orthographic projection on the substrate. A first metal layer is formed on the first surface using physical vapor deposition or atomic layer deposition techniques. The first metal layer is then patterned to form the first gate of the first transistor. The orthogonal projection of the first gate onto the substrate at least partially covers the first orthogonal projection. An active layer is formed on the side of the first metal layer away from the substrate, and the active layer is insulated from the first metal layer; wherein, the active layer is formed by physical vapor deposition or atomic layer deposition, and the active layer is patterned to form an active structure, the active structure including a channel region, at least a portion of the channel region and at least a portion of the first gate are disposed opposite to each other, the active structure includes a first part and a second part, the orthographic projection of the first part on the substrate at least partially covers the first orthographic projection, and the orthographic projection of the second part on the substrate at least partially covers the second orthographic projection; A second metal layer is formed on the side of the active layer away from the substrate, and the second metal layer is patterned to form a first electrode of the first transistor. The first electrode of the first transistor includes a second surface facing the substrate, and the second surface is in contact with a second portion of the active layer.

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