A display driving method and a display apparatus

Abstract

The application discloses a display driving method and a display device. The display driving method comprises the following steps: acquiring a pixel driving signal; detecting whether the pixel driving signal belongs to a pixel data signal; if the pixel driving signal does not belong to the pixel data signal, closing the control switch, so that the connection line between the output buffer and the voltage providing module is switched to a disconnected state. The application avoids keeping the output buffer in an open state, reduces the working duration of the output buffer, and further reduces the product power consumption.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display panel driving, and in particular to a display driving method and display device. BACKGROUND

[0002] With the pursuit of color and display utility of display panels, flat panel display panels including LCD (Liquid Crystal Display) and OLED (Organic Light Emitting Diode) are widely used in mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, desktop computers and other consumer electronic products due to their high image quality, power saving, thin body and wide application range, and have become the mainstream of display devices.

[0003] Among them, LCD has become the mainstream display technology in the market due to its high brightness, long service life, wide viewing angle, large size display and other advantages. LCD mainly consists of PCB (Printed Circuit Board), SDIC (Source Driver Integrated Circuit) and OC (open cell, liquid crystal display panel).

[0004] With the rapid development of display technology, users have higher and higher requirements for the power consumption of display devices, and thus the energy saving demand for display devices is becoming more and more stringent. Since the SDIC provides the deflection voltage for driving the OC, the power consumption accounts for a large proportion, therefore, how to reduce the driving power consumption of the SDIC, thereby reducing the power consumption of the OC and further reducing the power consumption of the LCD is an urgent problem to be solved. SUMMARY

[0005] The embodiments of the present application provide a display driving method and display device, which solve the technical problem of large power consumption of SDIC.

[0006] In a first aspect, the embodiments of the present application provide a display device, which comprises a source driver and a timing controller, the source driver is connected with the timing controller, the source driver comprises an output buffer, a voltage providing module and a control switch, the output buffer and the voltage providing module are connected through the control switch, and the timing controller comprises:

[0007] an acquisition module, configured to acquire a pixel driving signal;

[0008] a detection module, configured to detect whether the pixel driving signal belongs to a pixel data signal;

[0009] a control module configured to:

[0010] In some embodiments, the control module is configured to:

[0011] In some embodiments, the control module is configured to:

[0012] In some embodiments, the display device further comprises a display panel, the first end and the second end of the control switch are connected with the voltage providing module and the output buffer respectively, the timing controller comprises a buffer control pin, the buffer control pin is connected with the third end of the control switch; wherein,

[0013] In some embodiments, when the pixel driving signal belongs to the pixel data signal, the control module is configured to switch the buffer control pin from a first level to a second level, triggering the control switch to open, so that the connection line is connected to start transmitting the gray scale voltage output by the voltage providing module to the display panel.

[0014] In some embodiments, when the pixel driving signal does not belong to the pixel signal, the control module is configured to switch the buffer control pin from the second level to the first level, triggering the control switch to close, so that the connection line is disconnected to stop transmitting the gray scale voltage output by the voltage providing module to the display panel.

[0015] In some embodiments, the control switch is an N-type MOS tube, the first end, the second end and the third end are drain, source and gate respectively, and the first level is less than the second level.

[0016] In some embodiments, the control switch is a P-type MOS tube, the first end, the second end and the third end are source, drain and gate respectively, and the first level is greater than the second level.

[0017] In some embodiments, the display device further comprises a power supply circuit for providing an initial gray scale voltage, the voltage providing module is connected with the power supply circuit, and the voltage providing module is configured to access the initial gray scale voltage and output multiple gray scale voltages.

[0018] In some embodiments, the voltage providing module comprises:

[0019] a plurality of operational amplifiers connected in sequence on an output line of the power supply circuit, and any number of the operational amplifiers are cascaded according to the number of the initial gray scale voltages;

[0020] a plurality of voltage division resistors connected in sequence on an output line of the operational amplifier;

[0021] a plurality of gating units connected between the corresponding voltage division resistor and the control switch, and the corresponding gray scale voltage is output by a switch control signal output by the operational amplifier;

[0022] The first input terminal of the operational amplifier is connected to the output line of the power supply circuit, the output terminal of the operational amplifier is connected to the second input terminal of the operational amplifier and the corresponding voltage division resistor, and the output line of the gating unit is connected to the first terminal of the control switch.

[0023] In some embodiments, each of the gating units comprises: a first gating switch and a second gating switch; and the first gating switch and the second gating switch are connected in parallel.

[0024] The first gating switch and the second gating switch of the Nth gating unit are connected to two adjacent previous nodes, respectively.

[0025] The two adjacent previous nodes of the Nth gating unit are two adjacent voltage division resistors, the two adjacent previous nodes of the N+1th gating unit are two adjacent Nth gating units, and N is a positive integer.

[0026] In some embodiments, the detection module is configured to:

[0027] parse the pixel driving signal to obtain parsed data;

[0028] determine whether a preset identifier corresponding to the pixel data signal is found in the parsed data;

[0029] If the preset identifier is found in the parsed data, it is determined that the pixel driving signal belongs to the pixel data signal, and if the preset identifier is not found in the parsed data, it is determined that the pixel driving signal does not belong to the pixel data signal.

[0030] In a second aspect, the embodiments of the present application also provide a display driving method for a display device, wherein the display device comprises a source driver and a timing controller, the source driver is connected to the timing controller, the source driver comprises an output buffer, a voltage providing module and a control switch, the output buffer and the voltage providing module are connected through the control switch, and the display driving method comprises:

[0031] Acquire pixel drive signals;

[0032] Detect whether the pixel driving signal belongs to the pixel data signal;

[0033] If the pixel driving signal does not belong to the pixel data signal, the control switch is turned off so that the connection line between the output buffer and the voltage supply module is switched to the disconnected state.

[0034] The beneficial effects of this application are as follows: When the display panel is powered on and in normal driving operation, the source driver can determine whether the pixel driving signal received from the timing controller belongs to the pixel data signal. Then, based on the determination result of whether the pixel driving signal belongs to the pixel data signal, the source driver switches the on or off state of the output buffer that provides grayscale voltage to the display panel while ensuring the correct display effect during the non-display period of the display panel. This avoids the output buffer being in the on state all the time, reduces the working duration of the output buffer, and thus reduces the power consumption of the product. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of a state in which the output buffer receives a pixel driving signal, as provided in an embodiment of this application.

[0037] Figure 2 This is a schematic diagram of the structure of the display device provided in the embodiments of this application;

[0038] Figure 3 This is a flowchart illustrating the display driving method provided in an embodiment of this application;

[0039] Figure 4 This is a schematic diagram of another state of the output buffer receiving the pixel driving signal provided in the embodiments of this application;

[0040] Figure 5 This is a schematic diagram of the source driver provided in an embodiment of this application;

[0041] Figure 6 This is a schematic diagram of the voltage supply module provided in an embodiment of this application;

[0042] Figure 7 This is a schematic diagram of a circuit principle provided in an embodiment of this application;

[0043] Figure 8 This is another circuit schematic diagram provided in the embodiments of this application. Detailed Implementation

[0044] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0045] In the description of this application, it should be understood that the terms "one end," "the other end," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, the meaning of "" is two or more, unless otherwise explicitly specified.

[0046] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, a link, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0047] The following disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed. In the above embodiments, the descriptions of each embodiment have their own emphasis; parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments.

[0048] This application provides a display driving method. The display panel in the embodiments of this application can be used in mobile phones, tablets, desktop computers, laptops, e-readers, handheld computers, electronic display screens, laptops, ultra-mobile personal computers (UMPCs), netbooks, as well as cellular phones, personal digital assistants (PDAs), augmented reality (AR) / virtual reality (VR) devices, media players, wearable devices, digital cameras, car navigation systems, etc.

[0049] The display panel can be a liquid crystal display panel. This application does not limit the type of liquid crystal display panel. The liquid crystal display panel provided in this application can be a horizontal electric field type liquid crystal display panel, such as a fringe field switching (FFS) type liquid crystal display panel or an in-plane switching (IPS) type liquid crystal display panel, or a vertical electric field type liquid crystal display panel, such as a twisted nematic (TN) type liquid crystal display panel or a multi-domain vertical alignment (MVA) type liquid crystal display panel.

[0050] Please see Figure 2 and Figure 3 , Figure 2 This is a flowchart illustrating the display driving method provided in an embodiment of this application. Figure 3 This is a schematic diagram of the structure of the display device 1 provided in an embodiment of this application. Figure 2 As shown, this display driving method is applied to Figure 3 The display device 1 shown includes a source driver 200 and a timing controller 100. The source driver 200 is connected to the timing controller 100. The source driver 200 includes an output buffer 210, a voltage supply module 220, and a control switch Q1. The output buffer 210 is connected to the voltage supply module 220 through the control switch Q1. The display driving method may include the following steps:

[0051] S100, Acquire pixel driving signal.

[0052] Specifically, such as Figure 1As shown, display device 1 may include a display panel 120 for displaying images and a display driving circuit 110. According to the example embodiment, display device 1 can be equipped in an electronic device with image display capabilities. For example, the electronic device may include a smartphone, a personal computer (PC), a portable multimedia player (PMP), a camera, a wearable device, a television (TV), a digital video disk (DVD) player, a refrigerator, an air conditioner, an air purifier, a set-top box, a robot, a drone, various medical devices, navigation devices, a global positioning system (GPS) receiver, vehicle equipment, furniture, or various measuring devices.

[0053] The display panel 120 may include a plurality of gate G lines GL1 to GLn (where n is an integer of 2 or greater), a plurality of data lines DL1 to DLm (where m is an integer of 2 or greater) arranged along a direction intersecting the plurality of gate G lines GL1 to GLn, and a plurality of pixel units 121 respectively disposed in a plurality of regions defined by the intersection of the gate G lines GL1 to GLn and the data lines DL1 to DLm.

[0054] For example, when the display panel 120 is a TFT-LCD, the pixel unit 121 may include a thin-film transistor (TFT), a liquid crystal capacitor connected to the drain D of the TFT, and a storage capacitor. The TFT includes a gate G and a source S connected to its corresponding gate G line and data line, respectively. Furthermore, when a gate G line is selected from multiple gate G lines GL1 to GLn, the TFT of the pixel unit 121 connected to the selected gate G line can be turned on, and then the source driver 200 can apply a data voltage to multiple data lines DL1 to DLm. The data voltage can be applied to the liquid crystal capacitor and storage capacitor via the TFT of the corresponding pixel unit 121, and the liquid crystal capacitor and storage capacitor can be driven by the data voltage, thereby enabling image display.

[0055] The display panel 120 may include multiple horizontal lines (or rows), and each horizontal line may be configured with pixel units 121 connected to a corresponding gate G line. For example, pixel units 121 connected to a first gate G line GL1 in a first row may be configured as a first horizontal line, and pixel units 121 connected to a second gate G line GL2 in a second row may be configured as a second horizontal line.

[0056] The display driving circuit 110 may include a timing controller 100 (TCON), a source driver integrated circuit 200 (SIDC), a gate driver integrated circuit 300 (GIDC), and a power supply circuit 400. The display driving circuit 110 can convert image data I_DATA received from the outside into multiple analog signals (e.g., multiple data voltages) for driving the display panel 120, and can provide the multiple analog signals to the display panel 120.

[0057] The timing controller 100 can control all operations of the display driving circuit 110. For example, the timing controller 100 can control the components of the display driving circuit 110 (e.g., the source driver 200 and the gate driver 300) so that the display panel 120 displays an image corresponding to the image data I_DATA received from the outside. Specifically, the timing controller 100 can generate pixel data RGB_DATA based on the received image data I_DATA and can output the pixel data RGB_DATA to the source driver 200. In addition, the timing controller 100 can generate various control signals for timing the source driver 200 and the gate driver 300. For example, the timing controller 100 can output a first control signal CTRL1 to the source driver 200 and a second control signal CTRL2 to the gate driver 300.

[0058] The source driver 200 can convert pixel data RGB_DATA received from the timing controller 100 into multiple image signals (e.g., multiple data voltages), and can output the multiple data voltages to the display panel 120 via multiple data lines DL1 to DLm. Specifically, the source driver 200 can receive pixel data in units of horizontal lines (i.e., in units of data corresponding to multiple pixel units 121 included in a horizontal line of the display panel 120). Furthermore, the source driver 200 can convert the pixel data RGB_DATA received from the timing controller 100 into multiple data voltages based on multiple initial grayscale voltages VG[1:a] (also known as Gamma voltages) received from the power supply circuit 400. Furthermore, the source driver 200 can output multiple data voltages to the display panel 120 in units of horizontal lines via multiple data lines DL1 to DLm. For example, the source driver 200 can output multiple data voltages corresponding to multiple pixel units 121 included in the first horizontal line of the display panel 120, and then can output multiple data voltages corresponding to multiple pixel units 121 included in the second horizontal line.

[0059] The gate driver 300 can be connected to multiple gate G lines GL1 to GLn of the display panel 120 and can sequentially drive the multiple gate G lines GL1 to GLn of the display panel 120. Based on the control of the timing controller 100, the gate driver 300 can sequentially provide multiple gate G-on signals with valid levels (e.g., logic high levels) to the multiple gate G lines GL1 to GLn. Therefore, multiple gate G lines GL1 to GLn can be sequentially selected, and multiple data voltages can be applied to the pixel units 121 of the horizontal lines corresponding to the selected gate G lines via multiple data lines DL1 to DLm.

[0060] The power supply circuit 400 can generate various voltages for driving the display device 1. For example, the power supply circuit 400 can receive the source S voltage from an external source. Furthermore, the power supply circuit 400 can generate multiple initial grayscale voltages VgrayG[1:a] and a common voltage VCOM, and can output these multiple initial grayscale voltages VgrayG[1:a] and the common voltage VCOM to the source driver 200. Additionally, the power supply circuit 400 can generate and provide a gate G on-state voltage that switches the gate driver 300 to the on state, and a gate G off-state voltage that switches the gate driver 300 to the off state.

[0061] like Figure 1 As shown, the source driver 200 receives pixel drive signals from the timing controller 100 at the front end. The source driver 200 includes, but is not limited to, internal modules such as control logic 240, voltage supply module 220, data buffer, shift register, decoder, data latch, level shifter, digital-to-analog converter (DAC), and output buffer 210. Thus, the source driver 200 transmits the received pixel drive signals to the corresponding pixel unit 121 on the display panel 120 via the aforementioned internal modules.

[0062] The source driver 200 can output data voltages Y1 to Ym for driving the display panel 120 through m channels. The data voltages Y1 to Ym can be signals provided for driving pixel units 121 of the display panel 120 connected to a gate G line, and the data voltages Y1 to Ym can be output to m gate G lines GL1 to GLm.

[0063] A potential transferor is used to convert the low-voltage timing signal provided by the timing controller 100 into a high-voltage switching voltage signal to drive the thin-film transistors of the pixel unit 121 on the array substrate. A digital-to-analog converter is used to convert digital signals into analog signals.

[0064] The data latch can receive and latch multiple pixel data D1 to D2 for driving the display panel 120. m / 2 Pixel data D1 to D m / 2 It can be from Figure 1 The timing controller 100 provides pixel data RGB_DATA. The data latch can receive and store multiple pixel data D1 to D... m / 2 And it can store pixel data D1 to D m / 2 The parallel output is sent to the decoder. The decoder can process the pixel data D1 to D2 corresponding to the digital signal. m / 2 Decoded into grayscale voltages Vgray1 to Vgray m / 2 The grayscale voltage Vgray1 to Vgray from the decoder output. m / 2 The voltage supply module 220 can further divide the voltage to generate more grayscale voltages, such as Vgray1 to Vgraym. In other words, the voltage supply module 220 can achieve a small input and a large output, meaning it can generate a small amount of grayscale voltages from Vgray1 to Vgraym. m / 2 A more precise division yields a large number of grayscale voltages Vgray1 to Vgraym with more voltage values. The grayscale voltages Vgray1 to Vgraym output from the voltage supply module 220 can be provided as data voltages Y1 to Ym to data lines DL1 to DLm via the output buffer 210. The output buffer 210 receives and buffers the grayscale voltages Vgray1 to Vgraym to generate data voltages Y1 to Ym for driving data lines DL1 to DLm, which are then provided to each pixel unit 121. That is, the aforementioned internal module in the source driver 200 is responsible for converting digital image data into corresponding data voltages, and the final stage output buffer 210 converts these data voltages into corresponding grayscale voltages, enabling the output buffer 210 to drive the display panel 120. Based on m channels, m output buffers 210 can be included.

[0065] S200: Detect whether the pixel driving signal belongs to the pixel data signal.

[0066] S300. If the pixel driving signal does not belong to the pixel data signal, turn off the control switch Q1 so that the connection line between the output buffer 210 and the voltage supply module 220 is switched to the disconnected state.

[0067] Specifically, such as Figure 1As shown, a row of pixel driving signals consists of HBP (Horizontal Blank Period), command start signal, register configuration signal, pixel data signal, control signal, and VBP (Vertial Blank Period). The horizontal blank period refers to the interval between the end of one row of pixel data transmission and the start of the next row of pixel data transmission. The vertical blank period refers to the interval between the end of one frame of data transmission and the start of the next frame of data transmission.

[0068] After the power-on signal is sent, the display panel 120 remains in operation until the power is turned off. However, after the display panel 120 is powered on, each frame displayed will have a blank area, i.e., a blanking phase (or blank period). This blank area is the non-display period of the display panel 120. The source driver 200 receives the pixel drive signal from the timing controller 100 at the front end. Since the output buffer 210 amplifies the pixel drive signal, its power consumption is relatively high. Therefore, in this application, when the display panel 120 is powered on and in normal driving operation, the timing controller 100 can determine whether the pixel drive signal sent is a pixel data signal. Then, based on the judgment result of whether the pixel driving signal belongs to the pixel data signal, the timing controller 100 selectively switches the on / off state of the control switch Q1 while ensuring the correct display effect during the non-display period of the display panel 120. Since the output buffer 210 and the voltage supply module 220 are connected through the control switch Q1, the timing controller 100 can switch the connection line between the output buffer 210 and the voltage supply module 220 to the disconnected state (or connected state) by controlling the closed state (or the on state) of the control switch Q1. That is, the timing controller 100 switches the connection line of the voltage supply module 220 to provide grayscale voltage to the output buffer 210 based on the judgment result.

[0069] In this design, after determining that the pixel driving signal is not a pixel data signal, the timing controller 100 turns off the control switch Q1, disconnecting the connection between the output buffer 210 and the voltage supply module 220. This causes the voltage supply module 220 to stop supplying grayscale voltage to the output buffer 210, thereby switching the output buffer 210, which is connected to the display panel 120 and provides the required grayscale voltage to the pixel units 121 of the display panel 120, from an active state to an idle state. The idle state of the output buffer 210 means that when the connection is disconnected, the voltage supply module 220 stops supplying grayscale voltage to the output buffer 210, and the output buffer 210 stops receiving grayscale voltage and converting it into the corresponding data voltage. Therefore, by detecting that the pixel driving signal is not a pixel data signal, this application switches the output buffer 210 from an active state to an idle state, avoiding the output buffer 210 from being continuously active, reducing the operating duration of the output buffer 210, and thus reducing product power consumption.

[0070] In some embodiments of this application, the step of S200 determining whether the pixel driving signal belongs to a pixel data signal includes:

[0071] S210. Analyze the pixel driving signal to obtain parsed data;

[0072] S220. Determine whether a preset identifier corresponding to the pixel data signal is found in the parsed data;

[0073] S230. If the preset identifier is found in the parsed data, it is determined that the pixel driving signal belongs to the pixel data signal; if the preset identifier is not found in the parsed data, it is determined that the pixel driving signal does not belong to the pixel data signal.

[0074] Specifically, a frame cycle includes a display phase and a blanking phase. The pixel data signal is used in the above embodiment to allow the decoder to decode the pixel data corresponding to the digital signal into grayscale voltage and provide it to the output buffer 210 for output to each pixel unit 121 to drive light emission. For example... Figure 1As shown, the timing controller 100 can identify whether the current pixel driving signal belongs to the pixel data signal based on the composition of the pixel driving signal. The pixel driving signal consists of multiple data types, including HBP (Horizontal Blank Period), command start signal, register configuration signal, pixel data signal, control signal, and VBP (Vertial Blank Period). When the timing controller 100 transmits the pixel driving signal to the source driver 200, it can set a unique preset identifier for each of the above different data types. Since the preset identifiers corresponding to different data types are different, the timing controller 100 can parse the pixel driving signal and check whether there is a preset identifier corresponding to the pixel data signal in the parsing result. If it exists, it is determined that the pixel driving signal is a pixel data signal; otherwise, if it does not exist, it is determined that the pixel driving signal is not a pixel data signal.

[0075] In some embodiments of this application, the display driving method further includes:

[0076] S400. If the pixel driving signal belongs to the pixel data signal, turn on the control switch Q1 so that the connection line between the output buffer 210 and the voltage supply module 220 is switched to a connected state.

[0077] Specifically, referring to the above embodiment, after determining that the pixel driving signal is a pixel data signal, the timing controller 100 turns on the control switch Q1, causing the connection line between the output buffer 210 and the voltage supply module 220 to switch to a connected state. This allows the voltage supply module 220 to start providing grayscale voltage to the output buffer 210, thereby causing the output buffer 210, which is connected to the display panel 120 and provides the required grayscale voltage to the pixel units 121 of the display panel 120, to switch from an idle state to an operating state. This allows the output buffer 210 to transmit the required grayscale voltage from the pixel units 121 to the display panel 120 for image display. In this way, the timing controller 100 can control the output buffer 210 to remain in an operating state while sending pixel data signals to the source driver 200, reducing the effective operating time of the output buffer 210. This reduces the ineffective operating time of the output buffer 210 within the total time the source driver 200 provides grayscale voltage to the pixel units 121, thereby reducing the power consumption ratio of the source driver 200.

[0078] In some embodiments of this application, the display device 1 further includes a display panel 120, the first and second terminals of the control switch Q1 are respectively connected to the voltage supply module 220 and the output buffer 210, the timing controller 100 includes a buffer control pin, and the buffer control pin is connected to the third terminal of the control switch Q1; the step of turning on the control switch Q1 if the pixel driving signal belongs to the pixel data signal, so that the connection line between the output buffer 210 and the voltage supply module 220 is switched to a connected state includes:

[0079] S311. When the pixel driving signal belongs to the pixel data signal, the control module is configured to switch the buffer control pin from the first level V1 to the second level V2, triggering the control switch Q1 to turn on, so that the connection line is connected and the grayscale voltage output by the voltage supply module 220 is transmitted to the display panel 120.

[0080] Specifically, such as Figure 5 As shown, the source driver 200 includes an output buffer 210, a voltage supply module 220, and a control switch Q1. The control switch Q1 is connected to the voltage supply module 220, the output buffer 210, and the timing controller 100. Specifically, the first and second terminals of the control switch Q1 are connected to the voltage supply module 220 and the output buffer 210, respectively. The timing controller 100 includes a buffer control pin, which is connected to the third terminal of the control switch Q1. The first level V1 may be greater than the second level V2, or it may be less than the second level V2. The switching between the first level V1 and the second level V2 depends on the type of control switch Q1.

[0081] In the first scenario: when the pixel driving signal is a pixel data signal, if the control switch Q1 is an N-type MOSFET, then the first level V1 is less than the second level V2, and the first terminal of the control switch Q1 is the drain D of the N-type MOSFET, the second terminal of the control switch Q1 is the source S of the N-type MOSFET, and the third terminal of the control switch Q1 is the gate G of the N-type MOSFET. Since the first level V1 is less than the second level V2, the buffer control pin switches from the first level V1 to the second level V2. That is, the voltage supplied to the gate G of the N-type MOSFET by the buffer control pin increases from the first level V1 to the second level V2, meaning the gate G of the N-type MOSFET is at a high level, which satisfies the N-type MOSFET's turn-on condition V. GS >V th Then, the N-type MOSFET switches to the on state, thereby enabling... Figure 7 and Figure 8 The grayscale voltage required by the pixel unit 121 output by the voltage supply module 220 can be transmitted to the display panel 120 for driving display.

[0082] In the second scenario: when the pixel driving signal is a pixel data signal, if the control switch Q1 is a P-type MOS transistor, then the first level V1 is greater than the second level V2, and the first terminal of the control switch Q1 is the source S of the P-type MOS transistor, the second terminal of the control switch Q1 is the drain D of the P-type MOS transistor, and the third terminal of the control switch Q1 is the gate G of the P-type MOS transistor. Since the first level V1 is greater than the second level V2, the buffer control pin switches from the first level V1 to the second level V2. That is, the voltage supplied to the gate G of the P-type MOS transistor by the buffer control pin decreases from the first level V1 to the second level V2, meaning the gate G voltage of the P-type MOS transistor is low, which satisfies the P-type MOS transistor's turn-on condition V. GS <V th Then, the P-type MOSFET switches to the on state, thereby enabling... Figure 7 and Figure 8 The grayscale voltage required by the pixel unit 121 output by the voltage supply module 220 can be transmitted to the display panel 120 for driving display.

[0083] The step of turning off the control switch Q1 if the pixel driving signal does not belong to the pixel data signal, so that the connection line between the output buffer 210 and the voltage supply module 220 is switched to an open state, includes:

[0084] S321. When the pixel driving signal does not belong to the pixel signal, the control module is configured to switch the buffer control pin from the second level V2 to the first level V1, triggering the control switch Q1 to close, so that the connection line is disconnected and the grayscale voltage output by the voltage supply module 220 is stopped from being transmitted to the display panel 120.

[0085] The third scenario: When the pixel drive signal is not a pixel data signal, if the control switch Q1 is an N-type MOSFET, then the first level V1 is less than the second level V2, and the first terminal of the control switch Q1 is the drain D of the N-type MOSFET, the second terminal of the control switch Q1 is the source S of the N-type MOSFET, and the third terminal of the control switch Q1 is the gate G of the N-type MOSFET. Since the first level V1 is less than the second level V2, the buffer control pin switches from the second level V2 to the first level V1. That is, the voltage supplied to the gate G of the N-type MOSFET by the buffer control pin decreases from the second level V2 to the first level V1, meaning the gate G voltage of the N-type MOSFET is low, which cannot meet the N-type MOSFET's turn-on condition V. GS >V th Then, the N-type MOSFET switches to the cutoff state (or open state), thereby enabling... Figure 7 and Figure 8 The grayscale voltage required by the pixel unit 121 output by the voltage supply module 220 shown cannot be transmitted to the display panel 120 for driving display, or has stopped.

[0086] The fourth scenario: When the pixel drive signal is not a pixel data signal, if the control switch Q1 is a P-type MOS transistor, then the first level V1 is greater than the second level V2, and the first terminal of the control switch Q1 is the source S of the P-type MOS transistor, the second terminal of the control switch Q1 is the drain D of the P-type MOS transistor, and the third terminal of the control switch Q1 is the gate G of the P-type MOS transistor. Since the first level V1 is greater than the second level V2, the buffer control pin switches from the second level V2 to the first level V1. That is, the voltage supplied to the gate G of the P-type MOS transistor by the buffer control pin increases from the second level V2 to the first level V1, meaning the gate G of the P-type MOS transistor is at a high level, which cannot meet the P-type MOS transistor turn-on condition V. GS <V th Then, the P-type MOSFET switches to the cutoff state (or open state), thereby enabling... Figure 7 and Figure 8The grayscale voltage required by the pixel unit 121 output by the voltage supply module 220 shown cannot be transmitted to the display panel 120 for driving display, or has stopped.

[0087] In some embodiments of this application, the display device 1 further includes a power supply circuit 400 that provides an initial grayscale voltage, and a voltage providing module 220 is connected to the power supply circuit 400. The voltage providing module 220 is used to receive the initial grayscale voltage and output multiple grayscale voltages.

[0088] Specifically, such as Figure 5 As shown, the description of the power supply circuit 400 that provides the initial grayscale voltage can be found in the previous embodiment, and will not be repeated here. The power supply circuit 400 can provide a small amount of initial grayscale voltage VgrayG[1:a] to the source driver 200. Then, the voltage supply module 220 in the source driver splits the small amount of initial grayscale voltage VgrayG[1:a] provided by the power supply circuit 400 to output a large number of grayscale voltages with different values ​​to meet the display panel 120's requirements for finer grayscale or brightness display.

[0089] In some embodiments of this application, the voltage providing module 220 includes:

[0090] Multiple operational amplifiers Gamma OPi are connected sequentially to the output line of the power supply circuit 400, and any number of operational amplifiers Gamma OPi are cascaded according to the number of initial grayscale voltages.

[0091] Multiple voltage divider resistors Ri are connected sequentially to the output line of the operational amplifier Gamma OPi;

[0092] Multiple gating units KM are connected between the corresponding voltage divider resistor Ri and the control switch Q1, and the corresponding gray level voltage is output through the switch control signal output by the operational amplifier Gamma OPi;

[0093] The first input terminal of the operational amplifier Gamma OPi is connected to the output line of the power supply circuit 400, and the output terminal of the operational amplifier Gamma OPi is connected to the second input terminal of the operational amplifier Gamma OPi and the corresponding voltage divider resistor Ri; the output line of the gating unit KM is connected to the first terminal of the control switch Q1.

[0094] Specifically, such as Figure 6 As shown, the multiple operational amplifiers Gamma OPi may include Gamma OP1 to Gamma OPi, the multiple voltage divider resistors Ri may include R1 to Ri, and the multiple gating units KM may include K1 to K MWhere i, j, and M are all positive integers greater than 1.

[0095] For example, such as Figure 7 and Figure 8 As shown, the output terminal of the first operational amplifier Gamma OPi is connected to its first input terminal and the first terminal of the corresponding first voltage divider resistor Ri. The second input terminal of the first operational amplifier Gamma OPi is connected to the first initial grayscale voltage GMA n output by the power supply circuit 400. The output terminals of the first operational amplifier Gamma OPi and the second operational amplifier Gamma OPi are connected, and multiple voltage divider resistors Ri are connected in series on the output lines of the first and second operational amplifiers. For example, multiple voltage divider resistors R1 to R7 are connected in series between the output terminals of the first and second operational amplifiers Gamma OPi. Each gating unit KM is connected between the corresponding voltage divider resistor Ri and the control switch Q1. Two adjacent voltage divider resistors Ri form a voltage divider unit or a pair, i.e., a voltage divider unit or a pair includes an upper voltage divider resistor Ri and a lower voltage divider resistor Ri. One end of one gating unit KM is connected to the upper voltage divider resistor Ri in a pair of voltage divider units, and one end of another gating unit KM is connected to the upper voltage divider resistor Ri in another pair of voltage divider units, and so on.

[0096] In this embodiment, a voltage divider resistor Ri is connected in series on the output lines of multiple operational amplifiers Gamma OPI to divide the initial grayscale voltage provided by the power supply circuit 400. After the initial grayscale voltage is input to the corresponding operational amplifier Gamma OPI, the operational amplifier Gamma OPI performs a comparison operation and outputs a switch control signal. This causes one selection unit KM on the output line of the operational amplifier Gamma OPI to switch to the on state according to the switch control signal, while the remaining selection units KM switch to the off state according to the switch control signal, thereby outputting the corresponding grayscale voltage. For example, the initial grayscale voltage of 10V is divided and branched by the voltage supply module 220 to output grayscale voltages of 5V, 5.5V, 6V, ..., 9V, 9.5V and 10V.

[0097] In some embodiments of this application, each gating unit KM includes: a first gating switch Dn and a second gating switch Dn bar; the first gating switch Dn and the second gating switch Dn bar are connected in parallel;

[0098] The first gating switch Dn and the second gating switch Dn bar of the Nth gating unit KM are respectively connected to two adjacent preceding nodes;

[0099] Wherein, the two adjacent preceding nodes of the Nth level gating unit KM are two adjacent voltage divider resistors Ri, and the two adjacent preceding nodes of the (N+1)th level gating unit KM are two adjacent Nth level gating units KM; where N is a positive integer.

[0100] Specifically, such as Figure 7 and Figure 8 As shown, regardless of whether it's the primary gating unit KM, the secondary gating unit KM, the tertiary gating unit KM, or even the Nth-level gating unit KM, they all include two gating switches, namely Dn and Dn bar. For example, as... Figure 7 and Figure 8 As shown, the two ends of the first primary gating unit KM are connected to the first voltage divider resistor R1, and the two ends of the second primary gating unit KM are connected to the third voltage divider resistor R3. A second voltage divider resistor R2 located between the first voltage divider resistor R1 and the third voltage divider resistor R3 is connected in series on the connection line between the first primary gating unit KM and the second primary gating unit KM. That is, the first gating switch Dn is connected to the first end of the first voltage divider resistor R1 and the first end of the output terminal of the first operational amplifier Gamma OP1, and the second gating switch Dn bar is connected to the second end of the first voltage divider resistor R1 and the first end of the second voltage divider resistor R2, and so on.

[0101] Similarly, the two ends of the first-stage gating unit KM are connected to the outputs of the first primary gating unit KM and the second primary gating unit KM, respectively, and so on. The two ends of the first- and third-stage gating units KM are connected to the outputs of the first-stage gating unit KM and the second-stage gating unit KM, respectively, and so on. Finally, the output of the last-stage gating unit KM is connected to the first end of the control switch Q1.

[0102] For example, the first gating switch Dn can be set to be high-level and the second gating switch Dn bar can be set to be low-level. That is, if the switching control signal output by the operational amplifier Gamma OPi is high-level (which can be identified by 1), then... Figure 7 and Figure 8 The first selector switch Dn on the corresponding line is turned on, thus outputting the corresponding grayscale voltage. If the switch control signal output by the operational amplifier Gamma OPi is high (which can be identified by 0), then... Figure 7 and Figure 8 The second selector switch Dn bar on the corresponding line is turned on, thereby outputting the corresponding grayscale voltage. It should be noted that, as... Figure 1 and Figure 4The number of operational amplifiers, voltage divider resistors, first gating switch Dn, and second gating switch Dn bar in the example is only for illustration. The number of operational amplifiers, voltage divider resistors, first gating switch Dn, and second gating switch Dn bar can be selectively increased or decreased according to the initial grayscale voltage output by the power supply circuit 400 and the fineness of the grayscale voltage required by the pixels of the display panel 120.

[0103] In this embodiment, a voltage divider resistor Ri is connected in series on the output lines of multiple operational amplifiers Gamma OPI to divide the initial grayscale voltage provided by the power supply circuit 400. After the initial grayscale voltage is input to the corresponding operational amplifier Gamma OPI, the operational amplifier Gamma OPI outputs a switch control signal after comparison operation. This causes the first gating switch Dn or the second gating switch Dn bar in the corresponding gating unit KM on the output line of the operational amplifier Gamma OPI to switch to the on state according to the switch control signal. The remaining gating units KM switch to the off state according to the first gating switch Dn or the second gating switch Dn bar in the switch control signal, thereby outputting the corresponding grayscale voltage.

[0104] like Figure 7 As shown, the source driver 200 receives a row of pixel drive signals from the timing controller 100, which consists of HBP, command start signal, register configuration, and pixel data signal / control signal / VBP. During the transmission of the pixel drive signal, the output buffer 210 module inside the source driver 200 remains in the open state at all times. Figures 2 to 7 As shown, the output buffer 210 of this application detects whether the data sent by the timing controller 100 is a pixel data signal. During the transmission of the pixel data signal, if... ​ As shown, the timing controller 100 controls the Buffer Control pin to pull high to turn on the N-type MOS transistor and keep the output buffer 210 open; during the transmission of non-pixel data signals such as HBP, command start signal, register configuration, and control signal / VBP, the timing controller 100 controls the Buffer Control pin to pull low to turn off the N-type MOS transistor and turn off the output buffer 210 to reduce the power consumption of the source driver 200.

[0105] When the output buffer 210 receives a pixel drive signal from the timing controller 100, and determines that the received pixel drive signal is a pixel data signal, the output buffer 210 is switched to the on state. Thus, the output buffer 210 is in operation during the display period of the display panel 120. Conversely, when it is determined that the received pixel drive signal is not a pixel data signal, the output buffer 210 is switched to the off state. Thus, during the non-display period of the display panel 120, i.e., the blanking phase mentioned above, the output buffer 210 is in an idle state, thereby reducing the operating time of the output buffer 210, increasing its effective operating time, and reducing its power consumption ratio, thereby reducing the power consumption of the display device 1.

[0106] Based on the methods described in the above embodiments, this embodiment will further describe the method from the perspective of the apparatus. Please refer to [link / reference]. ​ The display device 1 provided in this application embodiment includes a source driver 200 and a timing controller 100. The source driver 200 is connected to the timing controller 100. The source driver 200 includes an output buffer 210, a voltage supply module 220, and a control switch Q1. The output buffer 210 is connected to the voltage supply module 220 through the control switch Q1. The timing controller 100 includes:

[0107] The acquisition module is used to acquire pixel driving signals;

[0108] The detection module is used to detect whether the pixel driving signal belongs to the pixel data signal;

[0109] The control module is used to turn off the control switch Q1 if the pixel driving signal does not belong to the pixel data signal, so that the output buffer 210 and the voltage supply module 220 are switched to the disconnected state.

[0110] In some embodiments, the display device 1 further includes a display panel 120, the source driver 200 further includes a control switch Q1, the first and second terminals of the control switch Q1 are respectively connected to the voltage supply module 220 and the output buffer 210, and the timing controller 100 includes a buffer control pin, the buffer control pin being connected to the third terminal of the control switch Q1; wherein:

[0111] When the pixel driving signal belongs to the pixel data signal, the control module is configured to switch the buffer control pin from the first level V1 to the second level V2, trigger the control switch Q1 to turn on, so that the connection line is connected and the grayscale voltage output by the voltage supply module 220 is transmitted to the display panel 120.

[0112] When the pixel driving signal does not belong to the pixel signal, the control module is configured to switch the buffer control pin from the second level V2 to the first level V1, triggering the control switch Q1 to turn off, so that the connection line is disconnected and the grayscale voltage output by the voltage supply module 220 is stopped from being transmitted to the display panel 120.

[0113] In some embodiments, the control switch Q1 is an N-type MOS transistor, with the first terminal, the second terminal, and the third terminal being the drain (D), the source (S), and the gate (G), respectively, and the first voltage level V1 being less than the second voltage level V2.

[0114] In some embodiments, the control switch Q1 is a P-type MOS transistor, with the first terminal, the second terminal, and the third terminal being the source (S), drain (D), and gate (G), respectively, and the first voltage level V1 being greater than the second voltage level V2.

[0115] In some embodiments, the display device 1 further includes a power supply circuit 400 that provides an initial grayscale voltage, and a voltage providing module 220 connected to the power supply circuit 400. The voltage providing module 220 is used to receive the initial grayscale voltage and output multiple grayscale voltages.

[0116] In some embodiments, the voltage providing module 220 includes:

[0117] Multiple operational amplifiers Gamma OPi are connected sequentially to the output line of the power supply circuit 400, and any number of operational amplifiers Gamma OPi are cascaded according to the number of initial grayscale voltages.

[0118] Multiple voltage divider resistors Ri are connected sequentially to the output line of the operational amplifier Gamma OPi;

[0119] Multiple gating units KM are connected between the corresponding voltage divider resistor Ri and the control switch Q1, and the corresponding gray level voltage is output through the switch control signal output by the operational amplifier Gamma OPi;

[0120] The first input terminal of the operational amplifier Gamma OPi is connected to the output line of the power supply circuit 400, and the output terminal of the operational amplifier Gamma OPi is connected to the second input terminal of the operational amplifier Gamma OPi and the corresponding voltage divider resistor Ri; the output line of the gating unit KM is connected to the first terminal of the control switch Q1.

[0121] In some embodiments, each of the gating units KM includes: a first gating switch Dn and a second gating switch Dn bar; the first gating switch Dn and the second gating switch Dn bar are connected in parallel;

[0122] The first gating switch Dn and the second gating switch Dn bar of the Nth gating unit KM are respectively connected to two adjacent preceding nodes;

[0123] Wherein, the two adjacent preceding nodes of the Nth level gating unit KM are two adjacent voltage divider resistors Ri, and the two adjacent preceding nodes of the (N+1)th level gating unit KM are two adjacent Nth level gating units KM; where N is a positive integer.

[0124] In some implementations, the detection module is further configured to:

[0125] The pixel driving signal is analyzed to obtain the parsed data;

[0126] Determine whether a preset identifier corresponding to the pixel data signal is found in the parsed data;

[0127] If the preset identifier is found in the parsed data, it is determined that the pixel driving signal belongs to the pixel data signal; if the preset identifier is not found in the parsed data, it is determined that the pixel driving signal does not belong to the pixel data signal.

[0128] It should be noted that, in specific implementation, the above modules can be implemented as independent entities or can be combined arbitrarily to be implemented as the same or several entities. For the specific implementation of the above modules, please refer to the previous method implementation examples, which will not be repeated here.

[0129] The above provides a detailed description of a display driving method and display device provided by the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display device comprising a source driver and a timing controller, the source driver being connected with the timing controller, characterized in that, The source driver comprises an output buffer, a voltage providing module and a control switch, the output buffer and the voltage providing module are connected through the control switch, and the timing controller comprises: An acquisition module is configured to acquire a pixel driving signal. A detection module is configured to detect whether the pixel driving signal belongs to a pixel data signal. A control module is configured to, if the pixel driving signal does not belong to the pixel data signal, close the control switch, so that a connection line between the output buffer and the voltage providing module is switched to a disconnected state. In the case that the connection line between the output buffer and the voltage providing module is in the disconnected state, the voltage providing module stops providing a gray scale voltage to the output buffer. The control module is further configured to: If the pixel driving signal belongs to the pixel data signal, open the control switch, so that the connection line between the output buffer and the voltage providing module is switched to a connected state.

2. The display device of claim 1, wherein, The display device further comprises a display panel, a first end and a second end of the control switch are connected with the voltage providing module and the output buffer respectively, the timing controller comprises a buffer control pin, and the buffer control pin is connected with a third end of the control switch; wherein When the pixel driving signal belongs to the pixel data signal, the control module is configured to switch the buffer control pin from a first level to a second level, trigger the control switch to open, so that the connection line is connected, and then the gray scale voltage output by the voltage providing module is transmitted to the display panel; When the pixel driving signal does not belong to the pixel data signal, the control module is configured to switch the buffer control pin from the second level to the first level, trigger the control switch to close, so that the connection line is disconnected, and then the transmission of the gray scale voltage output by the voltage providing module to the display panel is stopped.

3. The display device of claim 2, wherein The control switch is an N-type MOS tube, the first end, the second end and the third end are a drain, a source and a gate respectively, and the first level is less than the second level.

4. The display device of claim 2, wherein The control switch is a P-type MOS tube, the first end, the second end and the third end are a source, a drain and a gate respectively, and the first level is greater than the second level.

5. The display device of claim 2, wherein, The display device further comprises a power supply circuit for providing an initial gray scale voltage, the voltage providing module is connected with the power supply circuit, and the voltage providing module is configured to access the initial gray scale voltage and output multiple gray scale voltages.

6. The display device of claim 5, wherein, The voltage providing module comprises: A plurality of operational amplifiers are connected in sequence on an output line of the power supply circuit, and any plurality of operational amplifiers are cascaded according to the number of initial gray scale voltages. A plurality of voltage dividing resistors are connected in sequence on output lines of the operational amplifiers. A plurality of gating units are connected between corresponding voltage dividing resistors and the control switch, and output corresponding gray scale voltages through switch control signals output by the operational amplifiers. The first input end of the operational amplifier is connected to the output line of the power supply circuit, and the output end of the operational amplifier is connected with the second input end of the operational amplifier and the corresponding voltage dividing resistor; the output line of the gating unit is connected with the first end of the control switch.

7. The display device of claim 6, wherein, Each of the gating units comprises a first gating switch and a second gating switch; the first gating switch and the second gating switch are connected in parallel; The first gating switch and the second gating switch of the Nth gating unit are connected with two adjacent previous nodes respectively; The two adjacent previous nodes of the Nth gating unit are two adjacent voltage dividing resistors, and the two adjacent previous nodes of the N+1th gating unit are two adjacent Nth gating units; N is a positive integer.

8. The display device according to any of claims 1-7, characterized in that, The detection module is configured to: analyze the pixel driving signal to obtain analysis data; determine whether a preset identifier corresponding to the pixel data signal is found in the analysis data; if the preset identifier is found in the analysis data, it is determined that the pixel driving signal belongs to the pixel data signal, and if the preset identifier is not found in the analysis data, it is determined that the pixel driving signal does not belong to the pixel data signal.

9. A display driving method, the method being used for a display device, the display device comprising a source driver and a timing controller, the source driver being connected with the timing controller, characterized in that, The source driver comprises an output buffer, a voltage providing module and a control switch, the output buffer and the voltage providing module are connected through the control switch, and the display driving method comprises: acquiring a pixel driving signal; detecting whether the pixel driving signal belongs to a pixel data signal; if the pixel driving signal does not belong to the pixel data signal, the control switch is closed to switch the connection line between the output buffer and the voltage providing module to a disconnected state; if the pixel driving signal belongs to the pixel data signal, the control switch is opened to switch the connection line between the output buffer and the voltage providing module to a connected state; in the case that the connection line between the output buffer and the voltage providing module is in the disconnected state, the voltage providing module stops providing a gray scale voltage to the output buffer.

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