Array substrate, display panel, and method for preparing array substrate

Abstract

The embodiments of the present application disclose an array substrate, a display panel, and a method for preparing an array substrate. The array substrate includes a substrate, a doping layer, an active layer, a first insulating layer, a gate, a second insulating layer, and a source-drain layer. The doping layer is provided on the substrate and includes a first doping portion, a second doping portion, and a third doping portion. The active layer is provided on the substrate, and the active layer includes a first active sub-portion and a second active sub-portion, the first active sub-portion being connected to the first doping portion and the second doping portion, respectively, and the second active sub-portion being connected to the first doping portion and the third doping portion, respectively. The gate is electrically connected to the first doping portion, and the source-drain layer includes a first electrode and a second electrode, the first electrode being connected to the second doping portion, and the second electrode being connected to the third doping portion. The present application aims to solve the problem of how to improve mobility while avoiding excessive leakage current in the prior art.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel, and a method for preparing the array substrate. Background Art

[0002] With the development of low-temperature polysilicon (LTPS) semiconductor thin-film transistors (TFTs) and the ultra-high carrier mobility characteristics of LTPS semiconductors themselves, the corresponding panel peripheral integrated circuits have also become the focus of everyone's attention.

[0003] During the research and practice of the existing technology, the inventors of this application found that most of the existing LTPS TFTs use excimer laser annealing (ELA) technology, which results in small crystal grains and a mobility of only 50 to 100 cm 2 / Vs, while the LTPS-TFT made by blue laser annealing technology (Blue Laser Diode Annealing, BLDA) can achieve a mobility of 0cm due to its high energy density and large crystal grains. 2 / Vs or above, thus achieving a higher mobility. However, due to this high mobility, the leakage current of the LTPS-TFT device also becomes much larger, and this large leakage current can affect the normal operation of the device. Therefore, how to reduce the leakage current has become an important part of LTPS design. Summary of the Invention

[0004] The embodiments of the present application provide an array substrate, a display panel, and a method for manufacturing the array substrate, which can solve the problem in the prior art of how to improve mobility while avoiding excessive leakage current.

[0005] An embodiment of the present application provides an array substrate, comprising:

[0006] substrate;

[0007] a doping layer, the doping layer being disposed on the substrate, the doping layer being provided with a first opening and a second opening, the doping layer comprising a first doping portion, a second doping portion, and a third doping portion, the first doping portion being located between the first opening and the second opening, the second doping portion being located on a side of the first opening away from the second opening, and the third doping portion being located on a side of the second opening away from the first opening;

[0008] an active layer, the active layer being disposed on the substrate and comprising a first active sub-portion and a second active sub-portion, the first active sub-portion being located in the first opening and connected to the first doped portion and the second doped portion, respectively; and the second active sub-portion being located in the second opening and connected to the first doped portion and the third doped portion, respectively.

[0009] a first insulating layer, the first insulating layer being provided on the substrate and covering the doped layer and the active layer;

[0010] a gate, the gate being disposed on the first insulating layer and overlapping the first active sub-portion and the second active sub-portion respectively, a first connection hole being defined in the first insulating layer between the gate and the first doped portion, the gate being electrically connected to the first doped portion through the first connection hole;

[0011] a second insulating layer, the second insulating layer being disposed on the first insulating layer and covering the gate; and

[0012] A source-drain layer, wherein the source-drain layer is arranged on the second insulating layer, the first insulating layer and the second insulating layer between the source-drain layer and the second doped part are provided with a second connection hole, the first insulating layer and the second insulating layer between the source-drain layer and the third doped part are provided with a third connection hole, the source-drain layer includes a first electrode and a second electrode, the first electrode is connected to the second doped part through the second connection hole, and the second electrode is connected to the third doped part through the third connection hole.

[0013] Optionally, in some embodiments of the present application, the gate is a single-layer structure, and the gate is electrically connected to the first doped portion through the first connection hole.

[0014] Optionally, in some embodiments of the present application, the gate includes a first part and a second part, the first part is connected and arranged on the first doped part; the second part is arranged on the first insulating layer and overlaps with the first active sub-part and the second active sub-part, and the first part and the second part are connected through the first connection hole.

[0015] Optionally, in some embodiments of the present application, the first doped portion includes a first heavily doped portion and a first lightly doped portion arranged adjacent to each other, the first heavily doped portion is connected to the first active sub-portion, the first lightly doped portion is connected to the second active sub-portion, and the gate is electrically connected to the first heavily doped portion through the first connection hole.

[0016] Optionally, in some embodiments of the present application, the second doped portion includes a second heavily doped portion and a second lightly doped portion that are adjacent to each other, the second lightly doped portion is located on a side of the second heavily doped portion away from the first lightly doped portion, and the first electrode of the source / drain layer is connected to the second heavily doped portion through the second connection hole;

[0017] And / or, the third doped portion includes a third heavily doped portion and a third lightly doped portion arranged adjacent to each other, the third heavily doped portion is located on a side of the third lightly doped portion away from the first heavily doped portion, and the second electrode of the source and drain layer is connected to the third heavily doped portion through the third connection hole.

[0018] Optionally, in some embodiments of the present application, the thickness of the first active sub-portion is smaller than the thickness of the first doped portion and / or the thickness of the second doped portion;

[0019] And / or, the thickness of the second active sub-portion is smaller than the thickness of the first doped portion and / or the thickness of the third doped portion.

[0020] Accordingly, the embodiment of the present application further provides a display panel, comprising the above array substrate

[0021] Accordingly, an embodiment of the present application further provides a method for preparing an array substrate, comprising:

[0022] S1: providing a substrate;

[0023] S2: forming a doping layer on the substrate, and patterning the doping layer to form a first opening, a second opening, a first doping portion, a second doping portion, and a third doping portion, wherein the first doping portion is located between the first opening and the second opening, the second doping portion is located on a side of the first opening away from the second opening, and the third doping portion is located on a side of the second opening away from the first opening;

[0024] S3: forming an active layer on the substrate, the active layer comprising a first active sub-portion and a second active sub-portion, the first active sub-portion covering the first opening and connected to the first doped portion and the second doped portion, the second active sub-portion covering the second opening and connected to the first doped portion and the third doped portion respectively;

[0025] S4: performing annealing and crystallization treatment on the first active sub-section and the second active sub-section;

[0026] S5: forming a first portion of a gate on the first doped portion;

[0027] S6: forming a first insulating layer on the substrate, and covering the doped layer, the active layer and the first portion of the gate;

[0028] S7: forming a second portion of the gate on the first insulating layer, wherein the second portion overlaps the first active sub-portion and the second active sub-portion, and a first connection hole is formed in the first insulating layer between the gate and the first doped portion, and the second portion of the gate is connected to the first portion through the first connection hole;

[0029] S8: forming a second insulating layer on the first insulating layer and covering the second portion of the gate;

[0030] S9: forming a source-drain layer on the second insulating layer, wherein a second connection hole is formed in the first insulating layer and the second insulating layer between the source-drain layer and the second doped portion, and a third connection hole is formed in the first insulating layer and the second insulating layer between the source-drain layer and the third doped portion, and the source-drain layer is patterned to form a first electrode and a second electrode, the first electrode is connected to the second doped portion through the second connection hole, and the second electrode is connected to the third doped portion through the third connection hole;

[0031] S10: forming a passivation layer on the source / drain electrode layer and the insulating layer.

[0032] Optionally, in some embodiments of the present application, the step of S4: performing crystallization on the first active sub-section and the second active sub-section includes:

[0033] The blue laser moves along a predetermined direction to perform a laser annealing process on the first active sub-section and the second active sub-section.

[0034] Optionally, in some embodiments of the present application, the step of S4: performing crystallization on the first active sub-section and the second active sub-section further includes:

[0035] The blue laser also irradiates the first doping portion, the second doping portion and the third doping portion, so that the first doping portion melts and diffuses to form a first heavily doped portion and a first lightly doped portion adjacent to each other along the predetermined direction, the second doping portion melts and diffuses to form a second heavily doped portion and a second lightly doped portion adjacent to each other along the predetermined direction, and the third doping portion melts and diffuses to form a third heavily doped portion and a third lightly doped portion adjacent to each other along the predetermined direction.

[0036] The array substrate of the embodiment of the present application connects a gate to a first doped portion located between a first active sub-portion and a second active sub-portion. This gate not only provides control over the first and second active sub-portions, but also functions as a source and drain, meaning it can provide both input and output voltages. This generates an electric field between the second doped portion connected to the first electrode of the source / drain layer and the first doped portion, and between the third doped portion connected to the second electrode of the source / drain layer and the first doped portion. Compared to the prior art arrangement of a single conductive channel, the present application achieves the effect of extending the conductive channel by forming two active sub-portions to form two conductive channels. This increases the mobility of the active layer while also reducing leakage current. This solves the problem of increasing mobility while avoiding excessive leakage current. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 is a structural diagram of an array substrate provided in an embodiment of the present application;

[0039] Figure 2 1 is a schematic flow chart of a method for preparing an array substrate provided in an embodiment of the present application;

[0040] Figure 3 1 is a schematic structural diagram of step S1 in the method for preparing an array substrate provided in an embodiment of the present application;

[0041] Figure 4 1 is a schematic structural diagram of step S2 in the method for preparing an array substrate provided in an embodiment of the present application;

[0042] Figure 5 3 is a schematic structural diagram of step S3 in the method for preparing an array substrate provided in an embodiment of the present application;

[0043] Figure 6 4 is a schematic structural diagram of step S4 in the method for preparing an array substrate provided in an embodiment of the present application;

[0044] Figure 7 1 is a schematic structural diagram of step S5 in the method for preparing an array substrate provided in an embodiment of the present application;

[0045] Figure 8 1 is a schematic structural diagram of step S6 in the method for preparing an array substrate provided in an embodiment of the present application;

[0046] Figure 9 is a structural schematic diagram of step S7 in the method for preparing an array substrate provided in an embodiment of the present application;

[0047] Figure 10 1 is a schematic structural diagram of step S8 in the method for preparing an array substrate provided in an embodiment of the present application;

[0048] Figure 11 Schematic diagram of step S9 in the method for preparing an array substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0050] The embodiments of the present application provide an array substrate, a display panel, and a method for manufacturing the array substrate. Each of these is described in detail below. It should be noted that the order in which the following embodiments are described does not limit the preferred order of the embodiments.

[0051] Reference Figure 1 An embodiment of the present application provides an array substrate 100, which includes a substrate 10, a doping layer 20, an active layer, a first insulating layer 40, a gate 50, a second insulating layer 60 and a source and drain layer.

[0052] The doped layer 20 is disposed on the substrate 10 and defines a first opening 24 and a second opening 25. The doped layer 20 includes a first doped portion 21, a second doped portion 22, and a third doped portion 23. The first doped portion 21 is located between the first opening 24 and the second opening 25, the second doped portion 22 is located on the side of the first opening 24 away from the second opening 25, and the third doped portion 23 is located on the side of the second opening 25 away from the first opening 24. The active layer is disposed on the substrate 10 and includes a first active sub-portion 31 and a second active sub-portion 32. The first active sub-portion 31 is located within the first opening 24 and connected to the first doped portion 21 and the second doped portion 22, respectively. The second active sub-portion 32 is located within the second opening 25 and connected to the first doped portion 21 and the third doped portion 23, respectively. A first insulating layer 40 is disposed on the substrate 10 and covers the doped layer 20 and the active layer. The gate 50 is disposed on the first insulating layer 40 and overlaps the first active sub-section 31 and the second active sub-section 32, respectively. A first connection hole 41 is defined in the first insulating layer 40 between the gate 50 and the first doped section 21, through which the gate 50 is electrically connected to the first doped section 21. A second insulating layer 60 is disposed on the first insulating layer 40 and covers the gate 50. A source-drain electrode layer is disposed on the second insulating layer 60. A second connection hole 61 is defined in the first insulating layer 40 and the second insulating layer 60 between the source-drain electrode layer and the second doped section 22, and a third connection hole 62 is defined in the first insulating layer 40 and the second insulating layer 60 between the source-drain electrode layer and the third doped section 23. The source-drain electrode layer includes a first electrode 71 and a second electrode 72. The first electrode 71 is connected to the second doped section 22 through the second connection hole 61, and the second electrode 72 is connected to the third doped section 23 through the third connection hole 62.

[0053] The array substrate 100 of the present embodiment connects a gate 50 to the first doped portion 21 located between the first active sub-portion 31 and the second active sub-portion 32. This gate 50 not only provides control over the first and second active sub-portions 31 and 32 but also functions as a source and drain, meaning it can provide both input and output voltages. This generates an electric field between the second doped portion 22 connected to the first electrode 71 of the source / drain layer and the first doped portion 21, and between the third doped portion 23 connected to the second electrode 72 of the source / drain layer and the first doped portion 21. Compared to the single conductive channel arrangement of the prior art, the present invention achieves the effect of extending the conductive channel by forming two active sub-portions to create two conductive channels. This increases the mobility of the active layer while also reducing leakage current, thereby improving mobility while avoiding excessive leakage current.

[0054] Reference Figure 1The substrate 10 includes a base plate 11 and a buffer layer 12. The base plate 11 may be a glass substrate 11. The glass substrate 11 is made of a uniform material, has high transparency and low reflectivity, and has good thermal stability, thus maintaining stable properties after multiple high-temperature processes. Since many chemicals are used in the TFT manufacturing process, the glass substrate 11 must have excellent chemical resistance. The glass substrate 11 must also have sufficient mechanical strength, excellent precision machining properties, and excellent electrical insulation properties. The buffer layer 12 can be formed on the base plate 11 by chemical deposition. The buffer layer 12 may be a combination of one or more of silicon nitride and silicon oxide. The buffer layer 12 serves to isolate the glass substrate 11 from the active layer to prevent metal ions in the glass substrate 11 from diffusing into the active layer, further reducing leakage current. The buffer layer 12 also provides support and buffering for other film layers. Furthermore, a doping layer 20 may be formed on the buffer layer 12 by chemical vapor deposition to improve conductivity. The doping layer 20 may be a silicon layer doped with phosphorus ions (P). The doped layer 20 is patterned to form a first opening 24 and a second opening 25, and to form a first doped portion 21, a second doped portion 22, and a third doped portion 23 spaced apart. The active layer can be deposited by chemical vapor deposition to form a first active sub-portion 31 in the first opening 24 and a second active sub-portion 32 in the second opening 25, thereby connecting the first active sub-portion 31 to the first doped portion 21 and the second doped portion 22, and the second active sub-portion 32 to the first doped portion 21 and the third doped portion 23. In this way, the carrier migration path of the thin film transistor must pass through the first doped portion 21, the second doped portion 22, and the third doped portion 23, thereby simultaneously extending the conductive channel length and achieving the effects of reducing leakage current while also achieving high mobility.

[0055] It should be noted that the active layer can be low temperature polysilicon, which can be obtained by annealing amorphous silicon through blue laser, so that the first active sub-section 31 and the second active sub-section 32 have high mobility. The first insulating layer 40 and the second insulating layer 60 can be SiO x and SiN x The gate 50 may be made of a metal material such as Mo, Ti, or W. The first insulating layer 40 is provided with the gate 50 corresponding to the first connection hole 41. The first connection hole 41 extends along the stacking direction of the second insulating layer 60 toward the first insulating layer 40. The orthographic projection of the first connection hole 41 toward the substrate 10 is located on the first doped portion 21, so that the gate 50 can vertically pass through the first connection hole 41 to connect to the first doped portion 21.

[0056] The source-drain layer can be made of metals such as Mo, Ti, and Cu. The source-drain layer can be patterned to form a first electrode 71 and a second electrode 72. The first electrode 71 can be one of the source or the drain, and the second electrode 72 is the other of the source and the drain. The first insulating layer 40 and the second insulating layer 60 are provided with a second connection hole 61 and a third connection hole 62 corresponding to the first electrode 71 and the second electrode 72, respectively. The second connection hole 61 and the third connection hole 62 extend along the stacking direction of the second insulating layer 60 toward the first insulating layer 40, and the orthographic projection of the second connection hole 61 toward the substrate 10 is located on the second doped portion 22, and the orthographic projection of the third connection hole 62 toward the substrate 10 is located on the third doped portion 23, so that the first electrode 71 is electrically connected to the second doped portion 22 vertically through the second connection hole 61, and the second electrode 72 is electrically connected to the third doped portion 23 vertically through the third connection hole 62. In addition, the array substrate 100 may further include a passivation layer 80, which is formed on the first electrode 71 and the second electrode 72 by chemical vapor deposition. The material of the passivation layer 80 may be SiO x and SiN x etc. inorganic film layers or their stacks.

[0057] Reference Figure 1 Optionally, the gate 50 includes a first portion 51 and a second portion 52, and the first portion 51 is connected and arranged on the first doped portion 21. The second portion 52 is arranged on the first insulating layer 40 and overlaps with the first active sub-portion 31 and the second active sub-portion 32, and the first portion 51 and the second portion 52 are connected through the first connection hole 41. Among them, the first portion 51 can be directly connected to the first doped portion 21 to form the first portion 51, and the second portion 52 can be formed on the first insulating layer 40 after the first insulating layer 40 is set, and then the second portion 52 can be electrically connected to the first portion 51 through the first connection hole 41 of the first insulating layer 40. In this way, the gate 50 is formed into a double-layer structure, so as to control the contact area between the gate 50 and the first doped portion 21, and then control the conductivity between the gate 50 and the first doped portion 21, so as to adjust the driving capability according to the needs. It can be understood that the second portion 52 is orthographically projected toward the substrate 10 , and the second portion 52 completely overlaps with the first active sub-portion 31 and the second active sub-portion 32 , thereby controlling the first active sub-portion 31 and the second active sub-portion 32 .

[0058] In another embodiment, the gate is a single-layer structure, and the gate is electrically connected to the first doped portion through a first connection hole. It is understood that the gate can also be directly electrically connected to the first doped portion through the first connection hole after the first insulating layer is provided, by directly opening the first connection hole in the first insulating layer, thereby improving manufacturing efficiency.

[0059] Reference Figure 1 Optionally, the first doped portion 21 includes a first heavily doped portion 211 and a first lightly doped portion 212 that are adjacent to each other, the first heavily doped portion 211 is connected to the first active sub-portion 31, the first lightly doped portion 212 is connected to the second active sub-portion 32, and the gate 50 is electrically connected to the first heavily doped portion 211 through the first connection hole 41. It can be understood that the ion concentration of the first heavily doped portion 211 is greater than the ion concentration of the first lightly doped portion 212. By forming the first heavily doped portion 211 and the first lightly doped portion 212 in the first doped portion 21, a lightly doped drain (LDD) structure is formed to weaken the electric field, improve the hot carrier effect, and reduce the electron migration phenomenon at the connection end in the off state, thereby reducing the leakage current of the thin film transistor and reducing power loss, thereby further achieving the effect of reducing leakage current. It should be noted that the first heavily doped portion 211 and the first lightly doped portion 212 can be formed by directly using ion implantation to form an ion concentration difference. Alternatively, the first doped portion 21 may be irradiated with blue laser annealing technology to melt the first doped portion 21 instantaneously, so that the phosphorus ions injected into the first doped portion 21 diffuse after melting, i.e., an ion concentration difference is generated in the direction of laser scanning, thereby forming a first heavily doped portion 211 and a first lightly doped portion 212.

[0060] Furthermore, the second doped portion 22 includes a second heavily doped portion 221 and a second lightly doped portion 222 that are adjacently arranged. The second lightly doped portion 222 is located on the side of the second heavily doped portion 221 away from the first lightly doped portion 212, and the first electrode 71 of the source and drain layer is connected to the second heavily doped portion 221 through the second connection hole 61. It can be understood that the ion concentration of the second heavily doped portion 221 is greater than the ion concentration of the second lightly doped portion 222. By forming the second heavily doped portion 221 and the second lightly doped portion 222 in the second doped portion 22, a lightly doped drain structure is formed to weaken the electric field, improve the hot carrier effect, reduce the electron migration phenomenon at the connection end in the off state, and thus reduce the leakage current of the thin film transistor, reduce power loss, and further achieve the effect of reducing leakage current. It should be noted that the second heavily doped portion 221 and the second lightly doped portion 222 can be formed by directly using ion implantation to form an ion concentration difference. Alternatively, the second doped portion 22 may be irradiated with blue laser annealing technology to melt the second doped portion 22 instantaneously, so that the phosphorus ions injected into the second doped portion 22 diffuse after melting, i.e., an ion concentration difference is generated in the direction of laser scanning, thereby forming a second heavily doped portion 221 and a second lightly doped portion 222.

[0061] Optionally, the third doped portion 23 includes a third heavily doped portion 231 and a third lightly doped portion 232 that are adjacently arranged, the third heavily doped portion 231 being located on the side of the third lightly doped portion 232 away from the first heavily doped portion 211, and the second electrode 72 of the source / drain layer is connected to the third heavily doped portion 231 through the third connection hole 62. It can be understood that the ion concentration of the third heavily doped portion 231 is greater than the ion concentration of the third lightly doped portion 232. By forming the third heavily doped portion 231 and the third lightly doped portion 232 in the third doped portion 23, a lightly doped drain structure is formed to weaken the electric field, improve the hot carrier effect, reduce the electron migration phenomenon at the connection end in the off state, and thereby reduce the leakage current of the thin film transistor, reduce power loss, and further achieve the effect of reducing leakage current. It should be noted that the third heavily doped portion 231 and the third lightly doped portion 232 can be formed by directly using ion implantation to form an ion concentration difference. Alternatively, the third doped portion 23 may be irradiated with blue laser annealing technology to melt the third doped portion 23 instantaneously, so that the phosphorus ions injected into the third doped portion 23 diffuse after melting, that is, an ion concentration difference is generated in the direction of laser scanning, thereby forming a third heavily doped portion 231 and a third lightly doped portion 232.

[0062] Reference Figure 1 Optionally, the thickness of the first active sub-section 31 is less than the thickness of the first doped section 21 and / or the thickness of the second doped section 22. Specifically, on the substrate 10, the thickness of the first active sub-section 31 can be less than the thickness of the first doped section 21, or the thickness of the first active sub-section 31 can also be less than the thickness of the second doped section 22, or the first active sub-section 31 can be less than both the thickness of the first doped section 21 and the thickness of the second doped section 22. By thinning the thickness of the first active sub-section 31, the area of ​​the cross-section for carrier transport in the first active sub-section 31 is reduced, thereby increasing the resistance of the first active sub-section 31 and thereby facilitating reduction of leakage current of the thin film transistor. Furthermore, thinning the thickness of the first active sub-section 31 helps improve the gate 50's ability to control the first active sub-section 31.

[0063] Optionally, the thickness of the second active sub-section 32 is less than the thickness of the first doped section 21 and / or the thickness of the third doped section 23. Specifically, on the substrate 10, the thickness of the second active sub-section 32 can be less than the thickness of the first doped section 21, or the thickness of the second active sub-section 32 can also be less than the thickness of the third doped section 23, or the second active sub-section 32 can be less than both the thickness of the first doped section 21 and the thickness of the third doped section 23. By thinning the thickness of the second active sub-section 32, the cross-sectional area of ​​the second active sub-section 32 that transports carriers is reduced, thereby increasing the resistance of the second active sub-section 32 and thereby facilitating reduction of leakage current of the thin film transistor. Furthermore, the thinning of the second active sub-section 32 improves the control capability of the gate 50 over the second active sub-section 32.

[0064] The present application also provides a display panel, which includes the above-mentioned array substrate 100, a color filter substrate arranged opposite to the array substrate 100, and a liquid crystal layer arranged between the array substrate 100 and the color filter substrate.

[0065] Reference Figure 2 The present application also provides a method for preparing an array substrate 100, comprising:

[0066] S1: providing a substrate 10;

[0067] S2: forming a doping layer 20 on the substrate 10, and patterning the doping layer 20 to form a first opening 24, a second opening 25, a first doping portion 21, a second doping portion 22, and a third doping portion 23, wherein the first doping portion 21 is located between the first opening 24 and the second opening 25, the second doping portion 22 is located on a side of the first opening 24 away from the second opening 25, and the third doping portion 23 is located on a side of the second opening 25 away from the first opening 24;

[0068] S3: forming an active layer on the substrate 10, the active layer including a first active sub-portion 31 and a second active sub-portion 32, the first active sub-portion 31 covering the first opening 24 and connected to the first doped portion 21 and the second doped portion 22, the second active sub-portion 32 covering the second opening 25 and connected to the first doped portion 21 and the third doped portion 23 respectively;

[0069] S4: performing annealing and crystallization treatment on the first active sub-section 31 and the second active sub-section 32;

[0070] S5: forming a first portion 51 of the gate 50 on the first doped portion 21;

[0071] S6: forming a first insulating layer 40 on the substrate 10 and covering the doped layer 20 , the active layer and the first portion 51 of the gate 50 ;

[0072] S7: Forming the second portion 52 of the gate 50 on the first insulating layer 40 , wherein the second portion 52 overlaps the first active sub-portion 31 and the second active sub-portion 32 . A first connection hole 41 is defined in the first insulating layer 40 between the gate 50 and the first doped portion 21 , and the second portion 52 of the gate 50 is connected to the first portion 51 through the first connection hole 41 .

[0073] S8: forming a second insulating layer 60 on the first insulating layer 40 and covering the second portion 52 of the gate 50;

[0074] S9: A source-drain layer is formed on the second insulating layer 60, a second connection hole 61 is formed in the first insulating layer 40 and the second insulating layer 60 between the source-drain layer and the second doped portion 22, a third connection hole 62 is formed in the first insulating layer 40 and the second insulating layer 60 between the source-drain layer and the third doped portion 23, and the source-drain layer is patterned to form a first electrode 71 and a second electrode 72, the first electrode 71 is connected to the second doped portion 22 through the second connection hole 61, and the second electrode 72 is connected to the third doped portion 23 through the third connection hole 62.

[0075] S10: forming a passivation layer 80 on the source / drain layer and the insulating layer.

[0076] It will be appreciated that in the array substrate 100 of this embodiment, by connecting the gate 50 to the first doped portion 21 located between the first active sub-portion 31 and the second active sub-portion 32, the gate 50 not only provides control over the first and second active sub-portions 31 and 32 but also functions as a source and drain, i.e., the gate 50 can also provide input and output voltages. This generates an electric field between the second doped portion 22 connected to the first electrode 71 of the source / drain layer and the first doped portion 21, and between the third doped portion 23 connected to the second electrode 72 of the source / drain layer and the first doped portion 21. Thus, compared to the single conductive channel arrangement in the prior art, the present application achieves the effect of extending the conductive channel by forming two active sub-portions to form two conductive channels. This increases the mobility of the active layer while also reducing leakage current, thereby solving the problem of improving mobility while avoiding excessive leakage current.

[0077] The following is a detailed description of the method for preparing the array substrate 100:

[0078] Reference Figure 3S1: Provide a substrate 10. The substrate 10 includes a base plate 11 and a buffer layer 12. The base plate 11 may be a glass base plate 11. The buffer layer 12 may be formed on the base plate 11 by chemical deposition. The buffer layer 12 may be a combination of one or more of silicon nitride and silicon oxide. The buffer layer 12 isolates the glass base plate 11 from the active layer to prevent metal ions in the glass base plate 11 from diffusing into the active layer, thereby further reducing leakage current. The buffer layer 12 may also provide support and buffering for other film layers.

[0079] Reference Figure 4 S2: forming a doping layer 20 on the substrate 10, and patterning the doping layer 20 to form a first opening 24, a second opening 25, a first doping portion 21, a second doping portion 22, and a third doping portion 23. The first doping portion 21 is located between the first opening 24 and the second opening 25, the second doping portion 22 is located on a side of the first opening 24 away from the second opening 25, and the third doping portion 23 is located on a side of the second opening 25 away from the first opening 24. The doping layer 20 is formed on the buffer layer 12 by chemical deposition. The doping layer 20 may be a silicon layer doped with phosphorus ions (P). The doping layer 20 is then patterned by etching to form the first opening 24, the second opening 25, the first doping portion 21, the second doping portion 22, and the third doping portion 23.

[0080] Reference Figure 5 S3: An active layer is formed on the substrate 10. The active layer includes a first active sub-section 31 and a second active sub-section 32. The first active sub-section 31 covers the first opening 24 and is connected to the first doped section 21 and the second doped section 22. The second active sub-section 32 covers the second opening 25 and is connected to the first doped section 21 and the third doped section 23, respectively. The active layer can be formed by chemical vapor deposition to form the first active sub-section 31 in the first opening 24 and the second active sub-section 32 in the second opening 25, so that the first active sub-section 31 is connected to the first doped section 21 and the second doped section 22, and the second active sub-section 32 is connected to the first doped section 21 and the third doped section 23. In this way, the carrier migration path of the thin film transistor needs to pass through the first doped section 21, the second doped section 22 and the third doped section 23, thereby simultaneously extending the conductive channel length, reducing leakage current while achieving a high mobility.

[0081] S4: performing annealing and crystallization treatment on the first active sub-section 31 and the second active sub-section 32. The active layer can be annealed from amorphous silicon to low-temperature polysilicon to improve mobility.

[0082] Reference Figure 6Furthermore, the step S4 includes: moving the blue laser along a predetermined direction to perform laser annealing on the first active sub-section 31 and the second active sub-section 32. The blue laser can be emitted by the laser device 200, and the laser device 200 moves along the predetermined direction so that the blue laser emitted by the laser device 200 moves along the predetermined direction. The predetermined direction is as follows: Figure 6 Indicated by the dashed line. The predetermined direction can be from the first active sub-segment 31 toward the second active sub-segment 32, so that the blue laser scans the first and second active sub-segments 31 and 32 in sequence. Alternatively, the predetermined direction can be from the second active sub-segment 32 toward the first active sub-segment 31, so that the blue laser scans the second and first active sub-segments 32 and 31 in sequence. Using blue laser annealing technology, the amorphous silicon to polycrystalline silicon transition is achieved, significantly improving the mobility.

[0083] Furthermore, step S4 also includes: the blue laser is also irradiated on the first doping part 21, the second doping part 22 and the third doping part 23, so that the first doping part 21 is melted and diffused to form a first heavily doped part 211 and a first lightly doped part 212 adjacent to each other along a predetermined direction, the second doping part 22 is melted and diffused to form a second heavily doped part 221 and a second lightly doped part 222 adjacent to each other along a predetermined direction, and the third doping part 23 is melted and diffused to form a third heavily doped part 231 and a third lightly doped part 232 adjacent to each other along a predetermined direction.

[0084] It is understood that when the blue laser passes through the first active sub-section 31 and the second active sub-section 32, it also passes through the first doped section 21, the second doped section 22, and the third doped section 23. This causes the first doped section 21, the second doped section 22, and the third doped section 23 to be molten under the action of the blue laser. Consequently, the phosphorus ions injected into the first doped section 21, the second doped section 22, and the third doped section 23 diffuse after melting, i.e., an ion concentration difference is generated in the direction of the laser scanning, thereby forming the first heavily doped section 211 and the first lightly doped section 212, the second heavily doped section 221 and the second lightly doped section 222, and the third heavily doped section 231 and the third lightly doped section 232. This weakens the electric field, improves the hot carrier effect, reduces electron migration at the connection end in the off state, and thus reduces the leakage current of the thin film transistor, reducing power loss, thereby further achieving the effect of reducing leakage current.

[0085] It should be noted that, before step S4, the method for preparing the array substrate 100 further includes performing a dehydrogenation treatment on the active layer. The dehydrogenation treatment is performed on the active layer in a high-temperature baking furnace at a specific temperature between 400°C and 500°C, for example, 400°C, 450°C, and 500°C, for a heating time of 1 to 3 hours, for example, 1 hour, 2 hours, and 3 hours, to prevent the active layer from being ruptured by gases generated when the active layer is irradiated with high-energy lasers in subsequent steps.

[0086] Reference Figure 7 S5: forming a first portion 51 of the gate 50 on the first doped portion 21. The first portion 51 of the gate 50 may be formed on the first doped portion 21 by physical vapor deposition. The gate 50 may be made of a metal material such as Mo, Ti, or W.

[0087] Reference Figure 8 S6: forming a first insulating layer 40 on the substrate 10 and covering the doped layer 20, the active layer and the first portion 51 of the gate 50. The first insulating layer 40 may be SiO x and SiN x Inorganic film layer.

[0088] Reference Figure 9 S7: The second portion 52 of the gate 50 is formed on the first insulating layer 40, and the second portion 52 overlaps with the first active sub-portion 31 and the second active sub-portion 32. A first connection hole 41 is provided in the first insulating layer 40 between the gate 50 and the first doped portion 21, and the second portion 52 of the gate 50 is connected to the first portion 51 through the first connection hole 41. At the same time, a first connection hole 41 can be formed in the first insulating layer 40 at a position corresponding to the first portion 51 of the gate 50 by etching, so as to facilitate the subsequent connection between the second portion 52 of the gate 50 and the first portion 51. Then, the second portion 52 of the gate 50 is formed on the first insulating layer 40 by physical vapor deposition, so that the second portion 52 is electrically connected to the first portion 51 through the first connection hole 41. The second portion 52 completely overlaps with the first active sub-portion 31 and the second active sub-portion 32, so as to control the first active sub-portion 31 and the second active sub-portion 32.

[0089] Reference Figure 10 S8: forming a second insulating layer 60 on the first insulating layer 40 and covering the second portion 52 of the gate 50. The second insulating layer 60 is formed on the first insulating layer 40 by chemical vapor deposition, and the second insulating layer 60 may be SiO x and SiN x etc. inorganic film layers or their stacked layers to protect the second portion 52 of the gate 50 .

[0090] Reference Figure 11, S9: A source-drain layer is formed on the second insulating layer 60, a second connection hole 61 is formed in the first insulating layer 40 and the second insulating layer 60 between the source-drain layer and the second doped part 22, a third connection hole 62 is formed in the first insulating layer 40 and the second insulating layer 60 between the source-drain layer and the third doped part 23, and the source-drain layer is patterned to form a first electrode 71 and a second electrode 72, the first electrode 71 is connected to the second doped part 22 through the second connection hole 61, and the second electrode 72 is connected to the third doped part 23 through the third connection hole 62.

[0091] Among them, the second connection hole 61 can be formed by etching the first insulating layer 40 and the second insulating layer 60 at a position relative to the second doped portion 22 using an etching solution, and the third connection hole 62 can be formed by etching the first insulating layer 40 and the second insulating layer 60 at a position relative to the third doped portion 23. Then, a source and drain electrode layer is formed on the second insulating layer 60 by physical vapor deposition of metal materials such as Mo, Ti, and Cu. The source and drain electrode layer is deposited in the first connection hole 41 and the second connection hole 61 to connect to the second doped portion 22 and the third doped portion 23, respectively. Then, the source and drain electrode layer is etched to form a first electrode 71 and a second electrode 72, which serve as the source and drain, respectively.

[0092] Reference Figure 1 S10: forming a passivation layer 80 on the source / drain layer and the insulating layer. Optionally, the passivation layer 80 is formed on the first electrode 71 and the second electrode 72 by chemical vapor deposition. The material of the passivation layer 80 can be SiO x and SiN x etc. inorganic film layers or their stacks.

[0093] The above is a detailed introduction to an array substrate, a display panel and a method for preparing an array substrate provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: include: substrate; a doping layer, the doping layer being disposed on the substrate, the doping layer being provided with a first opening and a second opening, the doping layer comprising a first doping portion, a second doping portion, and a third doping portion, the first doping portion being located between the first opening and the second opening, the second doping portion being located on a side of the first opening away from the second opening, and the third doping portion being located on a side of the second opening away from the first opening; an active layer, the active layer being disposed on the substrate and comprising a first active sub-portion and a second active sub-portion, the first active sub-portion being located in the first opening and connected to the first doped portion and the second doped portion, respectively; and the second active sub-portion being located in the second opening and connected to the first doped portion and the third doped portion, respectively. a first insulating layer, the first insulating layer being provided on the substrate and covering the doped layer and the active layer; a gate, the gate being disposed on the first insulating layer and overlapping the first active sub-portion and the second active sub-portion respectively, a first connection hole being defined in the first insulating layer between the gate and the first doped portion, the gate being electrically connected to the first doped portion through the first connection hole; a second insulating layer, the second insulating layer being disposed on the first insulating layer and covering the gate; as well as A source-drain layer, wherein the source-drain layer is arranged on the second insulating layer, the first insulating layer and the second insulating layer between the source-drain layer and the second doped part are provided with a second connection hole, the first insulating layer and the second insulating layer between the source-drain layer and the third doped part are provided with a third connection hole, the source-drain layer includes a first electrode and a second electrode, the first electrode is connected to the second doped part through the second connection hole, and the second electrode is connected to the third doped part through the third connection hole.

2. The array substrate according to claim 1, wherein: The gate is a single-layer structure, and the gate is electrically connected to the first doping portion through the first connection hole.

3. The array substrate according to claim 1, wherein: The gate includes a first portion and a second portion, the first portion is connected and arranged on the first doped portion; the second portion is arranged on the first insulating layer and overlaps with the first active sub-portion and the second active sub-portion, and the first portion and the second portion are connected through the first connecting hole.

4. The array substrate according to claim 1, wherein: The first doped portion includes a first heavily doped portion and a first lightly doped portion that are adjacent to each other, the first heavily doped portion is connected to the first active sub-portion, the first lightly doped portion is connected to the second active sub-portion, and the gate is electrically connected to the first heavily doped portion through the first connection hole.

5. The array substrate according to claim 4, wherein: The second doped portion includes a second heavily doped portion and a second lightly doped portion that are adjacent to each other, the second lightly doped portion is located on a side of the second heavily doped portion away from the first lightly doped portion, and the first electrode of the source and drain layer is connected to the second heavily doped portion through the second connection hole; And / or, the third doped portion includes a third heavily doped portion and a third lightly doped portion arranged adjacent to each other, the third heavily doped portion is located on a side of the third lightly doped portion away from the first heavily doped portion, and the second electrode of the source and drain layer is connected to the third heavily doped portion through the third connection hole.

6. The array substrate according to claim 1, wherein: The thickness of the first active sub-portion is smaller than the thickness of the first doped portion and / or the thickness of the second doped portion; And / or, the thickness of the second active sub-portion is smaller than the thickness of the first doped portion and / or the thickness of the third doped portion.

7. A display panel, characterized in that: Comprising the array substrate according to any one of claims 1 to 6.

8. A method for preparing an array substrate, characterized in that: include: S1: providing a substrate; S2: forming a doping layer on the substrate, and patterning the doping layer to form a first opening, a second opening, a first doping portion, a second doping portion, and a third doping portion, wherein the first doping portion is located between the first opening and the second opening, the second doping portion is located on a side of the first opening away from the second opening, and the third doping portion is located on a side of the second opening away from the first opening; S3: forming an active layer on the substrate, the active layer comprising a first active sub-portion and a second active sub-portion, the first active sub-portion covering the first opening and connected to the first doped portion and the second doped portion, the second active sub-portion covering the second opening and connected to the first doped portion and the third doped portion respectively; S4: performing annealing and crystallization treatment on the first active sub-section and the second active sub-section; S5: forming a first portion of a gate on the first doped portion; S6: forming a first insulating layer on the substrate, and covering the doped layer, the active layer and the first portion of the gate; S7: forming a second portion of the gate on the first insulating layer, wherein the second portion overlaps the first active sub-portion and the second active sub-portion, and a first connection hole is formed in the first insulating layer between the gate and the first doped portion, and the second portion of the gate is connected to the first portion through the first connection hole; S8: forming a second insulating layer on the first insulating layer and covering the second portion of the gate; S9: forming a source-drain layer on the second insulating layer, wherein a second connection hole is formed in the first insulating layer and the second insulating layer between the source-drain layer and the second doped portion, and a third connection hole is formed in the first insulating layer and the second insulating layer between the source-drain layer and the third doped portion, and the source-drain layer is patterned to form a first electrode and a second electrode, the first electrode is connected to the second doped portion through the second connection hole, and the second electrode is connected to the third doped portion through the third connection hole; S10: forming a passivation layer on the source / drain electrode layer and the second insulating layer.

9. The preparation method according to claim 8, wherein The step of performing crystallization on the first active sub-section and the second active sub-section in step S4 includes: The blue laser moves along a predetermined direction to perform a laser annealing process on the first active sub-section and the second active sub-section.

10. The preparation method according to claim 9, characterized in that The step S4 of performing crystallization on the first active sub-section and the second active sub-section further includes: The blue laser also irradiates the first doping portion, the second doping portion and the third doping portion, so that the first doping portion melts and diffuses to form a first heavily doped portion and a first lightly doped portion adjacent to each other along the predetermined direction, the second doping portion melts and diffuses to form a second heavily doped portion and a second lightly doped portion adjacent to each other along the predetermined direction, and the third doping portion melts and diffuses to form a third heavily doped portion and a third lightly doped portion adjacent to each other along the predetermined direction.

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