Array substrate and display panel

Abstract

The present invention discloses an array substrate and a display panel. The array substrate includes a substrate, a light-shielding layer, an insulating dielectric layer, a metal wiring layer, and a thin-film transistor layer; the light-shielding layer is located on the substrate; the insulating dielectric layer includes a first dielectric layer and a second dielectric layer, the first dielectric layer covers the light-shielding layer and the substrate, the second dielectric layer is located on the first dielectric layer, and the first dielectric layer has a protruding structure formed at the portion covering the light-shielding layer; the metal wiring layer is located on the second dielectric layer, and has source-drain wiring formed thereon, with the protruding structure located between adjacent source-drain wirings; the thin-film transistor layer is connected to the source-drain wirings; during the formation of the metal wiring layer, metal wiring material of the metal wiring layer remains on the protruding structure, and during the formation of the second dielectric layer, the metal wiring material on the protruding structure is removed. On the array substrate of the present invention, no metal wiring material remains on the protruding structure, so a short circuit will not occur between the source-drain wirings due to the residual metal wiring material.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] Thin-film transistors (TFTs) are crucial components in display panels. To prevent external light from reaching the TFT's active layer, existing technologies employ a metal light-shielding layer beneath the TFT active layer to ensure TFT performance. Furthermore, to improve resolution, the width of the source and drain metal traces is reduced, while to increase refresh rates, the thickness of the metal traces is increased. Furthermore, to reduce the parasitic capacitance between the source and drain metal traces and the light-shielding layer, the thickness of the insulating dielectric layer between them also needs to be increased.

[0003] like Figure 1 As shown in FIG, as the thickness of the light shielding layer LS and the insulating dielectric layer ILD increases, a protruding structure A is formed on the insulating dielectric layer ILD at the climbing position of the light shielding layer LS, and the sidewall of the protruding structure A has a large angle or is concave; when the etching method of the source and drain metal traces SD is wet etching or dry etching, metal B residue is likely to appear on the protruding structure, as shown in FIG. Figure 2 As shown in FIG. 1 , the residual metal B may cause the source-drain metal trace SD to be short-circuited through the residual metal B. Summary of the Invention

[0004] In view of the above-mentioned deficiencies in the prior art, an object of the present invention is to provide an array substrate and a display panel, which can avoid short circuits between source and drain lines.

[0005] To achieve the above-mentioned object, the present invention first provides an array substrate, comprising:

[0006] substrate;

[0007] a light shielding layer, located on the substrate;

[0008] The insulating dielectric layer includes a first dielectric layer and a second dielectric layer, wherein the first dielectric layer covers the light shielding layer and the substrate, the second dielectric layer is located on the first dielectric layer, and a convex structure is formed on the first dielectric layer at a position covering the light shielding layer;

[0009] A metal wiring layer is located on the second dielectric layer and forms source and drain wirings, wherein the protruding structure is located between adjacent source and drain wirings;

[0010] a thin film transistor layer connected to the source and drain traces;

[0011] During the process of forming the metal wiring layer, metal wiring material of the metal wiring layer remains on the protruding structure. During the process of forming the second dielectric layer, the metal wiring material on the protruding structure is removed.

[0012] Optionally, the metal wiring layer includes a first conductive material layer and a second conductive material layer, the first conductive material layer is located on the second dielectric layer, and the second conductive material layer is located on the first conductive material layer.

[0013] Optionally, the size of the second dielectric layer is larger than the size of the first conductive material layer.

[0014] Optionally, the size of the second dielectric layer is 1 um to 3 um larger than the size of the first conductive material layer.

[0015] Optionally, a size of the first conductive material layer is larger than a size of the second conductive material layer.

[0016] Optionally, a size of the first conductive material layer is 0.4 um to 1 um larger than a size of the second conductive material layer.

[0017] Optionally, the first conductive material layer includes a titanium metal layer, and the second conductive material layer includes a copper metal layer.

[0018] Optionally, the first dielectric layer includes a silicon oxide layer and a silicon nitride layer, and the thickness of the silicon oxide layer is to The thickness of the silicon nitride layer is to

[0019] Optionally, the material of the second dielectric layer includes aluminum oxide, and the thickness of the second dielectric layer is to

[0020] The present invention also provides a display panel including the above array substrate.

[0021] Compared with the prior art, the present invention has the following beneficial effects: the array substrate of the present invention includes a substrate, a light-shielding layer, an insulating dielectric layer, a metal wiring layer, and a thin-film transistor layer; the light-shielding layer is located on the substrate; the insulating dielectric layer includes a first dielectric layer and a second dielectric layer, the first dielectric layer covering the light-shielding layer and the substrate, the second dielectric layer being located on the first dielectric layer, and the first dielectric layer having a protruding structure formed thereon where it covers the light-shielding layer; the metal wiring layer is located on the second dielectric layer, forming source and drain wiring, the protruding structure being located between adjacent source and drain wirings; and the thin-film transistor layer is connected to the source and drain wirings; during the formation of the metal wiring layer, metal wiring material of the metal wiring layer remains on the protruding structure, and during the formation of the second dielectric layer, the metal wiring material on the protruding structure is removed. On the array substrate of the present invention, no metal wiring material remains on the protruding structure, so a short circuit will not occur between the source and drain wirings due to the residual metal wiring material, thereby ensuring the operational stability of the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 It is a structural diagram of an array substrate in the prior art;

[0024] Figure 2 It is a top view of the source and drain metal wiring and the light shielding layer in the prior art;

[0025] Figure 3 2 is a schematic diagram of the structure of the array substrate after the residual metal Ti is removed according to an embodiment of the present invention;

[0026] Figure 4 FIG. 1 is a schematic diagram of the structure of the array substrate before the residual metal Ti is removed according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following descriptions of the various embodiments are with reference to the accompanying drawings to illustrate specific embodiments in which the present invention may be implemented. In the description of the present invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended only to facilitate the description of the present invention and simplify the description. They do not indicate or imply that the modules or components referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "multiple" means two or more, unless otherwise specifically defined.

[0028] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections, or mutual communication; direct connections or indirect connections through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0029] An embodiment of the present invention provides an array substrate, such as Figure 3 As shown, it includes a substrate 1, a light-shielding layer 2, an insulating dielectric layer 3, a metal wiring layer 4 and a thin film transistor layer (not shown); the light-shielding layer 2 is located on the substrate 1; the insulating dielectric layer 3 includes a first dielectric layer 31 and a second dielectric layer 32, the first dielectric layer 31 covers the light-shielding layer 2 and the substrate, the second dielectric layer 32 is located on the first dielectric layer 31, and the first dielectric layer 31 has a protruding structure 30 formed at the portion covering the light-shielding layer 2; the metal wiring layer 4 is located on the second dielectric layer 32, and has source-drain wiring 41 formed thereon, and the protruding structure 30 is located between adjacent source-drain wirings 41; the thin film transistor layer is connected to the source-drain wiring 41; in the process of forming the metal wiring layer 4, metal wiring material C of the metal wiring layer 4 remains on the protruding structure 30, as shown in FIG. Figure 3 and Figure 4 As shown, during the process of forming the second dielectric layer 32 , the metal wiring material C on the protruding structure 30 is removed.

[0030] On the array substrate of this embodiment, no metal wiring material C remains on the protruding structures 30 , so no short circuit occurs between the source and drain wirings 41 due to the remaining metal wiring material, thereby ensuring the working stability of the array substrate.

[0031] In one embodiment, the metal wiring layer 4 includes a first conductive material layer 401 and a second conductive material layer 402. The first conductive material layer 401 is located on the second dielectric layer 32, and the second conductive material layer 402 is located on the first conductive material layer 401. In this embodiment, the metal wiring layer 4 includes source and drain wiring 41, which adopts a two-layer structure to improve conductivity and facilitate the display panel to provide high resolution and refresh rate.

[0032] Specifically, the first conductive material layer 401 includes a titanium (Ti) metal layer, and the second conductive material layer 402 includes a copper (Cu) metal layer. The metal trace layer 4 of this embodiment adopts a Cu / Ti structure, with a titanium metal layer disposed below the copper metal layer as a substrate. This improves the conductivity of the source and drain traces 41, thereby facilitating the display panel's resolution and refresh rate.

[0033] During the process of forming the metal wiring layer 4 , the metal wiring material C of the metal wiring layer 4 , specifically the metal Ti, that is, Ti of the first conductive material layer 401 , remains on the protruding structure 30 .

[0034] In one embodiment, the second dielectric layer 32 is larger than the first conductive material layer 401. Specifically, the second dielectric layer 32 is 1 μm to 3 μm larger than the first conductive material layer 401. This prevents the risk of metal material Ti from remaining on the first dielectric layer 31, which could cause a short circuit between the source and drain traces 41.

[0035] In one embodiment, the first conductive material layer 401 is larger than the second conductive material layer 402. Specifically, the first conductive material layer 401 is 0.4 to 1 μm larger than the second conductive material layer 402. This facilitates the layout and etching of the source and drain traces 41.

[0036] In one embodiment, the first dielectric layer 31 includes a silicon oxide layer (SiO) and a silicon nitride layer (SiN), and the thickness of the silicon oxide layer is to The thickness of the silicon nitride layer is to In this way, the insulation stability of the first dielectric layer 31 can be ensured.

[0037] In one embodiment, the material of the second dielectric layer 32 includes aluminum oxide (Al2O3), and the thickness of the second dielectric layer 32 is to In this way, the insulation stability between the source-drain wiring 41 and the first dielectric layer 31 can be ensured.

[0038] In one embodiment, the thin film transistor layer includes a gate, a source, a drain, an active layer and a gate insulating layer; the active layer includes a source connection region, a drain connection region and a channel region, the source is connected to the source connection region, the drain is connected to the drain connection region, and the channel region is located between the source connection region and the drain connection region.

[0039] The gate is formed by the first metal layer, using a Cu / MoTi double-layer structure, with the Cu layer on top and the MoTi layer on the bottom. The source and drain are formed by the second metal layer, using the same material structure as the source-drain trace 41. Both the source and drain use a Cu / Ti double-layer structure, with the Cu metal on top and the Ti substrate below.

[0040] The active layer is made of indium gallium zinc oxide (IGZO), which has lower leakage current and better mobility than amorphous silicon (a-Si). It can be used as a Top Gate TFT device to drive OLED (organic light-emitting diode).

[0041] IGZO is an amorphous oxide containing indium, gallium, and zinc. Its carrier mobility is 20 to 30 times that of amorphous silicon. This significantly increases the charge and discharge rate of the TFT (thin-film transistor) to the pixel electrode, improving the pixel's response speed and achieving a faster refresh rate. This faster response also significantly increases the pixel's row scan rate. Furthermore, due to the reduced number of transistors and increased light transmittance per pixel, IGZO displays offer higher energy efficiency and are more efficient.

[0042] The gate insulating layer adopts silicon oxide (SiO) material, the gate insulating layer is located on the active layer, and the gate is located on the gate insulating layer.

[0043] In one embodiment, the array substrate further includes a buffer layer 5 , which covers the light shielding layer 2 and the substrate 1 , and the first dielectric layer 31 is located on the buffer layer 5 .

[0044] In the prior art, the sidewall of the protruding structure 30 (the climbing position of the insulating dielectric layer 3) has a large slope, generally above 80°, so that a recessed area is easily formed on the sidewall of the protruding structure 30. During the etching process of the second metal layer, metal material will remain in the recessed area of ​​the sidewall of the protruding structure 30, resulting in a short circuit between the source and drain lines 41.

[0045] Therefore, the insulating dielectric layer 3 of the array substrate of this embodiment is formed using a SiO+Al2O3 film formation method. The insulating dielectric layer 3 includes a first dielectric layer 31 and a second dielectric layer 32. The first dielectric layer 31 covers the light shielding layer 2 and the substrate, and the second dielectric layer 32 is located on the first dielectric layer 31. The first dielectric layer 31 has a protruding structure 30 formed at the portion covering the light shielding layer 2. The first dielectric layer 31 is composed of SiO and SiN, and the second dielectric layer 32 is composed of Al2O3.

[0046] The metal wiring layer 4 is located on the second dielectric layer 32 and forms source and drain wirings 41. The protruding structure 30 is located between adjacent source and drain wirings 41. The metal wiring layer 4 includes a first conductive material layer 401 and a second conductive material layer 402. The first conductive material layer 401 is located on the second dielectric layer 32. The second conductive material layer 402 is located on the first conductive material layer 401. The first conductive material layer 401 includes a titanium (Ti) metal layer, and the second conductive material layer 402 includes a copper (Cu) metal layer.

[0047] During the process of forming the metal wiring layer 4 , Ti of the metal wiring layer 4 remains on the protruding structure 30 . During the process of forming the second dielectric layer 32 , the Ti on the protruding structure 30 is etched away together with Al 2 O 3 .

[0048] In this embodiment, a SiO+Al2O3 film formation method is adopted when forming the insulating dielectric layer 3, wherein Al2O3 is on the top layer, so that the Ti of the source-drain wiring 41 is in contact with Al2O3. After the source-drain wiring 41 is patterned by wet etching and dry etching, Ti remains on the Al2O3. Then, a mask for the source-drain wiring 41 is used to pattern the source-drain wiring 41, and the exposure amount is reduced so that the photoresist PR covers the source-drain wiring 41 when the source-drain wiring 41 is patterned again. Then, Al acid is used to etch away the Al2O3 outside the pattern of the source-drain wiring 41. Because there is Al2O3 below the Ti residual position, the Al acid will penetrate under the Ti, etch away the Al2O3, and take away the residual Ti.

[0049] In this way, no metal wiring material remains on the protruding structure 30 , so that no short circuit occurs between the source and drain wirings 41 due to the remaining metal wiring material, thereby ensuring the working stability of the array substrate.

[0050] The manufacturing method of the array substrate of the embodiment of the present invention is as follows:

[0051] ① The light shielding layer 2 is formed by patterning the first mask. The light shielding layer 2 can adopt a Cu / Ti structure, with Cu in the upper layer and Ti in the bottom layer.

[0052] ② Perform SiN chemical vapor deposition to obtain a SiN layer with a thickness of to Then SiO2 chemical vapor deposition is performed to obtain a SiO2 layer with a thickness of approximately to

[0053] ③ The IGZO is patterned by a second mask to form an IGZO layer, which serves as an active layer. The thickness of the IGZO layer is to

[0054] ④ A gate insulating layer is obtained by forming a film through SiO2 chemical vapor deposition; then the first metal layer M1 is formed, and the first metal layer M1 adopts a Cu / MoTi structure with MoTi at the bottom layer; then through a third mask, wet etching and dry etching are used to form the pattern of the gate and the gate insulating layer.

[0055] ⑤ Perform SiO chemical vapor deposition to form a first dielectric layer 31, and perform Al2O3 physical vapor deposition to form an Al2O3 layer, the thickness of the Al2O3 layer is to The first dielectric layer 31 forms a protruding structure 30 at the climbing position of the light-shielding layer 2; through the fourth mask, dry etching patterning is used to form a contact hole between the light-shielding layer 2 and the second metal layer M2; and through the fifth mask, dry etching patterning is used to form a contact hole between the second metal layer M2 and the IGZO layer.

[0056] ⑥ The second metal layer M2 is patterned through the sixth mask to form source-drain electrodes and source-drain wiring 41 (metal wiring layer 4). The second metal layer M2 adopts a Cu / Ti structure, with Ti at the bottom layer; Cu is wet etched and Ti is dry etched; the second metal layer M2 is re-patterned, and the exposure amount is reduced so that the photoresist PR pattern on the source-drain wiring 41 covers the source-drain wiring 41 formed for the first time; Al acid is then used to etch away the exposed Al2O3. At the corner position of the insulating dielectric layer 3, Al acid penetrates and etches away the exposed Al2O3, while taking away the residual Ti on the Al2O3, forming a second dielectric layer 32 below the source-drain wiring 41.

[0057] ⑦ Perform SiO chemical vapor deposition to form a film, and pattern it through the seventh mask to obtain a passivation layer. The connection holes of the passivation layer are used to connect the bonding pad and the second metal layer M2.

[0058] ⑧ The Pad layer is formed by patterning through the eighth mask. The Pad material is MoTi, which is used to act as a bonding pad and is connected to the second metal layer M2 through the passivation layer connection hole.

[0059] ⑨ A flat layer is obtained by patterning through the ninth mask, and contact holes for the anode Anode and the pad are formed.

[0060] ⑩ The anode Anode is formed by patterning through the tenth mask.

[0061] The bank hole is formed by patterning with the eleventh mask for filling the electroluminescent layer EL.

[0062] In this embodiment, the insulating dielectric layer 3 is formed using a SiO+Al2O3 film formation method, with the Al2O3 layer at the top. This allows the Ti layer of the source / drain trace 41 to contact the Al2O3 layer. After the source / drain trace 41 is patterned by wet and dry etching, Ti remains above the Al2O3 layer. A photomask for the source / drain trace 41 is then used to pattern the source / drain trace 41, reducing the exposure. This allows the photoresist PR to cover the source / drain trace 41 during re-patterning. Al-acid is then used to completely etch away the Al2O3 layer outside the source / drain trace 41 pattern. Because Al2O3 is located below the Ti residue, the Al-acid will penetrate beneath the Ti layer, etching away the Al2O3 and removing the remaining Ti. This ensures that no metal trace material remains on the protruding structure 30, preventing short circuits between the source / drain traces 41 due to the remaining metal trace material, thereby ensuring the operational stability of the array substrate.

[0063] The present invention also provides a display panel, including the array substrate provided by the above embodiment.

[0064] In the display panel of this embodiment, the array substrate includes a substrate 1, a light shielding layer 2, an insulating dielectric layer 3, a metal wiring layer 4 and a thin film transistor layer (not shown);

[0065] The insulating dielectric layer 3 is formed using a SiO+Al2O3 film formation method. The insulating dielectric layer 3 includes a first dielectric layer 31 and a second dielectric layer 32. The first dielectric layer 31 covers the light shielding layer 2 and the substrate 1. The second dielectric layer 32 is located on the first dielectric layer 31. The first dielectric layer 31 has a protrusion structure 30 formed at the portion covering the light shielding layer 2. The first dielectric layer 31 is composed of SiO and SiN, and the second dielectric layer 32 is composed of Al2O3.

[0066] The metal wiring layer 4 is located on the second dielectric layer 32 and forms source and drain wirings 41. The protruding structure 30 is located between adjacent source and drain wirings 41. The metal wiring layer 4 includes a first conductive material layer 401 and a second conductive material layer 402. The first conductive material layer 401 is located on the second dielectric layer 32. The second conductive material layer 402 is located on the first conductive material layer 401. The first conductive material layer 401 includes a titanium (Ti) metal layer, and the second conductive material layer 402 includes a copper (Cu) metal layer.

[0067] During the process of forming the metal wiring layer 4 , Ti of the metal wiring layer 4 remains on the protruding structure 30 . During the process of forming the second dielectric layer 32 , the Ti on the protruding structure 30 is etched away together with Al 2 O 3 .

[0068] In this embodiment, a SiO+Al2O3 film formation method is adopted when forming the insulating dielectric layer 3, wherein Al2O3 is on the top layer, so that the Ti of the source-drain wiring 41 is in contact with Al2O3. After the source-drain wiring 41 is patterned by wet etching and dry etching, Ti remains on the Al2O3. Then, a mask for the source-drain wiring 41 is used to pattern the source-drain wiring 41, and the exposure amount is reduced so that the photoresist PR covers the source-drain wiring 41 when the source-drain wiring 41 is patterned again. Then, Al acid is used to etch away the Al2O3 outside the pattern of the source-drain wiring 41. Because there is Al2O3 below the Ti residual position, the Al acid will penetrate under the Ti, etch away the Al2O3, and take away the residual Ti.

[0069] In this way, no metal wiring material remains on the protruding structure 30 , so that no short circuit occurs between the source and drain wirings 41 due to the remaining metal wiring material, thereby ensuring the working stability of the array substrate.

[0070] The second dielectric layer 32 is larger than the first conductive material layer 401. Specifically, the second dielectric layer 32 is 1 μm to 3 μm larger than the first conductive material layer 401. This prevents the risk of metal material from remaining on the first dielectric layer 31 and causing a short circuit between the source and drain traces 41.

[0071] The size of the first conductive material layer 401 is larger than that of the second conductive material layer 402. Specifically, the size of the first conductive material layer 401 is 0.4um to 1um larger than that of the second conductive material layer 402. This facilitates the layout and etching of the source and drain traces 41.

[0072] The first dielectric layer 31 includes a silicon oxide layer (SiO) and a silicon nitride layer (SiN). The thickness of the silicon oxide layer is to The thickness of the silicon nitride layer is to In this way, the insulation stability of the first dielectric layer 31 can be ensured.

[0073] The material of the second dielectric layer 32 includes aluminum oxide (Al2O3), and the thickness of the second dielectric layer 32 is to In this way, the insulation stability between the source-drain wiring 41 and the first dielectric layer 31 can be ensured.

[0074] The thin film transistor layer includes a gate, a source, a drain, an active layer and a gate insulating layer; the active layer includes a source connection region, a drain connection region and a channel region, the source is connected to the source connection region, the drain is connected to the drain connection region, and the channel region is located between the source connection region and the drain connection region.

[0075] The gate is formed by the first metal layer, using a Cu / MoTi double-layer structure, with the Cu layer on top and the MoTi layer on the bottom. The source and drain are formed by the second metal layer, using the same material structure as the source-drain trace 41. Both the source and drain use a Cu / Ti double-layer structure, with the Cu metal on top and the Ti substrate below.

[0076] The active layer is made of indium gallium zinc oxide (IGZO), which has lower leakage current and better mobility than amorphous silicon (a-Si), and can be used as a Top Gate TFT device to drive OLED.

[0077] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. An array substrate, characterized in that: include: substrate; a light shielding layer, located on the substrate; an insulating dielectric layer, comprising a first dielectric layer and a second dielectric layer, wherein the first dielectric layer covers the light-shielding layer and the substrate, the second dielectric layer is located on the first dielectric layer, and a protrusion structure is formed on the first dielectric layer where the first dielectric layer covers the light-shielding layer; a metal wiring layer, located on the second dielectric layer, forming source and drain wirings, wherein the protruding structure is located between adjacent source and drain wirings; a thin film transistor layer connected to the source and drain wiring; During the process of forming the metal wiring layer, metal wiring material of the metal wiring layer remains on the protruding structure, and during the process of forming the second dielectric layer, the metal wiring material on the protruding structure is removed; The step of removing the metal wiring material on the protruding structure during the formation of the second dielectric layer includes: forming a second dielectric layer material to cover the first dielectric layer; The metal routing layer is formed on the second dielectric layer material. During the process of forming the metal routing layer, metal routing material of the metal routing layer remains on the second dielectric layer material covering the protruding structure. The second dielectric layer material except the second dielectric layer material below the metal routing layer is etched cleanly to form the second dielectric layer, while removing the remaining metal routing material.

2. The array substrate according to claim 1, wherein: The metal wiring layer includes a first conductive material layer and a second conductive material layer. The first conductive material layer is located on the second dielectric layer, and the second conductive material layer is located on the first conductive material layer.

3. The array substrate according to claim 2, wherein: The size of the second dielectric layer is larger than that of the first conductive material layer.

4. The array substrate according to claim 3, wherein: The size of the second dielectric layer is 1 um to 3 um larger than that of the first conductive material layer.

5. The array substrate according to claim 2, wherein: The size of the first conductive material layer is larger than that of the second conductive material layer.

6. The array substrate according to claim 5, wherein: The size of the first conductive material layer is larger than that of the second conductive material layer by 0.4 um to 1 um.

7. The array substrate according to claim 2, wherein: The first conductive material layer includes a titanium metal layer, and the second conductive material layer includes a copper metal layer.

8. The array substrate according to claim 1, wherein: The first dielectric layer includes a silicon oxide layer and a silicon nitride layer. The thickness of the silicon oxide layer is 2000 Å to 3000 Å, and the thickness of the silicon nitride layer is 500 Å to 2000 Å.

9. The array substrate according to claim 1, wherein: The material of the second dielectric layer includes aluminum oxide, and the thickness of the second dielectric layer is 200 Å to 500 Å.

10. A display panel, characterized in that: The array substrate comprises the array substrate according to any one of claims 1 to 9.

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